aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorKishon Vijay Abraham I <kishon@ti.com>2017-02-15 08:18:14 -0500
committerBjorn Helgaas <bhelgaas@google.com>2017-02-21 16:00:26 -0500
commit442ec4c04d1235f8c664a74004dae54a7a574d18 (patch)
tree66e1b54e8cabd635a378b48307175dac998fa47b
parent40f67fb2c384fe12741aa35010d62bfe8c98286c (diff)
PCI: dwc: all: Split struct pcie_port into host-only and core structures
Keep only the host-specific members in struct pcie_port and move the common members (i.e common to both host and endpoint) to struct dw_pcie. This is in preparation for adding endpoint mode support to designware driver. While at that also fix checkpatch warnings. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Jingoo Han <jingoohan1@gmail.com> CC: Richard Zhu <hongxing.zhu@nxp.com> CC: Lucas Stach <l.stach@pengutronix.de> CC: Murali Karicheri <m-karicheri2@ti.com> CC: Minghuan Lian <minghuan.Lian@freescale.com> CC: Mingkai Hu <mingkai.hu@freescale.com> CC: Roy Zang <tie-fei.zang@freescale.com> CC: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> CC: Niklas Cassel <niklas.cassel@axis.com> CC: Jesper Nilsson <jesper.nilsson@axis.com> CC: Joao Pinto <Joao.Pinto@synopsys.com> CC: Zhou Wang <wangzhou1@hisilicon.com> CC: Gabriele Paoloni <gabriele.paoloni@huawei.com> CC: Stanimir Varbanov <svarbanov@mm-sol.com> CC: Pratyush Anand <pratyush.anand@gmail.com>
Diffstat
-rw-r--r--drivers/pci/dwc/pci-dra7xx.c80
-rw-r--r--drivers/pci/dwc/pci-exynos.c78
-rw-r--r--drivers/pci/dwc/pci-imx6.c128
-rw-r--r--drivers/pci/dwc/pci-keystone-dw.c83
-rw-r--r--drivers/pci/dwc/pci-keystone.c54
-rw-r--r--drivers/pci/dwc/pci-keystone.h4
-rw-r--r--drivers/pci/dwc/pci-layerscape.c91
-rw-r--r--drivers/pci/dwc/pcie-armada8k.c85
-rw-r--r--drivers/pci/dwc/pcie-artpec6.c48
-rw-r--r--drivers/pci/dwc/pcie-designware-plat.c27
-rw-r--r--drivers/pci/dwc/pcie-designware.c203
-rw-r--r--drivers/pci/dwc/pcie-designware.h67
-rw-r--r--drivers/pci/dwc/pcie-hisi.c55
-rw-r--r--drivers/pci/dwc/pcie-qcom.c70
-rw-r--r--drivers/pci/dwc/pcie-spear13xx.c74
15 files changed, 666 insertions, 481 deletions
diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
index 4b9b1e1f00cb..0984baff07e3 100644
--- a/drivers/pci/dwc/pci-dra7xx.c
+++ b/drivers/pci/dwc/pci-dra7xx.c
@@ -67,7 +67,7 @@
67#define EXP_CAP_ID_OFFSET 0x70 67#define EXP_CAP_ID_OFFSET 0x70
68 68
69struct dra7xx_pcie { 69struct dra7xx_pcie {
70 struct pcie_port pp; 70 struct dw_pcie *pci;
71 void __iomem *base; /* DT ti_conf */ 71 void __iomem *base; /* DT ti_conf */
72 int phy_count; /* DT phy-names count */ 72 int phy_count; /* DT phy-names count */
73 struct phy **phy; 73 struct phy **phy;
@@ -75,7 +75,7 @@ struct dra7xx_pcie {
75 struct irq_domain *irq_domain; 75 struct irq_domain *irq_domain;
76}; 76};
77 77
78#define to_dra7xx_pcie(x) container_of((x), struct dra7xx_pcie, pp) 78#define to_dra7xx_pcie(x) dev_get_drvdata((x)->dev)
79 79
80static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset) 80static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset)
81{ 81{
@@ -88,9 +88,9 @@ static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
88 writel(value, pcie->base + offset); 88 writel(value, pcie->base + offset);
89} 89}
90 90
91static int dra7xx_pcie_link_up(struct pcie_port *pp) 91static int dra7xx_pcie_link_up(struct dw_pcie *pci)
92{ 92{
93 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp); 93 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
94 u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS); 94 u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS);
95 95
96 return !!(reg & LINK_UP); 96 return !!(reg & LINK_UP);
@@ -98,32 +98,32 @@ static int dra7xx_pcie_link_up(struct pcie_port *pp)
98 98
99static int dra7xx_pcie_establish_link(struct dra7xx_pcie *dra7xx) 99static int dra7xx_pcie_establish_link(struct dra7xx_pcie *dra7xx)
100{ 100{
101 struct pcie_port *pp = &dra7xx->pp; 101 struct dw_pcie *pci = dra7xx->pci;
102 struct device *dev = pp->dev; 102 struct device *dev = pci->dev;
103 u32 reg; 103 u32 reg;
104 u32 exp_cap_off = EXP_CAP_ID_OFFSET; 104 u32 exp_cap_off = EXP_CAP_ID_OFFSET;
105 105
106 if (dw_pcie_link_up(pp)) { 106 if (dw_pcie_link_up(pci)) {
107 dev_err(dev, "link is already up\n"); 107 dev_err(dev, "link is already up\n");
108 return 0; 108 return 0;
109 } 109 }
110 110
111 if (dra7xx->link_gen == 1) { 111 if (dra7xx->link_gen == 1) {
112 dw_pcie_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP, 112 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
113 4, &reg); 113 4, &reg);
114 if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { 114 if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
115 reg &= ~((u32)PCI_EXP_LNKCAP_SLS); 115 reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
116 reg |= PCI_EXP_LNKCAP_SLS_2_5GB; 116 reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
117 dw_pcie_write(pp->dbi_base + exp_cap_off + 117 dw_pcie_write(pci->dbi_base + exp_cap_off +
118 PCI_EXP_LNKCAP, 4, reg); 118 PCI_EXP_LNKCAP, 4, reg);
119 } 119 }
120 120
121 dw_pcie_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2, 121 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
122 2, &reg); 122 2, &reg);
123 if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { 123 if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
124 reg &= ~((u32)PCI_EXP_LNKCAP_SLS); 124 reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
125 reg |= PCI_EXP_LNKCAP_SLS_2_5GB; 125 reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
126 dw_pcie_write(pp->dbi_base + exp_cap_off + 126 dw_pcie_write(pci->dbi_base + exp_cap_off +
127 PCI_EXP_LNKCTL2, 2, reg); 127 PCI_EXP_LNKCTL2, 2, reg);
128 } 128 }
129 } 129 }
@@ -132,7 +132,7 @@ static int dra7xx_pcie_establish_link(struct dra7xx_pcie *dra7xx)
132 reg |= LTSSM_EN; 132 reg |= LTSSM_EN;
133 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg); 133 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
134 134
135 return dw_pcie_wait_for_link(pp); 135 return dw_pcie_wait_for_link(pci);
136} 136}
137 137
138static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx) 138static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
@@ -149,7 +149,8 @@ static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
149 149
150static void dra7xx_pcie_host_init(struct pcie_port *pp) 150static void dra7xx_pcie_host_init(struct pcie_port *pp)
151{ 151{
152 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp); 152 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
153 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
153 154
154 pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR; 155 pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR;
155 pp->mem_base &= DRA7XX_CPU_TO_BUS_ADDR; 156 pp->mem_base &= DRA7XX_CPU_TO_BUS_ADDR;
@@ -163,8 +164,7 @@ static void dra7xx_pcie_host_init(struct pcie_port *pp)
163 dra7xx_pcie_enable_interrupts(dra7xx); 164 dra7xx_pcie_enable_interrupts(dra7xx);
164} 165}
165 166
166static struct pcie_host_ops dra7xx_pcie_host_ops = { 167static struct dw_pcie_host_ops dra7xx_pcie_host_ops = {
167 .link_up = dra7xx_pcie_link_up,
168 .host_init = dra7xx_pcie_host_init, 168 .host_init = dra7xx_pcie_host_init,
169}; 169};
170 170
@@ -183,8 +183,9 @@ static const struct irq_domain_ops intx_domain_ops = {
183 183
184static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp) 184static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
185{ 185{
186 struct device *dev = pp->dev; 186 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
187 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp); 187 struct device *dev = pci->dev;
188 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
188 struct device_node *node = dev->of_node; 189 struct device_node *node = dev->of_node;
189 struct device_node *pcie_intc_node = of_get_next_child(node, NULL); 190 struct device_node *pcie_intc_node = of_get_next_child(node, NULL);
190 191
@@ -206,7 +207,8 @@ static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
206static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg) 207static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
207{ 208{
208 struct dra7xx_pcie *dra7xx = arg; 209 struct dra7xx_pcie *dra7xx = arg;
209 struct pcie_port *pp = &dra7xx->pp; 210 struct dw_pcie *pci = dra7xx->pci;
211 struct pcie_port *pp = &pci->pp;
210 u32 reg; 212 u32 reg;
211 213
212 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI); 214 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
@@ -233,7 +235,8 @@ static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
233static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg) 235static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
234{ 236{
235 struct dra7xx_pcie *dra7xx = arg; 237 struct dra7xx_pcie *dra7xx = arg;
236 struct device *dev = dra7xx->pp.dev; 238 struct dw_pcie *pci = dra7xx->pci;
239 struct device *dev = pci->dev;
237 u32 reg; 240 u32 reg;
238 241
239 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN); 242 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN);
@@ -288,8 +291,9 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
288 struct platform_device *pdev) 291 struct platform_device *pdev)
289{ 292{
290 int ret; 293 int ret;
291 struct pcie_port *pp = &dra7xx->pp; 294 struct dw_pcie *pci = dra7xx->pci;
292 struct device *dev = pp->dev; 295 struct pcie_port *pp = &pci->pp;
296 struct device *dev = pci->dev;
293 struct resource *res; 297 struct resource *res;
294 298
295 pp->irq = platform_get_irq(pdev, 1); 299 pp->irq = platform_get_irq(pdev, 1);
@@ -311,8 +315,8 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
311 return ret; 315 return ret;
312 316
313 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbics"); 317 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbics");
314 pp->dbi_base = devm_ioremap(dev, res->start, resource_size(res)); 318 pci->dbi_base = devm_ioremap(dev, res->start, resource_size(res));
315 if (!pp->dbi_base) 319 if (!pci->dbi_base)
316 return -ENOMEM; 320 return -ENOMEM;
317 321
318 ret = dw_pcie_host_init(pp); 322 ret = dw_pcie_host_init(pp);
@@ -324,6 +328,10 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
324 return 0; 328 return 0;
325} 329}
326 330
331static const struct dw_pcie_ops dw_pcie_ops = {
332 .link_up = dra7xx_pcie_link_up,
333};
334
327static void dra7xx_pcie_disable_phy(struct dra7xx_pcie *dra7xx) 335static void dra7xx_pcie_disable_phy(struct dra7xx_pcie *dra7xx)
328{ 336{
329 int phy_count = dra7xx->phy_count; 337 int phy_count = dra7xx->phy_count;
@@ -373,8 +381,9 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
373 struct phy **phy; 381 struct phy **phy;
374 void __iomem *base; 382 void __iomem *base;
375 struct resource *res; 383 struct resource *res;
376 struct dra7xx_pcie *dra7xx; 384 struct dw_pcie *pci;
377 struct pcie_port *pp; 385 struct pcie_port *pp;
386 struct dra7xx_pcie *dra7xx;
378 struct device *dev = &pdev->dev; 387 struct device *dev = &pdev->dev;
379 struct device_node *np = dev->of_node; 388 struct device_node *np = dev->of_node;
380 char name[10]; 389 char name[10];
@@ -384,8 +393,14 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
384 if (!dra7xx) 393 if (!dra7xx)
385 return -ENOMEM; 394 return -ENOMEM;
386 395
387 pp = &dra7xx->pp; 396 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
388 pp->dev = dev; 397 if (!pci)
398 return -ENOMEM;
399
400 pci->dev = dev;
401 pci->ops = &dw_pcie_ops;
402
403 pp = &pci->pp;
389 pp->ops = &dra7xx_pcie_host_ops; 404 pp->ops = &dra7xx_pcie_host_ops;
390 405
391 irq = platform_get_irq(pdev, 0); 406 irq = platform_get_irq(pdev, 0);
@@ -425,6 +440,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
425 440
426 dra7xx->base = base; 441 dra7xx->base = base;
427 dra7xx->phy = phy; 442 dra7xx->phy = phy;
443 dra7xx->pci = pci;
428 dra7xx->phy_count = phy_count; 444 dra7xx->phy_count = phy_count;
429 445
430 ret = dra7xx_pcie_enable_phy(dra7xx); 446 ret = dra7xx_pcie_enable_phy(dra7xx);
@@ -477,13 +493,13 @@ err_get_sync:
477static int dra7xx_pcie_suspend(struct device *dev) 493static int dra7xx_pcie_suspend(struct device *dev)
478{ 494{
479 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); 495 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
480 struct pcie_port *pp = &dra7xx->pp; 496 struct dw_pcie *pci = dra7xx->pci;
481 u32 val; 497 u32 val;
482 498
483 /* clear MSE */ 499 /* clear MSE */
484 val = dw_pcie_readl_rc(pp, PCI_COMMAND); 500 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
485 val &= ~PCI_COMMAND_MEMORY; 501 val &= ~PCI_COMMAND_MEMORY;
486 dw_pcie_writel_rc(pp, PCI_COMMAND, val); 502 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
487 503
488 return 0; 504 return 0;
489} 505}
@@ -491,13 +507,13 @@ static int dra7xx_pcie_suspend(struct device *dev)
491static int dra7xx_pcie_resume(struct device *dev) 507static int dra7xx_pcie_resume(struct device *dev)
492{ 508{
493 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev); 509 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
494 struct pcie_port *pp = &dra7xx->pp; 510 struct dw_pcie *pci = dra7xx->pci;
495 u32 val; 511 u32 val;
496 512
497 /* set MSE */ 513 /* set MSE */
498 val = dw_pcie_readl_rc(pp, PCI_COMMAND); 514 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
499 val |= PCI_COMMAND_MEMORY; 515 val |= PCI_COMMAND_MEMORY;
500 dw_pcie_writel_rc(pp, PCI_COMMAND, val); 516 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
501 517
502 return 0; 518 return 0;
503} 519}
diff --git a/drivers/pci/dwc/pci-exynos.c b/drivers/pci/dwc/pci-exynos.c
index e3fbff4d6de7..0295ec96f3d0 100644
--- a/drivers/pci/dwc/pci-exynos.c
+++ b/drivers/pci/dwc/pci-exynos.c
@@ -26,10 +26,10 @@
26 26
27#include "pcie-designware.h" 27#include "pcie-designware.h"
28 28
29#define to_exynos_pcie(x) container_of(x, struct exynos_pcie, pp) 29#define to_exynos_pcie(x) dev_get_drvdata((x)->dev)
30 30
31struct exynos_pcie { 31struct exynos_pcie {
32 struct pcie_port pp; 32 struct dw_pcie *pci;
33 void __iomem *elbi_base; /* DT 0th resource */ 33 void __iomem *elbi_base; /* DT 0th resource */
34 void __iomem *phy_base; /* DT 1st resource */ 34 void __iomem *phy_base; /* DT 1st resource */
35 void __iomem *block_base; /* DT 2nd resource */ 35 void __iomem *block_base; /* DT 2nd resource */
@@ -297,8 +297,8 @@ static void exynos_pcie_init_phy(struct exynos_pcie *exynos_pcie)
297 297
298static void exynos_pcie_assert_reset(struct exynos_pcie *exynos_pcie) 298static void exynos_pcie_assert_reset(struct exynos_pcie *exynos_pcie)
299{ 299{
300 struct pcie_port *pp = &exynos_pcie->pp; 300 struct dw_pcie *pci = exynos_pcie->pci;
301 struct device *dev = pp->dev; 301 struct device *dev = pci->dev;
302 302
303 if (exynos_pcie->reset_gpio >= 0) 303 if (exynos_pcie->reset_gpio >= 0)
304 devm_gpio_request_one(dev, exynos_pcie->reset_gpio, 304 devm_gpio_request_one(dev, exynos_pcie->reset_gpio,
@@ -307,11 +307,12 @@ static void exynos_pcie_assert_reset(struct exynos_pcie *exynos_pcie)
307 307
308static int exynos_pcie_establish_link(struct exynos_pcie *exynos_pcie) 308static int exynos_pcie_establish_link(struct exynos_pcie *exynos_pcie)
309{ 309{
310 struct pcie_port *pp = &exynos_pcie->pp; 310 struct dw_pcie *pci = exynos_pcie->pci;
311 struct device *dev = pp->dev; 311 struct pcie_port *pp = &pci->pp;
312 struct device *dev = pci->dev;
312 u32 val; 313 u32 val;
313 314
314 if (dw_pcie_link_up(pp)) { 315 if (dw_pcie_link_up(pci)) {
315 dev_err(dev, "Link already up\n"); 316 dev_err(dev, "Link already up\n");
316 return 0; 317 return 0;
317 } 318 }
@@ -336,7 +337,7 @@ static int exynos_pcie_establish_link(struct exynos_pcie *exynos_pcie)
336 PCIE_APP_LTSSM_ENABLE); 337 PCIE_APP_LTSSM_ENABLE);
337 338
338 /* check if the link is up or not */ 339 /* check if the link is up or not */
339 if (!dw_pcie_wait_for_link(pp)) 340 if (!dw_pcie_wait_for_link(pci))
340 return 0; 341 return 0;
341 342
342 while (exynos_phy_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED) == 0) { 343 while (exynos_phy_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED) == 0) {
@@ -376,14 +377,16 @@ static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg)
376static irqreturn_t exynos_pcie_msi_irq_handler(int irq, void *arg) 377static irqreturn_t exynos_pcie_msi_irq_handler(int irq, void *arg)
377{ 378{
378 struct exynos_pcie *exynos_pcie = arg; 379 struct exynos_pcie *exynos_pcie = arg;
379 struct pcie_port *pp = &exynos_pcie->pp; 380 struct dw_pcie *pci = exynos_pcie->pci;
381 struct pcie_port *pp = &pci->pp;
380 382
381 return dw_handle_msi_irq(pp); 383 return dw_handle_msi_irq(pp);
382} 384}
383 385
384static void exynos_pcie_msi_init(struct exynos_pcie *exynos_pcie) 386static void exynos_pcie_msi_init(struct exynos_pcie *exynos_pcie)
385{ 387{
386 struct pcie_port *pp = &exynos_pcie->pp; 388 struct dw_pcie *pci = exynos_pcie->pci;
389 struct pcie_port *pp = &pci->pp;
387 u32 val; 390 u32 val;
388 391
389 dw_pcie_msi_init(pp); 392 dw_pcie_msi_init(pp);
@@ -402,34 +405,35 @@ static void exynos_pcie_enable_interrupts(struct exynos_pcie *exynos_pcie)
402 exynos_pcie_msi_init(exynos_pcie); 405 exynos_pcie_msi_init(exynos_pcie);
403} 406}
404 407
405static u32 exynos_pcie_readl_rc(struct pcie_port *pp, u32 reg) 408static u32 exynos_pcie_readl_dbi(struct dw_pcie *pci, u32 reg)
406{ 409{
407 struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); 410 struct exynos_pcie *exynos_pcie = to_exynos_pcie(pci);
408 u32 val; 411 u32 val;
409 412
410 exynos_pcie_sideband_dbi_r_mode(exynos_pcie, true); 413 exynos_pcie_sideband_dbi_r_mode(exynos_pcie, true);
411 val = readl(pp->dbi_base + reg); 414 val = readl(pci->dbi_base + reg);
412 exynos_pcie_sideband_dbi_r_mode(exynos_pcie, false); 415 exynos_pcie_sideband_dbi_r_mode(exynos_pcie, false);
413 return val; 416 return val;
414} 417}
415 418
416static void exynos_pcie_writel_rc(struct pcie_port *pp, u32 reg, u32 val) 419static void exynos_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
417{ 420{
418 struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); 421 struct exynos_pcie *exynos_pcie = to_exynos_pcie(pci);
419 422
420 exynos_pcie_sideband_dbi_w_mode(exynos_pcie, true); 423 exynos_pcie_sideband_dbi_w_mode(exynos_pcie, true);
421 writel(val, pp->dbi_base + reg); 424 writel(val, pci->dbi_base + reg);
422 exynos_pcie_sideband_dbi_w_mode(exynos_pcie, false); 425 exynos_pcie_sideband_dbi_w_mode(exynos_pcie, false);
423} 426}
424 427
425static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, 428static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
426 u32 *val) 429 u32 *val)
427{ 430{
428 struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); 431 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
432 struct exynos_pcie *exynos_pcie = to_exynos_pcie(pci);
429 int ret; 433 int ret;
430 434
431 exynos_pcie_sideband_dbi_r_mode(exynos_pcie, true); 435 exynos_pcie_sideband_dbi_r_mode(exynos_pcie, true);
432 ret = dw_pcie_read(pp->dbi_base + where, size, val); 436 ret = dw_pcie_read(pci->dbi_base + where, size, val);
433 exynos_pcie_sideband_dbi_r_mode(exynos_pcie, false); 437 exynos_pcie_sideband_dbi_r_mode(exynos_pcie, false);
434 return ret; 438 return ret;
435} 439}
@@ -437,18 +441,19 @@ static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
437static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, 441static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
438 u32 val) 442 u32 val)
439{ 443{
440 struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); 444 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
445 struct exynos_pcie *exynos_pcie = to_exynos_pcie(pci);
441 int ret; 446 int ret;
442 447
443 exynos_pcie_sideband_dbi_w_mode(exynos_pcie, true); 448 exynos_pcie_sideband_dbi_w_mode(exynos_pcie, true);
444 ret = dw_pcie_write(pp->dbi_base + where, size, val); 449 ret = dw_pcie_write(pci->dbi_base + where, size, val);
445 exynos_pcie_sideband_dbi_w_mode(exynos_pcie, false); 450 exynos_pcie_sideband_dbi_w_mode(exynos_pcie, false);
446 return ret; 451 return ret;
447} 452}
448 453
449static int exynos_pcie_link_up(struct pcie_port *pp) 454static int exynos_pcie_link_up(struct dw_pcie *pci)
450{ 455{
451 struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); 456 struct exynos_pcie *exynos_pcie = to_exynos_pcie(pci);
452 u32 val; 457 u32 val;
453 458
454 val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_RDLH_LINKUP); 459 val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_RDLH_LINKUP);
@@ -460,26 +465,25 @@ static int exynos_pcie_link_up(struct pcie_port *pp)
460 465
461static void exynos_pcie_host_init(struct pcie_port *pp) 466static void exynos_pcie_host_init(struct pcie_port *pp)
462{ 467{
463 struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); 468 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
469 struct exynos_pcie *exynos_pcie = to_exynos_pcie(pci);
464 470
465 exynos_pcie_establish_link(exynos_pcie); 471 exynos_pcie_establish_link(exynos_pcie);
466 exynos_pcie_enable_interrupts(exynos_pcie); 472 exynos_pcie_enable_interrupts(exynos_pcie);
467} 473}
468 474
469static struct pcie_host_ops exynos_pcie_host_ops = { 475static struct dw_pcie_host_ops exynos_pcie_host_ops = {
470 .readl_rc = exynos_pcie_readl_rc,
471 .writel_rc = exynos_pcie_writel_rc,
472 .rd_own_conf = exynos_pcie_rd_own_conf, 476 .rd_own_conf = exynos_pcie_rd_own_conf,
473 .wr_own_conf = exynos_pcie_wr_own_conf, 477 .wr_own_conf = exynos_pcie_wr_own_conf,
474 .link_up = exynos_pcie_link_up,
475 .host_init = exynos_pcie_host_init, 478 .host_init = exynos_pcie_host_init,
476}; 479};
477 480
478static int __init exynos_add_pcie_port(struct exynos_pcie *exynos_pcie, 481static int __init exynos_add_pcie_port(struct exynos_pcie *exynos_pcie,
479 struct platform_device *pdev) 482 struct platform_device *pdev)
480{ 483{
481 struct pcie_port *pp = &exynos_pcie->pp; 484 struct dw_pcie *pci = exynos_pcie->pci;
482 struct device *dev = pp->dev; 485 struct pcie_port *pp = &pci->pp;
486 struct device *dev = &pdev->dev;
483 int ret; 487 int ret;
484 488
485 pp->irq = platform_get_irq(pdev, 1); 489 pp->irq = platform_get_irq(pdev, 1);
@@ -523,11 +527,17 @@ static int __init exynos_add_pcie_port(struct exynos_pcie *exynos_pcie,
523 return 0; 527 return 0;
524} 528}
525 529
530static const struct dw_pcie_ops dw_pcie_ops = {
531 .readl_dbi = exynos_pcie_readl_dbi,
532 .writel_dbi = exynos_pcie_writel_dbi,
533 .link_up = exynos_pcie_link_up,
534};
535
526static int __init exynos_pcie_probe(struct platform_device *pdev) 536static int __init exynos_pcie_probe(struct platform_device *pdev)
527{ 537{
528 struct device *dev = &pdev->dev; 538 struct device *dev = &pdev->dev;
539 struct dw_pcie *pci;
529 struct exynos_pcie *exynos_pcie; 540 struct exynos_pcie *exynos_pcie;
530 struct pcie_port *pp;
531 struct device_node *np = dev->of_node; 541 struct device_node *np = dev->of_node;
532 struct resource *elbi_base; 542 struct resource *elbi_base;
533 struct resource *phy_base; 543 struct resource *phy_base;
@@ -538,8 +548,12 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
538 if (!exynos_pcie) 548 if (!exynos_pcie)
539 return -ENOMEM; 549 return -ENOMEM;
540 550
541 pp = &exynos_pcie->pp; 551 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
542 pp->dev = dev; 552 if (!pci)
553 return -ENOMEM;
554
555 pci->dev = dev;
556 pci->ops = &dw_pcie_ops;
543 557
544 exynos_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0); 558 exynos_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
545 559
diff --git a/drivers/pci/dwc/pci-imx6.c b/drivers/pci/dwc/pci-imx6.c
index 6e5d06fb3b10..70fa380ea077 100644
--- a/drivers/pci/dwc/pci-imx6.c
+++ b/drivers/pci/dwc/pci-imx6.c
@@ -30,7 +30,7 @@
30 30
31#include "pcie-designware.h" 31#include "pcie-designware.h"
32 32
33#define to_imx6_pcie(x) container_of(x, struct imx6_pcie, pp) 33#define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
34 34
35enum imx6_pcie_variants { 35enum imx6_pcie_variants {
36 IMX6Q, 36 IMX6Q,
@@ -39,7 +39,7 @@ enum imx6_pcie_variants {
39}; 39};
40 40
41struct imx6_pcie { 41struct imx6_pcie {
42 struct pcie_port pp; /* pp.dbi_base is DT 0th resource */ 42 struct dw_pcie *pci;
43 int reset_gpio; 43 int reset_gpio;
44 bool gpio_active_high; 44 bool gpio_active_high;
45 struct clk *pcie_bus; 45 struct clk *pcie_bus;
@@ -97,13 +97,13 @@ struct imx6_pcie {
97 97
98static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val) 98static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val)
99{ 99{
100 struct pcie_port *pp = &imx6_pcie->pp; 100 struct dw_pcie *pci = imx6_pcie->pci;
101 u32 val; 101 u32 val;
102 u32 max_iterations = 10; 102 u32 max_iterations = 10;
103 u32 wait_counter = 0; 103 u32 wait_counter = 0;
104 104
105 do { 105 do {
106 val = dw_pcie_readl_rc(pp, PCIE_PHY_STAT); 106 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
107 val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1; 107 val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
108 wait_counter++; 108 wait_counter++;
109 109
@@ -118,22 +118,22 @@ static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val)
118 118
119static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr) 119static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
120{ 120{
121 struct pcie_port *pp = &imx6_pcie->pp; 121 struct dw_pcie *pci = imx6_pcie->pci;
122 u32 val; 122 u32 val;
123 int ret; 123 int ret;
124 124
125 val = addr << PCIE_PHY_CTRL_DATA_LOC; 125 val = addr << PCIE_PHY_CTRL_DATA_LOC;
126 dw_pcie_writel_rc(pp, PCIE_PHY_CTRL, val); 126 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
127 127
128 val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC); 128 val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
129 dw_pcie_writel_rc(pp, PCIE_PHY_CTRL, val); 129 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
130 130
131 ret = pcie_phy_poll_ack(imx6_pcie, 1); 131 ret = pcie_phy_poll_ack(imx6_pcie, 1);
132 if (ret) 132 if (ret)
133 return ret; 133 return ret;
134 134
135 val = addr << PCIE_PHY_CTRL_DATA_LOC; 135 val = addr << PCIE_PHY_CTRL_DATA_LOC;
136 dw_pcie_writel_rc(pp, PCIE_PHY_CTRL, val); 136 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
137 137
138 return pcie_phy_poll_ack(imx6_pcie, 0); 138 return pcie_phy_poll_ack(imx6_pcie, 0);
139} 139}
@@ -141,7 +141,7 @@ static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
141/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */ 141/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
142static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data) 142static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
143{ 143{
144 struct pcie_port *pp = &imx6_pcie->pp; 144 struct dw_pcie *pci = imx6_pcie->pci;
145 u32 val, phy_ctl; 145 u32 val, phy_ctl;
146 int ret; 146 int ret;
147 147
@@ -151,24 +151,24 @@ static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
151 151
152 /* assert Read signal */ 152 /* assert Read signal */
153 phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC; 153 phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
154 dw_pcie_writel_rc(pp, PCIE_PHY_CTRL, phy_ctl); 154 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl);
155 155
156 ret = pcie_phy_poll_ack(imx6_pcie, 1); 156 ret = pcie_phy_poll_ack(imx6_pcie, 1);
157 if (ret) 157 if (ret)
158 return ret; 158 return ret;
159 159
160 val = dw_pcie_readl_rc(pp, PCIE_PHY_STAT); 160 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
161 *data = val & 0xffff; 161 *data = val & 0xffff;
162 162
163 /* deassert Read signal */ 163 /* deassert Read signal */
164 dw_pcie_writel_rc(pp, PCIE_PHY_CTRL, 0x00); 164 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00);
165 165
166 return pcie_phy_poll_ack(imx6_pcie, 0); 166 return pcie_phy_poll_ack(imx6_pcie, 0);
167} 167}
168 168
169static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data) 169static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
170{ 170{
171 struct pcie_port *pp = &imx6_pcie->pp; 171 struct dw_pcie *pci = imx6_pcie->pci;
172 u32 var; 172 u32 var;
173 int ret; 173 int ret;
174 174
@@ -179,11 +179,11 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
179 return ret; 179 return ret;
180 180
181 var = data << PCIE_PHY_CTRL_DATA_LOC; 181 var = data << PCIE_PHY_CTRL_DATA_LOC;
182 dw_pcie_writel_rc(pp, PCIE_PHY_CTRL, var); 182 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
183 183
184 /* capture data */ 184 /* capture data */
185 var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC); 185 var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
186 dw_pcie_writel_rc(pp, PCIE_PHY_CTRL, var); 186 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
187 187
188 ret = pcie_phy_poll_ack(imx6_pcie, 1); 188 ret = pcie_phy_poll_ack(imx6_pcie, 1);
189 if (ret) 189 if (ret)
@@ -191,7 +191,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
191 191
192 /* deassert cap data */ 192 /* deassert cap data */
193 var = data << PCIE_PHY_CTRL_DATA_LOC; 193 var = data << PCIE_PHY_CTRL_DATA_LOC;
194 dw_pcie_writel_rc(pp, PCIE_PHY_CTRL, var); 194 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
195 195
196 /* wait for ack de-assertion */ 196 /* wait for ack de-assertion */
197 ret = pcie_phy_poll_ack(imx6_pcie, 0); 197 ret = pcie_phy_poll_ack(imx6_pcie, 0);
@@ -200,7 +200,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
200 200
201 /* assert wr signal */ 201 /* assert wr signal */
202 var = 0x1 << PCIE_PHY_CTRL_WR_LOC; 202 var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
203 dw_pcie_writel_rc(pp, PCIE_PHY_CTRL, var); 203 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
204 204
205 /* wait for ack */ 205 /* wait for ack */
206 ret = pcie_phy_poll_ack(imx6_pcie, 1); 206 ret = pcie_phy_poll_ack(imx6_pcie, 1);
@@ -209,14 +209,14 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
209 209
210 /* deassert wr signal */ 210 /* deassert wr signal */
211 var = data << PCIE_PHY_CTRL_DATA_LOC; 211 var = data << PCIE_PHY_CTRL_DATA_LOC;
212 dw_pcie_writel_rc(pp, PCIE_PHY_CTRL, var); 212 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
213 213
214 /* wait for ack de-assertion */ 214 /* wait for ack de-assertion */
215 ret = pcie_phy_poll_ack(imx6_pcie, 0); 215 ret = pcie_phy_poll_ack(imx6_pcie, 0);
216 if (ret) 216 if (ret)
217 return ret; 217 return ret;
218 218
219 dw_pcie_writel_rc(pp, PCIE_PHY_CTRL, 0x0); 219 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0);
220 220
221 return 0; 221 return 0;
222} 222}
@@ -247,7 +247,7 @@ static int imx6q_pcie_abort_handler(unsigned long addr,
247 247
248static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) 248static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
249{ 249{
250 struct pcie_port *pp = &imx6_pcie->pp; 250 struct dw_pcie *pci = imx6_pcie->pci;
251 u32 val, gpr1, gpr12; 251 u32 val, gpr1, gpr12;
252 252
253 switch (imx6_pcie->variant) { 253 switch (imx6_pcie->variant) {
@@ -284,10 +284,10 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
284 284
285 if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) && 285 if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) &&
286 (gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) { 286 (gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) {
287 val = dw_pcie_readl_rc(pp, PCIE_PL_PFLR); 287 val = dw_pcie_readl_dbi(pci, PCIE_PL_PFLR);
288 val &= ~PCIE_PL_PFLR_LINK_STATE_MASK; 288 val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
289 val |= PCIE_PL_PFLR_FORCE_LINK; 289 val |= PCIE_PL_PFLR_FORCE_LINK;
290 dw_pcie_writel_rc(pp, PCIE_PL_PFLR, val); 290 dw_pcie_writel_dbi(pci, PCIE_PL_PFLR, val);
291 291
292 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 292 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
293 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); 293 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
@@ -303,8 +303,8 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
303 303
304static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) 304static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
305{ 305{
306 struct pcie_port *pp = &imx6_pcie->pp; 306 struct dw_pcie *pci = imx6_pcie->pci;
307 struct device *dev = pp->dev; 307 struct device *dev = pci->dev;
308 int ret = 0; 308 int ret = 0;
309 309
310 switch (imx6_pcie->variant) { 310 switch (imx6_pcie->variant) {
@@ -340,8 +340,8 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
340 340
341static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) 341static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
342{ 342{
343 struct pcie_port *pp = &imx6_pcie->pp; 343 struct dw_pcie *pci = imx6_pcie->pci;
344 struct device *dev = pp->dev; 344 struct device *dev = pci->dev;
345 int ret; 345 int ret;
346 346
347 ret = clk_prepare_enable(imx6_pcie->pcie_phy); 347 ret = clk_prepare_enable(imx6_pcie->pcie_phy);
@@ -440,28 +440,28 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
440 440
441static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie) 441static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie)
442{ 442{
443 struct pcie_port *pp = &imx6_pcie->pp; 443 struct dw_pcie *pci = imx6_pcie->pci;
444 struct device *dev = pp->dev; 444 struct device *dev = pci->dev;
445 445
446 /* check if the link is up or not */ 446 /* check if the link is up or not */
447 if (!dw_pcie_wait_for_link(pp)) 447 if (!dw_pcie_wait_for_link(pci))
448 return 0; 448 return 0;
449 449
450 dev_dbg(dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", 450 dev_dbg(dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
451 dw_pcie_readl_rc(pp, PCIE_PHY_DEBUG_R0), 451 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
452 dw_pcie_readl_rc(pp, PCIE_PHY_DEBUG_R1)); 452 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
453 return -ETIMEDOUT; 453 return -ETIMEDOUT;
454} 454}
455 455
456static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie) 456static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
457{ 457{
458 struct pcie_port *pp = &imx6_pcie->pp; 458 struct dw_pcie *pci = imx6_pcie->pci;
459 struct device *dev = pp->dev; 459 struct device *dev = pci->dev;
460 u32 tmp; 460 u32 tmp;
461 unsigned int retries; 461 unsigned int retries;
462 462
463 for (retries = 0; retries < 200; retries++) { 463 for (retries = 0; retries < 200; retries++) {
464 tmp = dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL); 464 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
465 /* Test if the speed change finished. */ 465 /* Test if the speed change finished. */
466 if (!(tmp & PORT_LOGIC_SPEED_CHANGE)) 466 if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
467 return 0; 467 return 0;
@@ -475,15 +475,16 @@ static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
475static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg) 475static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg)
476{ 476{
477 struct imx6_pcie *imx6_pcie = arg; 477 struct imx6_pcie *imx6_pcie = arg;
478 struct pcie_port *pp = &imx6_pcie->pp; 478 struct dw_pcie *pci = imx6_pcie->pci;
479 struct pcie_port *pp = &pci->pp;
479 480
480 return dw_handle_msi_irq(pp); 481 return dw_handle_msi_irq(pp);
481} 482}
482 483
483static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie) 484static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
484{ 485{
485 struct pcie_port *pp = &imx6_pcie->pp; 486 struct dw_pcie *pci = imx6_pcie->pci;
486 struct device *dev = pp->dev; 487 struct device *dev = pci->dev;
487 u32 tmp; 488 u32 tmp;
488 int ret; 489 int ret;
489 490
@@ -492,10 +493,10 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
492 * started in Gen2 mode, there is a possibility the devices on the 493 * started in Gen2 mode, there is a possibility the devices on the
493 * bus will not be detected at all. This happens with PCIe switches. 494 * bus will not be detected at all. This happens with PCIe switches.
494 */ 495 */
495 tmp = dw_pcie_readl_rc(pp, PCIE_RC_LCR); 496 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR);
496 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; 497 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
497 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1; 498 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
498 dw_pcie_writel_rc(pp, PCIE_RC_LCR, tmp); 499 dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp);
499 500
500 /* Start LTSSM. */ 501 /* Start LTSSM. */
501 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 502 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
@@ -509,10 +510,10 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
509 510
510 if (imx6_pcie->link_gen == 2) { 511 if (imx6_pcie->link_gen == 2) {
511 /* Allow Gen2 mode after the link is up. */ 512 /* Allow Gen2 mode after the link is up. */
512 tmp = dw_pcie_readl_rc(pp, PCIE_RC_LCR); 513 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR);
513 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; 514 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
514 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2; 515 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
515 dw_pcie_writel_rc(pp, PCIE_RC_LCR, tmp); 516 dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp);
516 } else { 517 } else {
517 dev_info(dev, "Link: Gen2 disabled\n"); 518 dev_info(dev, "Link: Gen2 disabled\n");
518 } 519 }
@@ -521,9 +522,9 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
521 * Start Directed Speed Change so the best possible speed both link 522 * Start Directed Speed Change so the best possible speed both link
522 * partners support can be negotiated. 523 * partners support can be negotiated.
523 */ 524 */
524 tmp = dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL); 525 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
525 tmp |= PORT_LOGIC_SPEED_CHANGE; 526 tmp |= PORT_LOGIC_SPEED_CHANGE;
526 dw_pcie_writel_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); 527 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
527 528
528 ret = imx6_pcie_wait_for_speed_change(imx6_pcie); 529 ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
529 if (ret) { 530 if (ret) {
@@ -538,21 +539,22 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
538 goto err_reset_phy; 539 goto err_reset_phy;
539 } 540 }
540 541
541 tmp = dw_pcie_readl_rc(pp, PCIE_RC_LCSR); 542 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCSR);
542 dev_info(dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf); 543 dev_info(dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf);
543 return 0; 544 return 0;
544 545
545err_reset_phy: 546err_reset_phy:
546 dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n", 547 dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
547 dw_pcie_readl_rc(pp, PCIE_PHY_DEBUG_R0), 548 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
548 dw_pcie_readl_rc(pp, PCIE_PHY_DEBUG_R1)); 549 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
549 imx6_pcie_reset_phy(imx6_pcie); 550 imx6_pcie_reset_phy(imx6_pcie);
550 return ret; 551 return ret;
551} 552}
552 553
553static void imx6_pcie_host_init(struct pcie_port *pp) 554static void imx6_pcie_host_init(struct pcie_port *pp)
554{ 555{
555 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); 556 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
557 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
556 558
557 imx6_pcie_assert_core_reset(imx6_pcie); 559 imx6_pcie_assert_core_reset(imx6_pcie);
558 imx6_pcie_init_phy(imx6_pcie); 560 imx6_pcie_init_phy(imx6_pcie);
@@ -564,22 +566,22 @@ static void imx6_pcie_host_init(struct pcie_port *pp)
564 dw_pcie_msi_init(pp); 566 dw_pcie_msi_init(pp);
565} 567}
566 568
567static int imx6_pcie_link_up(struct pcie_port *pp) 569static int imx6_pcie_link_up(struct dw_pcie *pci)
568{ 570{
569 return dw_pcie_readl_rc(pp, PCIE_PHY_DEBUG_R1) & 571 return dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1) &
570 PCIE_PHY_DEBUG_R1_XMLH_LINK_UP; 572 PCIE_PHY_DEBUG_R1_XMLH_LINK_UP;
571} 573}
572 574
573static struct pcie_host_ops imx6_pcie_host_ops = { 575static struct dw_pcie_host_ops imx6_pcie_host_ops = {
574 .link_up = imx6_pcie_link_up,
575 .host_init = imx6_pcie_host_init, 576 .host_init = imx6_pcie_host_init,
576}; 577};
577 578
578static int __init imx6_add_pcie_port(struct imx6_pcie *imx6_pcie, 579static int __init imx6_add_pcie_port(struct imx6_pcie *imx6_pcie,
579 struct platform_device *pdev) 580 struct platform_device *pdev)
580{ 581{
581 struct pcie_port *pp = &imx6_pcie->pp; 582 struct dw_pcie *pci = imx6_pcie->pci;
582 struct device *dev = pp->dev; 583 struct pcie_port *pp = &pci->pp;
584 struct device *dev = &pdev->dev;
583 int ret; 585 int ret;
584 586
585 if (IS_ENABLED(CONFIG_PCI_MSI)) { 587 if (IS_ENABLED(CONFIG_PCI_MSI)) {
@@ -611,11 +613,15 @@ static int __init imx6_add_pcie_port(struct imx6_pcie *imx6_pcie,
611 return 0; 613 return 0;
612} 614}
613 615
616static const struct dw_pcie_ops dw_pcie_ops = {
617 .link_up = imx6_pcie_link_up,
618};
619
614static int __init imx6_pcie_probe(struct platform_device *pdev) 620static int __init imx6_pcie_probe(struct platform_device *pdev)
615{ 621{
616 struct device *dev = &pdev->dev; 622 struct device *dev = &pdev->dev;
623 struct dw_pcie *pci;
617 struct imx6_pcie *imx6_pcie; 624 struct imx6_pcie *imx6_pcie;
618 struct pcie_port *pp;
619 struct resource *dbi_base; 625 struct resource *dbi_base;
620 struct device_node *node = dev->of_node; 626 struct device_node *node = dev->of_node;
621 int ret; 627 int ret;
@@ -624,8 +630,12 @@ static int __init imx6_pcie_probe(struct platform_device *pdev)
624 if (!imx6_pcie) 630 if (!imx6_pcie)
625 return -ENOMEM; 631 return -ENOMEM;
626 632
627 pp = &imx6_pcie->pp; 633 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
628 pp->dev = dev; 634 if (!pci)
635 return -ENOMEM;
636
637 pci->dev = dev;
638 pci->ops = &dw_pcie_ops;
629 639
630 imx6_pcie->variant = 640 imx6_pcie->variant =
631 (enum imx6_pcie_variants)of_device_get_match_data(dev); 641 (enum imx6_pcie_variants)of_device_get_match_data(dev);
@@ -635,9 +645,9 @@ static int __init imx6_pcie_probe(struct platform_device *pdev)
635 "imprecise external abort"); 645 "imprecise external abort");
636 646
637 dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); 647 dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
638 pp->dbi_base = devm_ioremap_resource(dev, dbi_base); 648 pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
639 if (IS_ERR(pp->dbi_base)) 649 if (IS_ERR(pci->dbi_base))
640 return PTR_ERR(pp->dbi_base); 650 return PTR_ERR(pci->dbi_base);
641 651
642 /* Fetch GPIOs */ 652 /* Fetch GPIOs */
643 imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0); 653 imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
diff --git a/drivers/pci/dwc/pci-keystone-dw.c b/drivers/pci/dwc/pci-keystone-dw.c
index 48753345adc7..6b396f6b4615 100644
--- a/drivers/pci/dwc/pci-keystone-dw.c
+++ b/drivers/pci/dwc/pci-keystone-dw.c
@@ -72,7 +72,7 @@
72/* Config space registers */ 72/* Config space registers */
73#define DEBUG0 0x728 73#define DEBUG0 0x728
74 74
75#define to_keystone_pcie(x) container_of(x, struct keystone_pcie, pp) 75#define to_keystone_pcie(x) dev_get_drvdata((x)->dev)
76 76
77static inline void update_reg_offset_bit_pos(u32 offset, u32 *reg_offset, 77static inline void update_reg_offset_bit_pos(u32 offset, u32 *reg_offset,
78 u32 *bit_pos) 78 u32 *bit_pos)
@@ -83,7 +83,8 @@ static inline void update_reg_offset_bit_pos(u32 offset, u32 *reg_offset,
83 83
84phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp) 84phys_addr_t ks_dw_pcie_get_msi_addr(struct pcie_port *pp)
85{ 85{
86 struct keystone_pcie *ks_pcie = to_keystone_pcie(pp); 86 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
87 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
87 88
88 return ks_pcie->app.start + MSI_IRQ; 89 return ks_pcie->app.start + MSI_IRQ;
89} 90}
@@ -100,8 +101,9 @@ static void ks_dw_app_writel(struct keystone_pcie *ks_pcie, u32 offset, u32 val)
100 101
101void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset) 102void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset)
102{ 103{
103 struct pcie_port *pp = &ks_pcie->pp; 104 struct dw_pcie *pci = ks_pcie->pci;
104 struct device *dev = pp->dev; 105 struct pcie_port *pp = &pci->pp;
106 struct device *dev = pci->dev;
105 u32 pending, vector; 107 u32 pending, vector;
106 int src, virq; 108 int src, virq;
107 109
@@ -128,10 +130,12 @@ static void ks_dw_pcie_msi_irq_ack(struct irq_data *d)
128 struct keystone_pcie *ks_pcie; 130 struct keystone_pcie *ks_pcie;
129 struct msi_desc *msi; 131 struct msi_desc *msi;
130 struct pcie_port *pp; 132 struct pcie_port *pp;
133 struct dw_pcie *pci;
131 134
132 msi = irq_data_get_msi_desc(d); 135 msi = irq_data_get_msi_desc(d);
133 pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi); 136 pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
134 ks_pcie = to_keystone_pcie(pp); 137 pci = to_dw_pcie_from_pp(pp);
138 ks_pcie = to_keystone_pcie(pci);
135 offset = d->irq - irq_linear_revmap(pp->irq_domain, 0); 139 offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
136 update_reg_offset_bit_pos(offset, &reg_offset, &bit_pos); 140 update_reg_offset_bit_pos(offset, &reg_offset, &bit_pos);
137 141
@@ -143,7 +147,8 @@ static void ks_dw_pcie_msi_irq_ack(struct irq_data *d)
143void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq) 147void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
144{ 148{
145 u32 reg_offset, bit_pos; 149 u32 reg_offset, bit_pos;
146 struct keystone_pcie *ks_pcie = to_keystone_pcie(pp); 150 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
151 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
147 152
148 update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos); 153 update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
149 ks_dw_app_writel(ks_pcie, MSI0_IRQ_ENABLE_SET + (reg_offset << 4), 154 ks_dw_app_writel(ks_pcie, MSI0_IRQ_ENABLE_SET + (reg_offset << 4),
@@ -153,7 +158,8 @@ void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
153void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq) 158void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
154{ 159{
155 u32 reg_offset, bit_pos; 160 u32 reg_offset, bit_pos;
156 struct keystone_pcie *ks_pcie = to_keystone_pcie(pp); 161 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
162 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
157 163
158 update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos); 164 update_reg_offset_bit_pos(irq, &reg_offset, &bit_pos);
159 ks_dw_app_writel(ks_pcie, MSI0_IRQ_ENABLE_CLR + (reg_offset << 4), 165 ks_dw_app_writel(ks_pcie, MSI0_IRQ_ENABLE_CLR + (reg_offset << 4),
@@ -165,11 +171,13 @@ static void ks_dw_pcie_msi_irq_mask(struct irq_data *d)
165 struct keystone_pcie *ks_pcie; 171 struct keystone_pcie *ks_pcie;
166 struct msi_desc *msi; 172 struct msi_desc *msi;
167 struct pcie_port *pp; 173 struct pcie_port *pp;
174 struct dw_pcie *pci;
168 u32 offset; 175 u32 offset;
169 176
170 msi = irq_data_get_msi_desc(d); 177 msi = irq_data_get_msi_desc(d);
171 pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi); 178 pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
172 ks_pcie = to_keystone_pcie(pp); 179 pci = to_dw_pcie_from_pp(pp);
180 ks_pcie = to_keystone_pcie(pci);
173 offset = d->irq - irq_linear_revmap(pp->irq_domain, 0); 181 offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
174 182
175 /* Mask the end point if PVM implemented */ 183 /* Mask the end point if PVM implemented */
@@ -186,11 +194,13 @@ static void ks_dw_pcie_msi_irq_unmask(struct irq_data *d)
186 struct keystone_pcie *ks_pcie; 194 struct keystone_pcie *ks_pcie;
187 struct msi_desc *msi; 195 struct msi_desc *msi;
188 struct pcie_port *pp; 196 struct pcie_port *pp;
197 struct dw_pcie *pci;
189 u32 offset; 198 u32 offset;
190 199
191 msi = irq_data_get_msi_desc(d); 200 msi = irq_data_get_msi_desc(d);
192 pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi); 201 pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
193 ks_pcie = to_keystone_pcie(pp); 202 pci = to_dw_pcie_from_pp(pp);
203 ks_pcie = to_keystone_pcie(pci);
194 offset = d->irq - irq_linear_revmap(pp->irq_domain, 0); 204 offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
195 205
196 /* Mask the end point if PVM implemented */ 206 /* Mask the end point if PVM implemented */
@@ -225,8 +235,9 @@ static const struct irq_domain_ops ks_dw_pcie_msi_domain_ops = {
225 235
226int ks_dw_pcie_msi_host_init(struct pcie_port *pp, struct msi_controller *chip) 236int ks_dw_pcie_msi_host_init(struct pcie_port *pp, struct msi_controller *chip)
227{ 237{
228 struct keystone_pcie *ks_pcie = to_keystone_pcie(pp); 238 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
229 struct device *dev = pp->dev; 239 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
240 struct device *dev = pci->dev;
230 int i; 241 int i;
231 242
232 pp->irq_domain = irq_domain_add_linear(ks_pcie->msi_intc_np, 243 pp->irq_domain = irq_domain_add_linear(ks_pcie->msi_intc_np,
@@ -254,8 +265,8 @@ void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie)
254 265
255void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset) 266void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset)
256{ 267{
257 struct pcie_port *pp = &ks_pcie->pp; 268 struct dw_pcie *pci = ks_pcie->pci;
258 struct device *dev = pp->dev; 269 struct device *dev = pci->dev;
259 u32 pending; 270 u32 pending;
260 int virq; 271 int virq;
261 272
@@ -285,7 +296,7 @@ irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *ks_pcie)
285 return IRQ_NONE; 296 return IRQ_NONE;
286 297
287 if (status & ERR_FATAL_IRQ) 298 if (status & ERR_FATAL_IRQ)
288 dev_err(ks_pcie->pp.dev, "fatal error (status %#010x)\n", 299 dev_err(ks_pcie->pci->dev, "fatal error (status %#010x)\n",
289 status); 300 status);
290 301
291 /* Ack the IRQ; status bits are RW1C */ 302 /* Ack the IRQ; status bits are RW1C */
@@ -366,15 +377,16 @@ static void ks_dw_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie)
366 377
367void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) 378void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
368{ 379{
369 struct pcie_port *pp = &ks_pcie->pp; 380 struct dw_pcie *pci = ks_pcie->pci;
381 struct pcie_port *pp = &pci->pp;
370 u32 start = pp->mem->start, end = pp->mem->end; 382 u32 start = pp->mem->start, end = pp->mem->end;
371 int i, tr_size; 383 int i, tr_size;
372 u32 val; 384 u32 val;
373 385
374 /* Disable BARs for inbound access */ 386 /* Disable BARs for inbound access */
375 ks_dw_pcie_set_dbi_mode(ks_pcie); 387 ks_dw_pcie_set_dbi_mode(ks_pcie);
376 dw_pcie_writel_rc(pp, PCI_BASE_ADDRESS_0, 0); 388 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
377 dw_pcie_writel_rc(pp, PCI_BASE_ADDRESS_1, 0); 389 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0);
378 ks_dw_pcie_clear_dbi_mode(ks_pcie); 390 ks_dw_pcie_clear_dbi_mode(ks_pcie);
379 391
380 /* Set outbound translation size per window division */ 392 /* Set outbound translation size per window division */
@@ -415,11 +427,12 @@ static void __iomem *ks_pcie_cfg_setup(struct keystone_pcie *ks_pcie, u8 bus,
415 unsigned int devfn) 427 unsigned int devfn)
416{ 428{
417 u8 device = PCI_SLOT(devfn), function = PCI_FUNC(devfn); 429 u8 device = PCI_SLOT(devfn), function = PCI_FUNC(devfn);
418 struct pcie_port *pp = &ks_pcie->pp; 430 struct dw_pcie *pci = ks_pcie->pci;
431 struct pcie_port *pp = &pci->pp;
419 u32 regval; 432 u32 regval;
420 433
421 if (bus == 0) 434 if (bus == 0)
422 return pp->dbi_base; 435 return pci->dbi_base;
423 436
424 regval = (bus << 16) | (device << 8) | function; 437 regval = (bus << 16) | (device << 8) | function;
425 438
@@ -438,7 +451,8 @@ static void __iomem *ks_pcie_cfg_setup(struct keystone_pcie *ks_pcie, u8 bus,
438int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, 451int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
439 unsigned int devfn, int where, int size, u32 *val) 452 unsigned int devfn, int where, int size, u32 *val)
440{ 453{
441 struct keystone_pcie *ks_pcie = to_keystone_pcie(pp); 454 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
455 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
442 u8 bus_num = bus->number; 456 u8 bus_num = bus->number;
443 void __iomem *addr; 457 void __iomem *addr;
444 458
@@ -450,7 +464,8 @@ int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
450int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, 464int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
451 unsigned int devfn, int where, int size, u32 val) 465 unsigned int devfn, int where, int size, u32 val)
452{ 466{
453 struct keystone_pcie *ks_pcie = to_keystone_pcie(pp); 467 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
468 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
454 u8 bus_num = bus->number; 469 u8 bus_num = bus->number;
455 void __iomem *addr; 470 void __iomem *addr;
456 471
@@ -466,14 +481,15 @@ int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
466 */ 481 */
467void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp) 482void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
468{ 483{
469 struct keystone_pcie *ks_pcie = to_keystone_pcie(pp); 484 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
485 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
470 486
471 /* Configure and set up BAR0 */ 487 /* Configure and set up BAR0 */
472 ks_dw_pcie_set_dbi_mode(ks_pcie); 488 ks_dw_pcie_set_dbi_mode(ks_pcie);
473 489
474 /* Enable BAR0 */ 490 /* Enable BAR0 */
475 dw_pcie_writel_rc(pp, PCI_BASE_ADDRESS_0, 1); 491 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1);
476 dw_pcie_writel_rc(pp, PCI_BASE_ADDRESS_0, SZ_4K - 1); 492 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1);
477 493
478 ks_dw_pcie_clear_dbi_mode(ks_pcie); 494 ks_dw_pcie_clear_dbi_mode(ks_pcie);
479 495
@@ -481,17 +497,17 @@ void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp)
481 * For BAR0, just setting bus address for inbound writes (MSI) should 497 * For BAR0, just setting bus address for inbound writes (MSI) should
482 * be sufficient. Use physical address to avoid any conflicts. 498 * be sufficient. Use physical address to avoid any conflicts.
483 */ 499 */
484 dw_pcie_writel_rc(pp, PCI_BASE_ADDRESS_0, ks_pcie->app.start); 500 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start);
485} 501}
486 502
487/** 503/**
488 * ks_dw_pcie_link_up() - Check if link up 504 * ks_dw_pcie_link_up() - Check if link up
489 */ 505 */
490int ks_dw_pcie_link_up(struct pcie_port *pp) 506int ks_dw_pcie_link_up(struct dw_pcie *pci)
491{ 507{
492 u32 val; 508 u32 val;
493 509
494 val = dw_pcie_readl_rc(pp, DEBUG0); 510 val = dw_pcie_readl_dbi(pci, DEBUG0);
495 return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0; 511 return (val & LTSSM_STATE_MASK) == LTSSM_STATE_L0;
496} 512}
497 513
@@ -519,22 +535,23 @@ void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie)
519int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie, 535int __init ks_dw_pcie_host_init(struct keystone_pcie *ks_pcie,
520 struct device_node *msi_intc_np) 536 struct device_node *msi_intc_np)
521{ 537{
522 struct pcie_port *pp = &ks_pcie->pp; 538 struct dw_pcie *pci = ks_pcie->pci;
523 struct device *dev = pp->dev; 539 struct pcie_port *pp = &pci->pp;
540 struct device *dev = pci->dev;
524 struct platform_device *pdev = to_platform_device(dev); 541 struct platform_device *pdev = to_platform_device(dev);
525 struct resource *res; 542 struct resource *res;
526 543
527 /* Index 0 is the config reg. space address */ 544 /* Index 0 is the config reg. space address */
528 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 545 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
529 pp->dbi_base = devm_ioremap_resource(dev, res); 546 pci->dbi_base = devm_ioremap_resource(dev, res);
530 if (IS_ERR(pp->dbi_base)) 547 if (IS_ERR(pci->dbi_base))
531 return PTR_ERR(pp->dbi_base); 548 return PTR_ERR(pci->dbi_base);
532 549
533 /* 550 /*
534 * We set these same and is used in pcie rd/wr_other_conf 551 * We set these same and is used in pcie rd/wr_other_conf
535 * functions 552 * functions
536 */ 553 */
537 pp->va_cfg0_base = pp->dbi_base + SPACE0_REMOTE_CFG_OFFSET; 554 pp->va_cfg0_base = pci->dbi_base + SPACE0_REMOTE_CFG_OFFSET;
538 pp->va_cfg1_base = pp->va_cfg0_base; 555 pp->va_cfg1_base = pp->va_cfg0_base;
539 556
540 /* Index 1 is the application reg. space address */ 557 /* Index 1 is the application reg. space address */
diff --git a/drivers/pci/dwc/pci-keystone.c b/drivers/pci/dwc/pci-keystone.c
index 4c7ba3583450..8dc66409182d 100644
--- a/drivers/pci/dwc/pci-keystone.c
+++ b/drivers/pci/dwc/pci-keystone.c
@@ -44,7 +44,7 @@
44#define PCIE_RC_K2E 0xb009 44#define PCIE_RC_K2E 0xb009
45#define PCIE_RC_K2L 0xb00a 45#define PCIE_RC_K2L 0xb00a
46 46
47#define to_keystone_pcie(x) container_of(x, struct keystone_pcie, pp) 47#define to_keystone_pcie(x) dev_get_drvdata((x)->dev)
48 48
49static void quirk_limit_mrrs(struct pci_dev *dev) 49static void quirk_limit_mrrs(struct pci_dev *dev)
50{ 50{
@@ -88,13 +88,14 @@ DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, quirk_limit_mrrs);
88 88
89static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie) 89static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
90{ 90{
91 struct pcie_port *pp = &ks_pcie->pp; 91 struct dw_pcie *pci = ks_pcie->pci;
92 struct device *dev = pp->dev; 92 struct pcie_port *pp = &pci->pp;
93 struct device *dev = pci->dev;
93 unsigned int retries; 94 unsigned int retries;
94 95
95 dw_pcie_setup_rc(pp); 96 dw_pcie_setup_rc(pp);
96 97
97 if (dw_pcie_link_up(pp)) { 98 if (dw_pcie_link_up(pci)) {
98 dev_err(dev, "Link already up\n"); 99 dev_err(dev, "Link already up\n");
99 return 0; 100 return 0;
100 } 101 }
@@ -102,7 +103,7 @@ static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
102 /* check if the link is up or not */ 103 /* check if the link is up or not */
103 for (retries = 0; retries < 5; retries++) { 104 for (retries = 0; retries < 5; retries++) {
104 ks_dw_pcie_initiate_link_train(ks_pcie); 105 ks_dw_pcie_initiate_link_train(ks_pcie);
105 if (!dw_pcie_wait_for_link(pp)) 106 if (!dw_pcie_wait_for_link(pci))
106 return 0; 107 return 0;
107 } 108 }
108 109
@@ -115,8 +116,8 @@ static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
115 unsigned int irq = irq_desc_get_irq(desc); 116 unsigned int irq = irq_desc_get_irq(desc);
116 struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc); 117 struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
117 u32 offset = irq - ks_pcie->msi_host_irqs[0]; 118 u32 offset = irq - ks_pcie->msi_host_irqs[0];
118 struct pcie_port *pp = &ks_pcie->pp; 119 struct dw_pcie *pci = ks_pcie->pci;
119 struct device *dev = pp->dev; 120 struct device *dev = pci->dev;
120 struct irq_chip *chip = irq_desc_get_chip(desc); 121 struct irq_chip *chip = irq_desc_get_chip(desc);
121 122
122 dev_dbg(dev, "%s, irq %d\n", __func__, irq); 123 dev_dbg(dev, "%s, irq %d\n", __func__, irq);
@@ -143,8 +144,8 @@ static void ks_pcie_legacy_irq_handler(struct irq_desc *desc)
143{ 144{
144 unsigned int irq = irq_desc_get_irq(desc); 145 unsigned int irq = irq_desc_get_irq(desc);
145 struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc); 146 struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
146 struct pcie_port *pp = &ks_pcie->pp; 147 struct dw_pcie *pci = ks_pcie->pci;
147 struct device *dev = pp->dev; 148 struct device *dev = pci->dev;
148 u32 irq_offset = irq - ks_pcie->legacy_host_irqs[0]; 149 u32 irq_offset = irq - ks_pcie->legacy_host_irqs[0];
149 struct irq_chip *chip = irq_desc_get_chip(desc); 150 struct irq_chip *chip = irq_desc_get_chip(desc);
150 151
@@ -164,7 +165,7 @@ static int ks_pcie_get_irq_controller_info(struct keystone_pcie *ks_pcie,
164 char *controller, int *num_irqs) 165 char *controller, int *num_irqs)
165{ 166{
166 int temp, max_host_irqs, legacy = 1, *host_irqs; 167 int temp, max_host_irqs, legacy = 1, *host_irqs;
167 struct device *dev = ks_pcie->pp.dev; 168 struct device *dev = ks_pcie->pci->dev;
168 struct device_node *np_pcie = dev->of_node, **np_temp; 169 struct device_node *np_pcie = dev->of_node, **np_temp;
169 170
170 if (!strcmp(controller, "msi-interrupt-controller")) 171 if (!strcmp(controller, "msi-interrupt-controller"))
@@ -262,24 +263,25 @@ static int keystone_pcie_fault(unsigned long addr, unsigned int fsr,
262 263
263static void __init ks_pcie_host_init(struct pcie_port *pp) 264static void __init ks_pcie_host_init(struct pcie_port *pp)
264{ 265{
265 struct keystone_pcie *ks_pcie = to_keystone_pcie(pp); 266 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
267 struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
266 u32 val; 268 u32 val;
267 269
268 ks_pcie_establish_link(ks_pcie); 270 ks_pcie_establish_link(ks_pcie);
269 ks_dw_pcie_setup_rc_app_regs(ks_pcie); 271 ks_dw_pcie_setup_rc_app_regs(ks_pcie);
270 ks_pcie_setup_interrupts(ks_pcie); 272 ks_pcie_setup_interrupts(ks_pcie);
271 writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8), 273 writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8),
272 pp->dbi_base + PCI_IO_BASE); 274 pci->dbi_base + PCI_IO_BASE);
273 275
274 /* update the Vendor ID */ 276 /* update the Vendor ID */
275 writew(ks_pcie->device_id, pp->dbi_base + PCI_DEVICE_ID); 277 writew(ks_pcie->device_id, pci->dbi_base + PCI_DEVICE_ID);
276 278
277 /* update the DEV_STAT_CTRL to publish right mrrs */ 279 /* update the DEV_STAT_CTRL to publish right mrrs */
278 val = readl(pp->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL); 280 val = readl(pci->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);
279 val &= ~PCI_EXP_DEVCTL_READRQ; 281 val &= ~PCI_EXP_DEVCTL_READRQ;
280 /* set the mrrs to 256 bytes */ 282 /* set the mrrs to 256 bytes */
281 val |= BIT(12); 283 val |= BIT(12);
282 writel(val, pp->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL); 284 writel(val, pci->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);
283 285
284 /* 286 /*
285 * PCIe access errors that result into OCP errors are caught by ARM as 287 * PCIe access errors that result into OCP errors are caught by ARM as
@@ -289,10 +291,9 @@ static void __init ks_pcie_host_init(struct pcie_port *pp)
289 "Asynchronous external abort"); 291 "Asynchronous external abort");
290} 292}
291 293
292static struct pcie_host_ops keystone_pcie_host_ops = { 294static struct dw_pcie_host_ops keystone_pcie_host_ops = {
293 .rd_other_conf = ks_dw_pcie_rd_other_conf, 295 .rd_other_conf = ks_dw_pcie_rd_other_conf,
294 .wr_other_conf = ks_dw_pcie_wr_other_conf, 296 .wr_other_conf = ks_dw_pcie_wr_other_conf,
295 .link_up = ks_dw_pcie_link_up,
296 .host_init = ks_pcie_host_init, 297 .host_init = ks_pcie_host_init,
297 .msi_set_irq = ks_dw_pcie_msi_set_irq, 298 .msi_set_irq = ks_dw_pcie_msi_set_irq,
298 .msi_clear_irq = ks_dw_pcie_msi_clear_irq, 299 .msi_clear_irq = ks_dw_pcie_msi_clear_irq,
@@ -311,8 +312,9 @@ static irqreturn_t pcie_err_irq_handler(int irq, void *priv)
311static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie, 312static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie,
312 struct platform_device *pdev) 313 struct platform_device *pdev)
313{ 314{
314 struct pcie_port *pp = &ks_pcie->pp; 315 struct dw_pcie *pci = ks_pcie->pci;
315 struct device *dev = pp->dev; 316 struct pcie_port *pp = &pci->pp;
317 struct device *dev = &pdev->dev;
316 int ret; 318 int ret;
317 319
318 ret = ks_pcie_get_irq_controller_info(ks_pcie, 320 ret = ks_pcie_get_irq_controller_info(ks_pcie,
@@ -365,6 +367,10 @@ static const struct of_device_id ks_pcie_of_match[] = {
365 { }, 367 { },
366}; 368};
367 369
370static const struct dw_pcie_ops dw_pcie_ops = {
371 .link_up = ks_dw_pcie_link_up,
372};
373
368static int __exit ks_pcie_remove(struct platform_device *pdev) 374static int __exit ks_pcie_remove(struct platform_device *pdev)
369{ 375{
370 struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev); 376 struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev);
@@ -377,8 +383,8 @@ static int __exit ks_pcie_remove(struct platform_device *pdev)
377static int __init ks_pcie_probe(struct platform_device *pdev) 383static int __init ks_pcie_probe(struct platform_device *pdev)
378{ 384{
379 struct device *dev = &pdev->dev; 385 struct device *dev = &pdev->dev;
386 struct dw_pcie *pci;
380 struct keystone_pcie *ks_pcie; 387 struct keystone_pcie *ks_pcie;
381 struct pcie_port *pp;
382 struct resource *res; 388 struct resource *res;
383 void __iomem *reg_p; 389 void __iomem *reg_p;
384 struct phy *phy; 390 struct phy *phy;
@@ -388,8 +394,12 @@ static int __init ks_pcie_probe(struct platform_device *pdev)
388 if (!ks_pcie) 394 if (!ks_pcie)
389 return -ENOMEM; 395 return -ENOMEM;
390 396
391 pp = &ks_pcie->pp; 397 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
392 pp->dev = dev; 398 if (!pci)
399 return -ENOMEM;
400
401 pci->dev = dev;
402 pci->ops = &dw_pcie_ops;
393 403
394 /* initialize SerDes Phy if present */ 404 /* initialize SerDes Phy if present */
395 phy = devm_phy_get(dev, "pcie-phy"); 405 phy = devm_phy_get(dev, "pcie-phy");
diff --git a/drivers/pci/dwc/pci-keystone.h b/drivers/pci/dwc/pci-keystone.h
index bc54bafda068..74c5825882df 100644
--- a/drivers/pci/dwc/pci-keystone.h
+++ b/drivers/pci/dwc/pci-keystone.h
@@ -17,7 +17,7 @@
17#define MAX_LEGACY_HOST_IRQS 4 17#define MAX_LEGACY_HOST_IRQS 4
18 18
19struct keystone_pcie { 19struct keystone_pcie {
20 struct pcie_port pp; /* pp.dbi_base is DT 0th res */ 20 struct dw_pcie *pci;
21 struct clk *clk; 21 struct clk *clk;
22 /* PCI Device ID */ 22 /* PCI Device ID */
23 u32 device_id; 23 u32 device_id;
@@ -54,10 +54,10 @@ int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
54int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, 54int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
55 unsigned int devfn, int where, int size, u32 *val); 55 unsigned int devfn, int where, int size, u32 *val);
56void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie); 56void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie);
57int ks_dw_pcie_link_up(struct pcie_port *pp);
58void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie); 57void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie);
59void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq); 58void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq);
60void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq); 59void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq);
61void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp); 60void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp);
62int ks_dw_pcie_msi_host_init(struct pcie_port *pp, 61int ks_dw_pcie_msi_host_init(struct pcie_port *pp,
63 struct msi_controller *chip); 62 struct msi_controller *chip);
63int ks_dw_pcie_link_up(struct dw_pcie *pci);
diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
index 89e8817ae77d..f69d2fe6b84c 100644
--- a/drivers/pci/dwc/pci-layerscape.c
+++ b/drivers/pci/dwc/pci-layerscape.c
@@ -39,24 +39,26 @@ struct ls_pcie_drvdata {
39 u32 lut_offset; 39 u32 lut_offset;
40 u32 ltssm_shift; 40 u32 ltssm_shift;
41 u32 lut_dbg; 41 u32 lut_dbg;
42 struct pcie_host_ops *ops; 42 struct dw_pcie_host_ops *ops;
43 const struct dw_pcie_ops *dw_pcie_ops;
43}; 44};
44 45
45struct ls_pcie { 46struct ls_pcie {
46 struct pcie_port pp; /* pp.dbi_base is DT regs */ 47 struct dw_pcie *pci;
47 void __iomem *lut; 48 void __iomem *lut;
48 struct regmap *scfg; 49 struct regmap *scfg;
49 const struct ls_pcie_drvdata *drvdata; 50 const struct ls_pcie_drvdata *drvdata;
50 int index; 51 int index;
51}; 52};
52 53
53#define to_ls_pcie(x) container_of(x, struct ls_pcie, pp) 54#define to_ls_pcie(x) dev_get_drvdata((x)->dev)
54 55
55static bool ls_pcie_is_bridge(struct ls_pcie *pcie) 56static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
56{ 57{
58 struct dw_pcie *pci = pcie->pci;
57 u32 header_type; 59 u32 header_type;
58 60
59 header_type = ioread8(pcie->pp.dbi_base + PCI_HEADER_TYPE); 61 header_type = ioread8(pci->dbi_base + PCI_HEADER_TYPE);
60 header_type &= 0x7f; 62 header_type &= 0x7f;
61 63
62 return header_type == PCI_HEADER_TYPE_BRIDGE; 64 return header_type == PCI_HEADER_TYPE_BRIDGE;
@@ -65,29 +67,34 @@ static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
65/* Clear multi-function bit */ 67/* Clear multi-function bit */
66static void ls_pcie_clear_multifunction(struct ls_pcie *pcie) 68static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
67{ 69{
68 iowrite8(PCI_HEADER_TYPE_BRIDGE, pcie->pp.dbi_base + PCI_HEADER_TYPE); 70 struct dw_pcie *pci = pcie->pci;
71
72 iowrite8(PCI_HEADER_TYPE_BRIDGE, pci->dbi_base + PCI_HEADER_TYPE);
69} 73}
70 74
71/* Fix class value */ 75/* Fix class value */
72static void ls_pcie_fix_class(struct ls_pcie *pcie) 76static void ls_pcie_fix_class(struct ls_pcie *pcie)
73{ 77{
74 iowrite16(PCI_CLASS_BRIDGE_PCI, pcie->pp.dbi_base + PCI_CLASS_DEVICE); 78 struct dw_pcie *pci = pcie->pci;
79
80 iowrite16(PCI_CLASS_BRIDGE_PCI, pci->dbi_base + PCI_CLASS_DEVICE);
75} 81}
76 82
77/* Drop MSG TLP except for Vendor MSG */ 83/* Drop MSG TLP except for Vendor MSG */
78static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie) 84static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
79{ 85{
80 u32 val; 86 u32 val;
87 struct dw_pcie *pci = pcie->pci;
81 88
82 val = ioread32(pcie->pp.dbi_base + PCIE_STRFMR1); 89 val = ioread32(pci->dbi_base + PCIE_STRFMR1);
83 val &= 0xDFFFFFFF; 90 val &= 0xDFFFFFFF;
84 iowrite32(val, pcie->pp.dbi_base + PCIE_STRFMR1); 91 iowrite32(val, pci->dbi_base + PCIE_STRFMR1);
85} 92}
86 93
87static int ls1021_pcie_link_up(struct pcie_port *pp) 94static int ls1021_pcie_link_up(struct dw_pcie *pci)
88{ 95{
89 u32 state; 96 u32 state;
90 struct ls_pcie *pcie = to_ls_pcie(pp); 97 struct ls_pcie *pcie = to_ls_pcie(pci);
91 98
92 if (!pcie->scfg) 99 if (!pcie->scfg)
93 return 0; 100 return 0;
@@ -103,8 +110,9 @@ static int ls1021_pcie_link_up(struct pcie_port *pp)
103 110
104static void ls1021_pcie_host_init(struct pcie_port *pp) 111static void ls1021_pcie_host_init(struct pcie_port *pp)
105{ 112{
106 struct device *dev = pp->dev; 113 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
107 struct ls_pcie *pcie = to_ls_pcie(pp); 114 struct ls_pcie *pcie = to_ls_pcie(pci);
115 struct device *dev = pci->dev;
108 u32 index[2]; 116 u32 index[2];
109 117
110 pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node, 118 pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
@@ -127,9 +135,9 @@ static void ls1021_pcie_host_init(struct pcie_port *pp)
127 ls_pcie_drop_msg_tlp(pcie); 135 ls_pcie_drop_msg_tlp(pcie);
128} 136}
129 137
130static int ls_pcie_link_up(struct pcie_port *pp) 138static int ls_pcie_link_up(struct dw_pcie *pci)
131{ 139{
132 struct ls_pcie *pcie = to_ls_pcie(pp); 140 struct ls_pcie *pcie = to_ls_pcie(pci);
133 u32 state; 141 u32 state;
134 142
135 state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >> 143 state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >>
@@ -144,19 +152,21 @@ static int ls_pcie_link_up(struct pcie_port *pp)
144 152
145static void ls_pcie_host_init(struct pcie_port *pp) 153static void ls_pcie_host_init(struct pcie_port *pp)
146{ 154{
147 struct ls_pcie *pcie = to_ls_pcie(pp); 155 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
156 struct ls_pcie *pcie = to_ls_pcie(pci);
148 157
149 iowrite32(1, pcie->pp.dbi_base + PCIE_DBI_RO_WR_EN); 158 iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN);
150 ls_pcie_fix_class(pcie); 159 ls_pcie_fix_class(pcie);
151 ls_pcie_clear_multifunction(pcie); 160 ls_pcie_clear_multifunction(pcie);
152 ls_pcie_drop_msg_tlp(pcie); 161 ls_pcie_drop_msg_tlp(pcie);
153 iowrite32(0, pcie->pp.dbi_base + PCIE_DBI_RO_WR_EN); 162 iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN);
154} 163}
155 164
156static int ls_pcie_msi_host_init(struct pcie_port *pp, 165static int ls_pcie_msi_host_init(struct pcie_port *pp,
157 struct msi_controller *chip) 166 struct msi_controller *chip)
158{ 167{
159 struct device *dev = pp->dev; 168 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
169 struct device *dev = pci->dev;
160 struct device_node *np = dev->of_node; 170 struct device_node *np = dev->of_node;
161 struct device_node *msi_node; 171 struct device_node *msi_node;
162 172
@@ -175,20 +185,27 @@ static int ls_pcie_msi_host_init(struct pcie_port *pp,
175 return 0; 185 return 0;
176} 186}
177 187
178static struct pcie_host_ops ls1021_pcie_host_ops = { 188static struct dw_pcie_host_ops ls1021_pcie_host_ops = {
179 .link_up = ls1021_pcie_link_up,
180 .host_init = ls1021_pcie_host_init, 189 .host_init = ls1021_pcie_host_init,
181 .msi_host_init = ls_pcie_msi_host_init, 190 .msi_host_init = ls_pcie_msi_host_init,
182}; 191};
183 192
184static struct pcie_host_ops ls_pcie_host_ops = { 193static struct dw_pcie_host_ops ls_pcie_host_ops = {
185 .link_up = ls_pcie_link_up,
186 .host_init = ls_pcie_host_init, 194 .host_init = ls_pcie_host_init,
187 .msi_host_init = ls_pcie_msi_host_init, 195 .msi_host_init = ls_pcie_msi_host_init,
188}; 196};
189 197
198static const struct dw_pcie_ops dw_ls1021_pcie_ops = {
199 .link_up = ls1021_pcie_link_up,
200};
201
202static const struct dw_pcie_ops dw_ls_pcie_ops = {
203 .link_up = ls_pcie_link_up,
204};
205
190static struct ls_pcie_drvdata ls1021_drvdata = { 206static struct ls_pcie_drvdata ls1021_drvdata = {
191 .ops = &ls1021_pcie_host_ops, 207 .ops = &ls1021_pcie_host_ops,
208 .dw_pcie_ops = &dw_ls1021_pcie_ops,
192}; 209};
193 210
194static struct ls_pcie_drvdata ls1043_drvdata = { 211static struct ls_pcie_drvdata ls1043_drvdata = {
@@ -196,6 +213,7 @@ static struct ls_pcie_drvdata ls1043_drvdata = {
196 .ltssm_shift = 24, 213 .ltssm_shift = 24,
197 .lut_dbg = 0x7fc, 214 .lut_dbg = 0x7fc,
198 .ops = &ls_pcie_host_ops, 215 .ops = &ls_pcie_host_ops,
216 .dw_pcie_ops = &dw_ls_pcie_ops,
199}; 217};
200 218
201static struct ls_pcie_drvdata ls1046_drvdata = { 219static struct ls_pcie_drvdata ls1046_drvdata = {
@@ -203,6 +221,7 @@ static struct ls_pcie_drvdata ls1046_drvdata = {
203 .ltssm_shift = 24, 221 .ltssm_shift = 24,
204 .lut_dbg = 0x407fc, 222 .lut_dbg = 0x407fc,
205 .ops = &ls_pcie_host_ops, 223 .ops = &ls_pcie_host_ops,
224 .dw_pcie_ops = &dw_ls_pcie_ops,
206}; 225};
207 226
208static struct ls_pcie_drvdata ls2080_drvdata = { 227static struct ls_pcie_drvdata ls2080_drvdata = {
@@ -210,6 +229,7 @@ static struct ls_pcie_drvdata ls2080_drvdata = {
210 .ltssm_shift = 0, 229 .ltssm_shift = 0,
211 .lut_dbg = 0x7fc, 230 .lut_dbg = 0x7fc,
212 .ops = &ls_pcie_host_ops, 231 .ops = &ls_pcie_host_ops,
232 .dw_pcie_ops = &dw_ls_pcie_ops,
213}; 233};
214 234
215static const struct of_device_id ls_pcie_of_match[] = { 235static const struct of_device_id ls_pcie_of_match[] = {
@@ -223,10 +243,13 @@ static const struct of_device_id ls_pcie_of_match[] = {
223 243
224static int __init ls_add_pcie_port(struct ls_pcie *pcie) 244static int __init ls_add_pcie_port(struct ls_pcie *pcie)
225{ 245{
226 struct pcie_port *pp = &pcie->pp; 246 struct dw_pcie *pci = pcie->pci;
227 struct device *dev = pp->dev; 247 struct pcie_port *pp = &pci->pp;
248 struct device *dev = pci->dev;
228 int ret; 249 int ret;
229 250
251 pp->ops = pcie->drvdata->ops;
252
230 ret = dw_pcie_host_init(pp); 253 ret = dw_pcie_host_init(pp);
231 if (ret) { 254 if (ret) {
232 dev_err(dev, "failed to initialize host\n"); 255 dev_err(dev, "failed to initialize host\n");
@@ -240,8 +263,8 @@ static int __init ls_pcie_probe(struct platform_device *pdev)
240{ 263{
241 struct device *dev = &pdev->dev; 264 struct device *dev = &pdev->dev;
242 const struct of_device_id *match; 265 const struct of_device_id *match;
266 struct dw_pcie *pci;
243 struct ls_pcie *pcie; 267 struct ls_pcie *pcie;
244 struct pcie_port *pp;
245 struct resource *dbi_base; 268 struct resource *dbi_base;
246 int ret; 269 int ret;
247 270
@@ -253,17 +276,21 @@ static int __init ls_pcie_probe(struct platform_device *pdev)
253 if (!pcie) 276 if (!pcie)
254 return -ENOMEM; 277 return -ENOMEM;
255 278
256 pp = &pcie->pp; 279 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
257 pp->dev = dev; 280 if (!pci)
281 return -ENOMEM;
282
258 pcie->drvdata = match->data; 283 pcie->drvdata = match->data;
259 pp->ops = pcie->drvdata->ops; 284
285 pci->dev = dev;
286 pci->ops = pcie->drvdata->dw_pcie_ops;
260 287
261 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); 288 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
262 pcie->pp.dbi_base = devm_ioremap_resource(dev, dbi_base); 289 pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
263 if (IS_ERR(pcie->pp.dbi_base)) 290 if (IS_ERR(pci->dbi_base))
264 return PTR_ERR(pcie->pp.dbi_base); 291 return PTR_ERR(pci->dbi_base);
265 292
266 pcie->lut = pcie->pp.dbi_base + pcie->drvdata->lut_offset; 293 pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset;
267 294
268 if (!ls_pcie_is_bridge(pcie)) 295 if (!ls_pcie_is_bridge(pcie))
269 return -ENODEV; 296 return -ENODEV;
diff --git a/drivers/pci/dwc/pcie-armada8k.c b/drivers/pci/dwc/pcie-armada8k.c
index 5a28dcbf1866..66bac6fbfa9f 100644
--- a/drivers/pci/dwc/pcie-armada8k.c
+++ b/drivers/pci/dwc/pcie-armada8k.c
@@ -29,7 +29,7 @@
29#include "pcie-designware.h" 29#include "pcie-designware.h"
30 30
31struct armada8k_pcie { 31struct armada8k_pcie {
32 struct pcie_port pp; /* pp.dbi_base is DT ctrl */ 32 struct dw_pcie *pci;
33 struct clk *clk; 33 struct clk *clk;
34}; 34};
35 35
@@ -67,76 +67,77 @@ struct armada8k_pcie {
67#define AX_USER_DOMAIN_MASK 0x3 67#define AX_USER_DOMAIN_MASK 0x3
68#define AX_USER_DOMAIN_SHIFT 4 68#define AX_USER_DOMAIN_SHIFT 4
69 69
70#define to_armada8k_pcie(x) container_of(x, struct armada8k_pcie, pp) 70#define to_armada8k_pcie(x) dev_get_drvdata((x)->dev)
71 71
72static int armada8k_pcie_link_up(struct pcie_port *pp) 72static int armada8k_pcie_link_up(struct dw_pcie *pci)
73{ 73{
74 u32 reg; 74 u32 reg;
75 u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP; 75 u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP;
76 76
77 reg = dw_pcie_readl_rc(pp, PCIE_GLOBAL_STATUS_REG); 77 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_STATUS_REG);
78 78
79 if ((reg & mask) == mask) 79 if ((reg & mask) == mask)
80 return 1; 80 return 1;
81 81
82 dev_dbg(pp->dev, "No link detected (Global-Status: 0x%08x).\n", reg); 82 dev_dbg(pci->dev, "No link detected (Global-Status: 0x%08x).\n", reg);
83 return 0; 83 return 0;
84} 84}
85 85
86static void armada8k_pcie_establish_link(struct armada8k_pcie *pcie) 86static void armada8k_pcie_establish_link(struct armada8k_pcie *pcie)
87{ 87{
88 struct pcie_port *pp = &pcie->pp; 88 struct dw_pcie *pci = pcie->pci;
89 u32 reg; 89 u32 reg;
90 90
91 if (!dw_pcie_link_up(pp)) { 91 if (!dw_pcie_link_up(pci)) {
92 /* Disable LTSSM state machine to enable configuration */ 92 /* Disable LTSSM state machine to enable configuration */
93 reg = dw_pcie_readl_rc(pp, PCIE_GLOBAL_CONTROL_REG); 93 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG);
94 reg &= ~(PCIE_APP_LTSSM_EN); 94 reg &= ~(PCIE_APP_LTSSM_EN);
95 dw_pcie_writel_rc(pp, PCIE_GLOBAL_CONTROL_REG, reg); 95 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg);
96 } 96 }
97 97
98 /* Set the device to root complex mode */ 98 /* Set the device to root complex mode */
99 reg = dw_pcie_readl_rc(pp, PCIE_GLOBAL_CONTROL_REG); 99 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG);
100 reg &= ~(PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT); 100 reg &= ~(PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT);
101 reg |= PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT; 101 reg |= PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT;
102 dw_pcie_writel_rc(pp, PCIE_GLOBAL_CONTROL_REG, reg); 102 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg);
103 103
104 /* Set the PCIe master AxCache attributes */ 104 /* Set the PCIe master AxCache attributes */
105 dw_pcie_writel_rc(pp, PCIE_ARCACHE_TRC_REG, ARCACHE_DEFAULT_VALUE); 105 dw_pcie_writel_dbi(pci, PCIE_ARCACHE_TRC_REG, ARCACHE_DEFAULT_VALUE);
106 dw_pcie_writel_rc(pp, PCIE_AWCACHE_TRC_REG, AWCACHE_DEFAULT_VALUE); 106 dw_pcie_writel_dbi(pci, PCIE_AWCACHE_TRC_REG, AWCACHE_DEFAULT_VALUE);
107 107
108 /* Set the PCIe master AxDomain attributes */ 108 /* Set the PCIe master AxDomain attributes */
109 reg = dw_pcie_readl_rc(pp, PCIE_ARUSER_REG); 109 reg = dw_pcie_readl_dbi(pci, PCIE_ARUSER_REG);
110 reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); 110 reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT);
111 reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; 111 reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT;
112 dw_pcie_writel_rc(pp, PCIE_ARUSER_REG, reg); 112 dw_pcie_writel_dbi(pci, PCIE_ARUSER_REG, reg);
113 113
114 reg = dw_pcie_readl_rc(pp, PCIE_AWUSER_REG); 114 reg = dw_pcie_readl_dbi(pci, PCIE_AWUSER_REG);
115 reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT); 115 reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT);
116 reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT; 116 reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT;
117 dw_pcie_writel_rc(pp, PCIE_AWUSER_REG, reg); 117 dw_pcie_writel_dbi(pci, PCIE_AWUSER_REG, reg);
118 118
119 /* Enable INT A-D interrupts */ 119 /* Enable INT A-D interrupts */
120 reg = dw_pcie_readl_rc(pp, PCIE_GLOBAL_INT_MASK1_REG); 120 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG);
121 reg |= PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK | 121 reg |= PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK |
122 PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK; 122 PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK;
123 dw_pcie_writel_rc(pp, PCIE_GLOBAL_INT_MASK1_REG, reg); 123 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg);
124 124
125 if (!dw_pcie_link_up(pp)) { 125 if (!dw_pcie_link_up(pci)) {
126 /* Configuration done. Start LTSSM */ 126 /* Configuration done. Start LTSSM */
127 reg = dw_pcie_readl_rc(pp, PCIE_GLOBAL_CONTROL_REG); 127 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG);
128 reg |= PCIE_APP_LTSSM_EN; 128 reg |= PCIE_APP_LTSSM_EN;
129 dw_pcie_writel_rc(pp, PCIE_GLOBAL_CONTROL_REG, reg); 129 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg);
130 } 130 }
131 131
132 /* Wait until the link becomes active again */ 132 /* Wait until the link becomes active again */
133 if (dw_pcie_wait_for_link(pp)) 133 if (dw_pcie_wait_for_link(pci))
134 dev_err(pp->dev, "Link not up after reconfiguration\n"); 134 dev_err(pci->dev, "Link not up after reconfiguration\n");
135} 135}
136 136
137static void armada8k_pcie_host_init(struct pcie_port *pp) 137static void armada8k_pcie_host_init(struct pcie_port *pp)
138{ 138{
139 struct armada8k_pcie *pcie = to_armada8k_pcie(pp); 139 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
140 struct armada8k_pcie *pcie = to_armada8k_pcie(pci);
140 141
141 dw_pcie_setup_rc(pp); 142 dw_pcie_setup_rc(pp);
142 armada8k_pcie_establish_link(pcie); 143 armada8k_pcie_establish_link(pcie);
@@ -145,7 +146,7 @@ static void armada8k_pcie_host_init(struct pcie_port *pp)
145static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg) 146static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg)
146{ 147{
147 struct armada8k_pcie *pcie = arg; 148 struct armada8k_pcie *pcie = arg;
148 struct pcie_port *pp = &pcie->pp; 149 struct dw_pcie *pci = pcie->pci;
149 u32 val; 150 u32 val;
150 151
151 /* 152 /*
@@ -153,21 +154,21 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg)
153 * PCI device. However, they are also latched into the PCIe 154 * PCI device. However, they are also latched into the PCIe
154 * controller, so we simply discard them. 155 * controller, so we simply discard them.
155 */ 156 */
156 val = dw_pcie_readl_rc(pp, PCIE_GLOBAL_INT_CAUSE1_REG); 157 val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG);
157 dw_pcie_writel_rc(pp, PCIE_GLOBAL_INT_CAUSE1_REG, val); 158 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG, val);
158 159
159 return IRQ_HANDLED; 160 return IRQ_HANDLED;
160} 161}
161 162
162static struct pcie_host_ops armada8k_pcie_host_ops = { 163static struct dw_pcie_host_ops armada8k_pcie_host_ops = {
163 .link_up = armada8k_pcie_link_up,
164 .host_init = armada8k_pcie_host_init, 164 .host_init = armada8k_pcie_host_init,
165}; 165};
166 166
167static int armada8k_add_pcie_port(struct armada8k_pcie *pcie, 167static int armada8k_add_pcie_port(struct armada8k_pcie *pcie,
168 struct platform_device *pdev) 168 struct platform_device *pdev)
169{ 169{
170 struct pcie_port *pp = &pcie->pp; 170 struct dw_pcie *pci = pcie->pci;
171 struct pcie_port *pp = &pci->pp;
171 struct device *dev = &pdev->dev; 172 struct device *dev = &pdev->dev;
172 int ret; 173 int ret;
173 174
@@ -196,10 +197,14 @@ static int armada8k_add_pcie_port(struct armada8k_pcie *pcie,
196 return 0; 197 return 0;
197} 198}
198 199
200static const struct dw_pcie_ops dw_pcie_ops = {
201 .link_up = armada8k_pcie_link_up,
202};
203
199static int armada8k_pcie_probe(struct platform_device *pdev) 204static int armada8k_pcie_probe(struct platform_device *pdev)
200{ 205{
206 struct dw_pcie *pci;
201 struct armada8k_pcie *pcie; 207 struct armada8k_pcie *pcie;
202 struct pcie_port *pp;
203 struct device *dev = &pdev->dev; 208 struct device *dev = &pdev->dev;
204 struct resource *base; 209 struct resource *base;
205 int ret; 210 int ret;
@@ -208,21 +213,25 @@ static int armada8k_pcie_probe(struct platform_device *pdev)
208 if (!pcie) 213 if (!pcie)
209 return -ENOMEM; 214 return -ENOMEM;
210 215
216 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
217 if (!pci)
218 return -ENOMEM;
219
220 pci->dev = dev;
221 pci->ops = &dw_pcie_ops;
222
211 pcie->clk = devm_clk_get(dev, NULL); 223 pcie->clk = devm_clk_get(dev, NULL);
212 if (IS_ERR(pcie->clk)) 224 if (IS_ERR(pcie->clk))
213 return PTR_ERR(pcie->clk); 225 return PTR_ERR(pcie->clk);
214 226
215 clk_prepare_enable(pcie->clk); 227 clk_prepare_enable(pcie->clk);
216 228
217 pp = &pcie->pp;
218 pp->dev = dev;
219
220 /* Get the dw-pcie unit configuration/control registers base. */ 229 /* Get the dw-pcie unit configuration/control registers base. */
221 base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl"); 230 base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl");
222 pp->dbi_base = devm_ioremap_resource(dev, base); 231 pci->dbi_base = devm_ioremap_resource(dev, base);
223 if (IS_ERR(pp->dbi_base)) { 232 if (IS_ERR(pci->dbi_base)) {
224 dev_err(dev, "couldn't remap regs base %p\n", base); 233 dev_err(dev, "couldn't remap regs base %p\n", base);
225 ret = PTR_ERR(pp->dbi_base); 234 ret = PTR_ERR(pci->dbi_base);
226 goto fail; 235 goto fail;
227 } 236 }
228 237
diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c
index 187a98d621a8..59ecc9e66436 100644
--- a/drivers/pci/dwc/pcie-artpec6.c
+++ b/drivers/pci/dwc/pcie-artpec6.c
@@ -24,10 +24,10 @@
24 24
25#include "pcie-designware.h" 25#include "pcie-designware.h"
26 26
27#define to_artpec6_pcie(x) container_of(x, struct artpec6_pcie, pp) 27#define to_artpec6_pcie(x) dev_get_drvdata((x)->dev)
28 28
29struct artpec6_pcie { 29struct artpec6_pcie {
30 struct pcie_port pp; /* pp.dbi_base is DT dbi */ 30 struct dw_pcie *pci;
31 struct regmap *regmap; /* DT axis,syscon-pcie */ 31 struct regmap *regmap; /* DT axis,syscon-pcie */
32 void __iomem *phy_base; /* DT phy */ 32 void __iomem *phy_base; /* DT phy */
33}; 33};
@@ -80,7 +80,8 @@ static void artpec6_pcie_writel(struct artpec6_pcie *artpec6_pcie, u32 offset, u
80 80
81static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie) 81static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
82{ 82{
83 struct pcie_port *pp = &artpec6_pcie->pp; 83 struct dw_pcie *pci = artpec6_pcie->pci;
84 struct pcie_port *pp = &pci->pp;
84 u32 val; 85 u32 val;
85 unsigned int retries; 86 unsigned int retries;
86 87
@@ -139,7 +140,7 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
139 * Enable writing to config regs. This is required as the Synopsys 140 * Enable writing to config regs. This is required as the Synopsys
140 * driver changes the class code. That register needs DBI write enable. 141 * driver changes the class code. That register needs DBI write enable.
141 */ 142 */
142 dw_pcie_writel_rc(pp, MISC_CONTROL_1_OFF, DBI_RO_WR_EN); 143 dw_pcie_writel_dbi(pci, MISC_CONTROL_1_OFF, DBI_RO_WR_EN);
143 144
144 pp->io_base &= ARTPEC6_CPU_TO_BUS_ADDR; 145 pp->io_base &= ARTPEC6_CPU_TO_BUS_ADDR;
145 pp->mem_base &= ARTPEC6_CPU_TO_BUS_ADDR; 146 pp->mem_base &= ARTPEC6_CPU_TO_BUS_ADDR;
@@ -155,19 +156,20 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
155 artpec6_pcie_writel(artpec6_pcie, PCIECFG, val); 156 artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
156 157
157 /* check if the link is up or not */ 158 /* check if the link is up or not */
158 if (!dw_pcie_wait_for_link(pp)) 159 if (!dw_pcie_wait_for_link(pci))
159 return 0; 160 return 0;
160 161
161 dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", 162 dev_dbg(pci->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
162 dw_pcie_readl_rc(pp, PCIE_PHY_DEBUG_R0), 163 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
163 dw_pcie_readl_rc(pp, PCIE_PHY_DEBUG_R1)); 164 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
164 165
165 return -ETIMEDOUT; 166 return -ETIMEDOUT;
166} 167}
167 168
168static void artpec6_pcie_enable_interrupts(struct artpec6_pcie *artpec6_pcie) 169static void artpec6_pcie_enable_interrupts(struct artpec6_pcie *artpec6_pcie)
169{ 170{
170 struct pcie_port *pp = &artpec6_pcie->pp; 171 struct dw_pcie *pci = artpec6_pcie->pci;
172 struct pcie_port *pp = &pci->pp;
171 173
172 if (IS_ENABLED(CONFIG_PCI_MSI)) 174 if (IS_ENABLED(CONFIG_PCI_MSI))
173 dw_pcie_msi_init(pp); 175 dw_pcie_msi_init(pp);
@@ -175,20 +177,22 @@ static void artpec6_pcie_enable_interrupts(struct artpec6_pcie *artpec6_pcie)
175 177
176static void artpec6_pcie_host_init(struct pcie_port *pp) 178static void artpec6_pcie_host_init(struct pcie_port *pp)
177{ 179{
178 struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pp); 180 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
181 struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
179 182
180 artpec6_pcie_establish_link(artpec6_pcie); 183 artpec6_pcie_establish_link(artpec6_pcie);
181 artpec6_pcie_enable_interrupts(artpec6_pcie); 184 artpec6_pcie_enable_interrupts(artpec6_pcie);
182} 185}
183 186
184static struct pcie_host_ops artpec6_pcie_host_ops = { 187static struct dw_pcie_host_ops artpec6_pcie_host_ops = {
185 .host_init = artpec6_pcie_host_init, 188 .host_init = artpec6_pcie_host_init,
186}; 189};
187 190
188static irqreturn_t artpec6_pcie_msi_handler(int irq, void *arg) 191static irqreturn_t artpec6_pcie_msi_handler(int irq, void *arg)
189{ 192{
190 struct artpec6_pcie *artpec6_pcie = arg; 193 struct artpec6_pcie *artpec6_pcie = arg;
191 struct pcie_port *pp = &artpec6_pcie->pp; 194 struct dw_pcie *pci = artpec6_pcie->pci;
195 struct pcie_port *pp = &pci->pp;
192 196
193 return dw_handle_msi_irq(pp); 197 return dw_handle_msi_irq(pp);
194} 198}
@@ -196,8 +200,9 @@ static irqreturn_t artpec6_pcie_msi_handler(int irq, void *arg)
196static int artpec6_add_pcie_port(struct artpec6_pcie *artpec6_pcie, 200static int artpec6_add_pcie_port(struct artpec6_pcie *artpec6_pcie,
197 struct platform_device *pdev) 201 struct platform_device *pdev)
198{ 202{
199 struct pcie_port *pp = &artpec6_pcie->pp; 203 struct dw_pcie *pci = artpec6_pcie->pci;
200 struct device *dev = pp->dev; 204 struct pcie_port *pp = &pci->pp;
205 struct device *dev = pci->dev;
201 int ret; 206 int ret;
202 207
203 if (IS_ENABLED(CONFIG_PCI_MSI)) { 208 if (IS_ENABLED(CONFIG_PCI_MSI)) {
@@ -232,8 +237,8 @@ static int artpec6_add_pcie_port(struct artpec6_pcie *artpec6_pcie,
232static int artpec6_pcie_probe(struct platform_device *pdev) 237static int artpec6_pcie_probe(struct platform_device *pdev)
233{ 238{
234 struct device *dev = &pdev->dev; 239 struct device *dev = &pdev->dev;
240 struct dw_pcie *pci;
235 struct artpec6_pcie *artpec6_pcie; 241 struct artpec6_pcie *artpec6_pcie;
236 struct pcie_port *pp;
237 struct resource *dbi_base; 242 struct resource *dbi_base;
238 struct resource *phy_base; 243 struct resource *phy_base;
239 int ret; 244 int ret;
@@ -242,13 +247,16 @@ static int artpec6_pcie_probe(struct platform_device *pdev)
242 if (!artpec6_pcie) 247 if (!artpec6_pcie)
243 return -ENOMEM; 248 return -ENOMEM;
244 249
245 pp = &artpec6_pcie->pp; 250 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
246 pp->dev = dev; 251 if (!pci)
252 return -ENOMEM;
253
254 pci->dev = dev;
247 255
248 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 256 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
249 pp->dbi_base = devm_ioremap_resource(dev, dbi_base); 257 pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
250 if (IS_ERR(pp->dbi_base)) 258 if (IS_ERR(pci->dbi_base))
251 return PTR_ERR(pp->dbi_base); 259 return PTR_ERR(pci->dbi_base);
252 260
253 phy_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); 261 phy_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
254 artpec6_pcie->phy_base = devm_ioremap_resource(dev, phy_base); 262 artpec6_pcie->phy_base = devm_ioremap_resource(dev, phy_base);
diff --git a/drivers/pci/dwc/pcie-designware-plat.c b/drivers/pci/dwc/pcie-designware-plat.c
index bb5854059d46..65250f63515c 100644
--- a/drivers/pci/dwc/pcie-designware-plat.c
+++ b/drivers/pci/dwc/pcie-designware-plat.c
@@ -25,7 +25,7 @@
25#include "pcie-designware.h" 25#include "pcie-designware.h"
26 26
27struct dw_plat_pcie { 27struct dw_plat_pcie {
28 struct pcie_port pp; /* pp.dbi_base is DT 0th resource */ 28 struct dw_pcie *pci;
29}; 29};
30 30
31static irqreturn_t dw_plat_pcie_msi_irq_handler(int irq, void *arg) 31static irqreturn_t dw_plat_pcie_msi_irq_handler(int irq, void *arg)
@@ -37,21 +37,23 @@ static irqreturn_t dw_plat_pcie_msi_irq_handler(int irq, void *arg)
37 37
38static void dw_plat_pcie_host_init(struct pcie_port *pp) 38static void dw_plat_pcie_host_init(struct pcie_port *pp)
39{ 39{
40 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
41
40 dw_pcie_setup_rc(pp); 42 dw_pcie_setup_rc(pp);
41 dw_pcie_wait_for_link(pp); 43 dw_pcie_wait_for_link(pci);
42 44
43 if (IS_ENABLED(CONFIG_PCI_MSI)) 45 if (IS_ENABLED(CONFIG_PCI_MSI))
44 dw_pcie_msi_init(pp); 46 dw_pcie_msi_init(pp);
45} 47}
46 48
47static struct pcie_host_ops dw_plat_pcie_host_ops = { 49static struct dw_pcie_host_ops dw_plat_pcie_host_ops = {
48 .host_init = dw_plat_pcie_host_init, 50 .host_init = dw_plat_pcie_host_init,
49}; 51};
50 52
51static int dw_plat_add_pcie_port(struct pcie_port *pp, 53static int dw_plat_add_pcie_port(struct pcie_port *pp,
52 struct platform_device *pdev) 54 struct platform_device *pdev)
53{ 55{
54 struct device *dev = pp->dev; 56 struct device *dev = &pdev->dev;
55 int ret; 57 int ret;
56 58
57 pp->irq = platform_get_irq(pdev, 1); 59 pp->irq = platform_get_irq(pdev, 1);
@@ -88,7 +90,7 @@ static int dw_plat_pcie_probe(struct platform_device *pdev)
88{ 90{
89 struct device *dev = &pdev->dev; 91 struct device *dev = &pdev->dev;
90 struct dw_plat_pcie *dw_plat_pcie; 92 struct dw_plat_pcie *dw_plat_pcie;
91 struct pcie_port *pp; 93 struct dw_pcie *pci;
92 struct resource *res; /* Resource from DT */ 94 struct resource *res; /* Resource from DT */
93 int ret; 95 int ret;
94 96
@@ -96,17 +98,20 @@ static int dw_plat_pcie_probe(struct platform_device *pdev)
96 if (!dw_plat_pcie) 98 if (!dw_plat_pcie)
97 return -ENOMEM; 99 return -ENOMEM;
98 100
99 pp = &dw_plat_pcie->pp; 101 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
100 pp->dev = dev; 102 if (!pci)
103 return -ENOMEM;
104
105 pci->dev = dev;
101 106
102 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 107 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
103 pp->dbi_base = devm_ioremap_resource(dev, res); 108 pci->dbi_base = devm_ioremap_resource(dev, res);
104 if (IS_ERR(pp->dbi_base)) 109 if (IS_ERR(pci->dbi_base))
105 return PTR_ERR(pp->dbi_base); 110 return PTR_ERR(pci->dbi_base);
106 111
107 platform_set_drvdata(pdev, dw_plat_pcie); 112 platform_set_drvdata(pdev, dw_plat_pcie);
108 113
109 ret = dw_plat_add_pcie_port(pp, pdev); 114 ret = dw_plat_add_pcie_port(&pci->pp, pdev);
110 if (ret < 0) 115 if (ret < 0)
111 return ret; 116 return ret;
112 117
diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
index 6e95291d9cb4..be610391ff48 100644
--- a/drivers/pci/dwc/pcie-designware.c
+++ b/drivers/pci/dwc/pcie-designware.c
@@ -71,90 +71,97 @@ int dw_pcie_write(void __iomem *addr, int size, u32 val)
71 return PCIBIOS_SUCCESSFUL; 71 return PCIBIOS_SUCCESSFUL;
72} 72}
73 73
74u32 dw_pcie_readl_rc(struct pcie_port *pp, u32 reg) 74u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg)
75{ 75{
76 if (pp->ops->readl_rc) 76 if (pci->ops->readl_dbi)
77 return pp->ops->readl_rc(pp, reg); 77 return pci->ops->readl_dbi(pci, reg);
78 78
79 return readl(pp->dbi_base + reg); 79 return readl(pci->dbi_base + reg);
80} 80}
81 81
82void dw_pcie_writel_rc(struct pcie_port *pp, u32 reg, u32 val) 82void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
83{ 83{
84 if (pp->ops->writel_rc) 84 if (pci->ops->writel_dbi)
85 pp->ops->writel_rc(pp, reg, val); 85 pci->ops->writel_dbi(pci, reg, val);
86 else 86 else
87 writel(val, pp->dbi_base + reg); 87 writel(val, pci->dbi_base + reg);
88} 88}
89 89
90static u32 dw_pcie_readl_unroll(struct pcie_port *pp, u32 index, u32 reg) 90static u32 dw_pcie_readl_unroll(struct dw_pcie *pci, u32 index, u32 reg)
91{ 91{
92 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); 92 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
93 93
94 return dw_pcie_readl_rc(pp, offset + reg); 94 return dw_pcie_readl_dbi(pci, offset + reg);
95} 95}
96 96
97static void dw_pcie_writel_unroll(struct pcie_port *pp, u32 index, u32 reg, 97static void dw_pcie_writel_unroll(struct dw_pcie *pci, u32 index, u32 reg,
98 u32 val) 98 u32 val)
99{ 99{
100 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); 100 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
101 101
102 dw_pcie_writel_rc(pp, offset + reg, val); 102 dw_pcie_writel_dbi(pci, offset + reg, val);
103} 103}
104 104
105static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, 105static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
106 u32 *val) 106 u32 *val)
107{ 107{
108 struct dw_pcie *pci;
109
108 if (pp->ops->rd_own_conf) 110 if (pp->ops->rd_own_conf)
109 return pp->ops->rd_own_conf(pp, where, size, val); 111 return pp->ops->rd_own_conf(pp, where, size, val);
110 112
111 return dw_pcie_read(pp->dbi_base + where, size, val); 113 pci = to_dw_pcie_from_pp(pp);
114 return dw_pcie_read(pci->dbi_base + where, size, val);
112} 115}
113 116
114static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, 117static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
115 u32 val) 118 u32 val)
116{ 119{
120 struct dw_pcie *pci;
121
117 if (pp->ops->wr_own_conf) 122 if (pp->ops->wr_own_conf)
118 return pp->ops->wr_own_conf(pp, where, size, val); 123 return pp->ops->wr_own_conf(pp, where, size, val);
119 124
120 return dw_pcie_write(pp->dbi_base + where, size, val); 125 pci = to_dw_pcie_from_pp(pp);
126 return dw_pcie_write(pci->dbi_base + where, size, val);
121} 127}
122 128
123static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index, 129static void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
124 int type, u64 cpu_addr, u64 pci_addr, u32 size) 130 int type, u64 cpu_addr, u64 pci_addr,
131 u32 size)
125{ 132{
126 u32 retries, val; 133 u32 retries, val;
127 134
128 if (pp->iatu_unroll_enabled) { 135 if (pci->iatu_unroll_enabled) {
129 dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_LOWER_BASE, 136 dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
130 lower_32_bits(cpu_addr)); 137 lower_32_bits(cpu_addr));
131 dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_UPPER_BASE, 138 dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE,
132 upper_32_bits(cpu_addr)); 139 upper_32_bits(cpu_addr));
133 dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_LIMIT, 140 dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LIMIT,
134 lower_32_bits(cpu_addr + size - 1)); 141 lower_32_bits(cpu_addr + size - 1));
135 dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_LOWER_TARGET, 142 dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
136 lower_32_bits(pci_addr)); 143 lower_32_bits(pci_addr));
137 dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_UPPER_TARGET, 144 dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
138 upper_32_bits(pci_addr)); 145 upper_32_bits(pci_addr));
139 dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_REGION_CTRL1, 146 dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
140 type); 147 type);
141 dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_REGION_CTRL2, 148 dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
142 PCIE_ATU_ENABLE); 149 PCIE_ATU_ENABLE);
143 } else { 150 } else {
144 dw_pcie_writel_rc(pp, PCIE_ATU_VIEWPORT, 151 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT,
145 PCIE_ATU_REGION_OUTBOUND | index); 152 PCIE_ATU_REGION_OUTBOUND | index);
146 dw_pcie_writel_rc(pp, PCIE_ATU_LOWER_BASE, 153 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE,
147 lower_32_bits(cpu_addr)); 154 lower_32_bits(cpu_addr));
148 dw_pcie_writel_rc(pp, PCIE_ATU_UPPER_BASE, 155 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_BASE,
149 upper_32_bits(cpu_addr)); 156 upper_32_bits(cpu_addr));
150 dw_pcie_writel_rc(pp, PCIE_ATU_LIMIT, 157 dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
151 lower_32_bits(cpu_addr + size - 1)); 158 lower_32_bits(cpu_addr + size - 1));
152 dw_pcie_writel_rc(pp, PCIE_ATU_LOWER_TARGET, 159 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
153 lower_32_bits(pci_addr)); 160 lower_32_bits(pci_addr));
154 dw_pcie_writel_rc(pp, PCIE_ATU_UPPER_TARGET, 161 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
155 upper_32_bits(pci_addr)); 162 upper_32_bits(pci_addr));
156 dw_pcie_writel_rc(pp, PCIE_ATU_CR1, type); 163 dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type);
157 dw_pcie_writel_rc(pp, PCIE_ATU_CR2, PCIE_ATU_ENABLE); 164 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
158 } 165 }
159 166
160 /* 167 /*
@@ -162,18 +169,18 @@ static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
162 * and I/O accesses. 169 * and I/O accesses.
163 */ 170 */
164 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { 171 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
165 if (pp->iatu_unroll_enabled) 172 if (pci->iatu_unroll_enabled)
166 val = dw_pcie_readl_unroll(pp, index, 173 val = dw_pcie_readl_unroll(pci, index,
167 PCIE_ATU_UNR_REGION_CTRL2); 174 PCIE_ATU_UNR_REGION_CTRL2);
168 else 175 else
169 val = dw_pcie_readl_rc(pp, PCIE_ATU_CR2); 176 val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
170 177
171 if (val == PCIE_ATU_ENABLE) 178 if (val == PCIE_ATU_ENABLE)
172 return; 179 return;
173 180
174 usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX); 181 usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
175 } 182 }
176 dev_err(pp->dev, "iATU is not being enabled\n"); 183 dev_err(pci->dev, "iATU is not being enabled\n");
177} 184}
178 185
179static struct irq_chip dw_msi_irq_chip = { 186static struct irq_chip dw_msi_irq_chip = {
@@ -390,32 +397,32 @@ static struct msi_controller dw_pcie_msi_chip = {
390 .teardown_irq = dw_msi_teardown_irq, 397 .teardown_irq = dw_msi_teardown_irq,
391}; 398};
392 399
393int dw_pcie_wait_for_link(struct pcie_port *pp) 400int dw_pcie_wait_for_link(struct dw_pcie *pci)
394{ 401{
395 int retries; 402 int retries;
396 403
397 /* check if the link is up or not */ 404 /* check if the link is up or not */
398 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { 405 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
399 if (dw_pcie_link_up(pp)) { 406 if (dw_pcie_link_up(pci)) {
400 dev_info(pp->dev, "link up\n"); 407 dev_info(pci->dev, "link up\n");
401 return 0; 408 return 0;
402 } 409 }
403 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); 410 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
404 } 411 }
405 412
406 dev_err(pp->dev, "phy link never came up\n"); 413 dev_err(pci->dev, "phy link never came up\n");
407 414
408 return -ETIMEDOUT; 415 return -ETIMEDOUT;
409} 416}
410 417
411int dw_pcie_link_up(struct pcie_port *pp) 418int dw_pcie_link_up(struct dw_pcie *pci)
412{ 419{
413 u32 val; 420 u32 val;
414 421
415 if (pp->ops->link_up) 422 if (pci->ops->link_up)
416 return pp->ops->link_up(pp); 423 return pci->ops->link_up(pci);
417 424
418 val = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1); 425 val = readl(pci->dbi_base + PCIE_PHY_DEBUG_R1);
419 return ((val & PCIE_PHY_DEBUG_R1_LINK_UP) && 426 return ((val & PCIE_PHY_DEBUG_R1_LINK_UP) &&
420 (!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING))); 427 (!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING)));
421} 428}
@@ -433,11 +440,11 @@ static const struct irq_domain_ops msi_domain_ops = {
433 .map = dw_pcie_msi_map, 440 .map = dw_pcie_msi_map,
434}; 441};
435 442
436static u8 dw_pcie_iatu_unroll_enabled(struct pcie_port *pp) 443static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
437{ 444{
438 u32 val; 445 u32 val;
439 446
440 val = dw_pcie_readl_rc(pp, PCIE_ATU_VIEWPORT); 447 val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
441 if (val == 0xffffffff) 448 if (val == 0xffffffff)
442 return 1; 449 return 1;
443 450
@@ -446,7 +453,8 @@ static u8 dw_pcie_iatu_unroll_enabled(struct pcie_port *pp)
446 453
447int dw_pcie_host_init(struct pcie_port *pp) 454int dw_pcie_host_init(struct pcie_port *pp)
448{ 455{
449 struct device *dev = pp->dev; 456 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
457 struct device *dev = pci->dev;
450 struct device_node *np = dev->of_node; 458 struct device_node *np = dev->of_node;
451 struct platform_device *pdev = to_platform_device(dev); 459 struct platform_device *pdev = to_platform_device(dev);
452 struct pci_bus *bus, *child; 460 struct pci_bus *bus, *child;
@@ -508,10 +516,10 @@ int dw_pcie_host_init(struct pcie_port *pp)
508 } 516 }
509 } 517 }
510 518
511 if (!pp->dbi_base) { 519 if (!pci->dbi_base) {
512 pp->dbi_base = devm_ioremap(dev, pp->cfg->start, 520 pci->dbi_base = devm_ioremap(dev, pp->cfg->start,
513 resource_size(pp->cfg)); 521 resource_size(pp->cfg));
514 if (!pp->dbi_base) { 522 if (!pci->dbi_base) {
515 dev_err(dev, "error with ioremap\n"); 523 dev_err(dev, "error with ioremap\n");
516 ret = -ENOMEM; 524 ret = -ENOMEM;
517 goto error; 525 goto error;
@@ -540,13 +548,13 @@ int dw_pcie_host_init(struct pcie_port *pp)
540 } 548 }
541 } 549 }
542 550
543 ret = of_property_read_u32(np, "num-lanes", &pp->lanes); 551 ret = of_property_read_u32(np, "num-lanes", &pci->lanes);
544 if (ret) 552 if (ret)
545 pp->lanes = 0; 553 pci->lanes = 0;
546 554
547 ret = of_property_read_u32(np, "num-viewport", &pp->num_viewport); 555 ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport);
548 if (ret) 556 if (ret)
549 pp->num_viewport = 2; 557 pci->num_viewport = 2;
550 558
551 if (IS_ENABLED(CONFIG_PCI_MSI)) { 559 if (IS_ENABLED(CONFIG_PCI_MSI)) {
552 if (!pp->ops->msi_host_init) { 560 if (!pp->ops->msi_host_init) {
@@ -614,6 +622,7 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
614 u32 busdev, cfg_size; 622 u32 busdev, cfg_size;
615 u64 cpu_addr; 623 u64 cpu_addr;
616 void __iomem *va_cfg_base; 624 void __iomem *va_cfg_base;
625 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
617 626
618 if (pp->ops->rd_other_conf) 627 if (pp->ops->rd_other_conf)
619 return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val); 628 return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val);
@@ -633,12 +642,12 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
633 va_cfg_base = pp->va_cfg1_base; 642 va_cfg_base = pp->va_cfg1_base;
634 } 643 }
635 644
636 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, 645 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
637 type, cpu_addr, 646 type, cpu_addr,
638 busdev, cfg_size); 647 busdev, cfg_size);
639 ret = dw_pcie_read(va_cfg_base + where, size, val); 648 ret = dw_pcie_read(va_cfg_base + where, size, val);
640 if (pp->num_viewport <= 2) 649 if (pci->num_viewport <= 2)
641 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, 650 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
642 PCIE_ATU_TYPE_IO, pp->io_base, 651 PCIE_ATU_TYPE_IO, pp->io_base,
643 pp->io_bus_addr, pp->io_size); 652 pp->io_bus_addr, pp->io_size);
644 653
@@ -652,6 +661,7 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
652 u32 busdev, cfg_size; 661 u32 busdev, cfg_size;
653 u64 cpu_addr; 662 u64 cpu_addr;
654 void __iomem *va_cfg_base; 663 void __iomem *va_cfg_base;
664 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
655 665
656 if (pp->ops->wr_other_conf) 666 if (pp->ops->wr_other_conf)
657 return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val); 667 return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val);
@@ -671,12 +681,12 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
671 va_cfg_base = pp->va_cfg1_base; 681 va_cfg_base = pp->va_cfg1_base;
672 } 682 }
673 683
674 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, 684 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
675 type, cpu_addr, 685 type, cpu_addr,
676 busdev, cfg_size); 686 busdev, cfg_size);
677 ret = dw_pcie_write(va_cfg_base + where, size, val); 687 ret = dw_pcie_write(va_cfg_base + where, size, val);
678 if (pp->num_viewport <= 2) 688 if (pci->num_viewport <= 2)
679 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, 689 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
680 PCIE_ATU_TYPE_IO, pp->io_base, 690 PCIE_ATU_TYPE_IO, pp->io_base,
681 pp->io_bus_addr, pp->io_size); 691 pp->io_bus_addr, pp->io_size);
682 692
@@ -686,9 +696,11 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
686static int dw_pcie_valid_device(struct pcie_port *pp, struct pci_bus *bus, 696static int dw_pcie_valid_device(struct pcie_port *pp, struct pci_bus *bus,
687 int dev) 697 int dev)
688{ 698{
699 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
700
689 /* If there is no link, then there is no device */ 701 /* If there is no link, then there is no device */
690 if (bus->number != pp->root_bus_nr) { 702 if (bus->number != pp->root_bus_nr) {
691 if (!dw_pcie_link_up(pp)) 703 if (!dw_pcie_link_up(pci))
692 return 0; 704 return 0;
693 } 705 }
694 706
@@ -737,11 +749,12 @@ static struct pci_ops dw_pcie_ops = {
737void dw_pcie_setup_rc(struct pcie_port *pp) 749void dw_pcie_setup_rc(struct pcie_port *pp)
738{ 750{
739 u32 val; 751 u32 val;
752 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
740 753
741 /* set the number of lanes */ 754 /* set the number of lanes */
742 val = dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL); 755 val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
743 val &= ~PORT_LINK_MODE_MASK; 756 val &= ~PORT_LINK_MODE_MASK;
744 switch (pp->lanes) { 757 switch (pci->lanes) {
745 case 1: 758 case 1:
746 val |= PORT_LINK_MODE_1_LANES; 759 val |= PORT_LINK_MODE_1_LANES;
747 break; 760 break;
@@ -755,15 +768,15 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
755 val |= PORT_LINK_MODE_8_LANES; 768 val |= PORT_LINK_MODE_8_LANES;
756 break; 769 break;
757 default: 770 default:
758 dev_err(pp->dev, "num-lanes %u: invalid value\n", pp->lanes); 771 dev_err(pci->dev, "num-lanes %u: invalid value\n", pci->lanes);
759 return; 772 return;
760 } 773 }
761 dw_pcie_writel_rc(pp, PCIE_PORT_LINK_CONTROL, val); 774 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
762 775
763 /* set link width speed control register */ 776 /* set link width speed control register */
764 val = dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL); 777 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
765 val &= ~PORT_LOGIC_LINK_WIDTH_MASK; 778 val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
766 switch (pp->lanes) { 779 switch (pci->lanes) {
767 case 1: 780 case 1:
768 val |= PORT_LOGIC_LINK_WIDTH_1_LANES; 781 val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
769 break; 782 break;
@@ -777,30 +790,30 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
777 val |= PORT_LOGIC_LINK_WIDTH_8_LANES; 790 val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
778 break; 791 break;
779 } 792 }
780 dw_pcie_writel_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, val); 793 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
781 794
782 /* setup RC BARs */ 795 /* setup RC BARs */
783 dw_pcie_writel_rc(pp, PCI_BASE_ADDRESS_0, 0x00000004); 796 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);
784 dw_pcie_writel_rc(pp, PCI_BASE_ADDRESS_1, 0x00000000); 797 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
785 798
786 /* setup interrupt pins */ 799 /* setup interrupt pins */
787 val = dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE); 800 val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
788 val &= 0xffff00ff; 801 val &= 0xffff00ff;
789 val |= 0x00000100; 802 val |= 0x00000100;
790 dw_pcie_writel_rc(pp, PCI_INTERRUPT_LINE, val); 803 dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
791 804
792 /* setup bus numbers */ 805 /* setup bus numbers */
793 val = dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS); 806 val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
794 val &= 0xff000000; 807 val &= 0xff000000;
795 val |= 0x00010100; 808 val |= 0x00010100;
796 dw_pcie_writel_rc(pp, PCI_PRIMARY_BUS, val); 809 dw_pcie_writel_dbi(pci, PCI_PRIMARY_BUS, val);
797 810
798 /* setup command register */ 811 /* setup command register */
799 val = dw_pcie_readl_rc(pp, PCI_COMMAND); 812 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
800 val &= 0xffff0000; 813 val &= 0xffff0000;
801 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 814 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
802 PCI_COMMAND_MASTER | PCI_COMMAND_SERR; 815 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
803 dw_pcie_writel_rc(pp, PCI_COMMAND, val); 816 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
804 817
805 /* 818 /*
806 * If the platform provides ->rd_other_conf, it means the platform 819 * If the platform provides ->rd_other_conf, it means the platform
@@ -809,15 +822,15 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
809 */ 822 */
810 if (!pp->ops->rd_other_conf) { 823 if (!pp->ops->rd_other_conf) {
811 /* get iATU unroll support */ 824 /* get iATU unroll support */
812 pp->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pp); 825 pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci);
813 dev_dbg(pp->dev, "iATU unroll: %s\n", 826 dev_dbg(pci->dev, "iATU unroll: %s\n",
814 pp->iatu_unroll_enabled ? "enabled" : "disabled"); 827 pci->iatu_unroll_enabled ? "enabled" : "disabled");
815 828
816 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, 829 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,
817 PCIE_ATU_TYPE_MEM, pp->mem_base, 830 PCIE_ATU_TYPE_MEM, pp->mem_base,
818 pp->mem_bus_addr, pp->mem_size); 831 pp->mem_bus_addr, pp->mem_size);
819 if (pp->num_viewport > 2) 832 if (pci->num_viewport > 2)
820 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX2, 833 dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX2,
821 PCIE_ATU_TYPE_IO, pp->io_base, 834 PCIE_ATU_TYPE_IO, pp->io_base,
822 pp->io_bus_addr, pp->io_size); 835 pp->io_bus_addr, pp->io_size);
823 } 836 }
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index 5b71b5772dc6..b23a5b3728ae 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -93,10 +93,27 @@
93#define MAX_MSI_IRQS 32 93#define MAX_MSI_IRQS 32
94#define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32) 94#define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32)
95 95
96struct pcie_port;
97struct dw_pcie;
98
99struct dw_pcie_host_ops {
100 int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
101 int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val);
102 int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
103 unsigned int devfn, int where, int size, u32 *val);
104 int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
105 unsigned int devfn, int where, int size, u32 val);
106 void (*host_init)(struct pcie_port *pp);
107 void (*msi_set_irq)(struct pcie_port *pp, int irq);
108 void (*msi_clear_irq)(struct pcie_port *pp, int irq);
109 phys_addr_t (*get_msi_addr)(struct pcie_port *pp);
110 u32 (*get_msi_data)(struct pcie_port *pp, int pos);
111 void (*scan_bus)(struct pcie_port *pp);
112 int (*msi_host_init)(struct pcie_port *pp, struct msi_controller *chip);
113};
114
96struct pcie_port { 115struct pcie_port {
97 struct device *dev;
98 u8 root_bus_nr; 116 u8 root_bus_nr;
99 void __iomem *dbi_base;
100 u64 cfg0_base; 117 u64 cfg0_base;
101 void __iomem *va_cfg0_base; 118 void __iomem *va_cfg0_base;
102 u32 cfg0_size; 119 u32 cfg0_size;
@@ -114,44 +131,40 @@ struct pcie_port {
114 struct resource *mem; 131 struct resource *mem;
115 struct resource *busn; 132 struct resource *busn;
116 int irq; 133 int irq;
117 u32 lanes; 134 struct dw_pcie_host_ops *ops;
118 u32 num_viewport;
119 struct pcie_host_ops *ops;
120 int msi_irq; 135 int msi_irq;
121 struct irq_domain *irq_domain; 136 struct irq_domain *irq_domain;
122 unsigned long msi_data; 137 unsigned long msi_data;
123 u8 iatu_unroll_enabled;
124 DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); 138 DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
125}; 139};
126 140
127struct pcie_host_ops { 141struct dw_pcie_ops {
128 u32 (*readl_rc)(struct pcie_port *pp, u32 reg); 142 u32 (*readl_dbi)(struct dw_pcie *pcie, u32 reg);
129 void (*writel_rc)(struct pcie_port *pp, u32 reg, u32 val); 143 void (*writel_dbi)(struct dw_pcie *pcie, u32 reg, u32 val);
130 int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val); 144 int (*link_up)(struct dw_pcie *pcie);
131 int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val);
132 int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
133 unsigned int devfn, int where, int size, u32 *val);
134 int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
135 unsigned int devfn, int where, int size, u32 val);
136 int (*link_up)(struct pcie_port *pp);
137 void (*host_init)(struct pcie_port *pp);
138 void (*msi_set_irq)(struct pcie_port *pp, int irq);
139 void (*msi_clear_irq)(struct pcie_port *pp, int irq);
140 phys_addr_t (*get_msi_addr)(struct pcie_port *pp);
141 u32 (*get_msi_data)(struct pcie_port *pp, int pos);
142 void (*scan_bus)(struct pcie_port *pp);
143 int (*msi_host_init)(struct pcie_port *pp, struct msi_controller *chip);
144}; 145};
145 146
146u32 dw_pcie_readl_rc(struct pcie_port *pp, u32 reg); 147struct dw_pcie {
147void dw_pcie_writel_rc(struct pcie_port *pp, u32 reg, u32 val); 148 struct device *dev;
149 void __iomem *dbi_base;
150 u32 lanes;
151 u32 num_viewport;
152 u8 iatu_unroll_enabled;
153 struct pcie_port pp;
154 const struct dw_pcie_ops *ops;
155};
156
157#define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
158
148int dw_pcie_read(void __iomem *addr, int size, u32 *val); 159int dw_pcie_read(void __iomem *addr, int size, u32 *val);
149int dw_pcie_write(void __iomem *addr, int size, u32 val); 160int dw_pcie_write(void __iomem *addr, int size, u32 val);
150irqreturn_t dw_handle_msi_irq(struct pcie_port *pp); 161irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
151void dw_pcie_msi_init(struct pcie_port *pp); 162void dw_pcie_msi_init(struct pcie_port *pp);
152int dw_pcie_wait_for_link(struct pcie_port *pp);
153int dw_pcie_link_up(struct pcie_port *pp);
154void dw_pcie_setup_rc(struct pcie_port *pp); 163void dw_pcie_setup_rc(struct pcie_port *pp);
155int dw_pcie_host_init(struct pcie_port *pp); 164int dw_pcie_host_init(struct pcie_port *pp);
156 165
166u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg);
167void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val);
168int dw_pcie_link_up(struct dw_pcie *pci);
169int dw_pcie_wait_for_link(struct dw_pcie *pci);
157#endif /* _PCIE_DESIGNWARE_H */ 170#endif /* _PCIE_DESIGNWARE_H */
diff --git a/drivers/pci/dwc/pcie-hisi.c b/drivers/pci/dwc/pcie-hisi.c
index ecc1b08ff8e0..386467a4f00f 100644
--- a/drivers/pci/dwc/pcie-hisi.c
+++ b/drivers/pci/dwc/pcie-hisi.c
@@ -127,7 +127,7 @@ struct pci_ecam_ops hisi_pcie_ops = {
127#define PCIE_LTSSM_LINKUP_STATE 0x11 127#define PCIE_LTSSM_LINKUP_STATE 0x11
128#define PCIE_LTSSM_STATE_MASK 0x3F 128#define PCIE_LTSSM_STATE_MASK 0x3F
129 129
130#define to_hisi_pcie(x) container_of(x, struct hisi_pcie, pp) 130#define to_hisi_pcie(x) dev_get_drvdata((x)->dev)
131 131
132struct hisi_pcie; 132struct hisi_pcie;
133 133
@@ -136,7 +136,7 @@ struct pcie_soc_ops {
136}; 136};
137 137
138struct hisi_pcie { 138struct hisi_pcie {
139 struct pcie_port pp; /* pp.dbi_base is DT rc_dbi */ 139 struct dw_pcie *pci;
140 struct regmap *subctrl; 140 struct regmap *subctrl;
141 u32 port_id; 141 u32 port_id;
142 struct pcie_soc_ops *soc_ops; 142 struct pcie_soc_ops *soc_ops;
@@ -149,10 +149,11 @@ static int hisi_pcie_cfg_read(struct pcie_port *pp, int where, int size,
149 u32 reg; 149 u32 reg;
150 u32 reg_val; 150 u32 reg_val;
151 void *walker = &reg_val; 151 void *walker = &reg_val;
152 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
152 153
153 walker += (where & 0x3); 154 walker += (where & 0x3);
154 reg = where & ~0x3; 155 reg = where & ~0x3;
155 reg_val = dw_pcie_readl_rc(pp, reg); 156 reg_val = dw_pcie_readl_dbi(pci, reg);
156 157
157 if (size == 1) 158 if (size == 1)
158 *val = *(u8 __force *) walker; 159 *val = *(u8 __force *) walker;
@@ -173,19 +174,20 @@ static int hisi_pcie_cfg_write(struct pcie_port *pp, int where, int size,
173 u32 reg_val; 174 u32 reg_val;
174 u32 reg; 175 u32 reg;
175 void *walker = &reg_val; 176 void *walker = &reg_val;
177 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
176 178
177 walker += (where & 0x3); 179 walker += (where & 0x3);
178 reg = where & ~0x3; 180 reg = where & ~0x3;
179 if (size == 4) 181 if (size == 4)
180 dw_pcie_writel_rc(pp, reg, val); 182 dw_pcie_writel_dbi(pci, reg, val);
181 else if (size == 2) { 183 else if (size == 2) {
182 reg_val = dw_pcie_readl_rc(pp, reg); 184 reg_val = dw_pcie_readl_dbi(pci, reg);
183 *(u16 __force *) walker = val; 185 *(u16 __force *) walker = val;
184 dw_pcie_writel_rc(pp, reg, reg_val); 186 dw_pcie_writel_dbi(pci, reg, reg_val);
185 } else if (size == 1) { 187 } else if (size == 1) {
186 reg_val = dw_pcie_readl_rc(pp, reg); 188 reg_val = dw_pcie_readl_dbi(pci, reg);
187 *(u8 __force *) walker = val; 189 *(u8 __force *) walker = val;
188 dw_pcie_writel_rc(pp, reg, reg_val); 190 dw_pcie_writel_dbi(pci, reg, reg_val);
189 } else 191 } else
190 return PCIBIOS_BAD_REGISTER_NUMBER; 192 return PCIBIOS_BAD_REGISTER_NUMBER;
191 193
@@ -204,32 +206,32 @@ static int hisi_pcie_link_up_hip05(struct hisi_pcie *hisi_pcie)
204 206
205static int hisi_pcie_link_up_hip06(struct hisi_pcie *hisi_pcie) 207static int hisi_pcie_link_up_hip06(struct hisi_pcie *hisi_pcie)
206{ 208{
207 struct pcie_port *pp = &hisi_pcie->pp; 209 struct dw_pcie *pci = hisi_pcie->pci;
208 u32 val; 210 u32 val;
209 211
210 val = dw_pcie_readl_rc(pp, PCIE_SYS_STATE4); 212 val = dw_pcie_readl_dbi(pci, PCIE_SYS_STATE4);
211 213
212 return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE); 214 return ((val & PCIE_LTSSM_STATE_MASK) == PCIE_LTSSM_LINKUP_STATE);
213} 215}
214 216
215static int hisi_pcie_link_up(struct pcie_port *pp) 217static int hisi_pcie_link_up(struct dw_pcie *pci)
216{ 218{
217 struct hisi_pcie *hisi_pcie = to_hisi_pcie(pp); 219 struct hisi_pcie *hisi_pcie = to_hisi_pcie(pci);
218 220
219 return hisi_pcie->soc_ops->hisi_pcie_link_up(hisi_pcie); 221 return hisi_pcie->soc_ops->hisi_pcie_link_up(hisi_pcie);
220} 222}
221 223
222static struct pcie_host_ops hisi_pcie_host_ops = { 224static struct dw_pcie_host_ops hisi_pcie_host_ops = {
223 .rd_own_conf = hisi_pcie_cfg_read, 225 .rd_own_conf = hisi_pcie_cfg_read,
224 .wr_own_conf = hisi_pcie_cfg_write, 226 .wr_own_conf = hisi_pcie_cfg_write,
225 .link_up = hisi_pcie_link_up,
226}; 227};
227 228
228static int hisi_add_pcie_port(struct hisi_pcie *hisi_pcie, 229static int hisi_add_pcie_port(struct hisi_pcie *hisi_pcie,
229 struct platform_device *pdev) 230 struct platform_device *pdev)
230{ 231{
231 struct pcie_port *pp = &hisi_pcie->pp; 232 struct dw_pcie *pci = hisi_pcie->pci;
232 struct device *dev = pp->dev; 233 struct pcie_port *pp = &pci->pp;
234 struct device *dev = &pdev->dev;
233 int ret; 235 int ret;
234 u32 port_id; 236 u32 port_id;
235 237
@@ -254,11 +256,15 @@ static int hisi_add_pcie_port(struct hisi_pcie *hisi_pcie,
254 return 0; 256 return 0;
255} 257}
256 258
259static const struct dw_pcie_ops dw_pcie_ops = {
260 .link_up = hisi_pcie_link_up,
261};
262
257static int hisi_pcie_probe(struct platform_device *pdev) 263static int hisi_pcie_probe(struct platform_device *pdev)
258{ 264{
259 struct device *dev = &pdev->dev; 265 struct device *dev = &pdev->dev;
266 struct dw_pcie *pci;
260 struct hisi_pcie *hisi_pcie; 267 struct hisi_pcie *hisi_pcie;
261 struct pcie_port *pp;
262 const struct of_device_id *match; 268 const struct of_device_id *match;
263 struct resource *reg; 269 struct resource *reg;
264 struct device_driver *driver; 270 struct device_driver *driver;
@@ -268,8 +274,13 @@ static int hisi_pcie_probe(struct platform_device *pdev)
268 if (!hisi_pcie) 274 if (!hisi_pcie)
269 return -ENOMEM; 275 return -ENOMEM;
270 276
271 pp = &hisi_pcie->pp; 277 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
272 pp->dev = dev; 278 if (!pci)
279 return -ENOMEM;
280
281 pci->dev = dev;
282 pci->ops = &dw_pcie_ops;
283
273 driver = dev->driver; 284 driver = dev->driver;
274 285
275 match = of_match_device(driver->of_match_table, dev); 286 match = of_match_device(driver->of_match_table, dev);
@@ -283,9 +294,9 @@ static int hisi_pcie_probe(struct platform_device *pdev)
283 } 294 }
284 295
285 reg = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbi"); 296 reg = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbi");
286 pp->dbi_base = devm_ioremap_resource(dev, reg); 297 pci->dbi_base = devm_ioremap_resource(dev, reg);
287 if (IS_ERR(pp->dbi_base)) 298 if (IS_ERR(pci->dbi_base))
288 return PTR_ERR(pp->dbi_base); 299 return PTR_ERR(pci->dbi_base);
289 300
290 platform_set_drvdata(pdev, hisi_pcie); 301 platform_set_drvdata(pdev, hisi_pcie);
291 302
diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/pci/dwc/pcie-qcom.c
index ac27b67d303e..e36abe0d9d6f 100644
--- a/drivers/pci/dwc/pcie-qcom.c
+++ b/drivers/pci/dwc/pcie-qcom.c
@@ -103,7 +103,7 @@ struct qcom_pcie_ops {
103}; 103};
104 104
105struct qcom_pcie { 105struct qcom_pcie {
106 struct pcie_port pp; /* pp.dbi_base is DT dbi */ 106 struct dw_pcie *pci;
107 void __iomem *parf; /* DT parf */ 107 void __iomem *parf; /* DT parf */
108 void __iomem *elbi; /* DT elbi */ 108 void __iomem *elbi; /* DT elbi */
109 union qcom_pcie_resources res; 109 union qcom_pcie_resources res;
@@ -112,7 +112,7 @@ struct qcom_pcie {
112 struct qcom_pcie_ops *ops; 112 struct qcom_pcie_ops *ops;
113}; 113};
114 114
115#define to_qcom_pcie(x) container_of(x, struct qcom_pcie, pp) 115#define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
116 116
117static void qcom_ep_reset_assert(struct qcom_pcie *pcie) 117static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
118{ 118{
@@ -155,21 +155,23 @@ static void qcom_pcie_v2_ltssm_enable(struct qcom_pcie *pcie)
155 155
156static int qcom_pcie_establish_link(struct qcom_pcie *pcie) 156static int qcom_pcie_establish_link(struct qcom_pcie *pcie)
157{ 157{
158 struct dw_pcie *pci = pcie->pci;
158 159
159 if (dw_pcie_link_up(&pcie->pp)) 160 if (dw_pcie_link_up(pci))
160 return 0; 161 return 0;
161 162
162 /* Enable Link Training state machine */ 163 /* Enable Link Training state machine */
163 if (pcie->ops->ltssm_enable) 164 if (pcie->ops->ltssm_enable)
164 pcie->ops->ltssm_enable(pcie); 165 pcie->ops->ltssm_enable(pcie);
165 166
166 return dw_pcie_wait_for_link(&pcie->pp); 167 return dw_pcie_wait_for_link(pci);
167} 168}
168 169
169static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie) 170static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie)
170{ 171{
171 struct qcom_pcie_resources_v0 *res = &pcie->res.v0; 172 struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
172 struct device *dev = pcie->pp.dev; 173 struct dw_pcie *pci = pcie->pci;
174 struct device *dev = pci->dev;
173 175
174 res->vdda = devm_regulator_get(dev, "vdda"); 176 res->vdda = devm_regulator_get(dev, "vdda");
175 if (IS_ERR(res->vdda)) 177 if (IS_ERR(res->vdda))
@@ -218,7 +220,8 @@ static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie)
218static int qcom_pcie_get_resources_v1(struct qcom_pcie *pcie) 220static int qcom_pcie_get_resources_v1(struct qcom_pcie *pcie)
219{ 221{
220 struct qcom_pcie_resources_v1 *res = &pcie->res.v1; 222 struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
221 struct device *dev = pcie->pp.dev; 223 struct dw_pcie *pci = pcie->pci;
224 struct device *dev = pci->dev;
222 225
223 res->vdda = devm_regulator_get(dev, "vdda"); 226 res->vdda = devm_regulator_get(dev, "vdda");
224 if (IS_ERR(res->vdda)) 227 if (IS_ERR(res->vdda))
@@ -264,7 +267,8 @@ static void qcom_pcie_deinit_v0(struct qcom_pcie *pcie)
264static int qcom_pcie_init_v0(struct qcom_pcie *pcie) 267static int qcom_pcie_init_v0(struct qcom_pcie *pcie)
265{ 268{
266 struct qcom_pcie_resources_v0 *res = &pcie->res.v0; 269 struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
267 struct device *dev = pcie->pp.dev; 270 struct dw_pcie *pci = pcie->pci;
271 struct device *dev = pci->dev;
268 u32 val; 272 u32 val;
269 int ret; 273 int ret;
270 274
@@ -386,7 +390,8 @@ static void qcom_pcie_deinit_v1(struct qcom_pcie *pcie)
386static int qcom_pcie_init_v1(struct qcom_pcie *pcie) 390static int qcom_pcie_init_v1(struct qcom_pcie *pcie)
387{ 391{
388 struct qcom_pcie_resources_v1 *res = &pcie->res.v1; 392 struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
389 struct device *dev = pcie->pp.dev; 393 struct dw_pcie *pci = pcie->pci;
394 struct device *dev = pci->dev;
390 int ret; 395 int ret;
391 396
392 ret = reset_control_deassert(res->core); 397 ret = reset_control_deassert(res->core);
@@ -453,7 +458,8 @@ err_res:
453static int qcom_pcie_get_resources_v2(struct qcom_pcie *pcie) 458static int qcom_pcie_get_resources_v2(struct qcom_pcie *pcie)
454{ 459{
455 struct qcom_pcie_resources_v2 *res = &pcie->res.v2; 460 struct qcom_pcie_resources_v2 *res = &pcie->res.v2;
456 struct device *dev = pcie->pp.dev; 461 struct dw_pcie *pci = pcie->pci;
462 struct device *dev = pci->dev;
457 463
458 res->aux_clk = devm_clk_get(dev, "aux"); 464 res->aux_clk = devm_clk_get(dev, "aux");
459 if (IS_ERR(res->aux_clk)) 465 if (IS_ERR(res->aux_clk))
@@ -478,7 +484,8 @@ static int qcom_pcie_get_resources_v2(struct qcom_pcie *pcie)
478static int qcom_pcie_init_v2(struct qcom_pcie *pcie) 484static int qcom_pcie_init_v2(struct qcom_pcie *pcie)
479{ 485{
480 struct qcom_pcie_resources_v2 *res = &pcie->res.v2; 486 struct qcom_pcie_resources_v2 *res = &pcie->res.v2;
481 struct device *dev = pcie->pp.dev; 487 struct dw_pcie *pci = pcie->pci;
488 struct device *dev = pci->dev;
482 u32 val; 489 u32 val;
483 int ret; 490 int ret;
484 491
@@ -542,7 +549,8 @@ err_cfg_clk:
542static int qcom_pcie_post_init_v2(struct qcom_pcie *pcie) 549static int qcom_pcie_post_init_v2(struct qcom_pcie *pcie)
543{ 550{
544 struct qcom_pcie_resources_v2 *res = &pcie->res.v2; 551 struct qcom_pcie_resources_v2 *res = &pcie->res.v2;
545 struct device *dev = pcie->pp.dev; 552 struct dw_pcie *pci = pcie->pci;
553 struct device *dev = pci->dev;
546 int ret; 554 int ret;
547 555
548 ret = clk_prepare_enable(res->pipe_clk); 556 ret = clk_prepare_enable(res->pipe_clk);
@@ -554,10 +562,9 @@ static int qcom_pcie_post_init_v2(struct qcom_pcie *pcie)
554 return 0; 562 return 0;
555} 563}
556 564
557static int qcom_pcie_link_up(struct pcie_port *pp) 565static int qcom_pcie_link_up(struct dw_pcie *pci)
558{ 566{
559 struct qcom_pcie *pcie = to_qcom_pcie(pp); 567 u16 val = readw(pci->dbi_base + PCIE20_CAP + PCI_EXP_LNKSTA);
560 u16 val = readw(pcie->pp.dbi_base + PCIE20_CAP + PCI_EXP_LNKSTA);
561 568
562 return !!(val & PCI_EXP_LNKSTA_DLLLA); 569 return !!(val & PCI_EXP_LNKSTA_DLLLA);
563} 570}
@@ -575,7 +582,8 @@ static void qcom_pcie_deinit_v2(struct qcom_pcie *pcie)
575 582
576static void qcom_pcie_host_init(struct pcie_port *pp) 583static void qcom_pcie_host_init(struct pcie_port *pp)
577{ 584{
578 struct qcom_pcie *pcie = to_qcom_pcie(pp); 585 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
586 struct qcom_pcie *pcie = to_qcom_pcie(pci);
579 int ret; 587 int ret;
580 588
581 qcom_ep_reset_assert(pcie); 589 qcom_ep_reset_assert(pcie);
@@ -613,19 +621,20 @@ err_deinit:
613static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, 621static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
614 u32 *val) 622 u32 *val)
615{ 623{
624 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
625
616 /* the device class is not reported correctly from the register */ 626 /* the device class is not reported correctly from the register */
617 if (where == PCI_CLASS_REVISION && size == 4) { 627 if (where == PCI_CLASS_REVISION && size == 4) {
618 *val = readl(pp->dbi_base + PCI_CLASS_REVISION); 628 *val = readl(pci->dbi_base + PCI_CLASS_REVISION);
619 *val &= 0xff; /* keep revision id */ 629 *val &= 0xff; /* keep revision id */
620 *val |= PCI_CLASS_BRIDGE_PCI << 16; 630 *val |= PCI_CLASS_BRIDGE_PCI << 16;
621 return PCIBIOS_SUCCESSFUL; 631 return PCIBIOS_SUCCESSFUL;
622 } 632 }
623 633
624 return dw_pcie_read(pp->dbi_base + where, size, val); 634 return dw_pcie_read(pci->dbi_base + where, size, val);
625} 635}
626 636
627static struct pcie_host_ops qcom_pcie_dw_ops = { 637static struct dw_pcie_host_ops qcom_pcie_dw_ops = {
628 .link_up = qcom_pcie_link_up,
629 .host_init = qcom_pcie_host_init, 638 .host_init = qcom_pcie_host_init,
630 .rd_own_conf = qcom_pcie_rd_own_conf, 639 .rd_own_conf = qcom_pcie_rd_own_conf,
631}; 640};
@@ -652,19 +661,31 @@ static const struct qcom_pcie_ops ops_v2 = {
652 .ltssm_enable = qcom_pcie_v2_ltssm_enable, 661 .ltssm_enable = qcom_pcie_v2_ltssm_enable,
653}; 662};
654 663
664static const struct dw_pcie_ops dw_pcie_ops = {
665 .link_up = qcom_pcie_link_up,
666};
667
655static int qcom_pcie_probe(struct platform_device *pdev) 668static int qcom_pcie_probe(struct platform_device *pdev)
656{ 669{
657 struct device *dev = &pdev->dev; 670 struct device *dev = &pdev->dev;
658 struct resource *res; 671 struct resource *res;
659 struct qcom_pcie *pcie;
660 struct pcie_port *pp; 672 struct pcie_port *pp;
673 struct dw_pcie *pci;
674 struct qcom_pcie *pcie;
661 int ret; 675 int ret;
662 676
663 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); 677 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
664 if (!pcie) 678 if (!pcie)
665 return -ENOMEM; 679 return -ENOMEM;
666 680
667 pp = &pcie->pp; 681 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
682 if (!pci)
683 return -ENOMEM;
684
685 pci->dev = dev;
686 pci->ops = &dw_pcie_ops;
687 pp = &pci->pp;
688
668 pcie->ops = (struct qcom_pcie_ops *)of_device_get_match_data(dev); 689 pcie->ops = (struct qcom_pcie_ops *)of_device_get_match_data(dev);
669 690
670 pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_LOW); 691 pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_LOW);
@@ -677,9 +698,9 @@ static int qcom_pcie_probe(struct platform_device *pdev)
677 return PTR_ERR(pcie->parf); 698 return PTR_ERR(pcie->parf);
678 699
679 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 700 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
680 pp->dbi_base = devm_ioremap_resource(dev, res); 701 pci->dbi_base = devm_ioremap_resource(dev, res);
681 if (IS_ERR(pp->dbi_base)) 702 if (IS_ERR(pci->dbi_base))
682 return PTR_ERR(pp->dbi_base); 703 return PTR_ERR(pci->dbi_base);
683 704
684 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi"); 705 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
685 pcie->elbi = devm_ioremap_resource(dev, res); 706 pcie->elbi = devm_ioremap_resource(dev, res);
@@ -690,7 +711,6 @@ static int qcom_pcie_probe(struct platform_device *pdev)
690 if (IS_ERR(pcie->phy)) 711 if (IS_ERR(pcie->phy))
691 return PTR_ERR(pcie->phy); 712 return PTR_ERR(pcie->phy);
692 713
693 pp->dev = dev;
694 ret = pcie->ops->get_resources(pcie); 714 ret = pcie->ops->get_resources(pcie);
695 if (ret) 715 if (ret)
696 return ret; 716 return ret;
diff --git a/drivers/pci/dwc/pcie-spear13xx.c b/drivers/pci/dwc/pcie-spear13xx.c
index 7acf91e07f5d..348f9c5e0433 100644
--- a/drivers/pci/dwc/pcie-spear13xx.c
+++ b/drivers/pci/dwc/pcie-spear13xx.c
@@ -25,7 +25,7 @@
25#include "pcie-designware.h" 25#include "pcie-designware.h"
26 26
27struct spear13xx_pcie { 27struct spear13xx_pcie {
28 struct pcie_port pp; /* DT dbi is pp.dbi_base */ 28 struct dw_pcie *pci;
29 void __iomem *app_base; 29 void __iomem *app_base;
30 struct phy *phy; 30 struct phy *phy;
31 struct clk *clk; 31 struct clk *clk;
@@ -70,17 +70,18 @@ struct pcie_app_reg {
70 70
71#define EXP_CAP_ID_OFFSET 0x70 71#define EXP_CAP_ID_OFFSET 0x70
72 72
73#define to_spear13xx_pcie(x) container_of(x, struct spear13xx_pcie, pp) 73#define to_spear13xx_pcie(x) dev_get_drvdata((x)->dev)
74 74
75static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie) 75static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie)
76{ 76{
77 struct pcie_port *pp = &spear13xx_pcie->pp; 77 struct dw_pcie *pci = spear13xx_pcie->pci;
78 struct pcie_port *pp = &pci->pp;
78 struct pcie_app_reg *app_reg = spear13xx_pcie->app_base; 79 struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
79 u32 val; 80 u32 val;
80 u32 exp_cap_off = EXP_CAP_ID_OFFSET; 81 u32 exp_cap_off = EXP_CAP_ID_OFFSET;
81 82
82 if (dw_pcie_link_up(pp)) { 83 if (dw_pcie_link_up(pci)) {
83 dev_err(pp->dev, "link already up\n"); 84 dev_err(pci->dev, "link already up\n");
84 return 0; 85 return 0;
85 } 86 }
86 87
@@ -91,33 +92,33 @@ static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie)
91 * default value in capability register is 512 bytes. So force 92 * default value in capability register is 512 bytes. So force
92 * it to 128 here. 93 * it to 128 here.
93 */ 94 */
94 dw_pcie_read(pp->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, &val); 95 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, &val);
95 val &= ~PCI_EXP_DEVCTL_READRQ; 96 val &= ~PCI_EXP_DEVCTL_READRQ;
96 dw_pcie_write(pp->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, val); 97 dw_pcie_write(pci->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, val);
97 98
98 dw_pcie_write(pp->dbi_base + PCI_VENDOR_ID, 2, 0x104A); 99 dw_pcie_write(pci->dbi_base + PCI_VENDOR_ID, 2, 0x104A);
99 dw_pcie_write(pp->dbi_base + PCI_DEVICE_ID, 2, 0xCD80); 100 dw_pcie_write(pci->dbi_base + PCI_DEVICE_ID, 2, 0xCD80);
100 101
101 /* 102 /*
102 * if is_gen1 is set then handle it, so that some buggy card 103 * if is_gen1 is set then handle it, so that some buggy card
103 * also works 104 * also works
104 */ 105 */
105 if (spear13xx_pcie->is_gen1) { 106 if (spear13xx_pcie->is_gen1) {
106 dw_pcie_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP, 107 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
107 4, &val); 108 4, &val);
108 if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { 109 if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
109 val &= ~((u32)PCI_EXP_LNKCAP_SLS); 110 val &= ~((u32)PCI_EXP_LNKCAP_SLS);
110 val |= PCI_EXP_LNKCAP_SLS_2_5GB; 111 val |= PCI_EXP_LNKCAP_SLS_2_5GB;
111 dw_pcie_write(pp->dbi_base + exp_cap_off + 112 dw_pcie_write(pci->dbi_base + exp_cap_off +
112 PCI_EXP_LNKCAP, 4, val); 113 PCI_EXP_LNKCAP, 4, val);
113 } 114 }
114 115
115 dw_pcie_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2, 116 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
116 2, &val); 117 2, &val);
117 if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { 118 if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
118 val &= ~((u32)PCI_EXP_LNKCAP_SLS); 119 val &= ~((u32)PCI_EXP_LNKCAP_SLS);
119 val |= PCI_EXP_LNKCAP_SLS_2_5GB; 120 val |= PCI_EXP_LNKCAP_SLS_2_5GB;
120 dw_pcie_write(pp->dbi_base + exp_cap_off + 121 dw_pcie_write(pci->dbi_base + exp_cap_off +
121 PCI_EXP_LNKCTL2, 2, val); 122 PCI_EXP_LNKCTL2, 2, val);
122 } 123 }
123 } 124 }
@@ -128,14 +129,15 @@ static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie)
128 | ((u32)1 << REG_TRANSLATION_ENABLE), 129 | ((u32)1 << REG_TRANSLATION_ENABLE),
129 &app_reg->app_ctrl_0); 130 &app_reg->app_ctrl_0);
130 131
131 return dw_pcie_wait_for_link(pp); 132 return dw_pcie_wait_for_link(pci);
132} 133}
133 134
134static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg) 135static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
135{ 136{
136 struct spear13xx_pcie *spear13xx_pcie = arg; 137 struct spear13xx_pcie *spear13xx_pcie = arg;
137 struct pcie_app_reg *app_reg = spear13xx_pcie->app_base; 138 struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
138 struct pcie_port *pp = &spear13xx_pcie->pp; 139 struct dw_pcie *pci = spear13xx_pcie->pci;
140 struct pcie_port *pp = &pci->pp;
139 unsigned int status; 141 unsigned int status;
140 142
141 status = readl(&app_reg->int_sts); 143 status = readl(&app_reg->int_sts);
@@ -152,7 +154,8 @@ static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
152 154
153static void spear13xx_pcie_enable_interrupts(struct spear13xx_pcie *spear13xx_pcie) 155static void spear13xx_pcie_enable_interrupts(struct spear13xx_pcie *spear13xx_pcie)
154{ 156{
155 struct pcie_port *pp = &spear13xx_pcie->pp; 157 struct dw_pcie *pci = spear13xx_pcie->pci;
158 struct pcie_port *pp = &pci->pp;
156 struct pcie_app_reg *app_reg = spear13xx_pcie->app_base; 159 struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
157 160
158 /* Enable MSI interrupt */ 161 /* Enable MSI interrupt */
@@ -163,9 +166,9 @@ static void spear13xx_pcie_enable_interrupts(struct spear13xx_pcie *spear13xx_pc
163 } 166 }
164} 167}
165 168
166static int spear13xx_pcie_link_up(struct pcie_port *pp) 169static int spear13xx_pcie_link_up(struct dw_pcie *pci)
167{ 170{
168 struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp); 171 struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci);
169 struct pcie_app_reg *app_reg = spear13xx_pcie->app_base; 172 struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
170 173
171 if (readl(&app_reg->app_status_1) & XMLH_LINK_UP) 174 if (readl(&app_reg->app_status_1) & XMLH_LINK_UP)
@@ -176,22 +179,23 @@ static int spear13xx_pcie_link_up(struct pcie_port *pp)
176 179
177static void spear13xx_pcie_host_init(struct pcie_port *pp) 180static void spear13xx_pcie_host_init(struct pcie_port *pp)
178{ 181{
179 struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp); 182 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
183 struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci);
180 184
181 spear13xx_pcie_establish_link(spear13xx_pcie); 185 spear13xx_pcie_establish_link(spear13xx_pcie);
182 spear13xx_pcie_enable_interrupts(spear13xx_pcie); 186 spear13xx_pcie_enable_interrupts(spear13xx_pcie);
183} 187}
184 188
185static struct pcie_host_ops spear13xx_pcie_host_ops = { 189static struct dw_pcie_host_ops spear13xx_pcie_host_ops = {
186 .link_up = spear13xx_pcie_link_up,
187 .host_init = spear13xx_pcie_host_init, 190 .host_init = spear13xx_pcie_host_init,
188}; 191};
189 192
190static int spear13xx_add_pcie_port(struct spear13xx_pcie *spear13xx_pcie, 193static int spear13xx_add_pcie_port(struct spear13xx_pcie *spear13xx_pcie,
191 struct platform_device *pdev) 194 struct platform_device *pdev)
192{ 195{
193 struct pcie_port *pp = &spear13xx_pcie->pp; 196 struct dw_pcie *pci = spear13xx_pcie->pci;
194 struct device *dev = pp->dev; 197 struct pcie_port *pp = &pci->pp;
198 struct device *dev = &pdev->dev;
195 int ret; 199 int ret;
196 200
197 pp->irq = platform_get_irq(pdev, 0); 201 pp->irq = platform_get_irq(pdev, 0);
@@ -219,11 +223,15 @@ static int spear13xx_add_pcie_port(struct spear13xx_pcie *spear13xx_pcie,
219 return 0; 223 return 0;
220} 224}
221 225
226static const struct dw_pcie_ops dw_pcie_ops = {
227 .link_up = spear13xx_pcie_link_up,
228};
229
222static int spear13xx_pcie_probe(struct platform_device *pdev) 230static int spear13xx_pcie_probe(struct platform_device *pdev)
223{ 231{
224 struct device *dev = &pdev->dev; 232 struct device *dev = &pdev->dev;
233 struct dw_pcie *pci;
225 struct spear13xx_pcie *spear13xx_pcie; 234 struct spear13xx_pcie *spear13xx_pcie;
226 struct pcie_port *pp;
227 struct device_node *np = dev->of_node; 235 struct device_node *np = dev->of_node;
228 struct resource *dbi_base; 236 struct resource *dbi_base;
229 int ret; 237 int ret;
@@ -232,6 +240,13 @@ static int spear13xx_pcie_probe(struct platform_device *pdev)
232 if (!spear13xx_pcie) 240 if (!spear13xx_pcie)
233 return -ENOMEM; 241 return -ENOMEM;
234 242
243 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
244 if (!pci)
245 return -ENOMEM;
246
247 pci->dev = dev;
248 pci->ops = &dw_pcie_ops;
249
235 spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy"); 250 spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
236 if (IS_ERR(spear13xx_pcie->phy)) { 251 if (IS_ERR(spear13xx_pcie->phy)) {
237 ret = PTR_ERR(spear13xx_pcie->phy); 252 ret = PTR_ERR(spear13xx_pcie->phy);
@@ -255,17 +270,14 @@ static int spear13xx_pcie_probe(struct platform_device *pdev)
255 return ret; 270 return ret;
256 } 271 }
257 272
258 pp = &spear13xx_pcie->pp;
259 pp->dev = dev;
260
261 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); 273 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
262 pp->dbi_base = devm_ioremap_resource(dev, dbi_base); 274 pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
263 if (IS_ERR(pp->dbi_base)) { 275 if (IS_ERR(pci->dbi_base)) {
264 dev_err(dev, "couldn't remap dbi base %p\n", dbi_base); 276 dev_err(dev, "couldn't remap dbi base %p\n", dbi_base);
265 ret = PTR_ERR(pp->dbi_base); 277 ret = PTR_ERR(pci->dbi_base);
266 goto fail_clk; 278 goto fail_clk;
267 } 279 }
268 spear13xx_pcie->app_base = pp->dbi_base + 0x2000; 280 spear13xx_pcie->app_base = pci->dbi_base + 0x2000;
269 281
270 if (of_property_read_bool(np, "st,pcie-is-gen1")) 282 if (of_property_read_bool(np, "st,pcie-is-gen1"))
271 spear13xx_pcie->is_gen1 = true; 283 spear13xx_pcie->is_gen1 = true;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-22 22:39:23 -0400