Merge tag 'sunxi-dt-for-4.7-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/dt

Merge "Allwinner DT changes for 4.7, round 2" from Maxime Ripard:

Mostly DT patches to enable the new DRM driver on the CHIP, preliminary
support for the A10 and A20, and a support for a new variant of the Olimex
A20-Olinuxino-Lime2 featuring an eMMC

* tag 'sunxi-dt-for-4.7-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
  ARM: sun7i: dt: Add pll3 and pll7 clocks
  ARM: dts: sunxi: Add a olinuxino-lime2-emmc
  ARM: sun4i: dt: Add pll3 and pll7 clocks
  ARM: sun5i: chip: Enable the TV Encoder
  ARM: sun5i: r8: Add display blocks to the DTSI
  ARM: sun5i: a13: Add display and TCON clocks

6 files changed, 355 insertions, 4 deletions

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 268a1504d984..a03e56fb5dbc 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -184,6 +184,15 @@
                         clock-output-names = "osc24M";
                 };
 
+                osc3M: osc3M_clk {
+                        compatible = "fixed-factor-clock";
+                        #clock-cells = <0>;
+                        clock-div = <8>;
+                        clock-mult = <1>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "osc3M";
+                };
+
                 osc32k: clk@0 {
                         #clock-cells = <0>;
                         compatible = "fixed-clock";
@@ -208,6 +217,23 @@
                                              "pll2-4x", "pll2-8x";
                 };
 
+                pll3: clk@01c20010 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-pll3-clk";
+                        reg = <0x01c20010 0x4>;
+                        clocks = <&osc3M>;
+                        clock-output-names = "pll3";
+                };
+
+                pll3x2: pll3x2_clk {
+                        compatible = "fixed-factor-clock";
+                        #clock-cells = <0>;
+                        clock-div = <1>;
+                        clock-mult = <2>;
+                        clocks = <&pll3>;
+                        clock-output-names = "pll3-2x";
+                };
+
                 pll4: clk@01c20018 {
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-a10-pll1-clk";
@@ -232,6 +258,23 @@
                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
                 };
 
+                pll7: clk@01c20030 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-pll3-clk";
+                        reg = <0x01c20030 0x4>;
+                        clocks = <&osc3M>;
+                        clock-output-names = "pll7";
+                };
+
+                pll7x2: pll7x2_clk {
+                        compatible = "fixed-factor-clock";
+                        #clock-cells = <0>;
+                        clock-div = <1>;
+                        clock-mult = <2>;
+                        clocks = <&pll7>;
+                        clock-output-names = "pll7-2x";
+                };
+
                 /* dummy is 200M */
                 cpu: cpu@01c20054 {
                         #clock-cells = <0>;
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 39f23b1ebc8f..263d46dbc7e6 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -61,8 +61,8 @@
                         compatible = "allwinner,simple-framebuffer",
                                      "simple-framebuffer";
                         allwinner,pipeline = "de_be0-lcd0";
-                        clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
-                                 <&dram_gates 26>;
+                        clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&de_be_clk>,
+                                 <&tcon_ch0_clk>, <&dram_gates 26>;
                         status = "disabled";
                 };
         };
@@ -170,6 +170,41 @@
                                              "dram_ace",
                                              "dram_iep";
                 };
+
+                de_be_clk: clk@01c20104 {
+                        #clock-cells = <0>;
+                        #reset-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-display-clk";
+                        reg = <0x01c20104 0x4>;
+                        clocks = <&pll3>, <&pll7>, <&pll5 1>;
+                        clock-output-names = "de-be";
+                };
+
+                de_fe_clk: clk@01c2010c {
+                        #clock-cells = <0>;
+                        #reset-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-display-clk";
+                        reg = <0x01c2010c 0x4>;
+                        clocks = <&pll3>, <&pll7>, <&pll5 1>;
+                        clock-output-names = "de-fe";
+                };
+
+                tcon_ch0_clk: clk@01c20118 {
+                        #clock-cells = <0>;
+                        #reset-cells = <1>;
+                        compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
+                        reg = <0x01c20118 0x4>;
+                        clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
+                        clock-output-names = "tcon-ch0-sclk";
+                };
+
+                tcon_ch1_clk: clk@01c2012c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
+                        reg = <0x01c2012c 0x4>;
+                        clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
+                        clock-output-names = "tcon-ch1-sclk";
+                };
         };
 
         soc@01c00000 {
diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts
index f6898c6b84d4..a8d8b4582397 100644
--- a/arch/arm/boot/dts/sun5i-r8-chip.dts
+++ b/arch/arm/boot/dts/sun5i-r8-chip.dts
@@ -66,6 +66,10 @@
         };
 };
 
+&be0 {
+        status = "okay";
+};
+
 &codec {
         status = "okay";
 };
@@ -188,6 +192,14 @@
         status = "okay";
 };
 
+&tcon0 {
+        status = "okay";
+};
+
+&tve0 {
+        status = "okay";
+};
+
 &uart1 {
         pinctrl-names = "default";
         pinctrl-0 = <&uart1_pins_b>;
diff --git a/arch/arm/boot/dts/sun5i-r8.dtsi b/arch/arm/boot/dts/sun5i-r8.dtsi
index e346ba76db5d..c04cf690b858 100644
--- a/arch/arm/boot/dts/sun5i-r8.dtsi
+++ b/arch/arm/boot/dts/sun5i-r8.dtsi
@@ -51,9 +51,147 @@
                         compatible = "allwinner,simple-framebuffer",
                                      "simple-framebuffer";
                         allwinner,pipeline = "de_be0-lcd0-tve0";
-                        clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
-                                 <&ahb_gates 44>, <&dram_gates 26>;
+                        clocks = <&ahb_gates 34>, <&ahb_gates 36>,
+                                 <&ahb_gates 44>, <&de_be_clk>,
+                                 <&tcon_ch1_clk>, <&dram_gates 26>;
                         status = "disabled";
                 };
         };
+
+        soc@01c00000 {
+                tve0: tv-encoder@01c0a000 {
+                        compatible = "allwinner,sun4i-a10-tv-encoder";
+                        reg = <0x01c0a000 0x1000>;
+                        clocks = <&ahb_gates 34>;
+                        resets = <&tcon_ch0_clk 0>;
+                        status = "disabled";
+
+                        port {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                tve0_in_tcon0: endpoint@0 {
+                                        reg = <0>;
+                                        remote-endpoint = <&tcon0_out_tve0>;
+                                };
+                        };
+                };
+
+                tcon0: lcd-controller@01c0c000 {
+                        compatible = "allwinner,sun5i-a13-tcon";
+                        reg = <0x01c0c000 0x1000>;
+                        interrupts = <44>;
+                        resets = <&tcon_ch0_clk 1>;
+                        reset-names = "lcd";
+                        clocks = <&ahb_gates 36>,
+                                 <&tcon_ch0_clk>,
+                                 <&tcon_ch1_clk>;
+                        clock-names = "ahb",
+                                      "tcon-ch0",
+                                      "tcon-ch1";
+                        clock-output-names = "tcon-pixel-clock";
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                tcon0_in: port@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <0>;
+
+                                        tcon0_in_be0: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&be0_out_tcon0>;
+                                        };
+                                };
+
+                                tcon0_out: port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <1>;
+
+                                        tcon0_out_tve0: endpoint@1 {
+                                                reg = <1>;
+                                                remote-endpoint = <&tve0_in_tcon0>;
+                                        };
+                                };
+                        };
+                };
+
+                fe0: display-frontend@01e00000 {
+                        compatible = "allwinner,sun5i-a13-display-frontend";
+                        reg = <0x01e00000 0x20000>;
+                        interrupts = <47>;
+                        clocks = <&ahb_gates 46>, <&de_fe_clk>,
+                                 <&dram_gates 25>;
+                        clock-names = "ahb", "mod",
+                                      "ram";
+                        resets = <&de_fe_clk>;
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                fe0_out: port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <1>;
+
+                                        fe0_out_be0: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&be0_in_fe0>;
+                                        };
+                                };
+                        };
+                };
+
+                be0: display-backend@01e60000 {
+                        compatible = "allwinner,sun5i-a13-display-backend";
+                        reg = <0x01e60000 0x10000>;
+                        clocks = <&ahb_gates 44>, <&de_be_clk>,
+                                 <&dram_gates 26>;
+                        clock-names = "ahb", "mod",
+                                      "ram";
+                        resets = <&de_be_clk>;
+                        status = "disabled";
+
+                        assigned-clocks = <&de_be_clk>;
+                        assigned-clock-rates = <300000000>;
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                be0_in: port@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <0>;
+
+                                        be0_in_fe0: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&fe0_out_be0>;
+                                        };
+                                };
+
+                                be0_out: port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <1>;
+
+                                        be0_out_tcon0: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&tcon0_in_be0>;
+                                        };
+                                };
+                        };
+                };
+        };
+
+        display-engine {
+                compatible = "allwinner,sun5i-a13-display-engine";
+                allwinner,pipelines = <&fe0>;
+        };
 };
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts
new file mode 100644
index 000000000000..5ea4915f6d75
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts
@@ -0,0 +1,82 @@
+ /*
+ * Copyright 2015 - Ultimaker B.V.
+ * Author Olliver Schinagl <oliver@schinagl.nl>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sun7i-a20-olinuxino-lime2.dts"
+
+/ {
+        model = "Olimex A20-OLinuXino-LIME2-eMMC";
+        compatible = "olimex,a20-olinuxino-lime2-emmc", "allwinner,sun7i-a20";
+
+        mmc2_pwrseq: pwrseq {
+                pinctrl-0 = <&mmc2_pins_nrst>;
+                pinctrl-names = "default";
+                compatible = "mmc-pwrseq-emmc";
+                reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>;
+        };
+};
+
+&pio {
+        mmc2_pins_nrst: mmc2@0 {
+                allwinner,pins = "PC16";
+                allwinner,function = "gpio_out";
+                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+        };
+};
+
+&mmc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_pins_a>;
+        vmmc-supply = <&reg_vcc3v3>;
+        vqmmc-supply = <&reg_vcc3v3>;
+        bus-width = <4>;
+        non-removable;
+        mmc-pwrseq = <&mmc2_pwrseq>;
+        status = "okay";
+
+        emmc: emmc@0 {
+                reg = <0>;
+                compatible = "mmc-card";
+                broken-hpi;
+        };
+};
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index bf5d05685d7d..febdf4c72fb0 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -187,6 +187,15 @@
                         clock-output-names = "osc24M";
                 };
 
+                osc3M: osc3M_clk {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <8>;
+                        clock-mult = <1>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "osc3M";
+                };
+
                 osc32k: clk@0 {
                         #clock-cells = <0>;
                         compatible = "fixed-clock";
@@ -211,6 +220,22 @@
                                              "pll2-4x", "pll2-8x";
                 };
 
+                pll3: clk@01c20010 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-pll3-clk";
+                        reg = <0x01c20010 0x4>;
+                        clocks = <&osc3M>;
+                        clock-output-names = "pll3";
+                };
+
+                pll3x2: pll3x2_clk {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <1>;
+                        clock-mult = <2>;
+                        clock-output-names = "pll3-2x";
+                };
+
                 pll4: clk@01c20018 {
                         #clock-cells = <0>;
                         compatible = "allwinner,sun7i-a20-pll4-clk";
@@ -236,6 +261,22 @@
                                              "pll6_div_4";
                 };
 
+                pll7: clk@01c20030 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-pll3-clk";
+                        reg = <0x01c20030 0x4>;
+                        clocks = <&osc3M>;
+                        clock-output-names = "pll7";
+                };
+
+                pll7x2: pll7x2_clk {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <1>;
+                        clock-mult = <2>;
+                        clock-output-names = "pll7-2x";
+                };
+
                 pll8: clk@01c20040 {
                         #clock-cells = <0>;
                         compatible = "allwinner,sun7i-a20-pll4-clk";