aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorHariprasad Shenai <hariprasad@chelsio.com>2015-01-05 06:00:47 -0500
committerDavid S. Miller <davem@davemloft.net>2015-01-05 16:34:48 -0500
commit0d8043389bf3abc86016995bfe3d3314dd5b3db7 (patch)
treedebb2518945bbe8c781fc9e9acc36a614a2f9bee
parent837e4a42bbb5c41ce555bcd544a9c24c28134e24 (diff)
cxgb4/cxgb4vf/csiostor: Cleanup PL, XGMAC, SF and MC related register defines
This patch cleanups all PL, XGMAC and SF related macros/register defines that are defined in t4_regs.h and the affected files Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c56
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/l2t.c9
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/t4_hw.c258
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/t4_regs.h538
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/t4_values.h33
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c2
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c6
-rw-r--r--drivers/scsi/csiostor/csio_hw.c186
-rw-r--r--drivers/scsi/csiostor/csio_hw.h8
-rw-r--r--drivers/scsi/csiostor/csio_hw_chip.h4
-rw-r--r--drivers/scsi/csiostor/csio_mb.c6
-rw-r--r--drivers/scsi/csiostor/csio_wr.c2
12 files changed, 594 insertions, 514 deletions
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
index 53ad8d3d9e4c..04e675b8218a 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
@@ -834,11 +834,11 @@ static void disable_msi(struct adapter *adapter)
834static irqreturn_t t4_nondata_intr(int irq, void *cookie) 834static irqreturn_t t4_nondata_intr(int irq, void *cookie)
835{ 835{
836 struct adapter *adap = cookie; 836 struct adapter *adap = cookie;
837 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A));
837 838
838 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE)); 839 if (v & PFSW_F) {
839 if (v & PFSW) {
840 adap->swintr = 1; 840 adap->swintr = 1;
841 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE), v); 841 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
842 } 842 }
843 t4_slow_intr_handler(adap); 843 t4_slow_intr_handler(adap);
844 return IRQ_HANDLED; 844 return IRQ_HANDLED;
@@ -3654,10 +3654,10 @@ void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
3654{ 3654{
3655 struct adapter *adap = netdev2adap(dev); 3655 struct adapter *adap = netdev2adap(dev);
3656 3656
3657 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK, tag_mask); 3657 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask);
3658 t4_write_reg(adap, ULP_RX_ISCSI_PSZ, HPZ0(pgsz_order[0]) | 3658 t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) |
3659 HPZ1(pgsz_order[1]) | HPZ2(pgsz_order[2]) | 3659 HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) |
3660 HPZ3(pgsz_order[3])); 3660 HPZ3_V(pgsz_order[3]));
3661} 3661}
3662EXPORT_SYMBOL(cxgb4_iscsi_init); 3662EXPORT_SYMBOL(cxgb4_iscsi_init);
3663 3663
@@ -4580,13 +4580,13 @@ int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
4580 f->fs.val.lip[i] = val[i]; 4580 f->fs.val.lip[i] = val[i];
4581 f->fs.mask.lip[i] = ~0; 4581 f->fs.mask.lip[i] = ~0;
4582 } 4582 }
4583 if (adap->params.tp.vlan_pri_map & F_PORT) { 4583 if (adap->params.tp.vlan_pri_map & PORT_F) {
4584 f->fs.val.iport = port; 4584 f->fs.val.iport = port;
4585 f->fs.mask.iport = mask; 4585 f->fs.mask.iport = mask;
4586 } 4586 }
4587 } 4587 }
4588 4588
4589 if (adap->params.tp.vlan_pri_map & F_PROTOCOL) { 4589 if (adap->params.tp.vlan_pri_map & PROTOCOL_F) {
4590 f->fs.val.proto = IPPROTO_TCP; 4590 f->fs.val.proto = IPPROTO_TCP;
4591 f->fs.mask.proto = ~0; 4591 f->fs.mask.proto = ~0;
4592 } 4592 }
@@ -4950,37 +4950,37 @@ static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
4950 4950
4951 /* tweak some settings */ 4951 /* tweak some settings */
4952 t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849); 4952 t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849);
4953 t4_write_reg(adap, ULP_RX_TDDP_PSZ, HPZ0(PAGE_SHIFT - 12)); 4953 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12));
4954 t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A); 4954 t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A);
4955 v = t4_read_reg(adap, TP_PIO_DATA_A); 4955 v = t4_read_reg(adap, TP_PIO_DATA_A);
4956 t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F); 4956 t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F);
4957 4957
4958 /* first 4 Tx modulation queues point to consecutive Tx channels */ 4958 /* first 4 Tx modulation queues point to consecutive Tx channels */
4959 adap->params.tp.tx_modq_map = 0xE4; 4959 adap->params.tp.tx_modq_map = 0xE4;
4960 t4_write_reg(adap, A_TP_TX_MOD_QUEUE_REQ_MAP, 4960 t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A,
4961 V_TX_MOD_QUEUE_REQ_MAP(adap->params.tp.tx_modq_map)); 4961 TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map));
4962 4962
4963 /* associate each Tx modulation queue with consecutive Tx channels */ 4963 /* associate each Tx modulation queue with consecutive Tx channels */
4964 v = 0x84218421; 4964 v = 0x84218421;
4965 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, 4965 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4966 &v, 1, A_TP_TX_SCHED_HDR); 4966 &v, 1, TP_TX_SCHED_HDR_A);
4967 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, 4967 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4968 &v, 1, A_TP_TX_SCHED_FIFO); 4968 &v, 1, TP_TX_SCHED_FIFO_A);
4969 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, 4969 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4970 &v, 1, A_TP_TX_SCHED_PCMD); 4970 &v, 1, TP_TX_SCHED_PCMD_A);
4971 4971
4972#define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */ 4972#define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
4973 if (is_offload(adap)) { 4973 if (is_offload(adap)) {
4974 t4_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0, 4974 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A,
4975 V_TX_MODQ_WEIGHT0(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 4975 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4976 V_TX_MODQ_WEIGHT1(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 4976 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4977 V_TX_MODQ_WEIGHT2(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 4977 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4978 V_TX_MODQ_WEIGHT3(T4_TX_MODQ_10G_WEIGHT_DEFAULT)); 4978 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
4979 t4_write_reg(adap, A_TP_TX_MOD_CHANNEL_WEIGHT, 4979 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A,
4980 V_TX_MODQ_WEIGHT0(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 4980 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4981 V_TX_MODQ_WEIGHT1(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 4981 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4982 V_TX_MODQ_WEIGHT2(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 4982 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4983 V_TX_MODQ_WEIGHT3(T4_TX_MODQ_10G_WEIGHT_DEFAULT)); 4983 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
4984 } 4984 }
4985 4985
4986 /* get basic stuff going */ 4986 /* get basic stuff going */
@@ -5059,7 +5059,7 @@ static int adap_init0_config(struct adapter *adapter, int reset)
5059 */ 5059 */
5060 if (reset) { 5060 if (reset) {
5061 ret = t4_fw_reset(adapter, adapter->mbox, 5061 ret = t4_fw_reset(adapter, adapter->mbox,
5062 PIORSTMODE | PIORST); 5062 PIORSTMODE_F | PIORST_F);
5063 if (ret < 0) 5063 if (ret < 0)
5064 goto bye; 5064 goto bye;
5065 } 5065 }
@@ -5264,7 +5264,7 @@ static int adap_init0_no_config(struct adapter *adapter, int reset)
5264 */ 5264 */
5265 if (reset) { 5265 if (reset) {
5266 ret = t4_fw_reset(adapter, adapter->mbox, 5266 ret = t4_fw_reset(adapter, adapter->mbox,
5267 PIORSTMODE | PIORST); 5267 PIORSTMODE_F | PIORST_F);
5268 if (ret < 0) 5268 if (ret < 0)
5269 goto bye; 5269 goto bye;
5270 } 5270 }
@@ -6413,7 +6413,7 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6413 goto out_unmap_bar0; 6413 goto out_unmap_bar0;
6414 6414
6415 /* We control everything through one PF */ 6415 /* We control everything through one PF */
6416 func = SOURCEPF_GET(readl(regs + PL_WHOAMI)); 6416 func = SOURCEPF_G(readl(regs + PL_WHOAMI_A));
6417 if (func != ent->driver_data) { 6417 if (func != ent->driver_data) {
6418 iounmap(regs); 6418 iounmap(regs);
6419 pci_disable_device(pdev); 6419 pci_disable_device(pdev);
diff --git a/drivers/net/ethernet/chelsio/cxgb4/l2t.c b/drivers/net/ethernet/chelsio/cxgb4/l2t.c
index a047baa9fd04..5ae14451c3a4 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/l2t.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/l2t.c
@@ -46,6 +46,7 @@
46#include "t4_msg.h" 46#include "t4_msg.h"
47#include "t4fw_api.h" 47#include "t4fw_api.h"
48#include "t4_regs.h" 48#include "t4_regs.h"
49#include "t4_values.h"
49 50
50#define VLAN_NONE 0xfff 51#define VLAN_NONE 0xfff
51 52
@@ -425,7 +426,7 @@ u64 cxgb4_select_ntuple(struct net_device *dev,
425 * in the Compressed Filter Tuple. 426 * in the Compressed Filter Tuple.
426 */ 427 */
427 if (tp->vlan_shift >= 0 && l2t->vlan != VLAN_NONE) 428 if (tp->vlan_shift >= 0 && l2t->vlan != VLAN_NONE)
428 ntuple |= (u64)(F_FT_VLAN_VLD | l2t->vlan) << tp->vlan_shift; 429 ntuple |= (u64)(FT_VLAN_VLD_F | l2t->vlan) << tp->vlan_shift;
429 430
430 if (tp->port_shift >= 0) 431 if (tp->port_shift >= 0)
431 ntuple |= (u64)l2t->lport << tp->port_shift; 432 ntuple |= (u64)l2t->lport << tp->port_shift;
@@ -439,9 +440,9 @@ u64 cxgb4_select_ntuple(struct net_device *dev,
439 u32 pf = FW_VIID_PFN_G(viid); 440 u32 pf = FW_VIID_PFN_G(viid);
440 u32 vld = FW_VIID_VIVLD_G(viid); 441 u32 vld = FW_VIID_VIVLD_G(viid);
441 442
442 ntuple |= (u64)(V_FT_VNID_ID_VF(vf) | 443 ntuple |= (u64)(FT_VNID_ID_VF_V(vf) |
443 V_FT_VNID_ID_PF(pf) | 444 FT_VNID_ID_PF_V(pf) |
444 V_FT_VNID_ID_VLD(vld)) << tp->vnic_shift; 445 FT_VNID_ID_VLD_V(vld)) << tp->vnic_shift;
445 } 446 }
446 447
447 return ntuple; 448 return ntuple;
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
index cf0bf79a6193..3776279337c8 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
@@ -761,14 +761,13 @@ static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
761 761
762 if (!byte_cnt || byte_cnt > 4) 762 if (!byte_cnt || byte_cnt > 4)
763 return -EINVAL; 763 return -EINVAL;
764 if (t4_read_reg(adapter, SF_OP) & SF_BUSY) 764 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
765 return -EBUSY; 765 return -EBUSY;
766 cont = cont ? SF_CONT : 0; 766 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
767 lock = lock ? SF_LOCK : 0; 767 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
768 t4_write_reg(adapter, SF_OP, lock | cont | BYTECNT(byte_cnt - 1)); 768 ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
769 ret = t4_wait_op_done(adapter, SF_OP, SF_BUSY, 0, SF_ATTEMPTS, 5);
770 if (!ret) 769 if (!ret)
771 *valp = t4_read_reg(adapter, SF_DATA); 770 *valp = t4_read_reg(adapter, SF_DATA_A);
772 return ret; 771 return ret;
773} 772}
774 773
@@ -789,14 +788,12 @@ static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
789{ 788{
790 if (!byte_cnt || byte_cnt > 4) 789 if (!byte_cnt || byte_cnt > 4)
791 return -EINVAL; 790 return -EINVAL;
792 if (t4_read_reg(adapter, SF_OP) & SF_BUSY) 791 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
793 return -EBUSY; 792 return -EBUSY;
794 cont = cont ? SF_CONT : 0; 793 t4_write_reg(adapter, SF_DATA_A, val);
795 lock = lock ? SF_LOCK : 0; 794 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
796 t4_write_reg(adapter, SF_DATA, val); 795 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
797 t4_write_reg(adapter, SF_OP, lock | 796 return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
798 cont | BYTECNT(byte_cnt - 1) | OP_WR);
799 return t4_wait_op_done(adapter, SF_OP, SF_BUSY, 0, SF_ATTEMPTS, 5);
800} 797}
801 798
802/** 799/**
@@ -855,7 +852,7 @@ static int t4_read_flash(struct adapter *adapter, unsigned int addr,
855 for ( ; nwords; nwords--, data++) { 852 for ( ; nwords; nwords--, data++) {
856 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data); 853 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
857 if (nwords == 1) 854 if (nwords == 1)
858 t4_write_reg(adapter, SF_OP, 0); /* unlock SF */ 855 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
859 if (ret) 856 if (ret)
860 return ret; 857 return ret;
861 if (byte_oriented) 858 if (byte_oriented)
@@ -903,7 +900,7 @@ static int t4_write_flash(struct adapter *adapter, unsigned int addr,
903 if (ret) 900 if (ret)
904 goto unlock; 901 goto unlock;
905 902
906 t4_write_reg(adapter, SF_OP, 0); /* unlock SF */ 903 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
907 904
908 /* Read the page to verify the write succeeded */ 905 /* Read the page to verify the write succeeded */
909 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1); 906 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
@@ -919,7 +916,7 @@ static int t4_write_flash(struct adapter *adapter, unsigned int addr,
919 return 0; 916 return 0;
920 917
921unlock: 918unlock:
922 t4_write_reg(adapter, SF_OP, 0); /* unlock SF */ 919 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
923 return ret; 920 return ret;
924} 921}
925 922
@@ -1114,7 +1111,7 @@ static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
1114 } 1111 }
1115 start++; 1112 start++;
1116 } 1113 }
1117 t4_write_reg(adapter, SF_OP, 0); /* unlock SF */ 1114 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
1118 return ret; 1115 return ret;
1119} 1116}
1120 1117
@@ -1619,7 +1616,7 @@ static void ulprx_intr_handler(struct adapter *adapter)
1619 { 0 } 1616 { 0 }
1620 }; 1617 };
1621 1618
1622 if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE, ulprx_intr_info)) 1619 if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
1623 t4_fatal_err(adapter); 1620 t4_fatal_err(adapter);
1624} 1621}
1625 1622
@@ -1694,16 +1691,16 @@ static void pmrx_intr_handler(struct adapter *adapter)
1694static void cplsw_intr_handler(struct adapter *adapter) 1691static void cplsw_intr_handler(struct adapter *adapter)
1695{ 1692{
1696 static const struct intr_info cplsw_intr_info[] = { 1693 static const struct intr_info cplsw_intr_info[] = {
1697 { CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error", -1, 1 }, 1694 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
1698 { CIM_OVFL_ERROR, "CPLSW CIM overflow", -1, 1 }, 1695 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
1699 { TP_FRAMING_ERROR, "CPLSW TP framing error", -1, 1 }, 1696 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
1700 { SGE_FRAMING_ERROR, "CPLSW SGE framing error", -1, 1 }, 1697 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
1701 { CIM_FRAMING_ERROR, "CPLSW CIM framing error", -1, 1 }, 1698 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
1702 { ZERO_SWITCH_ERROR, "CPLSW no-switch error", -1, 1 }, 1699 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
1703 { 0 } 1700 { 0 }
1704 }; 1701 };
1705 1702
1706 if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE, cplsw_intr_info)) 1703 if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
1707 t4_fatal_err(adapter); 1704 t4_fatal_err(adapter);
1708} 1705}
1709 1706
@@ -1713,15 +1710,15 @@ static void cplsw_intr_handler(struct adapter *adapter)
1713static void le_intr_handler(struct adapter *adap) 1710static void le_intr_handler(struct adapter *adap)
1714{ 1711{
1715 static const struct intr_info le_intr_info[] = { 1712 static const struct intr_info le_intr_info[] = {
1716 { LIPMISS, "LE LIP miss", -1, 0 }, 1713 { LIPMISS_F, "LE LIP miss", -1, 0 },
1717 { LIP0, "LE 0 LIP error", -1, 0 }, 1714 { LIP0_F, "LE 0 LIP error", -1, 0 },
1718 { PARITYERR, "LE parity error", -1, 1 }, 1715 { PARITYERR_F, "LE parity error", -1, 1 },
1719 { UNKNOWNCMD, "LE unknown command", -1, 1 }, 1716 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
1720 { REQQPARERR, "LE request queue parity error", -1, 1 }, 1717 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
1721 { 0 } 1718 { 0 }
1722 }; 1719 };
1723 1720
1724 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE, le_intr_info)) 1721 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A, le_intr_info))
1725 t4_fatal_err(adap); 1722 t4_fatal_err(adap);
1726} 1723}
1727 1724
@@ -1879,13 +1876,13 @@ static void ma_intr_handler(struct adapter *adap)
1879static void smb_intr_handler(struct adapter *adap) 1876static void smb_intr_handler(struct adapter *adap)
1880{ 1877{
1881 static const struct intr_info smb_intr_info[] = { 1878 static const struct intr_info smb_intr_info[] = {
1882 { MSTTXFIFOPARINT, "SMB master Tx FIFO parity error", -1, 1 }, 1879 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
1883 { MSTRXFIFOPARINT, "SMB master Rx FIFO parity error", -1, 1 }, 1880 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
1884 { SLVFIFOPARINT, "SMB slave FIFO parity error", -1, 1 }, 1881 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
1885 { 0 } 1882 { 0 }
1886 }; 1883 };
1887 1884
1888 if (t4_handle_intr_status(adap, SMB_INT_CAUSE, smb_intr_info)) 1885 if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
1889 t4_fatal_err(adap); 1886 t4_fatal_err(adap);
1890} 1887}
1891 1888
@@ -1895,14 +1892,14 @@ static void smb_intr_handler(struct adapter *adap)
1895static void ncsi_intr_handler(struct adapter *adap) 1892static void ncsi_intr_handler(struct adapter *adap)
1896{ 1893{
1897 static const struct intr_info ncsi_intr_info[] = { 1894 static const struct intr_info ncsi_intr_info[] = {
1898 { CIM_DM_PRTY_ERR, "NC-SI CIM parity error", -1, 1 }, 1895 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
1899 { MPS_DM_PRTY_ERR, "NC-SI MPS parity error", -1, 1 }, 1896 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
1900 { TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error", -1, 1 }, 1897 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
1901 { RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error", -1, 1 }, 1898 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
1902 { 0 } 1899 { 0 }
1903 }; 1900 };
1904 1901
1905 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE, ncsi_intr_info)) 1902 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
1906 t4_fatal_err(adap); 1903 t4_fatal_err(adap);
1907} 1904}
1908 1905
@@ -1914,23 +1911,23 @@ static void xgmac_intr_handler(struct adapter *adap, int port)
1914 u32 v, int_cause_reg; 1911 u32 v, int_cause_reg;
1915 1912
1916 if (is_t4(adap->params.chip)) 1913 if (is_t4(adap->params.chip))
1917 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE); 1914 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
1918 else 1915 else
1919 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE); 1916 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
1920 1917
1921 v = t4_read_reg(adap, int_cause_reg); 1918 v = t4_read_reg(adap, int_cause_reg);
1922 1919
1923 v &= TXFIFO_PRTY_ERR | RXFIFO_PRTY_ERR; 1920 v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
1924 if (!v) 1921 if (!v)
1925 return; 1922 return;
1926 1923
1927 if (v & TXFIFO_PRTY_ERR) 1924 if (v & TXFIFO_PRTY_ERR_F)
1928 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n", 1925 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
1929 port); 1926 port);
1930 if (v & RXFIFO_PRTY_ERR) 1927 if (v & RXFIFO_PRTY_ERR_F)
1931 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n", 1928 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
1932 port); 1929 port);
1933 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE), v); 1930 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
1934 t4_fatal_err(adap); 1931 t4_fatal_err(adap);
1935} 1932}
1936 1933
@@ -1940,19 +1937,19 @@ static void xgmac_intr_handler(struct adapter *adap, int port)
1940static void pl_intr_handler(struct adapter *adap) 1937static void pl_intr_handler(struct adapter *adap)
1941{ 1938{
1942 static const struct intr_info pl_intr_info[] = { 1939 static const struct intr_info pl_intr_info[] = {
1943 { FATALPERR, "T4 fatal parity error", -1, 1 }, 1940 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
1944 { PERRVFID, "PL VFID_MAP parity error", -1, 1 }, 1941 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
1945 { 0 } 1942 { 0 }
1946 }; 1943 };
1947 1944
1948 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE, pl_intr_info)) 1945 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
1949 t4_fatal_err(adap); 1946 t4_fatal_err(adap);
1950} 1947}
1951 1948
1952#define PF_INTR_MASK (PFSW) 1949#define PF_INTR_MASK (PFSW_F)
1953#define GLBL_INTR_MASK (CIM | MPS | PL | PCIE | MC | EDC0 | \ 1950#define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
1954 EDC1 | LE | TP | MA | PM_TX | PM_RX | ULP_RX | \ 1951 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
1955 CPL_SWITCH | SGE | ULP_TX) 1952 CPL_SWITCH_F | SGE_F | ULP_TX_F)
1956 1953
1957/** 1954/**
1958 * t4_slow_intr_handler - control path interrupt handler 1955 * t4_slow_intr_handler - control path interrupt handler
@@ -1964,60 +1961,60 @@ static void pl_intr_handler(struct adapter *adap)
1964 */ 1961 */
1965int t4_slow_intr_handler(struct adapter *adapter) 1962int t4_slow_intr_handler(struct adapter *adapter)
1966{ 1963{
1967 u32 cause = t4_read_reg(adapter, PL_INT_CAUSE); 1964 u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
1968 1965
1969 if (!(cause & GLBL_INTR_MASK)) 1966 if (!(cause & GLBL_INTR_MASK))
1970 return 0; 1967 return 0;
1971 if (cause & CIM) 1968 if (cause & CIM_F)
1972 cim_intr_handler(adapter); 1969 cim_intr_handler(adapter);
1973 if (cause & MPS) 1970 if (cause & MPS_F)
1974 mps_intr_handler(adapter); 1971 mps_intr_handler(adapter);
1975 if (cause & NCSI) 1972 if (cause & NCSI_F)
1976 ncsi_intr_handler(adapter); 1973 ncsi_intr_handler(adapter);
1977 if (cause & PL) 1974 if (cause & PL_F)
1978 pl_intr_handler(adapter); 1975 pl_intr_handler(adapter);
1979 if (cause & SMB) 1976 if (cause & SMB_F)
1980 smb_intr_handler(adapter); 1977 smb_intr_handler(adapter);
1981 if (cause & XGMAC0) 1978 if (cause & XGMAC0_F)
1982 xgmac_intr_handler(adapter, 0); 1979 xgmac_intr_handler(adapter, 0);
1983 if (cause & XGMAC1) 1980 if (cause & XGMAC1_F)
1984 xgmac_intr_handler(adapter, 1); 1981 xgmac_intr_handler(adapter, 1);
1985 if (cause & XGMAC_KR0) 1982 if (cause & XGMAC_KR0_F)
1986 xgmac_intr_handler(adapter, 2); 1983 xgmac_intr_handler(adapter, 2);
1987 if (cause & XGMAC_KR1) 1984 if (cause & XGMAC_KR1_F)
1988 xgmac_intr_handler(adapter, 3); 1985 xgmac_intr_handler(adapter, 3);
1989 if (cause & PCIE) 1986 if (cause & PCIE_F)
1990 pcie_intr_handler(adapter); 1987 pcie_intr_handler(adapter);
1991 if (cause & MC) 1988 if (cause & MC_F)
1992 mem_intr_handler(adapter, MEM_MC); 1989 mem_intr_handler(adapter, MEM_MC);
1993 if (!is_t4(adapter->params.chip) && (cause & MC1)) 1990 if (!is_t4(adapter->params.chip) && (cause & MC1_S))
1994 mem_intr_handler(adapter, MEM_MC1); 1991 mem_intr_handler(adapter, MEM_MC1);
1995 if (cause & EDC0) 1992 if (cause & EDC0_F)
1996 mem_intr_handler(adapter, MEM_EDC0); 1993 mem_intr_handler(adapter, MEM_EDC0);
1997 if (cause & EDC1) 1994 if (cause & EDC1_F)
1998 mem_intr_handler(adapter, MEM_EDC1); 1995 mem_intr_handler(adapter, MEM_EDC1);
1999 if (cause & LE) 1996 if (cause & LE_F)
2000 le_intr_handler(adapter); 1997 le_intr_handler(adapter);
2001 if (cause & TP) 1998 if (cause & TP_F)
2002 tp_intr_handler(adapter); 1999 tp_intr_handler(adapter);
2003 if (cause & MA) 2000 if (cause & MA_F)
2004 ma_intr_handler(adapter); 2001 ma_intr_handler(adapter);
2005 if (cause & PM_TX) 2002 if (cause & PM_TX_F)
2006 pmtx_intr_handler(adapter); 2003 pmtx_intr_handler(adapter);
2007 if (cause & PM_RX) 2004 if (cause & PM_RX_F)
2008 pmrx_intr_handler(adapter); 2005 pmrx_intr_handler(adapter);
2009 if (cause & ULP_RX) 2006 if (cause & ULP_RX_F)
2010 ulprx_intr_handler(adapter); 2007 ulprx_intr_handler(adapter);
2011 if (cause & CPL_SWITCH) 2008 if (cause & CPL_SWITCH_F)
2012 cplsw_intr_handler(adapter); 2009 cplsw_intr_handler(adapter);
2013 if (cause & SGE) 2010 if (cause & SGE_F)
2014 sge_intr_handler(adapter); 2011 sge_intr_handler(adapter);
2015 if (cause & ULP_TX) 2012 if (cause & ULP_TX_F)
2016 ulptx_intr_handler(adapter); 2013 ulptx_intr_handler(adapter);
2017 2014
2018 /* Clear the interrupts just processed for which we are the master. */ 2015 /* Clear the interrupts just processed for which we are the master. */
2019 t4_write_reg(adapter, PL_INT_CAUSE, cause & GLBL_INTR_MASK); 2016 t4_write_reg(adapter, PL_INT_CAUSE_A, cause & GLBL_INTR_MASK);
2020 (void) t4_read_reg(adapter, PL_INT_CAUSE); /* flush */ 2017 (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
2021 return 1; 2018 return 1;
2022} 2019}
2023 2020
@@ -2036,7 +2033,7 @@ int t4_slow_intr_handler(struct adapter *adapter)
2036 */ 2033 */
2037void t4_intr_enable(struct adapter *adapter) 2034void t4_intr_enable(struct adapter *adapter)
2038{ 2035{
2039 u32 pf = SOURCEPF_GET(t4_read_reg(adapter, PL_WHOAMI)); 2036 u32 pf = SOURCEPF_G(t4_read_reg(adapter, PL_WHOAMI_A));
2040 2037
2041 t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F | 2038 t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
2042 ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F | 2039 ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
@@ -2047,8 +2044,8 @@ void t4_intr_enable(struct adapter *adapter)
2047 ERR_EGR_CTXT_PRIO_F | INGRESS_SIZE_ERR_F | 2044 ERR_EGR_CTXT_PRIO_F | INGRESS_SIZE_ERR_F |
2048 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F | 2045 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F |
2049 EGRESS_SIZE_ERR_F); 2046 EGRESS_SIZE_ERR_F);
2050 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE), PF_INTR_MASK); 2047 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
2051 t4_set_reg_field(adapter, PL_INT_MAP0, 0, 1 << pf); 2048 t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
2052} 2049}
2053 2050
2054/** 2051/**
@@ -2061,10 +2058,10 @@ void t4_intr_enable(struct adapter *adapter)
2061 */ 2058 */
2062void t4_intr_disable(struct adapter *adapter) 2059void t4_intr_disable(struct adapter *adapter)
2063{ 2060{
2064 u32 pf = SOURCEPF_GET(t4_read_reg(adapter, PL_WHOAMI)); 2061 u32 pf = SOURCEPF_G(t4_read_reg(adapter, PL_WHOAMI_A));
2065 2062
2066 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE), 0); 2063 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
2067 t4_set_reg_field(adapter, PL_INT_MAP0, 1 << pf, 0); 2064 t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
2068} 2065}
2069 2066
2070/** 2067/**
@@ -2498,7 +2495,7 @@ void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
2498 if (is_t4(adap->params.chip)) { 2495 if (is_t4(adap->params.chip)) {
2499 mag_id_reg_l = PORT_REG(port, XGMAC_PORT_MAGIC_MACID_LO); 2496 mag_id_reg_l = PORT_REG(port, XGMAC_PORT_MAGIC_MACID_LO);
2500 mag_id_reg_h = PORT_REG(port, XGMAC_PORT_MAGIC_MACID_HI); 2497 mag_id_reg_h = PORT_REG(port, XGMAC_PORT_MAGIC_MACID_HI);
2501 port_cfg_reg = PORT_REG(port, XGMAC_PORT_CFG2); 2498 port_cfg_reg = PORT_REG(port, XGMAC_PORT_CFG2_A);
2502 } else { 2499 } else {
2503 mag_id_reg_l = T5_PORT_REG(port, MAC_PORT_MAGIC_MACID_LO); 2500 mag_id_reg_l = T5_PORT_REG(port, MAC_PORT_MAGIC_MACID_LO);
2504 mag_id_reg_h = T5_PORT_REG(port, MAC_PORT_MAGIC_MACID_HI); 2501 mag_id_reg_h = T5_PORT_REG(port, MAC_PORT_MAGIC_MACID_HI);
@@ -2512,8 +2509,8 @@ void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
2512 t4_write_reg(adap, mag_id_reg_h, 2509 t4_write_reg(adap, mag_id_reg_h,
2513 (addr[0] << 8) | addr[1]); 2510 (addr[0] << 8) | addr[1]);
2514 } 2511 }
2515 t4_set_reg_field(adap, port_cfg_reg, MAGICEN, 2512 t4_set_reg_field(adap, port_cfg_reg, MAGICEN_F,
2516 addr ? MAGICEN : 0); 2513 addr ? MAGICEN_F : 0);
2517} 2514}
2518 2515
2519/** 2516/**
@@ -2538,20 +2535,21 @@ int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
2538 u32 port_cfg_reg; 2535 u32 port_cfg_reg;
2539 2536
2540 if (is_t4(adap->params.chip)) 2537 if (is_t4(adap->params.chip))
2541 port_cfg_reg = PORT_REG(port, XGMAC_PORT_CFG2); 2538 port_cfg_reg = PORT_REG(port, XGMAC_PORT_CFG2_A);
2542 else 2539 else
2543 port_cfg_reg = T5_PORT_REG(port, MAC_PORT_CFG2_A); 2540 port_cfg_reg = T5_PORT_REG(port, MAC_PORT_CFG2_A);
2544 2541
2545 if (!enable) { 2542 if (!enable) {
2546 t4_set_reg_field(adap, port_cfg_reg, PATEN, 0); 2543 t4_set_reg_field(adap, port_cfg_reg, PATEN_F, 0);
2547 return 0; 2544 return 0;
2548 } 2545 }
2549 if (map > 0xff) 2546 if (map > 0xff)
2550 return -EINVAL; 2547 return -EINVAL;
2551 2548
2552#define EPIO_REG(name) \ 2549#define EPIO_REG(name) \
2553 (is_t4(adap->params.chip) ? PORT_REG(port, XGMAC_PORT_EPIO_##name) : \ 2550 (is_t4(adap->params.chip) ? \
2554 T5_PORT_REG(port, MAC_PORT_EPIO_##name##_A)) 2551 PORT_REG(port, XGMAC_PORT_EPIO_##name##_A) : \
2552 T5_PORT_REG(port, MAC_PORT_EPIO_##name##_A))
2555 2553
2556 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32); 2554 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32);
2557 t4_write_reg(adap, EPIO_REG(DATA2), mask1); 2555 t4_write_reg(adap, EPIO_REG(DATA2), mask1);
@@ -2563,21 +2561,21 @@ int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
2563 2561
2564 /* write byte masks */ 2562 /* write byte masks */
2565 t4_write_reg(adap, EPIO_REG(DATA0), mask0); 2563 t4_write_reg(adap, EPIO_REG(DATA0), mask0);
2566 t4_write_reg(adap, EPIO_REG(OP), ADDRESS(i) | EPIOWR); 2564 t4_write_reg(adap, EPIO_REG(OP), ADDRESS_V(i) | EPIOWR_F);
2567 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 2565 t4_read_reg(adap, EPIO_REG(OP)); /* flush */
2568 if (t4_read_reg(adap, EPIO_REG(OP)) & SF_BUSY) 2566 if (t4_read_reg(adap, EPIO_REG(OP)) & SF_BUSY_F)
2569 return -ETIMEDOUT; 2567 return -ETIMEDOUT;
2570 2568
2571 /* write CRC */ 2569 /* write CRC */
2572 t4_write_reg(adap, EPIO_REG(DATA0), crc); 2570 t4_write_reg(adap, EPIO_REG(DATA0), crc);
2573 t4_write_reg(adap, EPIO_REG(OP), ADDRESS(i + 32) | EPIOWR); 2571 t4_write_reg(adap, EPIO_REG(OP), ADDRESS_V(i + 32) | EPIOWR_F);
2574 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 2572 t4_read_reg(adap, EPIO_REG(OP)); /* flush */
2575 if (t4_read_reg(adap, EPIO_REG(OP)) & SF_BUSY) 2573 if (t4_read_reg(adap, EPIO_REG(OP)) & SF_BUSY_F)
2576 return -ETIMEDOUT; 2574 return -ETIMEDOUT;
2577 } 2575 }
2578#undef EPIO_REG 2576#undef EPIO_REG
2579 2577
2580 t4_set_reg_field(adap, PORT_REG(port, XGMAC_PORT_CFG2), 0, PATEN); 2578 t4_set_reg_field(adap, PORT_REG(port, XGMAC_PORT_CFG2_A), 0, PATEN_F);
2581 return 0; 2579 return 0;
2582} 2580}
2583 2581
@@ -2998,7 +2996,7 @@ static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
2998 2996
2999 memset(&c, 0, sizeof(c)); 2997 memset(&c, 0, sizeof(c));
3000 INIT_CMD(c, RESET, WRITE); 2998 INIT_CMD(c, RESET, WRITE);
3001 c.val = htonl(PIORST | PIORSTMODE); 2999 c.val = htonl(PIORST_F | PIORSTMODE_F);
3002 c.halt_pkd = htonl(FW_RESET_CMD_HALT_F); 3000 c.halt_pkd = htonl(FW_RESET_CMD_HALT_F);
3003 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 3001 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3004 } 3002 }
@@ -3071,11 +3069,11 @@ static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
3071 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0); 3069 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
3072 msleep(100); 3070 msleep(100);
3073 if (t4_fw_reset(adap, mbox, 3071 if (t4_fw_reset(adap, mbox,
3074 PIORST | PIORSTMODE) == 0) 3072 PIORST_F | PIORSTMODE_F) == 0)
3075 return 0; 3073 return 0;
3076 } 3074 }
3077 3075
3078 t4_write_reg(adap, PL_RST, PIORST | PIORSTMODE); 3076 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
3079 msleep(2000); 3077 msleep(2000);
3080 } else { 3078 } else {
3081 int ms; 3079 int ms;
@@ -3246,7 +3244,7 @@ int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
3246 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1) 3244 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
3247 & ~(fl_align-1)); 3245 & ~(fl_align-1));
3248 3246
3249 t4_write_reg(adap, ULP_RX_TDDP_PSZ, HPZ0(page_shift - 12)); 3247 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
3250 3248
3251 return 0; 3249 return 0;
3252} 3250}
@@ -3931,12 +3929,12 @@ int t4_wait_dev_ready(void __iomem *regs)
3931{ 3929{
3932 u32 whoami; 3930 u32 whoami;
3933 3931
3934 whoami = readl(regs + PL_WHOAMI); 3932 whoami = readl(regs + PL_WHOAMI_A);
3935 if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS) 3933 if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
3936 return 0; 3934 return 0;
3937 3935
3938 msleep(500); 3936 msleep(500);
3939 whoami = readl(regs + PL_WHOAMI); 3937 whoami = readl(regs + PL_WHOAMI_A);
3940 return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO); 3938 return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
3941} 3939}
3942 3940
@@ -3960,7 +3958,7 @@ static int get_flash_params(struct adapter *adap)
3960 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID); 3958 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
3961 if (!ret) 3959 if (!ret)
3962 ret = sf1_read(adap, 3, 0, 1, &info); 3960 ret = sf1_read(adap, 3, 0, 1, &info);
3963 t4_write_reg(adap, SF_OP, 0); /* unlock SF */ 3961 t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */
3964 if (ret) 3962 if (ret)
3965 return ret; 3963 return ret;
3966 3964
@@ -4007,7 +4005,7 @@ int t4_prep_adapter(struct adapter *adapter)
4007 u32 pl_rev; 4005 u32 pl_rev;
4008 4006
4009 get_pci_mode(adapter, &adapter->params.pci); 4007 get_pci_mode(adapter, &adapter->params.pci);
4010 pl_rev = G_REV(t4_read_reg(adapter, PL_REV)); 4008 pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
4011 4009
4012 ret = get_flash_params(adapter); 4010 ret = get_flash_params(adapter);
4013 if (ret < 0) { 4011 if (ret < 0) {
@@ -4197,16 +4195,16 @@ int t4_init_tp_params(struct adapter *adap)
4197 * shift positions of several elements of the Compressed Filter Tuple 4195 * shift positions of several elements of the Compressed Filter Tuple
4198 * for this adapter which we need frequently ... 4196 * for this adapter which we need frequently ...
4199 */ 4197 */
4200 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, F_VLAN); 4198 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
4201 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID); 4199 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
4202 adap->params.tp.port_shift = t4_filter_field_shift(adap, F_PORT); 4200 adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
4203 adap->params.tp.protocol_shift = t4_filter_field_shift(adap, 4201 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
4204 F_PROTOCOL); 4202 PROTOCOL_F);
4205 4203
4206 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID 4204 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
4207 * represents the presense of an Outer VLAN instead of a VNIC ID. 4205 * represents the presense of an Outer VLAN instead of a VNIC ID.
4208 */ 4206 */
4209 if ((adap->params.tp.ingress_config & F_VNIC) == 0) 4207 if ((adap->params.tp.ingress_config & VNIC_F) == 0)
4210 adap->params.tp.vnic_shift = -1; 4208 adap->params.tp.vnic_shift = -1;
4211 4209
4212 return 0; 4210 return 0;
@@ -4232,35 +4230,35 @@ int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
4232 4230
4233 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) { 4231 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
4234 switch (filter_mode & sel) { 4232 switch (filter_mode & sel) {
4235 case F_FCOE: 4233 case FCOE_F:
4236 field_shift += W_FT_FCOE; 4234 field_shift += FT_FCOE_W;
4237 break; 4235 break;
4238 case F_PORT: 4236 case PORT_F:
4239 field_shift += W_FT_PORT; 4237 field_shift += FT_PORT_W;
4240 break; 4238 break;
4241 case F_VNIC_ID: 4239 case VNIC_ID_F:
4242 field_shift += W_FT_VNIC_ID; 4240 field_shift += FT_VNIC_ID_W;
4243 break; 4241 break;
4244 case F_VLAN: 4242 case VLAN_F:
4245 field_shift += W_FT_VLAN; 4243 field_shift += FT_VLAN_W;
4246 break; 4244 break;
4247 case F_TOS: 4245 case TOS_F:
4248 field_shift += W_FT_TOS; 4246 field_shift += FT_TOS_W;
4249 break; 4247 break;
4250 case F_PROTOCOL: 4248 case PROTOCOL_F:
4251 field_shift += W_FT_PROTOCOL; 4249 field_shift += FT_PROTOCOL_W;
4252 break; 4250 break;
4253 case F_ETHERTYPE: 4251 case ETHERTYPE_F:
4254 field_shift += W_FT_ETHERTYPE; 4252 field_shift += FT_ETHERTYPE_W;
4255 break; 4253 break;
4256 case F_MACMATCH: 4254 case MACMATCH_F:
4257 field_shift += W_FT_MACMATCH; 4255 field_shift += FT_MACMATCH_W;
4258 break; 4256 break;
4259 case F_MPSHITTYPE: 4257 case MPSHITTYPE_F:
4260 field_shift += W_FT_MPSHITTYPE; 4258 field_shift += FT_MPSHITTYPE_W;
4261 break; 4259 break;
4262 case F_FRAGMENTATION: 4260 case FRAGMENTATION_F:
4263 field_shift += W_FT_FRAGMENTATION; 4261 field_shift += FT_FRAGMENTATION_W;
4264 break; 4262 break;
4265 } 4263 }
4266 } 4264 }
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h b/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
index ec0addc85bb6..4077227b5cea 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
@@ -1708,233 +1708,323 @@
1708 1708
1709#define MPS_RX_PERR_INT_CAUSE_A 0x11074 1709#define MPS_RX_PERR_INT_CAUSE_A 0x11074
1710 1710
1711#define CPL_INTR_CAUSE 0x19054 1711#define CPL_INTR_CAUSE_A 0x19054
1712#define CIM_OP_MAP_PERR 0x00000020U
1713#define CIM_OVFL_ERROR 0x00000010U
1714#define TP_FRAMING_ERROR 0x00000008U
1715#define SGE_FRAMING_ERROR 0x00000004U
1716#define CIM_FRAMING_ERROR 0x00000002U
1717#define ZERO_SWITCH_ERROR 0x00000001U
1718
1719#define SMB_INT_CAUSE 0x19090
1720#define MSTTXFIFOPARINT 0x00200000U
1721#define MSTRXFIFOPARINT 0x00100000U
1722#define SLVFIFOPARINT 0x00080000U
1723
1724#define ULP_RX_INT_CAUSE 0x19158
1725#define ULP_RX_ISCSI_TAGMASK 0x19164
1726#define ULP_RX_ISCSI_PSZ 0x19168
1727#define HPZ3_MASK 0x0f000000U
1728#define HPZ3_SHIFT 24
1729#define HPZ3(x) ((x) << HPZ3_SHIFT)
1730#define HPZ2_MASK 0x000f0000U
1731#define HPZ2_SHIFT 16
1732#define HPZ2(x) ((x) << HPZ2_SHIFT)
1733#define HPZ1_MASK 0x00000f00U
1734#define HPZ1_SHIFT 8
1735#define HPZ1(x) ((x) << HPZ1_SHIFT)
1736#define HPZ0_MASK 0x0000000fU
1737#define HPZ0_SHIFT 0
1738#define HPZ0(x) ((x) << HPZ0_SHIFT)
1739
1740#define ULP_RX_TDDP_PSZ 0x19178
1741
1742#define SF_DATA 0x193f8
1743#define SF_OP 0x193fc
1744#define SF_BUSY 0x80000000U
1745#define SF_LOCK 0x00000010U
1746#define SF_CONT 0x00000008U
1747#define BYTECNT_MASK 0x00000006U
1748#define BYTECNT_SHIFT 1
1749#define BYTECNT(x) ((x) << BYTECNT_SHIFT)
1750#define OP_WR 0x00000001U
1751
1752#define PL_PF_INT_CAUSE 0x3c0
1753#define PFSW 0x00000008U
1754#define PFSGE 0x00000004U
1755#define PFCIM 0x00000002U
1756#define PFMPS 0x00000001U
1757
1758#define PL_PF_INT_ENABLE 0x3c4
1759#define PL_PF_CTL 0x3c8
1760#define SWINT 0x00000001U
1761
1762#define PL_WHOAMI 0x19400
1763#define SOURCEPF_MASK 0x00000700U
1764#define SOURCEPF_SHIFT 8
1765#define SOURCEPF(x) ((x) << SOURCEPF_SHIFT)
1766#define SOURCEPF_GET(x) (((x) & SOURCEPF_MASK) >> SOURCEPF_SHIFT)
1767#define ISVF 0x00000080U
1768#define VFID_MASK 0x0000007fU
1769#define VFID_SHIFT 0
1770#define VFID(x) ((x) << VFID_SHIFT)
1771#define VFID_GET(x) (((x) & VFID_MASK) >> VFID_SHIFT)
1772
1773#define PL_INT_CAUSE 0x1940c
1774#define ULP_TX 0x08000000U
1775#define SGE 0x04000000U
1776#define HMA 0x02000000U
1777#define CPL_SWITCH 0x01000000U
1778#define ULP_RX 0x00800000U
1779#define PM_RX 0x00400000U
1780#define PM_TX 0x00200000U
1781#define MA 0x00100000U
1782#define TP 0x00080000U
1783#define LE 0x00040000U
1784#define EDC1 0x00020000U
1785#define EDC0 0x00010000U
1786#define MC 0x00008000U
1787#define PCIE 0x00004000U
1788#define PMU 0x00002000U
1789#define XGMAC_KR1 0x00001000U
1790#define XGMAC_KR0 0x00000800U
1791#define XGMAC1 0x00000400U
1792#define XGMAC0 0x00000200U
1793#define SMB 0x00000100U
1794#define SF 0x00000080U
1795#define PL 0x00000040U
1796#define NCSI 0x00000020U
1797#define MPS 0x00000010U
1798#define MI 0x00000008U
1799#define DBG 0x00000004U
1800#define I2CM 0x00000002U
1801#define CIM 0x00000001U
1802
1803#define MC1 0x31
1804#define PL_INT_ENABLE 0x19410
1805#define PL_INT_MAP0 0x19414
1806#define PL_RST 0x19428
1807#define PIORST 0x00000002U
1808#define PIORSTMODE 0x00000001U
1809
1810#define PL_PL_INT_CAUSE 0x19430
1811#define FATALPERR 0x00000010U
1812#define PERRVFID 0x00000001U
1813
1814#define PL_REV 0x1943c
1815
1816#define S_REV 0
1817#define M_REV 0xfU
1818#define V_REV(x) ((x) << S_REV)
1819#define G_REV(x) (((x) >> S_REV) & M_REV)
1820
1821#define LE_DB_CONFIG 0x19c04
1822#define HASHEN 0x00100000U
1823
1824#define LE_DB_SERVER_INDEX 0x19c18
1825#define LE_DB_ACT_CNT_IPV4 0x19c20
1826#define LE_DB_ACT_CNT_IPV6 0x19c24
1827
1828#define LE_DB_INT_CAUSE 0x19c3c
1829#define REQQPARERR 0x00010000U
1830#define UNKNOWNCMD 0x00008000U
1831#define PARITYERR 0x00000040U
1832#define LIPMISS 0x00000020U
1833#define LIP0 0x00000010U
1834
1835#define LE_DB_TID_HASHBASE 0x19df8
1836
1837#define NCSI_INT_CAUSE 0x1a0d8
1838#define CIM_DM_PRTY_ERR 0x00000100U
1839#define MPS_DM_PRTY_ERR 0x00000080U
1840#define TXFIFO_PRTY_ERR 0x00000002U
1841#define RXFIFO_PRTY_ERR 0x00000001U
1842
1843#define XGMAC_PORT_CFG2 0x1018
1844#define PATEN 0x00040000U
1845#define MAGICEN 0x00020000U
1846 1712
1847#define XGMAC_PORT_MAGIC_MACID_LO 0x1024 1713#define CIM_OP_MAP_PERR_S 5
1848#define XGMAC_PORT_MAGIC_MACID_HI 0x1028 1714#define CIM_OP_MAP_PERR_V(x) ((x) << CIM_OP_MAP_PERR_S)
1715#define CIM_OP_MAP_PERR_F CIM_OP_MAP_PERR_V(1U)
1716
1717#define CIM_OVFL_ERROR_S 4
1718#define CIM_OVFL_ERROR_V(x) ((x) << CIM_OVFL_ERROR_S)
1719#define CIM_OVFL_ERROR_F CIM_OVFL_ERROR_V(1U)
1720
1721#define TP_FRAMING_ERROR_S 3
1722#define TP_FRAMING_ERROR_V(x) ((x) << TP_FRAMING_ERROR_S)
1723#define TP_FRAMING_ERROR_F TP_FRAMING_ERROR_V(1U)
1724
1725#define SGE_FRAMING_ERROR_S 2
1726#define SGE_FRAMING_ERROR_V(x) ((x) << SGE_FRAMING_ERROR_S)
1727#define SGE_FRAMING_ERROR_F SGE_FRAMING_ERROR_V(1U)
1728
1729#define CIM_FRAMING_ERROR_S 1
1730#define CIM_FRAMING_ERROR_V(x) ((x) << CIM_FRAMING_ERROR_S)
1731#define CIM_FRAMING_ERROR_F CIM_FRAMING_ERROR_V(1U)
1732
1733#define ZERO_SWITCH_ERROR_S 0
1734#define ZERO_SWITCH_ERROR_V(x) ((x) << ZERO_SWITCH_ERROR_S)
1735#define ZERO_SWITCH_ERROR_F ZERO_SWITCH_ERROR_V(1U)
1736
1737#define SMB_INT_CAUSE_A 0x19090
1738
1739#define MSTTXFIFOPARINT_S 21
1740#define MSTTXFIFOPARINT_V(x) ((x) << MSTTXFIFOPARINT_S)
1741#define MSTTXFIFOPARINT_F MSTTXFIFOPARINT_V(1U)
1742
1743#define MSTRXFIFOPARINT_S 20
1744#define MSTRXFIFOPARINT_V(x) ((x) << MSTRXFIFOPARINT_S)
1745#define MSTRXFIFOPARINT_F MSTRXFIFOPARINT_V(1U)
1746
1747#define SLVFIFOPARINT_S 19
1748#define SLVFIFOPARINT_V(x) ((x) << SLVFIFOPARINT_S)
1749#define SLVFIFOPARINT_F SLVFIFOPARINT_V(1U)
1750
1751#define ULP_RX_INT_CAUSE_A 0x19158
1752#define ULP_RX_ISCSI_TAGMASK_A 0x19164
1753#define ULP_RX_ISCSI_PSZ_A 0x19168
1754
1755#define HPZ3_S 24
1756#define HPZ3_V(x) ((x) << HPZ3_S)
1757
1758#define HPZ2_S 16
1759#define HPZ2_V(x) ((x) << HPZ2_S)
1760
1761#define HPZ1_S 8
1762#define HPZ1_V(x) ((x) << HPZ1_S)
1763
1764#define HPZ0_S 0
1765#define HPZ0_V(x) ((x) << HPZ0_S)
1766
1767#define ULP_RX_TDDP_PSZ_A 0x19178
1768
1769/* registers for module SF */
1770#define SF_DATA_A 0x193f8
1771#define SF_OP_A 0x193fc
1772
1773#define SF_BUSY_S 31
1774#define SF_BUSY_V(x) ((x) << SF_BUSY_S)
1775#define SF_BUSY_F SF_BUSY_V(1U)
1776
1777#define SF_LOCK_S 4
1778#define SF_LOCK_V(x) ((x) << SF_LOCK_S)
1779#define SF_LOCK_F SF_LOCK_V(1U)
1780
1781#define SF_CONT_S 3
1782#define SF_CONT_V(x) ((x) << SF_CONT_S)
1783#define SF_CONT_F SF_CONT_V(1U)
1784
1785#define BYTECNT_S 1
1786#define BYTECNT_V(x) ((x) << BYTECNT_S)
1787
1788#define OP_S 0
1789#define OP_V(x) ((x) << OP_S)
1790#define OP_F OP_V(1U)
1791
1792#define PL_PF_INT_CAUSE_A 0x3c0
1793
1794#define PFSW_S 3
1795#define PFSW_V(x) ((x) << PFSW_S)
1796#define PFSW_F PFSW_V(1U)
1797
1798#define PFCIM_S 1
1799#define PFCIM_V(x) ((x) << PFCIM_S)
1800#define PFCIM_F PFCIM_V(1U)
1801
1802#define PL_PF_INT_ENABLE_A 0x3c4
1803#define PL_PF_CTL_A 0x3c8
1804
1805#define PL_WHOAMI_A 0x19400
1806
1807#define SOURCEPF_S 8
1808#define SOURCEPF_M 0x7U
1809#define SOURCEPF_G(x) (((x) >> SOURCEPF_S) & SOURCEPF_M)
1810
1811#define PL_INT_CAUSE_A 0x1940c
1812
1813#define ULP_TX_S 27
1814#define ULP_TX_V(x) ((x) << ULP_TX_S)
1815#define ULP_TX_F ULP_TX_V(1U)
1816
1817#define SGE_S 26
1818#define SGE_V(x) ((x) << SGE_S)
1819#define SGE_F SGE_V(1U)
1820
1821#define CPL_SWITCH_S 24
1822#define CPL_SWITCH_V(x) ((x) << CPL_SWITCH_S)
1823#define CPL_SWITCH_F CPL_SWITCH_V(1U)
1824
1825#define ULP_RX_S 23
1826#define ULP_RX_V(x) ((x) << ULP_RX_S)
1827#define ULP_RX_F ULP_RX_V(1U)
1828
1829#define PM_RX_S 22
1830#define PM_RX_V(x) ((x) << PM_RX_S)
1831#define PM_RX_F PM_RX_V(1U)
1832
1833#define PM_TX_S 21
1834#define PM_TX_V(x) ((x) << PM_TX_S)
1835#define PM_TX_F PM_TX_V(1U)
1836
1837#define MA_S 20
1838#define MA_V(x) ((x) << MA_S)
1839#define MA_F MA_V(1U)
1849 1840
1850#define XGMAC_PORT_EPIO_DATA0 0x10c0 1841#define TP_S 19
1851#define XGMAC_PORT_EPIO_DATA1 0x10c4 1842#define TP_V(x) ((x) << TP_S)
1852#define XGMAC_PORT_EPIO_DATA2 0x10c8 1843#define TP_F TP_V(1U)
1853#define XGMAC_PORT_EPIO_DATA3 0x10cc
1854#define XGMAC_PORT_EPIO_OP 0x10d0
1855#define EPIOWR 0x00000100U
1856#define ADDRESS_MASK 0x000000ffU
1857#define ADDRESS_SHIFT 0
1858#define ADDRESS(x) ((x) << ADDRESS_SHIFT)
1859 1844
1860#define MAC_PORT_INT_CAUSE 0x8dc 1845#define LE_S 18
1861#define XGMAC_PORT_INT_CAUSE 0x10dc 1846#define LE_V(x) ((x) << LE_S)
1847#define LE_F LE_V(1U)
1862 1848
1863#define A_TP_TX_MOD_QUEUE_REQ_MAP 0x7e28 1849#define EDC1_S 17
1850#define EDC1_V(x) ((x) << EDC1_S)
1851#define EDC1_F EDC1_V(1U)
1864 1852
1865#define A_TP_TX_MOD_CHANNEL_WEIGHT 0x7e34 1853#define EDC0_S 16
1854#define EDC0_V(x) ((x) << EDC0_S)
1855#define EDC0_F EDC0_V(1U)
1866 1856
1867#define S_TX_MOD_QUEUE_REQ_MAP 0 1857#define MC_S 15
1868#define M_TX_MOD_QUEUE_REQ_MAP 0xffffU 1858#define MC_V(x) ((x) << MC_S)
1869#define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP) 1859#define MC_F MC_V(1U)
1870 1860
1871#define A_TP_TX_MOD_QUEUE_WEIGHT0 0x7e30 1861#define PCIE_S 14
1862#define PCIE_V(x) ((x) << PCIE_S)
1863#define PCIE_F PCIE_V(1U)
1872 1864
1873#define S_TX_MODQ_WEIGHT3 24 1865#define XGMAC_KR1_S 12
1874#define M_TX_MODQ_WEIGHT3 0xffU 1866#define XGMAC_KR1_V(x) ((x) << XGMAC_KR1_S)
1875#define V_TX_MODQ_WEIGHT3(x) ((x) << S_TX_MODQ_WEIGHT3) 1867#define XGMAC_KR1_F XGMAC_KR1_V(1U)
1876 1868
1877#define S_TX_MODQ_WEIGHT2 16 1869#define XGMAC_KR0_S 11
1878#define M_TX_MODQ_WEIGHT2 0xffU 1870#define XGMAC_KR0_V(x) ((x) << XGMAC_KR0_S)
1879#define V_TX_MODQ_WEIGHT2(x) ((x) << S_TX_MODQ_WEIGHT2) 1871#define XGMAC_KR0_F XGMAC_KR0_V(1U)
1880 1872
1881#define S_TX_MODQ_WEIGHT1 8 1873#define XGMAC1_S 10
1882#define M_TX_MODQ_WEIGHT1 0xffU 1874#define XGMAC1_V(x) ((x) << XGMAC1_S)
1883#define V_TX_MODQ_WEIGHT1(x) ((x) << S_TX_MODQ_WEIGHT1) 1875#define XGMAC1_F XGMAC1_V(1U)
1884 1876
1885#define S_TX_MODQ_WEIGHT0 0 1877#define XGMAC0_S 9
1886#define M_TX_MODQ_WEIGHT0 0xffU 1878#define XGMAC0_V(x) ((x) << XGMAC0_S)
1887#define V_TX_MODQ_WEIGHT0(x) ((x) << S_TX_MODQ_WEIGHT0) 1879#define XGMAC0_F XGMAC0_V(1U)
1888 1880
1889#define A_TP_TX_SCHED_HDR 0x23 1881#define SMB_S 8
1882#define SMB_V(x) ((x) << SMB_S)
1883#define SMB_F SMB_V(1U)
1890 1884
1891#define A_TP_TX_SCHED_FIFO 0x24 1885#define SF_S 7
1886#define SF_V(x) ((x) << SF_S)
1887#define SF_F SF_V(1U)
1892 1888
1893#define A_TP_TX_SCHED_PCMD 0x25 1889#define PL_S 6
1890#define PL_V(x) ((x) << PL_S)
1891#define PL_F PL_V(1U)
1894 1892
1895#define S_VNIC 11 1893#define NCSI_S 5
1896#define V_VNIC(x) ((x) << S_VNIC) 1894#define NCSI_V(x) ((x) << NCSI_S)
1897#define F_VNIC V_VNIC(1U) 1895#define NCSI_F NCSI_V(1U)
1898 1896
1899#define S_FRAGMENTATION 9 1897#define MPS_S 4
1900#define V_FRAGMENTATION(x) ((x) << S_FRAGMENTATION) 1898#define MPS_V(x) ((x) << MPS_S)
1901#define F_FRAGMENTATION V_FRAGMENTATION(1U) 1899#define MPS_F MPS_V(1U)
1902 1900
1903#define S_MPSHITTYPE 8 1901#define CIM_S 0
1904#define V_MPSHITTYPE(x) ((x) << S_MPSHITTYPE) 1902#define CIM_V(x) ((x) << CIM_S)
1905#define F_MPSHITTYPE V_MPSHITTYPE(1U) 1903#define CIM_F CIM_V(1U)
1906 1904
1907#define S_MACMATCH 7 1905#define MC1_S 31
1908#define V_MACMATCH(x) ((x) << S_MACMATCH)
1909#define F_MACMATCH V_MACMATCH(1U)
1910 1906
1911#define S_ETHERTYPE 6 1907#define PL_INT_ENABLE_A 0x19410
1912#define V_ETHERTYPE(x) ((x) << S_ETHERTYPE) 1908#define PL_INT_MAP0_A 0x19414
1913#define F_ETHERTYPE V_ETHERTYPE(1U) 1909#define PL_RST_A 0x19428
1914 1910
1915#define S_PROTOCOL 5 1911#define PIORST_S 1
1916#define V_PROTOCOL(x) ((x) << S_PROTOCOL) 1912#define PIORST_V(x) ((x) << PIORST_S)
1917#define F_PROTOCOL V_PROTOCOL(1U) 1913#define PIORST_F PIORST_V(1U)
1918 1914
1919#define S_TOS 4 1915#define PIORSTMODE_S 0
1920#define V_TOS(x) ((x) << S_TOS) 1916#define PIORSTMODE_V(x) ((x) << PIORSTMODE_S)
1921#define F_TOS V_TOS(1U) 1917#define PIORSTMODE_F PIORSTMODE_V(1U)
1922 1918
1923#define S_VLAN 3 1919#define PL_PL_INT_CAUSE_A 0x19430
1924#define V_VLAN(x) ((x) << S_VLAN)
1925#define F_VLAN V_VLAN(1U)
1926 1920
1927#define S_VNIC_ID 2 1921#define FATALPERR_S 4
1928#define V_VNIC_ID(x) ((x) << S_VNIC_ID) 1922#define FATALPERR_V(x) ((x) << FATALPERR_S)
1929#define F_VNIC_ID V_VNIC_ID(1U) 1923#define FATALPERR_F FATALPERR_V(1U)
1930 1924
1931#define S_PORT 1 1925#define PERRVFID_S 0
1932#define V_PORT(x) ((x) << S_PORT) 1926#define PERRVFID_V(x) ((x) << PERRVFID_S)
1933#define F_PORT V_PORT(1U) 1927#define PERRVFID_F PERRVFID_V(1U)
1934 1928
1935#define S_FCOE 0 1929#define PL_REV_A 0x1943c
1936#define V_FCOE(x) ((x) << S_FCOE) 1930
1937#define F_FCOE V_FCOE(1U) 1931#define REV_S 0
1932#define REV_M 0xfU
1933#define REV_V(x) ((x) << REV_S)
1934#define REV_G(x) (((x) >> REV_S) & REV_M)
1935
1936#define LE_DB_INT_CAUSE_A 0x19c3c
1937
1938#define REQQPARERR_S 16
1939#define REQQPARERR_V(x) ((x) << REQQPARERR_S)
1940#define REQQPARERR_F REQQPARERR_V(1U)
1941
1942#define UNKNOWNCMD_S 15
1943#define UNKNOWNCMD_V(x) ((x) << UNKNOWNCMD_S)
1944#define UNKNOWNCMD_F UNKNOWNCMD_V(1U)
1945
1946#define PARITYERR_S 6
1947#define PARITYERR_V(x) ((x) << PARITYERR_S)
1948#define PARITYERR_F PARITYERR_V(1U)
1949
1950#define LIPMISS_S 5
1951#define LIPMISS_V(x) ((x) << LIPMISS_S)
1952#define LIPMISS_F LIPMISS_V(1U)
1953
1954#define LIP0_S 4
1955#define LIP0_V(x) ((x) << LIP0_S)
1956#define LIP0_F LIP0_V(1U)
1957
1958#define NCSI_INT_CAUSE_A 0x1a0d8
1959
1960#define CIM_DM_PRTY_ERR_S 8
1961#define CIM_DM_PRTY_ERR_V(x) ((x) << CIM_DM_PRTY_ERR_S)
1962#define CIM_DM_PRTY_ERR_F CIM_DM_PRTY_ERR_V(1U)
1963
1964#define MPS_DM_PRTY_ERR_S 7
1965#define MPS_DM_PRTY_ERR_V(x) ((x) << MPS_DM_PRTY_ERR_S)
1966#define MPS_DM_PRTY_ERR_F MPS_DM_PRTY_ERR_V(1U)
1967
1968#define TXFIFO_PRTY_ERR_S 1
1969#define TXFIFO_PRTY_ERR_V(x) ((x) << TXFIFO_PRTY_ERR_S)
1970#define TXFIFO_PRTY_ERR_F TXFIFO_PRTY_ERR_V(1U)
1971
1972#define RXFIFO_PRTY_ERR_S 0
1973#define RXFIFO_PRTY_ERR_V(x) ((x) << RXFIFO_PRTY_ERR_S)
1974#define RXFIFO_PRTY_ERR_F RXFIFO_PRTY_ERR_V(1U)
1975
1976#define XGMAC_PORT_CFG2_A 0x1018
1977
1978#define PATEN_S 18
1979#define PATEN_V(x) ((x) << PATEN_S)
1980#define PATEN_F PATEN_V(1U)
1981
1982#define MAGICEN_S 17
1983#define MAGICEN_V(x) ((x) << MAGICEN_S)
1984#define MAGICEN_F MAGICEN_V(1U)
1985
1986#define XGMAC_PORT_MAGIC_MACID_LO 0x1024
1987#define XGMAC_PORT_MAGIC_MACID_HI 0x1028
1988
1989#define XGMAC_PORT_EPIO_DATA0_A 0x10c0
1990#define XGMAC_PORT_EPIO_DATA1_A 0x10c4
1991#define XGMAC_PORT_EPIO_DATA2_A 0x10c8
1992#define XGMAC_PORT_EPIO_DATA3_A 0x10cc
1993#define XGMAC_PORT_EPIO_OP_A 0x10d0
1994
1995#define EPIOWR_S 8
1996#define EPIOWR_V(x) ((x) << EPIOWR_S)
1997#define EPIOWR_F EPIOWR_V(1U)
1998
1999#define ADDRESS_S 0
2000#define ADDRESS_V(x) ((x) << ADDRESS_S)
2001
2002#define MAC_PORT_INT_CAUSE_A 0x8dc
2003#define XGMAC_PORT_INT_CAUSE_A 0x10dc
2004
2005#define TP_TX_MOD_QUEUE_REQ_MAP_A 0x7e28
2006
2007#define TP_TX_MOD_QUEUE_WEIGHT0_A 0x7e30
2008#define TP_TX_MOD_CHANNEL_WEIGHT_A 0x7e34
2009
2010#define TX_MOD_QUEUE_REQ_MAP_S 0
2011#define TX_MOD_QUEUE_REQ_MAP_V(x) ((x) << TX_MOD_QUEUE_REQ_MAP_S)
2012
2013#define TX_MODQ_WEIGHT3_S 24
2014#define TX_MODQ_WEIGHT3_V(x) ((x) << TX_MODQ_WEIGHT3_S)
2015
2016#define TX_MODQ_WEIGHT2_S 16
2017#define TX_MODQ_WEIGHT2_V(x) ((x) << TX_MODQ_WEIGHT2_S)
2018
2019#define TX_MODQ_WEIGHT1_S 8
2020#define TX_MODQ_WEIGHT1_V(x) ((x) << TX_MODQ_WEIGHT1_S)
2021
2022#define TX_MODQ_WEIGHT0_S 0
2023#define TX_MODQ_WEIGHT0_V(x) ((x) << TX_MODQ_WEIGHT0_S)
2024
2025#define TP_TX_SCHED_HDR_A 0x23
2026#define TP_TX_SCHED_FIFO_A 0x24
2027#define TP_TX_SCHED_PCMD_A 0x25
1938 2028
1939#define NUM_MPS_CLS_SRAM_L_INSTANCES 336 2029#define NUM_MPS_CLS_SRAM_L_INSTANCES 336
1940#define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512 2030#define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512
@@ -1968,46 +2058,8 @@
1968#define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) 2058#define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
1969#define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx) 2059#define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx)
1970 2060
1971#define A_PL_VF_REV 0x4 2061#define PL_VF_REV_A 0x4
1972#define A_PL_VF_WHOAMI 0x0 2062#define PL_VF_WHOAMI_A 0x0
1973#define A_PL_VF_REVISION 0x8 2063#define PL_VF_REVISION_A 0x8
1974
1975#define S_CHIPID 4
1976#define M_CHIPID 0xfU
1977#define V_CHIPID(x) ((x) << S_CHIPID)
1978#define G_CHIPID(x) (((x) >> S_CHIPID) & M_CHIPID)
1979
1980/* TP_VLAN_PRI_MAP controls which subset of fields will be present in the
1981 * Compressed Filter Tuple for LE filters. Each bit set in TP_VLAN_PRI_MAP
1982 * selects for a particular field being present. These fields, when present
1983 * in the Compressed Filter Tuple, have the following widths in bits.
1984 */
1985#define W_FT_FCOE 1
1986#define W_FT_PORT 3
1987#define W_FT_VNIC_ID 17
1988#define W_FT_VLAN 17
1989#define W_FT_TOS 8
1990#define W_FT_PROTOCOL 8
1991#define W_FT_ETHERTYPE 16
1992#define W_FT_MACMATCH 9
1993#define W_FT_MPSHITTYPE 3
1994#define W_FT_FRAGMENTATION 1
1995
1996/* Some of the Compressed Filter Tuple fields have internal structure. These
1997 * bit shifts/masks describe those structures. All shifts are relative to the
1998 * base position of the fields within the Compressed Filter Tuple
1999 */
2000#define S_FT_VLAN_VLD 16
2001#define V_FT_VLAN_VLD(x) ((x) << S_FT_VLAN_VLD)
2002#define F_FT_VLAN_VLD V_FT_VLAN_VLD(1U)
2003
2004#define S_FT_VNID_ID_VF 0
2005#define V_FT_VNID_ID_VF(x) ((x) << S_FT_VNID_ID_VF)
2006
2007#define S_FT_VNID_ID_PF 7
2008#define V_FT_VNID_ID_PF(x) ((x) << S_FT_VNID_ID_PF)
2009
2010#define S_FT_VNID_ID_VLD 16
2011#define V_FT_VNID_ID_VLD(x) ((x) << S_FT_VNID_ID_VLD)
2012 2064
2013#endif /* __T4_REGS_H */ 2065#endif /* __T4_REGS_H */
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_values.h b/drivers/net/ethernet/chelsio/cxgb4/t4_values.h
index ecf7459f8217..a40484432ebf 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_values.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_values.h
@@ -82,4 +82,37 @@
82#define WINDOW_SHIFT_X 10 82#define WINDOW_SHIFT_X 10
83#define PCIEOFST_SHIFT_X 10 83#define PCIEOFST_SHIFT_X 10
84 84
85/* TP_VLAN_PRI_MAP controls which subset of fields will be present in the
86 * Compressed Filter Tuple for LE filters. Each bit set in TP_VLAN_PRI_MAP
87 * selects for a particular field being present. These fields, when present
88 * in the Compressed Filter Tuple, have the following widths in bits.
89 */
90#define FT_FCOE_W 1
91#define FT_PORT_W 3
92#define FT_VNIC_ID_W 17
93#define FT_VLAN_W 17
94#define FT_TOS_W 8
95#define FT_PROTOCOL_W 8
96#define FT_ETHERTYPE_W 16
97#define FT_MACMATCH_W 9
98#define FT_MPSHITTYPE_W 3
99#define FT_FRAGMENTATION_W 1
100
101/* Some of the Compressed Filter Tuple fields have internal structure. These
102 * bit shifts/masks describe those structures. All shifts are relative to the
103 * base position of the fields within the Compressed Filter Tuple
104 */
105#define FT_VLAN_VLD_S 16
106#define FT_VLAN_VLD_V(x) ((x) << FT_VLAN_VLD_S)
107#define FT_VLAN_VLD_F FT_VLAN_VLD_V(1U)
108
109#define FT_VNID_ID_VF_S 0
110#define FT_VNID_ID_VF_V(x) ((x) << FT_VNID_ID_VF_S)
111
112#define FT_VNID_ID_PF_S 7
113#define FT_VNID_ID_PF_V(x) ((x) << FT_VNID_ID_PF_S)
114
115#define FT_VNID_ID_VLD_S 16
116#define FT_VNID_ID_VLD_V(x) ((x) << FT_VNID_ID_VLD_S)
117
85#endif /* __T4_VALUES_H__ */ 118#endif /* __T4_VALUES_H__ */
diff --git a/drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c b/drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
index aa9f9cd7a3c7..7bfbacd63f7a 100644
--- a/drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
+++ b/drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
@@ -1673,7 +1673,7 @@ static void cxgb4vf_get_regs(struct net_device *dev,
1673 reg_block_dump(adapter, regbuf, 1673 reg_block_dump(adapter, regbuf,
1674 T4VF_PL_BASE_ADDR + T4VF_MOD_MAP_PL_FIRST, 1674 T4VF_PL_BASE_ADDR + T4VF_MOD_MAP_PL_FIRST,
1675 T4VF_PL_BASE_ADDR + (is_t4(adapter->params.chip) 1675 T4VF_PL_BASE_ADDR + (is_t4(adapter->params.chip)
1676 ? A_PL_VF_WHOAMI : A_PL_VF_REVISION)); 1676 ? PL_VF_WHOAMI_A : PL_VF_REVISION_A));
1677 reg_block_dump(adapter, regbuf, 1677 reg_block_dump(adapter, regbuf,
1678 T4VF_CIM_BASE_ADDR + T4VF_MOD_MAP_CIM_FIRST, 1678 T4VF_CIM_BASE_ADDR + T4VF_MOD_MAP_CIM_FIRST,
1679 T4VF_CIM_BASE_ADDR + T4VF_MOD_MAP_CIM_LAST); 1679 T4VF_CIM_BASE_ADDR + T4VF_MOD_MAP_CIM_LAST);
diff --git a/drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c b/drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
index 5e83c183faa1..fcc610813856 100644
--- a/drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
+++ b/drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
@@ -616,8 +616,8 @@ int t4vf_get_sge_params(struct adapter *adapter)
616 * the driver can just use it. 616 * the driver can just use it.
617 */ 617 */
618 whoami = t4_read_reg(adapter, 618 whoami = t4_read_reg(adapter,
619 T4VF_PL_BASE_ADDR + A_PL_VF_WHOAMI); 619 T4VF_PL_BASE_ADDR + PL_VF_WHOAMI_A);
620 pf = SOURCEPF_GET(whoami); 620 pf = SOURCEPF_G(whoami);
621 621
622 s_hps = (HOSTPAGESIZEPF0_S + 622 s_hps = (HOSTPAGESIZEPF0_S +
623 (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * pf); 623 (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * pf);
@@ -1591,7 +1591,7 @@ int t4vf_prep_adapter(struct adapter *adapter)
1591 break; 1591 break;
1592 1592
1593 case CHELSIO_T5: 1593 case CHELSIO_T5:
1594 chipid = G_REV(t4_read_reg(adapter, A_PL_VF_REV)); 1594 chipid = REV_G(t4_read_reg(adapter, PL_VF_REV_A));
1595 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, chipid); 1595 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, chipid);
1596 break; 1596 break;
1597 } 1597 }
diff --git a/drivers/scsi/csiostor/csio_hw.c b/drivers/scsi/csiostor/csio_hw.c
index c641931d4ae1..660283528ada 100644
--- a/drivers/scsi/csiostor/csio_hw.c
+++ b/drivers/scsi/csiostor/csio_hw.c
@@ -421,17 +421,15 @@ csio_hw_sf1_read(struct csio_hw *hw, uint32_t byte_cnt, int32_t cont,
421 421
422 if (!byte_cnt || byte_cnt > 4) 422 if (!byte_cnt || byte_cnt > 4)
423 return -EINVAL; 423 return -EINVAL;
424 if (csio_rd_reg32(hw, SF_OP) & SF_BUSY) 424 if (csio_rd_reg32(hw, SF_OP_A) & SF_BUSY_F)
425 return -EBUSY; 425 return -EBUSY;
426 426
427 cont = cont ? SF_CONT : 0; 427 csio_wr_reg32(hw, SF_LOCK_V(lock) | SF_CONT_V(cont) |
428 lock = lock ? SF_LOCK : 0; 428 BYTECNT_V(byte_cnt - 1), SF_OP_A);
429 429 ret = csio_hw_wait_op_done_val(hw, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS,
430 csio_wr_reg32(hw, lock | cont | BYTECNT(byte_cnt - 1), SF_OP); 430 10, NULL);
431 ret = csio_hw_wait_op_done_val(hw, SF_OP, SF_BUSY, 0, SF_ATTEMPTS,
432 10, NULL);
433 if (!ret) 431 if (!ret)
434 *valp = csio_rd_reg32(hw, SF_DATA); 432 *valp = csio_rd_reg32(hw, SF_DATA_A);
435 return ret; 433 return ret;
436} 434}
437 435
@@ -453,16 +451,14 @@ csio_hw_sf1_write(struct csio_hw *hw, uint32_t byte_cnt, uint32_t cont,
453{ 451{
454 if (!byte_cnt || byte_cnt > 4) 452 if (!byte_cnt || byte_cnt > 4)
455 return -EINVAL; 453 return -EINVAL;
456 if (csio_rd_reg32(hw, SF_OP) & SF_BUSY) 454 if (csio_rd_reg32(hw, SF_OP_A) & SF_BUSY_F)
457 return -EBUSY; 455 return -EBUSY;
458 456
459 cont = cont ? SF_CONT : 0; 457 csio_wr_reg32(hw, val, SF_DATA_A);
460 lock = lock ? SF_LOCK : 0; 458 csio_wr_reg32(hw, SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) |
461 459 OP_V(1) | SF_LOCK_V(lock), SF_OP_A);
462 csio_wr_reg32(hw, val, SF_DATA);
463 csio_wr_reg32(hw, cont | BYTECNT(byte_cnt - 1) | OP_WR | lock, SF_OP);
464 460
465 return csio_hw_wait_op_done_val(hw, SF_OP, SF_BUSY, 0, SF_ATTEMPTS, 461 return csio_hw_wait_op_done_val(hw, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS,
466 10, NULL); 462 10, NULL);
467} 463}
468 464
@@ -533,7 +529,7 @@ csio_hw_read_flash(struct csio_hw *hw, uint32_t addr, uint32_t nwords,
533 for ( ; nwords; nwords--, data++) { 529 for ( ; nwords; nwords--, data++) {
534 ret = csio_hw_sf1_read(hw, 4, nwords > 1, nwords == 1, data); 530 ret = csio_hw_sf1_read(hw, 4, nwords > 1, nwords == 1, data);
535 if (nwords == 1) 531 if (nwords == 1)
536 csio_wr_reg32(hw, 0, SF_OP); /* unlock SF */ 532 csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */
537 if (ret) 533 if (ret)
538 return ret; 534 return ret;
539 if (byte_oriented) 535 if (byte_oriented)
@@ -586,7 +582,7 @@ csio_hw_write_flash(struct csio_hw *hw, uint32_t addr,
586 if (ret) 582 if (ret)
587 goto unlock; 583 goto unlock;
588 584
589 csio_wr_reg32(hw, 0, SF_OP); /* unlock SF */ 585 csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */
590 586
591 /* Read the page to verify the write succeeded */ 587 /* Read the page to verify the write succeeded */
592 ret = csio_hw_read_flash(hw, addr & ~0xff, ARRAY_SIZE(buf), buf, 1); 588 ret = csio_hw_read_flash(hw, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
@@ -603,7 +599,7 @@ csio_hw_write_flash(struct csio_hw *hw, uint32_t addr,
603 return 0; 599 return 0;
604 600
605unlock: 601unlock:
606 csio_wr_reg32(hw, 0, SF_OP); /* unlock SF */ 602 csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */
607 return ret; 603 return ret;
608} 604}
609 605
@@ -641,7 +637,7 @@ out:
641 if (ret) 637 if (ret)
642 csio_err(hw, "erase of flash sector %d failed, error %d\n", 638 csio_err(hw, "erase of flash sector %d failed, error %d\n",
643 start, ret); 639 start, ret);
644 csio_wr_reg32(hw, 0, SF_OP); /* unlock SF */ 640 csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */
645 return 0; 641 return 0;
646} 642}
647 643
@@ -833,7 +829,7 @@ csio_hw_get_flash_params(struct csio_hw *hw)
833 ret = csio_hw_sf1_write(hw, 1, 1, 0, SF_RD_ID); 829 ret = csio_hw_sf1_write(hw, 1, 1, 0, SF_RD_ID);
834 if (!ret) 830 if (!ret)
835 ret = csio_hw_sf1_read(hw, 3, 0, 1, &info); 831 ret = csio_hw_sf1_read(hw, 3, 0, 1, &info);
836 csio_wr_reg32(hw, 0, SF_OP); /* unlock SF */ 832 csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */
837 if (ret != 0) 833 if (ret != 0)
838 return ret; 834 return ret;
839 835
@@ -861,17 +857,17 @@ csio_hw_dev_ready(struct csio_hw *hw)
861 uint32_t reg; 857 uint32_t reg;
862 int cnt = 6; 858 int cnt = 6;
863 859
864 while (((reg = csio_rd_reg32(hw, PL_WHOAMI)) == 0xFFFFFFFF) && 860 while (((reg = csio_rd_reg32(hw, PL_WHOAMI_A)) == 0xFFFFFFFF) &&
865 (--cnt != 0)) 861 (--cnt != 0))
866 mdelay(100); 862 mdelay(100);
867 863
868 if ((cnt == 0) && (((int32_t)(SOURCEPF_GET(reg)) < 0) || 864 if ((cnt == 0) && (((int32_t)(SOURCEPF_G(reg)) < 0) ||
869 (SOURCEPF_GET(reg) >= CSIO_MAX_PFN))) { 865 (SOURCEPF_G(reg) >= CSIO_MAX_PFN))) {
870 csio_err(hw, "PL_WHOAMI returned 0x%x, cnt:%d\n", reg, cnt); 866 csio_err(hw, "PL_WHOAMI returned 0x%x, cnt:%d\n", reg, cnt);
871 return -EIO; 867 return -EIO;
872 } 868 }
873 869
874 hw->pfn = SOURCEPF_GET(reg); 870 hw->pfn = SOURCEPF_G(reg);
875 871
876 return 0; 872 return 0;
877} 873}
@@ -1078,7 +1074,7 @@ csio_do_reset(struct csio_hw *hw, bool fw_rst)
1078 1074
1079 if (!fw_rst) { 1075 if (!fw_rst) {
1080 /* PIO reset */ 1076 /* PIO reset */
1081 csio_wr_reg32(hw, PIORSTMODE | PIORST, PL_RST); 1077 csio_wr_reg32(hw, PIORSTMODE_F | PIORST_F, PL_RST_A);
1082 mdelay(2000); 1078 mdelay(2000);
1083 return 0; 1079 return 0;
1084 } 1080 }
@@ -1090,7 +1086,7 @@ csio_do_reset(struct csio_hw *hw, bool fw_rst)
1090 } 1086 }
1091 1087
1092 csio_mb_reset(hw, mbp, CSIO_MB_DEFAULT_TMO, 1088 csio_mb_reset(hw, mbp, CSIO_MB_DEFAULT_TMO,
1093 PIORSTMODE | PIORST, 0, NULL); 1089 PIORSTMODE_F | PIORST_F, 0, NULL);
1094 1090
1095 if (csio_mb_issue(hw, mbp)) { 1091 if (csio_mb_issue(hw, mbp)) {
1096 csio_err(hw, "Issue of RESET command failed.n"); 1092 csio_err(hw, "Issue of RESET command failed.n");
@@ -1166,7 +1162,7 @@ csio_hw_fw_halt(struct csio_hw *hw, uint32_t mbox, int32_t force)
1166 } 1162 }
1167 1163
1168 csio_mb_reset(hw, mbp, CSIO_MB_DEFAULT_TMO, 1164 csio_mb_reset(hw, mbp, CSIO_MB_DEFAULT_TMO,
1169 PIORSTMODE | PIORST, FW_RESET_CMD_HALT_F, 1165 PIORSTMODE_F | PIORST_F, FW_RESET_CMD_HALT_F,
1170 NULL); 1166 NULL);
1171 1167
1172 if (csio_mb_issue(hw, mbp)) { 1168 if (csio_mb_issue(hw, mbp)) {
@@ -1251,7 +1247,7 @@ csio_hw_fw_restart(struct csio_hw *hw, uint32_t mbox, int32_t reset)
1251 return 0; 1247 return 0;
1252 } 1248 }
1253 1249
1254 csio_wr_reg32(hw, PIORSTMODE | PIORST, PL_RST); 1250 csio_wr_reg32(hw, PIORSTMODE_F | PIORST_F, PL_RST_A);
1255 msleep(2000); 1251 msleep(2000);
1256 } else { 1252 } else {
1257 int ms; 1253 int ms;
@@ -2040,7 +2036,7 @@ csio_hw_configure(struct csio_hw *hw)
2040 } 2036 }
2041 2037
2042 /* HW version */ 2038 /* HW version */
2043 hw->chip_ver = (char)csio_rd_reg32(hw, PL_REV); 2039 hw->chip_ver = (char)csio_rd_reg32(hw, PL_REV_A);
2044 2040
2045 /* Needed for FW download */ 2041 /* Needed for FW download */
2046 rv = csio_hw_get_flash_params(hw); 2042 rv = csio_hw_get_flash_params(hw);
@@ -2218,7 +2214,7 @@ out:
2218 return; 2214 return;
2219} 2215}
2220 2216
2221#define PF_INTR_MASK (PFSW | PFCIM) 2217#define PF_INTR_MASK (PFSW_F | PFCIM_F)
2222 2218
2223/* 2219/*
2224 * csio_hw_intr_enable - Enable HW interrupts 2220 * csio_hw_intr_enable - Enable HW interrupts
@@ -2230,8 +2226,8 @@ static void
2230csio_hw_intr_enable(struct csio_hw *hw) 2226csio_hw_intr_enable(struct csio_hw *hw)
2231{ 2227{
2232 uint16_t vec = (uint16_t)csio_get_mb_intr_idx(csio_hw_to_mbm(hw)); 2228 uint16_t vec = (uint16_t)csio_get_mb_intr_idx(csio_hw_to_mbm(hw));
2233 uint32_t pf = SOURCEPF_GET(csio_rd_reg32(hw, PL_WHOAMI)); 2229 uint32_t pf = SOURCEPF_G(csio_rd_reg32(hw, PL_WHOAMI_A));
2234 uint32_t pl = csio_rd_reg32(hw, PL_INT_ENABLE); 2230 uint32_t pl = csio_rd_reg32(hw, PL_INT_ENABLE_A);
2235 2231
2236 /* 2232 /*
2237 * Set aivec for MSI/MSIX. PCIE_PF_CFG.INTXType is set up 2233 * Set aivec for MSI/MSIX. PCIE_PF_CFG.INTXType is set up
@@ -2244,7 +2240,7 @@ csio_hw_intr_enable(struct csio_hw *hw)
2244 csio_set_reg_field(hw, MYPF_REG(PCIE_PF_CFG_A), 2240 csio_set_reg_field(hw, MYPF_REG(PCIE_PF_CFG_A),
2245 AIVEC_V(AIVEC_M), 0); 2241 AIVEC_V(AIVEC_M), 0);
2246 2242
2247 csio_wr_reg32(hw, PF_INTR_MASK, MYPF_REG(PL_PF_INT_ENABLE)); 2243 csio_wr_reg32(hw, PF_INTR_MASK, MYPF_REG(PL_PF_INT_ENABLE_A));
2248 2244
2249 /* Turn on MB interrupts - this will internally flush PIO as well */ 2245 /* Turn on MB interrupts - this will internally flush PIO as well */
2250 csio_mb_intr_enable(hw); 2246 csio_mb_intr_enable(hw);
@@ -2254,8 +2250,8 @@ csio_hw_intr_enable(struct csio_hw *hw)
2254 /* 2250 /*
2255 * Disable the Serial FLASH interrupt, if enabled! 2251 * Disable the Serial FLASH interrupt, if enabled!
2256 */ 2252 */
2257 pl &= (~SF); 2253 pl &= (~SF_F);
2258 csio_wr_reg32(hw, pl, PL_INT_ENABLE); 2254 csio_wr_reg32(hw, pl, PL_INT_ENABLE_A);
2259 2255
2260 csio_wr_reg32(hw, ERR_CPL_EXCEED_IQE_SIZE_F | 2256 csio_wr_reg32(hw, ERR_CPL_EXCEED_IQE_SIZE_F |
2261 EGRESS_SIZE_ERR_F | ERR_INVALID_CIDX_INC_F | 2257 EGRESS_SIZE_ERR_F | ERR_INVALID_CIDX_INC_F |
@@ -2266,7 +2262,7 @@ csio_hw_intr_enable(struct csio_hw *hw)
2266 ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F | 2262 ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
2267 ERR_EGR_CTXT_PRIO_F | INGRESS_SIZE_ERR_F, 2263 ERR_EGR_CTXT_PRIO_F | INGRESS_SIZE_ERR_F,
2268 SGE_INT_ENABLE3_A); 2264 SGE_INT_ENABLE3_A);
2269 csio_set_reg_field(hw, PL_INT_MAP0, 0, 1 << pf); 2265 csio_set_reg_field(hw, PL_INT_MAP0_A, 0, 1 << pf);
2270 } 2266 }
2271 2267
2272 hw->flags |= CSIO_HWF_HW_INTR_ENABLED; 2268 hw->flags |= CSIO_HWF_HW_INTR_ENABLED;
@@ -2282,16 +2278,16 @@ csio_hw_intr_enable(struct csio_hw *hw)
2282void 2278void
2283csio_hw_intr_disable(struct csio_hw *hw) 2279csio_hw_intr_disable(struct csio_hw *hw)
2284{ 2280{
2285 uint32_t pf = SOURCEPF_GET(csio_rd_reg32(hw, PL_WHOAMI)); 2281 uint32_t pf = SOURCEPF_G(csio_rd_reg32(hw, PL_WHOAMI_A));
2286 2282
2287 if (!(hw->flags & CSIO_HWF_HW_INTR_ENABLED)) 2283 if (!(hw->flags & CSIO_HWF_HW_INTR_ENABLED))
2288 return; 2284 return;
2289 2285
2290 hw->flags &= ~CSIO_HWF_HW_INTR_ENABLED; 2286 hw->flags &= ~CSIO_HWF_HW_INTR_ENABLED;
2291 2287
2292 csio_wr_reg32(hw, 0, MYPF_REG(PL_PF_INT_ENABLE)); 2288 csio_wr_reg32(hw, 0, MYPF_REG(PL_PF_INT_ENABLE_A));
2293 if (csio_is_hw_master(hw)) 2289 if (csio_is_hw_master(hw))
2294 csio_set_reg_field(hw, PL_INT_MAP0, 1 << pf, 0); 2290 csio_set_reg_field(hw, PL_INT_MAP0_A, 1 << pf, 0);
2295 2291
2296 /* Turn off MB interrupts */ 2292 /* Turn off MB interrupts */
2297 csio_mb_intr_disable(hw); 2293 csio_mb_intr_disable(hw);
@@ -2595,7 +2591,7 @@ csio_hws_removing(struct csio_hw *hw, enum csio_hw_ev evt)
2595 * register directly. 2591 * register directly.
2596 */ 2592 */
2597 csio_err(hw, "Resetting HW and waiting 2 seconds...\n"); 2593 csio_err(hw, "Resetting HW and waiting 2 seconds...\n");
2598 csio_wr_reg32(hw, PIORSTMODE | PIORST, PL_RST); 2594 csio_wr_reg32(hw, PIORSTMODE_F | PIORST_F, PL_RST_A);
2599 mdelay(2000); 2595 mdelay(2000);
2600 break; 2596 break;
2601 2597
@@ -2814,7 +2810,7 @@ static void csio_ulprx_intr_handler(struct csio_hw *hw)
2814 { 0, NULL, 0, 0 } 2810 { 0, NULL, 0, 0 }
2815 }; 2811 };
2816 2812
2817 if (csio_handle_intr_status(hw, ULP_RX_INT_CAUSE, ulprx_intr_info)) 2813 if (csio_handle_intr_status(hw, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
2818 csio_hw_fatal_err(hw); 2814 csio_hw_fatal_err(hw);
2819} 2815}
2820 2816
@@ -2889,16 +2885,16 @@ static void csio_pmrx_intr_handler(struct csio_hw *hw)
2889static void csio_cplsw_intr_handler(struct csio_hw *hw) 2885static void csio_cplsw_intr_handler(struct csio_hw *hw)
2890{ 2886{
2891 static struct intr_info cplsw_intr_info[] = { 2887 static struct intr_info cplsw_intr_info[] = {
2892 { CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error", -1, 1 }, 2888 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
2893 { CIM_OVFL_ERROR, "CPLSW CIM overflow", -1, 1 }, 2889 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
2894 { TP_FRAMING_ERROR, "CPLSW TP framing error", -1, 1 }, 2890 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
2895 { SGE_FRAMING_ERROR, "CPLSW SGE framing error", -1, 1 }, 2891 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
2896 { CIM_FRAMING_ERROR, "CPLSW CIM framing error", -1, 1 }, 2892 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
2897 { ZERO_SWITCH_ERROR, "CPLSW no-switch error", -1, 1 }, 2893 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
2898 { 0, NULL, 0, 0 } 2894 { 0, NULL, 0, 0 }
2899 }; 2895 };
2900 2896
2901 if (csio_handle_intr_status(hw, CPL_INTR_CAUSE, cplsw_intr_info)) 2897 if (csio_handle_intr_status(hw, CPL_INTR_CAUSE_A, cplsw_intr_info))
2902 csio_hw_fatal_err(hw); 2898 csio_hw_fatal_err(hw);
2903} 2899}
2904 2900
@@ -2908,15 +2904,15 @@ static void csio_cplsw_intr_handler(struct csio_hw *hw)
2908static void csio_le_intr_handler(struct csio_hw *hw) 2904static void csio_le_intr_handler(struct csio_hw *hw)
2909{ 2905{
2910 static struct intr_info le_intr_info[] = { 2906 static struct intr_info le_intr_info[] = {
2911 { LIPMISS, "LE LIP miss", -1, 0 }, 2907 { LIPMISS_F, "LE LIP miss", -1, 0 },
2912 { LIP0, "LE 0 LIP error", -1, 0 }, 2908 { LIP0_F, "LE 0 LIP error", -1, 0 },
2913 { PARITYERR, "LE parity error", -1, 1 }, 2909 { PARITYERR_F, "LE parity error", -1, 1 },
2914 { UNKNOWNCMD, "LE unknown command", -1, 1 }, 2910 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
2915 { REQQPARERR, "LE request queue parity error", -1, 1 }, 2911 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
2916 { 0, NULL, 0, 0 } 2912 { 0, NULL, 0, 0 }
2917 }; 2913 };
2918 2914
2919 if (csio_handle_intr_status(hw, LE_DB_INT_CAUSE, le_intr_info)) 2915 if (csio_handle_intr_status(hw, LE_DB_INT_CAUSE_A, le_intr_info))
2920 csio_hw_fatal_err(hw); 2916 csio_hw_fatal_err(hw);
2921} 2917}
2922 2918
@@ -3054,13 +3050,13 @@ static void csio_ma_intr_handler(struct csio_hw *hw)
3054static void csio_smb_intr_handler(struct csio_hw *hw) 3050static void csio_smb_intr_handler(struct csio_hw *hw)
3055{ 3051{
3056 static struct intr_info smb_intr_info[] = { 3052 static struct intr_info smb_intr_info[] = {
3057 { MSTTXFIFOPARINT, "SMB master Tx FIFO parity error", -1, 1 }, 3053 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
3058 { MSTRXFIFOPARINT, "SMB master Rx FIFO parity error", -1, 1 }, 3054 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
3059 { SLVFIFOPARINT, "SMB slave FIFO parity error", -1, 1 }, 3055 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
3060 { 0, NULL, 0, 0 } 3056 { 0, NULL, 0, 0 }
3061 }; 3057 };
3062 3058
3063 if (csio_handle_intr_status(hw, SMB_INT_CAUSE, smb_intr_info)) 3059 if (csio_handle_intr_status(hw, SMB_INT_CAUSE_A, smb_intr_info))
3064 csio_hw_fatal_err(hw); 3060 csio_hw_fatal_err(hw);
3065} 3061}
3066 3062
@@ -3070,14 +3066,14 @@ static void csio_smb_intr_handler(struct csio_hw *hw)
3070static void csio_ncsi_intr_handler(struct csio_hw *hw) 3066static void csio_ncsi_intr_handler(struct csio_hw *hw)
3071{ 3067{
3072 static struct intr_info ncsi_intr_info[] = { 3068 static struct intr_info ncsi_intr_info[] = {
3073 { CIM_DM_PRTY_ERR, "NC-SI CIM parity error", -1, 1 }, 3069 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
3074 { MPS_DM_PRTY_ERR, "NC-SI MPS parity error", -1, 1 }, 3070 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
3075 { TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error", -1, 1 }, 3071 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
3076 { RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error", -1, 1 }, 3072 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
3077 { 0, NULL, 0, 0 } 3073 { 0, NULL, 0, 0 }
3078 }; 3074 };
3079 3075
3080 if (csio_handle_intr_status(hw, NCSI_INT_CAUSE, ncsi_intr_info)) 3076 if (csio_handle_intr_status(hw, NCSI_INT_CAUSE_A, ncsi_intr_info))
3081 csio_hw_fatal_err(hw); 3077 csio_hw_fatal_err(hw);
3082} 3078}
3083 3079
@@ -3088,13 +3084,13 @@ static void csio_xgmac_intr_handler(struct csio_hw *hw, int port)
3088{ 3084{
3089 uint32_t v = csio_rd_reg32(hw, CSIO_MAC_INT_CAUSE_REG(hw, port)); 3085 uint32_t v = csio_rd_reg32(hw, CSIO_MAC_INT_CAUSE_REG(hw, port));
3090 3086
3091 v &= TXFIFO_PRTY_ERR | RXFIFO_PRTY_ERR; 3087 v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
3092 if (!v) 3088 if (!v)
3093 return; 3089 return;
3094 3090
3095 if (v & TXFIFO_PRTY_ERR) 3091 if (v & TXFIFO_PRTY_ERR_F)
3096 csio_fatal(hw, "XGMAC %d Tx FIFO parity error\n", port); 3092 csio_fatal(hw, "XGMAC %d Tx FIFO parity error\n", port);
3097 if (v & RXFIFO_PRTY_ERR) 3093 if (v & RXFIFO_PRTY_ERR_F)
3098 csio_fatal(hw, "XGMAC %d Rx FIFO parity error\n", port); 3094 csio_fatal(hw, "XGMAC %d Rx FIFO parity error\n", port);
3099 csio_wr_reg32(hw, v, CSIO_MAC_INT_CAUSE_REG(hw, port)); 3095 csio_wr_reg32(hw, v, CSIO_MAC_INT_CAUSE_REG(hw, port));
3100 csio_hw_fatal_err(hw); 3096 csio_hw_fatal_err(hw);
@@ -3106,12 +3102,12 @@ static void csio_xgmac_intr_handler(struct csio_hw *hw, int port)
3106static void csio_pl_intr_handler(struct csio_hw *hw) 3102static void csio_pl_intr_handler(struct csio_hw *hw)
3107{ 3103{
3108 static struct intr_info pl_intr_info[] = { 3104 static struct intr_info pl_intr_info[] = {
3109 { FATALPERR, "T4 fatal parity error", -1, 1 }, 3105 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
3110 { PERRVFID, "PL VFID_MAP parity error", -1, 1 }, 3106 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
3111 { 0, NULL, 0, 0 } 3107 { 0, NULL, 0, 0 }
3112 }; 3108 };
3113 3109
3114 if (csio_handle_intr_status(hw, PL_PL_INT_CAUSE, pl_intr_info)) 3110 if (csio_handle_intr_status(hw, PL_PL_INT_CAUSE_A, pl_intr_info))
3115 csio_hw_fatal_err(hw); 3111 csio_hw_fatal_err(hw);
3116} 3112}
3117 3113
@@ -3126,7 +3122,7 @@ static void csio_pl_intr_handler(struct csio_hw *hw)
3126int 3122int
3127csio_hw_slow_intr_handler(struct csio_hw *hw) 3123csio_hw_slow_intr_handler(struct csio_hw *hw)
3128{ 3124{
3129 uint32_t cause = csio_rd_reg32(hw, PL_INT_CAUSE); 3125 uint32_t cause = csio_rd_reg32(hw, PL_INT_CAUSE_A);
3130 3126
3131 if (!(cause & CSIO_GLBL_INTR_MASK)) { 3127 if (!(cause & CSIO_GLBL_INTR_MASK)) {
3132 CSIO_INC_STATS(hw, n_plint_unexp); 3128 CSIO_INC_STATS(hw, n_plint_unexp);
@@ -3137,75 +3133,75 @@ csio_hw_slow_intr_handler(struct csio_hw *hw)
3137 3133
3138 CSIO_INC_STATS(hw, n_plint_cnt); 3134 CSIO_INC_STATS(hw, n_plint_cnt);
3139 3135
3140 if (cause & CIM) 3136 if (cause & CIM_F)
3141 csio_cim_intr_handler(hw); 3137 csio_cim_intr_handler(hw);
3142 3138
3143 if (cause & MPS) 3139 if (cause & MPS_F)
3144 csio_mps_intr_handler(hw); 3140 csio_mps_intr_handler(hw);
3145 3141
3146 if (cause & NCSI) 3142 if (cause & NCSI_F)
3147 csio_ncsi_intr_handler(hw); 3143 csio_ncsi_intr_handler(hw);
3148 3144
3149 if (cause & PL) 3145 if (cause & PL_F)
3150 csio_pl_intr_handler(hw); 3146 csio_pl_intr_handler(hw);
3151 3147
3152 if (cause & SMB) 3148 if (cause & SMB_F)
3153 csio_smb_intr_handler(hw); 3149 csio_smb_intr_handler(hw);
3154 3150
3155 if (cause & XGMAC0) 3151 if (cause & XGMAC0_F)
3156 csio_xgmac_intr_handler(hw, 0); 3152 csio_xgmac_intr_handler(hw, 0);
3157 3153
3158 if (cause & XGMAC1) 3154 if (cause & XGMAC1_F)
3159 csio_xgmac_intr_handler(hw, 1); 3155 csio_xgmac_intr_handler(hw, 1);
3160 3156
3161 if (cause & XGMAC_KR0) 3157 if (cause & XGMAC_KR0_F)
3162 csio_xgmac_intr_handler(hw, 2); 3158 csio_xgmac_intr_handler(hw, 2);
3163 3159
3164 if (cause & XGMAC_KR1) 3160 if (cause & XGMAC_KR1_F)
3165 csio_xgmac_intr_handler(hw, 3); 3161 csio_xgmac_intr_handler(hw, 3);
3166 3162
3167 if (cause & PCIE) 3163 if (cause & PCIE_F)
3168 hw->chip_ops->chip_pcie_intr_handler(hw); 3164 hw->chip_ops->chip_pcie_intr_handler(hw);
3169 3165
3170 if (cause & MC) 3166 if (cause & MC_F)
3171 csio_mem_intr_handler(hw, MEM_MC); 3167 csio_mem_intr_handler(hw, MEM_MC);
3172 3168
3173 if (cause & EDC0) 3169 if (cause & EDC0_F)
3174 csio_mem_intr_handler(hw, MEM_EDC0); 3170 csio_mem_intr_handler(hw, MEM_EDC0);
3175 3171
3176 if (cause & EDC1) 3172 if (cause & EDC1_F)
3177 csio_mem_intr_handler(hw, MEM_EDC1); 3173 csio_mem_intr_handler(hw, MEM_EDC1);
3178 3174
3179 if (cause & LE) 3175 if (cause & LE_F)
3180 csio_le_intr_handler(hw); 3176 csio_le_intr_handler(hw);
3181 3177
3182 if (cause & TP) 3178 if (cause & TP_F)
3183 csio_tp_intr_handler(hw); 3179 csio_tp_intr_handler(hw);
3184 3180
3185 if (cause & MA) 3181 if (cause & MA_F)
3186 csio_ma_intr_handler(hw); 3182 csio_ma_intr_handler(hw);
3187 3183
3188 if (cause & PM_TX) 3184 if (cause & PM_TX_F)
3189 csio_pmtx_intr_handler(hw); 3185 csio_pmtx_intr_handler(hw);
3190 3186
3191 if (cause & PM_RX) 3187 if (cause & PM_RX_F)
3192 csio_pmrx_intr_handler(hw); 3188 csio_pmrx_intr_handler(hw);
3193 3189
3194 if (cause & ULP_RX) 3190 if (cause & ULP_RX_F)
3195 csio_ulprx_intr_handler(hw); 3191 csio_ulprx_intr_handler(hw);
3196 3192
3197 if (cause & CPL_SWITCH) 3193 if (cause & CPL_SWITCH_F)
3198 csio_cplsw_intr_handler(hw); 3194 csio_cplsw_intr_handler(hw);
3199 3195
3200 if (cause & SGE) 3196 if (cause & SGE_F)
3201 csio_sge_intr_handler(hw); 3197 csio_sge_intr_handler(hw);
3202 3198
3203 if (cause & ULP_TX) 3199 if (cause & ULP_TX_F)
3204 csio_ulptx_intr_handler(hw); 3200 csio_ulptx_intr_handler(hw);
3205 3201
3206 /* Clear the interrupts just processed for which we are the master. */ 3202 /* Clear the interrupts just processed for which we are the master. */
3207 csio_wr_reg32(hw, cause & CSIO_GLBL_INTR_MASK, PL_INT_CAUSE); 3203 csio_wr_reg32(hw, cause & CSIO_GLBL_INTR_MASK, PL_INT_CAUSE_A);
3208 csio_rd_reg32(hw, PL_INT_CAUSE); /* flush */ 3204 csio_rd_reg32(hw, PL_INT_CAUSE_A); /* flush */
3209 3205
3210 return 1; 3206 return 1;
3211} 3207}
diff --git a/drivers/scsi/csiostor/csio_hw.h b/drivers/scsi/csiostor/csio_hw.h
index 68248da1b9af..bd9720467aa3 100644
--- a/drivers/scsi/csiostor/csio_hw.h
+++ b/drivers/scsi/csiostor/csio_hw.h
@@ -117,10 +117,10 @@ extern int csio_msi;
117#define CSIO_ASIC_DEVID_PROTO_MASK 0xFF00 117#define CSIO_ASIC_DEVID_PROTO_MASK 0xFF00
118#define CSIO_ASIC_DEVID_TYPE_MASK 0x00FF 118#define CSIO_ASIC_DEVID_TYPE_MASK 0x00FF
119 119
120#define CSIO_GLBL_INTR_MASK (CIM | MPS | PL | PCIE | MC | EDC0 | \ 120#define CSIO_GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | \
121 EDC1 | LE | TP | MA | PM_TX | PM_RX | \ 121 EDC0_F | EDC1_F | LE_F | TP_F | MA_F | \
122 ULP_RX | CPL_SWITCH | SGE | \ 122 PM_TX_F | PM_RX_F | ULP_RX_F | \
123 ULP_TX | SF) 123 CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
124 124
125/* 125/*
126 * Hard parameters used to initialize the card in the absence of a 126 * Hard parameters used to initialize the card in the absence of a
diff --git a/drivers/scsi/csiostor/csio_hw_chip.h b/drivers/scsi/csiostor/csio_hw_chip.h
index 01986623b2bd..70c0bdd7c796 100644
--- a/drivers/scsi/csiostor/csio_hw_chip.h
+++ b/drivers/scsi/csiostor/csio_hw_chip.h
@@ -77,8 +77,8 @@ static inline int csio_is_t5(uint16_t chip)
77 (csio_is_t4(hw->chip_id) ? (LP_INT_THRESH_M) : (LP_INT_THRESH_T5_M)) 77 (csio_is_t4(hw->chip_id) ? (LP_INT_THRESH_M) : (LP_INT_THRESH_T5_M))
78 78
79#define CSIO_MAC_INT_CAUSE_REG(hw, port) \ 79#define CSIO_MAC_INT_CAUSE_REG(hw, port) \
80 (csio_is_t4(hw->chip_id) ? (PORT_REG(port, XGMAC_PORT_INT_CAUSE)) : \ 80 (csio_is_t4(hw->chip_id) ? (PORT_REG(port, XGMAC_PORT_INT_CAUSE_A)) : \
81 (T5_PORT_REG(port, MAC_PORT_INT_CAUSE))) 81 (T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A)))
82 82
83#define FW_VERSION_MAJOR(hw) (csio_is_t4(hw->chip_id) ? 1 : 0) 83#define FW_VERSION_MAJOR(hw) (csio_is_t4(hw->chip_id) ? 1 : 0)
84#define FW_VERSION_MINOR(hw) (csio_is_t4(hw->chip_id) ? 2 : 0) 84#define FW_VERSION_MINOR(hw) (csio_is_t4(hw->chip_id) ? 2 : 0)
diff --git a/drivers/scsi/csiostor/csio_mb.c b/drivers/scsi/csiostor/csio_mb.c
index cb53985975a7..1132c41d99ce 100644
--- a/drivers/scsi/csiostor/csio_mb.c
+++ b/drivers/scsi/csiostor/csio_mb.c
@@ -1464,10 +1464,10 @@ csio_mb_isr_handler(struct csio_hw *hw)
1464 __be64 hdr; 1464 __be64 hdr;
1465 struct fw_cmd_hdr *fw_hdr; 1465 struct fw_cmd_hdr *fw_hdr;
1466 1466
1467 pl_cause = csio_rd_reg32(hw, MYPF_REG(PL_PF_INT_CAUSE)); 1467 pl_cause = csio_rd_reg32(hw, MYPF_REG(PL_PF_INT_CAUSE_A));
1468 cim_cause = csio_rd_reg32(hw, MYPF_REG(CIM_PF_HOST_INT_CAUSE_A)); 1468 cim_cause = csio_rd_reg32(hw, MYPF_REG(CIM_PF_HOST_INT_CAUSE_A));
1469 1469
1470 if (!(pl_cause & PFCIM) || !(cim_cause & MBMSGRDYINT_F)) { 1470 if (!(pl_cause & PFCIM_F) || !(cim_cause & MBMSGRDYINT_F)) {
1471 CSIO_INC_STATS(hw, n_mbint_unexp); 1471 CSIO_INC_STATS(hw, n_mbint_unexp);
1472 return -EINVAL; 1472 return -EINVAL;
1473 } 1473 }
@@ -1479,7 +1479,7 @@ csio_mb_isr_handler(struct csio_hw *hw)
1479 * first followed by PL-Cause next. 1479 * first followed by PL-Cause next.
1480 */ 1480 */
1481 csio_wr_reg32(hw, MBMSGRDYINT_F, MYPF_REG(CIM_PF_HOST_INT_CAUSE_A)); 1481 csio_wr_reg32(hw, MBMSGRDYINT_F, MYPF_REG(CIM_PF_HOST_INT_CAUSE_A));
1482 csio_wr_reg32(hw, PFCIM, MYPF_REG(PL_PF_INT_CAUSE)); 1482 csio_wr_reg32(hw, PFCIM_F, MYPF_REG(PL_PF_INT_CAUSE_A));
1483 1483
1484 ctl = csio_rd_reg32(hw, ctl_reg); 1484 ctl = csio_rd_reg32(hw, ctl_reg);
1485 1485
diff --git a/drivers/scsi/csiostor/csio_wr.c b/drivers/scsi/csiostor/csio_wr.c
index e22503b011cd..b47ea336e912 100644
--- a/drivers/scsi/csiostor/csio_wr.c
+++ b/drivers/scsi/csiostor/csio_wr.c
@@ -1343,7 +1343,7 @@ csio_wr_fixup_host_params(struct csio_hw *hw)
1343 SGE_FL_BUFFER_SIZE3_A); 1343 SGE_FL_BUFFER_SIZE3_A);
1344 } 1344 }
1345 1345
1346 csio_wr_reg32(hw, HPZ0(PAGE_SHIFT - 12), ULP_RX_TDDP_PSZ); 1346 csio_wr_reg32(hw, HPZ0_V(PAGE_SHIFT - 12), ULP_RX_TDDP_PSZ_A);
1347 1347
1348 /* default value of rx_dma_offset of the NIC driver */ 1348 /* default value of rx_dma_offset of the NIC driver */
1349 csio_set_reg_field(hw, SGE_CONTROL_A, 1349 csio_set_reg_field(hw, SGE_CONTROL_A,
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-23 09:09:13 -0400