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authorThierry Reding <treding@nvidia.com>2015-04-27 08:50:30 -0400
committerThierry Reding <treding@nvidia.com>2015-08-13 07:47:46 -0400
commit08f580ef2fcef724db1107545bc14306b7c9eae2 (patch)
tree21e5e19d24afff016f1772b50fef8c9e096f6010
parentddfb406b2f9f83e85734e43d043cdd1b2519df13 (diff)
drm/tegra: dpaux: Provide error message in probe
When probing the dpaux device fails, output proper error messages to help diagnose the cause of the failure. Signed-off-by: Thierry Reding <treding@nvidia.com>
-rw-r--r--drivers/gpu/drm/tegra/dpaux.c30
1 files changed, 24 insertions, 6 deletions
diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c
index 07b26972f487..c96c21bd91c1 100644
--- a/drivers/gpu/drm/tegra/dpaux.c
+++ b/drivers/gpu/drm/tegra/dpaux.c
@@ -294,26 +294,41 @@ static int tegra_dpaux_probe(struct platform_device *pdev)
294 } 294 }
295 295
296 dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux"); 296 dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux");
297 if (IS_ERR(dpaux->rst)) 297 if (IS_ERR(dpaux->rst)) {
298 dev_err(&pdev->dev, "failed to get reset control: %ld\n",
299 PTR_ERR(dpaux->rst));
298 return PTR_ERR(dpaux->rst); 300 return PTR_ERR(dpaux->rst);
301 }
299 302
300 dpaux->clk = devm_clk_get(&pdev->dev, NULL); 303 dpaux->clk = devm_clk_get(&pdev->dev, NULL);
301 if (IS_ERR(dpaux->clk)) 304 if (IS_ERR(dpaux->clk)) {
305 dev_err(&pdev->dev, "failed to get module clock: %ld\n",
306 PTR_ERR(dpaux->clk));
302 return PTR_ERR(dpaux->clk); 307 return PTR_ERR(dpaux->clk);
308 }
303 309
304 err = clk_prepare_enable(dpaux->clk); 310 err = clk_prepare_enable(dpaux->clk);
305 if (err < 0) 311 if (err < 0) {
312 dev_err(&pdev->dev, "failed to enable module clock: %d\n",
313 err);
306 return err; 314 return err;
315 }
307 316
308 reset_control_deassert(dpaux->rst); 317 reset_control_deassert(dpaux->rst);
309 318
310 dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent"); 319 dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent");
311 if (IS_ERR(dpaux->clk_parent)) 320 if (IS_ERR(dpaux->clk_parent)) {
321 dev_err(&pdev->dev, "failed to get parent clock: %ld\n",
322 PTR_ERR(dpaux->clk_parent));
312 return PTR_ERR(dpaux->clk_parent); 323 return PTR_ERR(dpaux->clk_parent);
324 }
313 325
314 err = clk_prepare_enable(dpaux->clk_parent); 326 err = clk_prepare_enable(dpaux->clk_parent);
315 if (err < 0) 327 if (err < 0) {
328 dev_err(&pdev->dev, "failed to enable parent clock: %d\n",
329 err);
316 return err; 330 return err;
331 }
317 332
318 err = clk_set_rate(dpaux->clk_parent, 270000000); 333 err = clk_set_rate(dpaux->clk_parent, 270000000);
319 if (err < 0) { 334 if (err < 0) {
@@ -323,8 +338,11 @@ static int tegra_dpaux_probe(struct platform_device *pdev)
323 } 338 }
324 339
325 dpaux->vdd = devm_regulator_get(&pdev->dev, "vdd"); 340 dpaux->vdd = devm_regulator_get(&pdev->dev, "vdd");
326 if (IS_ERR(dpaux->vdd)) 341 if (IS_ERR(dpaux->vdd)) {
342 dev_err(&pdev->dev, "failed to get VDD supply: %ld\n",
343 PTR_ERR(dpaux->vdd));
327 return PTR_ERR(dpaux->vdd); 344 return PTR_ERR(dpaux->vdd);
345 }
328 346
329 err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0, 347 err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0,
330 dev_name(dpaux->dev), dpaux); 348 dev_name(dpaux->dev), dpaux);