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authorLinus Torvalds <torvalds@linux-foundation.org>2016-05-24 18:46:06 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2016-05-24 18:46:06 -0400
commit08344f3b43a6bfaf2926122cef44d9a9583c2a4e (patch)
tree9333cc6bf35dae1810656bebb4d92af69e343270
parentd04f90ffecb7f6d7358197d7544f5536b6d4d8cc (diff)
parent88f1847639d68d732f83adb7aae94e0d989f7e28 (diff)
Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC late DT updates from Arnd Bergmann: "This is a collection of a few late fixes and other misc stuff that had dependencies on things being merged from other trees. The Renesas R-Car power domain handling, and the Nvidia Tegra USB support both hand notable changes that required changing the DT binding in a way that only provides compatibility with old DT blobs on new kernels but not vice versa. As a consequence, the DT changes are based on top of the driver changes and are now in this branch. For NXP i.MX and Samsung Exynos, the changes in here depend on other changes that got merged through the clk maintainer tree" * tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (35 commits) ARM: dts: exynos: Add support of Bus frequency using VDD_INT for exynos5422-odroidxu3 ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos542x SoC ARM: dts: exynos: Add NoC Probe dt node for Exynos542x SoC ARM: dts: exynos: Add support of bus frequency for exynos4412-trats/odroidu3 ARM: dts: exynos: Expand the voltage range of buck1/3 regulator for exynos4412-odroidu3 ARM: dts: exynos: Add support of bus frequency using VDD_INT for exynos3250-rinato ARM: dts: exynos: Add exynos4412-ppmu-common dtsi to delete duplicate PPMU nodes ARM: dts: exynos: Add bus nodes using VDD_MIF for Exynos4210 ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos4x12 ARM: dts: exynos: Add bus nodes using VDD_MIF for Exynos4x12 ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos3250 ARM: dts: exynos: Add DMC bus frequency for exynos3250-rinato/monk ARM: dts: exynos: Add DMC bus node for Exynos3250 ARM: tegra: Enable XUSB on Nyan ARM: tegra: Enable XUSB on Jetson TK1 ARM: tegra: Enable XUSB on Venice2 ARM: tegra: Add Tegra124 XUSB controller ARM: tegra: Move Tegra124 to the new XUSB pad controller binding ARM: dts: r8a7794: Use SYSC "always-on" PM Domain ARM: dts: r8a7793: Use SYSC "always-on" PM Domain ...
Diffstat
-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/exynos3250-monk.dts47
-rw-r--r--arch/arm/boot/dts/exynos3250-rinato.dts88
-rw-r--r--arch/arm/boot/dts/exynos3250.dtsi181
-rw-r--r--arch/arm/boot/dts/exynos4210.dtsi159
-rw-r--r--arch/arm/boot/dts/exynos4412-odroid-common.dtsi56
-rw-r--r--arch/arm/boot/dts/exynos4412-ppmu-common.dtsi50
-rw-r--r--arch/arm/boot/dts/exynos4412-trats2.dts88
-rw-r--r--arch/arm/boot/dts/exynos4x12.dtsi174
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi407
-rw-r--r--arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi99
-rw-r--r--arch/arm/boot/dts/imx7d-nitrogen7.dts745
-rw-r--r--arch/arm/boot/dts/imx7d.dtsi31
-rw-r--r--arch/arm/boot/dts/r8a7779.dtsi54
-rw-r--r--arch/arm/boot/dts/r8a7790.dtsi155
-rw-r--r--arch/arm/boot/dts/r8a7791.dtsi156
-rw-r--r--arch/arm/boot/dts/r8a7793.dtsi111
-rw-r--r--arch/arm/boot/dts/r8a7794.dtsi116
-rw-r--r--arch/arm/boot/dts/tegra124-jetson-tk1.dts116
-rw-r--r--arch/arm/boot/dts/tegra124-nyan.dtsi122
-rw-r--r--arch/arm/boot/dts/tegra124-venice2.dts101
-rw-r--r--arch/arm/boot/dts/tegra124.dtsi167
-rw-r--r--arch/arm/boot/dts/vf-colibri-eval-v3.dtsi16
-rw-r--r--arch/arm/boot/dts/vf-colibri.dtsi33
-rw-r--r--arch/arm/boot/dts/vfxxx.dtsi19
-rw-r--r--arch/arm64/boot/dts/renesas/r8a7795.dtsi123
26 files changed, 2918 insertions, 497 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 0f89d87cb2a0..06b6c2d695bf 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -399,6 +399,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
399 imx6ul-tx6ul-mainboard.dtb 399 imx6ul-tx6ul-mainboard.dtb
400dtb-$(CONFIG_SOC_IMX7D) += \ 400dtb-$(CONFIG_SOC_IMX7D) += \
401 imx7d-cl-som-imx7.dtb \ 401 imx7d-cl-som-imx7.dtb \
402 imx7d-nitrogen7.dtb \
402 imx7d-sbc-imx7.dtb \ 403 imx7d-sbc-imx7.dtb \
403 imx7d-sdb.dtb 404 imx7d-sdb.dtb
404dtb-$(CONFIG_SOC_LS1021A) += \ 405dtb-$(CONFIG_SOC_LS1021A) += \
diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts
index 267f81adb42f..8c8906266310 100644
--- a/arch/arm/boot/dts/exynos3250-monk.dts
+++ b/arch/arm/boot/dts/exynos3250-monk.dts
@@ -14,6 +14,7 @@
14 14
15/dts-v1/; 15/dts-v1/;
16#include "exynos3250.dtsi" 16#include "exynos3250.dtsi"
17#include "exynos4412-ppmu-common.dtsi"
17#include <dt-bindings/input/input.h> 18#include <dt-bindings/input/input.h>
18#include <dt-bindings/gpio/gpio.h> 19#include <dt-bindings/gpio/gpio.h>
19#include <dt-bindings/clock/samsung,s2mps11.h> 20#include <dt-bindings/clock/samsung,s2mps11.h>
@@ -156,6 +157,12 @@
156 }; 157 };
157}; 158};
158 159
160&bus_dmc {
161 devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
162 vdd-supply = <&buck1_reg>;
163 status = "okay";
164};
165
159&cpu0 { 166&cpu0 {
160 cpu0-supply = <&buck2_reg>; 167 cpu0-supply = <&buck2_reg>;
161}; 168};
@@ -458,46 +465,6 @@
458 status = "okay"; 465 status = "okay";
459}; 466};
460 467
461&ppmu_dmc0 {
462 status = "okay";
463
464 events {
465 ppmu_dmc0_3: ppmu-event3-dmc0 {
466 event-name = "ppmu-event3-dmc0";
467 };
468 };
469};
470
471&ppmu_dmc1 {
472 status = "okay";
473
474 events {
475 ppmu_dmc1_3: ppmu-event3-dmc1 {
476 event-name = "ppmu-event3-dmc1";
477 };
478 };
479};
480
481&ppmu_leftbus {
482 status = "okay";
483
484 events {
485 ppmu_leftbus_3: ppmu-event3-leftbus {
486 event-name = "ppmu-event3-leftbus";
487 };
488 };
489};
490
491&ppmu_rightbus {
492 status = "okay";
493
494 events {
495 ppmu_rightbus_3: ppmu-event3-rightbus {
496 event-name = "ppmu-event3-rightbus";
497 };
498 };
499};
500
501&xusbxti { 468&xusbxti {
502 clock-frequency = <24000000>; 469 clock-frequency = <24000000>;
503}; 470};
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts
index 31eb09bae0a2..e422819591dc 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -14,6 +14,7 @@
14 14
15/dts-v1/; 15/dts-v1/;
16#include "exynos3250.dtsi" 16#include "exynos3250.dtsi"
17#include "exynos4412-ppmu-common.dtsi"
17#include <dt-bindings/input/input.h> 18#include <dt-bindings/input/input.h>
18#include <dt-bindings/gpio/gpio.h> 19#include <dt-bindings/gpio/gpio.h>
19#include <dt-bindings/clock/samsung,s2mps11.h> 20#include <dt-bindings/clock/samsung,s2mps11.h>
@@ -147,6 +148,53 @@
147 }; 148 };
148}; 149};
149 150
151&bus_dmc {
152 devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
153 vdd-supply = <&buck1_reg>;
154 status = "okay";
155};
156
157&bus_leftbus {
158 devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
159 vdd-supply = <&buck3_reg>;
160 status = "okay";
161};
162
163&bus_rightbus {
164 devfreq = <&bus_leftbus>;
165 status = "okay";
166};
167
168&bus_lcd0 {
169 devfreq = <&bus_leftbus>;
170 status = "okay";
171};
172
173&bus_fsys {
174 devfreq = <&bus_leftbus>;
175 status = "okay";
176};
177
178&bus_mcuisp {
179 devfreq = <&bus_leftbus>;
180 status = "okay";
181};
182
183&bus_isp {
184 devfreq = <&bus_leftbus>;
185 status = "okay";
186};
187
188&bus_peril {
189 devfreq = <&bus_leftbus>;
190 status = "okay";
191};
192
193&bus_mfc {
194 devfreq = <&bus_leftbus>;
195 status = "okay";
196};
197
150&cpu0 { 198&cpu0 {
151 cpu0-supply = <&buck2_reg>; 199 cpu0-supply = <&buck2_reg>;
152}; 200};
@@ -635,46 +683,6 @@
635 status = "okay"; 683 status = "okay";
636}; 684};
637 685
638&ppmu_dmc0 {
639 status = "okay";
640
641 events {
642 ppmu_dmc0_3: ppmu-event3-dmc0 {
643 event-name = "ppmu-event3-dmc0";
644 };
645 };
646};
647
648&ppmu_dmc1 {
649 status = "okay";
650
651 events {
652 ppmu_dmc1_3: ppmu-event3-dmc1 {
653 event-name = "ppmu-event3-dmc1";
654 };
655 };
656};
657
658&ppmu_leftbus {
659 status = "okay";
660
661 events {
662 ppmu_leftbus_3: ppmu-event3-leftbus {
663 event-name = "ppmu-event3-leftbus";
664 };
665 };
666};
667
668&ppmu_rightbus {
669 status = "okay";
670
671 events {
672 ppmu_rightbus_3: ppmu-event3-rightbus {
673 event-name = "ppmu-event3-rightbus";
674 };
675 };
676};
677
678&xusbxti { 686&xusbxti {
679 clock-frequency = <24000000>; 687 clock-frequency = <24000000>;
680}; 688};
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 094782b207ee..62f3dcd9e046 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -713,6 +713,187 @@
713 clock-names = "ppmu"; 713 clock-names = "ppmu";
714 status = "disabled"; 714 status = "disabled";
715 }; 715 };
716
717 bus_dmc: bus_dmc {
718 compatible = "samsung,exynos-bus";
719 clocks = <&cmu_dmc CLK_DIV_DMC>;
720 clock-names = "bus";
721 operating-points-v2 = <&bus_dmc_opp_table>;
722 status = "disabled";
723 };
724
725 bus_dmc_opp_table: opp_table1 {
726 compatible = "operating-points-v2";
727 opp-shared;
728
729 opp@50000000 {
730 opp-hz = /bits/ 64 <50000000>;
731 opp-microvolt = <800000>;
732 };
733 opp@100000000 {
734 opp-hz = /bits/ 64 <100000000>;
735 opp-microvolt = <800000>;
736 };
737 opp@134000000 {
738 opp-hz = /bits/ 64 <134000000>;
739 opp-microvolt = <800000>;
740 };
741 opp@200000000 {
742 opp-hz = /bits/ 64 <200000000>;
743 opp-microvolt = <825000>;
744 };
745 opp@400000000 {
746 opp-hz = /bits/ 64 <400000000>;
747 opp-microvolt = <875000>;
748 };
749 };
750
751 bus_leftbus: bus_leftbus {
752 compatible = "samsung,exynos-bus";
753 clocks = <&cmu CLK_DIV_GDL>;
754 clock-names = "bus";
755 operating-points-v2 = <&bus_leftbus_opp_table>;
756 status = "disabled";
757 };
758
759 bus_rightbus: bus_rightbus {
760 compatible = "samsung,exynos-bus";
761 clocks = <&cmu CLK_DIV_GDR>;
762 clock-names = "bus";
763 operating-points-v2 = <&bus_leftbus_opp_table>;
764 status = "disabled";
765 };
766
767 bus_lcd0: bus_lcd0 {
768 compatible = "samsung,exynos-bus";
769 clocks = <&cmu CLK_DIV_ACLK_160>;
770 clock-names = "bus";
771 operating-points-v2 = <&bus_leftbus_opp_table>;
772 status = "disabled";
773 };
774
775 bus_fsys: bus_fsys {
776 compatible = "samsung,exynos-bus";
777 clocks = <&cmu CLK_DIV_ACLK_200>;
778 clock-names = "bus";
779 operating-points-v2 = <&bus_leftbus_opp_table>;
780 status = "disabled";
781 };
782
783 bus_mcuisp: bus_mcuisp {
784 compatible = "samsung,exynos-bus";
785 clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
786 clock-names = "bus";
787 operating-points-v2 = <&bus_mcuisp_opp_table>;
788 status = "disabled";
789 };
790
791 bus_isp: bus_isp {
792 compatible = "samsung,exynos-bus";
793 clocks = <&cmu CLK_DIV_ACLK_266>;
794 clock-names = "bus";
795 operating-points-v2 = <&bus_isp_opp_table>;
796 status = "disabled";
797 };
798
799 bus_peril: bus_peril {
800 compatible = "samsung,exynos-bus";
801 clocks = <&cmu CLK_DIV_ACLK_100>;
802 clock-names = "bus";
803 operating-points-v2 = <&bus_peril_opp_table>;
804 status = "disabled";
805 };
806
807 bus_mfc: bus_mfc {
808 compatible = "samsung,exynos-bus";
809 clocks = <&cmu CLK_SCLK_MFC>;
810 clock-names = "bus";
811 operating-points-v2 = <&bus_leftbus_opp_table>;
812 status = "disabled";
813 };
814
815 bus_leftbus_opp_table: opp_table2 {
816 compatible = "operating-points-v2";
817 opp-shared;
818
819 opp@50000000 {
820 opp-hz = /bits/ 64 <50000000>;
821 opp-microvolt = <900000>;
822 };
823 opp@80000000 {
824 opp-hz = /bits/ 64 <80000000>;
825 opp-microvolt = <900000>;
826 };
827 opp@100000000 {
828 opp-hz = /bits/ 64 <100000000>;
829 opp-microvolt = <1000000>;
830 };
831 opp@134000000 {
832 opp-hz = /bits/ 64 <134000000>;
833 opp-microvolt = <1000000>;
834 };
835 opp@200000000 {
836 opp-hz = /bits/ 64 <200000000>;
837 opp-microvolt = <1000000>;
838 };
839 };
840
841 bus_mcuisp_opp_table: opp_table3 {
842 compatible = "operating-points-v2";
843 opp-shared;
844
845 opp@50000000 {
846 opp-hz = /bits/ 64 <50000000>;
847 };
848 opp@80000000 {
849 opp-hz = /bits/ 64 <80000000>;
850 };
851 opp@100000000 {
852 opp-hz = /bits/ 64 <100000000>;
853 };
854 opp@200000000 {
855 opp-hz = /bits/ 64 <200000000>;
856 };
857 opp@400000000 {
858 opp-hz = /bits/ 64 <400000000>;
859 };
860 };
861
862 bus_isp_opp_table: opp_table4 {
863 compatible = "operating-points-v2";
864 opp-shared;
865
866 opp@50000000 {
867 opp-hz = /bits/ 64 <50000000>;
868 };
869 opp@80000000 {
870 opp-hz = /bits/ 64 <80000000>;
871 };
872 opp@100000000 {
873 opp-hz = /bits/ 64 <100000000>;
874 };
875 opp@200000000 {
876 opp-hz = /bits/ 64 <200000000>;
877 };
878 opp@300000000 {
879 opp-hz = /bits/ 64 <300000000>;
880 };
881 };
882
883 bus_peril_opp_table: opp_table5 {
884 compatible = "operating-points-v2";
885 opp-shared;
886
887 opp@50000000 {
888 opp-hz = /bits/ 64 <50000000>;
889 };
890 opp@80000000 {
891 opp-hz = /bits/ 64 <80000000>;
892 };
893 opp@100000000 {
894 opp-hz = /bits/ 64 <100000000>;
895 };
896 };
716 }; 897 };
717}; 898};
718 899
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index c1cb8df6da07..2d9b02967105 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -257,6 +257,165 @@
257 power-domains = <&pd_lcd1>; 257 power-domains = <&pd_lcd1>;
258 #iommu-cells = <0>; 258 #iommu-cells = <0>;
259 }; 259 };
260
261 bus_dmc: bus_dmc {
262 compatible = "samsung,exynos-bus";
263 clocks = <&clock CLK_DIV_DMC>;
264 clock-names = "bus";
265 operating-points-v2 = <&bus_dmc_opp_table>;
266 status = "disabled";
267 };
268
269 bus_acp: bus_acp {
270 compatible = "samsung,exynos-bus";
271 clocks = <&clock CLK_DIV_ACP>;
272 clock-names = "bus";
273 operating-points-v2 = <&bus_acp_opp_table>;
274 status = "disabled";
275 };
276
277 bus_peri: bus_peri {
278 compatible = "samsung,exynos-bus";
279 clocks = <&clock CLK_ACLK100>;
280 clock-names = "bus";
281 operating-points-v2 = <&bus_peri_opp_table>;
282 status = "disabled";
283 };
284
285 bus_fsys: bus_fsys {
286 compatible = "samsung,exynos-bus";
287 clocks = <&clock CLK_ACLK133>;
288 clock-names = "bus";
289 operating-points-v2 = <&bus_fsys_opp_table>;
290 status = "disabled";
291 };
292
293 bus_display: bus_display {
294 compatible = "samsung,exynos-bus";
295 clocks = <&clock CLK_ACLK160>;
296 clock-names = "bus";
297 operating-points-v2 = <&bus_display_opp_table>;
298 status = "disabled";
299 };
300
301 bus_lcd0: bus_lcd0 {
302 compatible = "samsung,exynos-bus";
303 clocks = <&clock CLK_ACLK200>;
304 clock-names = "bus";
305 operating-points-v2 = <&bus_leftbus_opp_table>;
306 status = "disabled";
307 };
308
309 bus_leftbus: bus_leftbus {
310 compatible = "samsung,exynos-bus";
311 clocks = <&clock CLK_DIV_GDL>;
312 clock-names = "bus";
313 operating-points-v2 = <&bus_leftbus_opp_table>;
314 status = "disabled";
315 };
316
317 bus_rightbus: bus_rightbus {
318 compatible = "samsung,exynos-bus";
319 clocks = <&clock CLK_DIV_GDR>;
320 clock-names = "bus";
321 operating-points-v2 = <&bus_leftbus_opp_table>;
322 status = "disabled";
323 };
324
325 bus_mfc: bus_mfc {
326 compatible = "samsung,exynos-bus";
327 clocks = <&clock CLK_SCLK_MFC>;
328 clock-names = "bus";
329 operating-points-v2 = <&bus_leftbus_opp_table>;
330 status = "disabled";
331 };
332
333 bus_dmc_opp_table: opp_table1 {
334 compatible = "operating-points-v2";
335 opp-shared;
336
337 opp@134000000 {
338 opp-hz = /bits/ 64 <134000000>;
339 opp-microvolt = <1025000>;
340 };
341 opp@267000000 {
342 opp-hz = /bits/ 64 <267000000>;
343 opp-microvolt = <1050000>;
344 };
345 opp@400000000 {
346 opp-hz = /bits/ 64 <400000000>;
347 opp-microvolt = <1150000>;
348 };
349 };
350
351 bus_acp_opp_table: opp_table2 {
352 compatible = "operating-points-v2";
353 opp-shared;
354
355 opp@134000000 {
356 opp-hz = /bits/ 64 <134000000>;
357 };
358 opp@160000000 {
359 opp-hz = /bits/ 64 <160000000>;
360 };
361 opp@200000000 {
362 opp-hz = /bits/ 64 <200000000>;
363 };
364 };
365
366 bus_peri_opp_table: opp_table3 {
367 compatible = "operating-points-v2";
368 opp-shared;
369
370 opp@5000000 {
371 opp-hz = /bits/ 64 <5000000>;
372 };
373 opp@100000000 {
374 opp-hz = /bits/ 64 <100000000>;
375 };
376 };
377
378 bus_fsys_opp_table: opp_table4 {
379 compatible = "operating-points-v2";
380 opp-shared;
381
382 opp@10000000 {
383 opp-hz = /bits/ 64 <10000000>;
384 };
385 opp@134000000 {
386 opp-hz = /bits/ 64 <134000000>;
387 };
388 };
389
390 bus_display_opp_table: opp_table5 {
391 compatible = "operating-points-v2";
392 opp-shared;
393
394 opp@100000000 {
395 opp-hz = /bits/ 64 <100000000>;
396 };
397 opp@134000000 {
398 opp-hz = /bits/ 64 <134000000>;
399 };
400 opp@160000000 {
401 opp-hz = /bits/ 64 <160000000>;
402 };
403 };
404
405 bus_leftbus_opp_table: opp_table6 {
406 compatible = "operating-points-v2";
407 opp-shared;
408
409 opp@100000000 {
410 opp-hz = /bits/ 64 <100000000>;
411 };
412 opp@160000000 {
413 opp-hz = /bits/ 64 <160000000>;
414 };
415 opp@200000000 {
416 opp-hz = /bits/ 64 <200000000>;
417 };
418 };
260}; 419};
261 420
262&gic { 421&gic {
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index cab0f07d7d28..ec7619a384a2 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -11,6 +11,7 @@
11#include <dt-bindings/input/input.h> 11#include <dt-bindings/input/input.h>
12#include <dt-bindings/clock/maxim,max77686.h> 12#include <dt-bindings/clock/maxim,max77686.h>
13#include "exynos4412.dtsi" 13#include "exynos4412.dtsi"
14#include "exynos4412-ppmu-common.dtsi"
14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/gpio/gpio.h>
15 16
16/ { 17/ {
@@ -108,6 +109,53 @@
108 }; 109 };
109}; 110};
110 111
112&bus_dmc {
113 devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
114 vdd-supply = <&buck1_reg>;
115 status = "okay";
116};
117
118&bus_acp {
119 devfreq = <&bus_dmc>;
120 status = "okay";
121};
122
123&bus_c2c {
124 devfreq = <&bus_dmc>;
125 status = "okay";
126};
127
128&bus_leftbus {
129 devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
130 vdd-supply = <&buck3_reg>;
131 status = "okay";
132};
133
134&bus_rightbus {
135 devfreq = <&bus_leftbus>;
136 status = "okay";
137};
138
139&bus_display {
140 devfreq = <&bus_leftbus>;
141 status = "okay";
142};
143
144&bus_fsys {
145 devfreq = <&bus_leftbus>;
146 status = "okay";
147};
148
149&bus_peri {
150 devfreq = <&bus_leftbus>;
151 status = "okay";
152};
153
154&bus_mfc {
155 devfreq = <&bus_leftbus>;
156 status = "okay";
157};
158
111&cpu0 { 159&cpu0 {
112 cpu0-supply = <&buck2_reg>; 160 cpu0-supply = <&buck2_reg>;
113}; 161};
@@ -359,8 +407,8 @@
359 407
360 buck1_reg: BUCK1 { 408 buck1_reg: BUCK1 {
361 regulator-name = "vdd_mif"; 409 regulator-name = "vdd_mif";
362 regulator-min-microvolt = <1000000>; 410 regulator-min-microvolt = <900000>;
363 regulator-max-microvolt = <1000000>; 411 regulator-max-microvolt = <1100000>;
364 regulator-always-on; 412 regulator-always-on;
365 regulator-boot-on; 413 regulator-boot-on;
366 }; 414 };
@@ -375,8 +423,8 @@
375 423
376 buck3_reg: BUCK3 { 424 buck3_reg: BUCK3 {
377 regulator-name = "vdd_int"; 425 regulator-name = "vdd_int";
378 regulator-min-microvolt = <1000000>; 426 regulator-min-microvolt = <900000>;
379 regulator-max-microvolt = <1000000>; 427 regulator-max-microvolt = <1050000>;
380 regulator-always-on; 428 regulator-always-on;
381 regulator-boot-on; 429 regulator-boot-on;
382 }; 430 };
diff --git a/arch/arm/boot/dts/exynos4412-ppmu-common.dtsi b/arch/arm/boot/dts/exynos4412-ppmu-common.dtsi
new file mode 100644
index 000000000000..16e4b77d8cb1
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-ppmu-common.dtsi
@@ -0,0 +1,50 @@
1/*
2 * Device tree sources for Exynos4412 PPMU common device tree
3 *
4 * Copyright (C) 2015 Samsung Electronics
5 * Author: Chanwoo Choi <cw00.choi@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12&ppmu_dmc0 {
13 status = "okay";
14
15 events {
16 ppmu_dmc0_3: ppmu-event3-dmc0 {
17 event-name = "ppmu-event3-dmc0";
18 };
19 };
20};
21
22&ppmu_dmc1 {
23 status = "okay";
24
25 events {
26 ppmu_dmc1_3: ppmu-event3-dmc1 {
27 event-name = "ppmu-event3-dmc1";
28 };
29 };
30};
31
32&ppmu_leftbus {
33 status = "okay";
34
35 events {
36 ppmu_leftbus_3: ppmu-event3-leftbus {
37 event-name = "ppmu-event3-leftbus";
38 };
39 };
40};
41
42&ppmu_rightbus {
43 status = "okay";
44
45 events {
46 ppmu_rightbus_3: ppmu-event3-rightbus {
47 event-name = "ppmu-event3-rightbus";
48 };
49 };
50};
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index 5d1eaea3f778..9336fd4824d9 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -14,6 +14,7 @@
14 14
15/dts-v1/; 15/dts-v1/;
16#include "exynos4412.dtsi" 16#include "exynos4412.dtsi"
17#include "exynos4412-ppmu-common.dtsi"
17#include <dt-bindings/gpio/gpio.h> 18#include <dt-bindings/gpio/gpio.h>
18#include <dt-bindings/interrupt-controller/irq.h> 19#include <dt-bindings/interrupt-controller/irq.h>
19#include <dt-bindings/clock/maxim,max77686.h> 20#include <dt-bindings/clock/maxim,max77686.h>
@@ -288,6 +289,53 @@
288 status = "okay"; 289 status = "okay";
289}; 290};
290 291
292&bus_dmc {
293 devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
294 vdd-supply = <&buck1_reg>;
295 status = "okay";
296};
297
298&bus_acp {
299 devfreq = <&bus_dmc>;
300 status = "okay";
301};
302
303&bus_c2c {
304 devfreq = <&bus_dmc>;
305 status = "okay";
306};
307
308&bus_leftbus {
309 devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
310 vdd-supply = <&buck3_reg>;
311 status = "okay";
312};
313
314&bus_rightbus {
315 devfreq = <&bus_leftbus>;
316 status = "okay";
317};
318
319&bus_display {
320 devfreq = <&bus_leftbus>;
321 status = "okay";
322};
323
324&bus_fsys {
325 devfreq = <&bus_leftbus>;
326 status = "okay";
327};
328
329&bus_peri {
330 devfreq = <&bus_leftbus>;
331 status = "okay";
332};
333
334&bus_mfc {
335 devfreq = <&bus_leftbus>;
336 status = "okay";
337};
338
291&cpu0 { 339&cpu0 {
292 cpu0-supply = <&buck2_reg>; 340 cpu0-supply = <&buck2_reg>;
293}; 341};
@@ -871,46 +919,6 @@
871 assigned-clock-parents = <&clock CLK_XUSBXTI>; 919 assigned-clock-parents = <&clock CLK_XUSBXTI>;
872}; 920};
873 921
874&ppmu_dmc0 {
875 status = "okay";
876
877 events {
878 ppmu_dmc0_3: ppmu-event3-dmc0 {
879 event-name = "ppmu-event3-dmc0";
880 };
881 };
882};
883
884&ppmu_dmc1 {
885 status = "okay";
886
887 events {
888 ppmu_dmc1_3: ppmu-event3-dmc1 {
889 event-name = "ppmu-event3-dmc1";
890 };
891 };
892};
893
894&ppmu_leftbus {
895 status = "okay";
896
897 events {
898 ppmu_leftbus_3: ppmu-event3-leftbus {
899 event-name = "ppmu-event3-leftbus";
900 };
901 };
902};
903
904&ppmu_rightbus {
905 status = "okay";
906
907 events {
908 ppmu_rightbus_3: ppmu-event3-rightbus {
909 event-name = "ppmu-event3-rightbus";
910 };
911 };
912};
913
914&pinctrl_0 { 922&pinctrl_0 {
915 pinctrl-names = "default"; 923 pinctrl-names = "default";
916 pinctrl-0 = <&sleep0>; 924 pinctrl-0 = <&sleep0>;
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index b7490ea0c75c..c452499ae8c9 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -281,6 +281,180 @@
281 clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>; 281 clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>;
282 #iommu-cells = <0>; 282 #iommu-cells = <0>;
283 }; 283 };
284
285 bus_dmc: bus_dmc {
286 compatible = "samsung,exynos-bus";
287 clocks = <&clock CLK_DIV_DMC>;
288 clock-names = "bus";
289 operating-points-v2 = <&bus_dmc_opp_table>;
290 status = "disabled";
291 };
292
293 bus_acp: bus_acp {
294 compatible = "samsung,exynos-bus";
295 clocks = <&clock CLK_DIV_ACP>;
296 clock-names = "bus";
297 operating-points-v2 = <&bus_acp_opp_table>;
298 status = "disabled";
299 };
300
301 bus_c2c: bus_c2c {
302 compatible = "samsung,exynos-bus";
303 clocks = <&clock CLK_DIV_C2C>;
304 clock-names = "bus";
305 operating-points-v2 = <&bus_dmc_opp_table>;
306 status = "disabled";
307 };
308
309 bus_dmc_opp_table: opp_table1 {
310 compatible = "operating-points-v2";
311 opp-shared;
312
313 opp@100000000 {
314 opp-hz = /bits/ 64 <100000000>;
315 opp-microvolt = <900000>;
316 };
317 opp@134000000 {
318 opp-hz = /bits/ 64 <134000000>;
319 opp-microvolt = <900000>;
320 };
321 opp@160000000 {
322 opp-hz = /bits/ 64 <160000000>;
323 opp-microvolt = <900000>;
324 };
325 opp@267000000 {
326 opp-hz = /bits/ 64 <267000000>;
327 opp-microvolt = <950000>;
328 };
329 opp@400000000 {
330 opp-hz = /bits/ 64 <400000000>;
331 opp-microvolt = <1050000>;
332 };
333 };
334
335 bus_acp_opp_table: opp_table2 {
336 compatible = "operating-points-v2";
337 opp-shared;
338
339 opp@100000000 {
340 opp-hz = /bits/ 64 <100000000>;
341 };
342 opp@134000000 {
343 opp-hz = /bits/ 64 <134000000>;
344 };
345 opp@160000000 {
346 opp-hz = /bits/ 64 <160000000>;
347 };
348 opp@267000000 {
349 opp-hz = /bits/ 64 <267000000>;
350 };
351 };
352
353 bus_leftbus: bus_leftbus {
354 compatible = "samsung,exynos-bus";
355 clocks = <&clock CLK_DIV_GDL>;
356 clock-names = "bus";
357 operating-points-v2 = <&bus_leftbus_opp_table>;
358 status = "disabled";
359 };
360
361 bus_rightbus: bus_rightbus {
362 compatible = "samsung,exynos-bus";
363 clocks = <&clock CLK_DIV_GDR>;
364 clock-names = "bus";
365 operating-points-v2 = <&bus_leftbus_opp_table>;
366 status = "disabled";
367 };
368
369 bus_display: bus_display {
370 compatible = "samsung,exynos-bus";
371 clocks = <&clock CLK_ACLK160>;
372 clock-names = "bus";
373 operating-points-v2 = <&bus_display_opp_table>;
374 status = "disabled";
375 };
376
377 bus_fsys: bus_fsys {
378 compatible = "samsung,exynos-bus";
379 clocks = <&clock CLK_ACLK133>;
380 clock-names = "bus";
381 operating-points-v2 = <&bus_fsys_opp_table>;
382 status = "disabled";
383 };
384
385 bus_peri: bus_peri {
386 compatible = "samsung,exynos-bus";
387 clocks = <&clock CLK_ACLK100>;
388 clock-names = "bus";
389 operating-points-v2 = <&bus_peri_opp_table>;
390 status = "disabled";
391 };
392
393 bus_mfc: bus_mfc {
394 compatible = "samsung,exynos-bus";
395 clocks = <&clock CLK_SCLK_MFC>;
396 clock-names = "bus";
397 operating-points-v2 = <&bus_leftbus_opp_table>;
398 status = "disabled";
399 };
400
401 bus_leftbus_opp_table: opp_table3 {
402 compatible = "operating-points-v2";
403 opp-shared;
404
405 opp@100000000 {
406 opp-hz = /bits/ 64 <100000000>;
407 opp-microvolt = <900000>;
408 };
409 opp@134000000 {
410 opp-hz = /bits/ 64 <134000000>;
411 opp-microvolt = <925000>;
412 };
413 opp@160000000 {
414 opp-hz = /bits/ 64 <160000000>;
415 opp-microvolt = <950000>;
416 };
417 opp@200000000 {
418 opp-hz = /bits/ 64 <200000000>;
419 opp-microvolt = <1000000>;
420 };
421 };
422
423 bus_display_opp_table: opp_table4 {
424 compatible = "operating-points-v2";
425 opp-shared;
426
427 opp@160000000 {
428 opp-hz = /bits/ 64 <160000000>;
429 };
430 opp@200000000 {
431 opp-hz = /bits/ 64 <200000000>;
432 };
433 };
434
435 bus_fsys_opp_table: opp_table5 {
436 compatible = "operating-points-v2";
437 opp-shared;
438
439 opp@100000000 {
440 opp-hz = /bits/ 64 <100000000>;
441 };
442 opp@134000000 {
443 opp-hz = /bits/ 64 <134000000>;
444 };
445 };
446
447 bus_peri_opp_table: opp_table6 {
448 compatible = "operating-points-v2";
449 opp-shared;
450
451 opp@50000000 {
452 opp-hz = /bits/ 64 <50000000>;
453 };
454 opp@100000000 {
455 opp-hz = /bits/ 64 <100000000>;
456 };
457 };
284}; 458};
285 459
286&combiner { 460&combiner {
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 4c8523471c65..c6e05eb88937 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -294,6 +294,42 @@
294 }; 294 };
295 }; 295 };
296 296
297 nocp_mem0_0: nocp@10CA1000 {
298 compatible = "samsung,exynos5420-nocp";
299 reg = <0x10CA1000 0x200>;
300 status = "disabled";
301 };
302
303 nocp_mem0_1: nocp@10CA1400 {
304 compatible = "samsung,exynos5420-nocp";
305 reg = <0x10CA1400 0x200>;
306 status = "disabled";
307 };
308
309 nocp_mem1_0: nocp@10CA1800 {
310 compatible = "samsung,exynos5420-nocp";
311 reg = <0x10CA1800 0x200>;
312 status = "disabled";
313 };
314
315 nocp_mem1_1: nocp@10CA1C00 {
316 compatible = "samsung,exynos5420-nocp";
317 reg = <0x10CA1C00 0x200>;
318 status = "disabled";
319 };
320
321 nocp_g3d_0: nocp@11A51000 {
322 compatible = "samsung,exynos5420-nocp";
323 reg = <0x11A51000 0x200>;
324 status = "disabled";
325 };
326
327 nocp_g3d_1: nocp@11A51400 {
328 compatible = "samsung,exynos5420-nocp";
329 reg = <0x11A51400 0x200>;
330 status = "disabled";
331 };
332
297 gsc_pd: power-domain@10044000 { 333 gsc_pd: power-domain@10044000 {
298 compatible = "samsung,exynos4210-pd"; 334 compatible = "samsung,exynos4210-pd";
299 reg = <0x10044000 0x20>; 335 reg = <0x10044000 0x20>;
@@ -1188,6 +1224,377 @@
1188 power-domains = <&disp_pd>; 1224 power-domains = <&disp_pd>;
1189 #iommu-cells = <0>; 1225 #iommu-cells = <0>;
1190 }; 1226 };
1227
1228 bus_wcore: bus_wcore {
1229 compatible = "samsung,exynos-bus";
1230 clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
1231 clock-names = "bus";
1232 operating-points-v2 = <&bus_wcore_opp_table>;
1233 status = "disabled";
1234 };
1235
1236 bus_noc: bus_noc {
1237 compatible = "samsung,exynos-bus";
1238 clocks = <&clock CLK_DOUT_ACLK100_NOC>;
1239 clock-names = "bus";
1240 operating-points-v2 = <&bus_noc_opp_table>;
1241 status = "disabled";
1242 };
1243
1244 bus_fsys_apb: bus_fsys_apb {
1245 compatible = "samsung,exynos-bus";
1246 clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
1247 clock-names = "bus";
1248 operating-points-v2 = <&bus_fsys_apb_opp_table>;
1249 status = "disabled";
1250 };
1251
1252 bus_fsys: bus_fsys {
1253 compatible = "samsung,exynos-bus";
1254 clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
1255 clock-names = "bus";
1256 operating-points-v2 = <&bus_fsys_apb_opp_table>;
1257 status = "disabled";
1258 };
1259
1260 bus_fsys2: bus_fsys2 {
1261 compatible = "samsung,exynos-bus";
1262 clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
1263 clock-names = "bus";
1264 operating-points-v2 = <&bus_fsys2_opp_table>;
1265 status = "disabled";
1266 };
1267
1268 bus_mfc: bus_mfc {
1269 compatible = "samsung,exynos-bus";
1270 clocks = <&clock CLK_DOUT_ACLK333>;
1271 clock-names = "bus";
1272 operating-points-v2 = <&bus_mfc_opp_table>;
1273 status = "disabled";
1274 };
1275
1276 bus_gen: bus_gen {
1277 compatible = "samsung,exynos-bus";
1278 clocks = <&clock CLK_DOUT_ACLK266>;
1279 clock-names = "bus";
1280 operating-points-v2 = <&bus_gen_opp_table>;
1281 status = "disabled";
1282 };
1283
1284 bus_peri: bus_peri {
1285 compatible = "samsung,exynos-bus";
1286 clocks = <&clock CLK_DOUT_ACLK66>;
1287 clock-names = "bus";
1288 operating-points-v2 = <&bus_peri_opp_table>;
1289 status = "disabled";
1290 };
1291
1292 bus_g2d: bus_g2d {
1293 compatible = "samsung,exynos-bus";
1294 clocks = <&clock CLK_DOUT_ACLK333_G2D>;
1295 clock-names = "bus";
1296 operating-points-v2 = <&bus_g2d_opp_table>;
1297 status = "disabled";
1298 };
1299
1300 bus_g2d_acp: bus_g2d_acp {
1301 compatible = "samsung,exynos-bus";
1302 clocks = <&clock CLK_DOUT_ACLK266_G2D>;
1303 clock-names = "bus";
1304 operating-points-v2 = <&bus_g2d_acp_opp_table>;
1305 status = "disabled";
1306 };
1307
1308 bus_jpeg: bus_jpeg {
1309 compatible = "samsung,exynos-bus";
1310 clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
1311 clock-names = "bus";
1312 operating-points-v2 = <&bus_jpeg_opp_table>;
1313 status = "disabled";
1314 };
1315
1316 bus_jpeg_apb: bus_jpeg_apb {
1317 compatible = "samsung,exynos-bus";
1318 clocks = <&clock CLK_DOUT_ACLK166>;
1319 clock-names = "bus";
1320 operating-points-v2 = <&bus_jpeg_apb_opp_table>;
1321 status = "disabled";
1322 };
1323
1324 bus_disp1_fimd: bus_disp1_fimd {
1325 compatible = "samsung,exynos-bus";
1326 clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
1327 clock-names = "bus";
1328 operating-points-v2 = <&bus_disp1_fimd_opp_table>;
1329 status = "disabled";
1330 };
1331
1332 bus_disp1: bus_disp1 {
1333 compatible = "samsung,exynos-bus";
1334 clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
1335 clock-names = "bus";
1336 operating-points-v2 = <&bus_disp1_opp_table>;
1337 status = "disabled";
1338 };
1339
1340 bus_gscl_scaler: bus_gscl_scaler {
1341 compatible = "samsung,exynos-bus";
1342 clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
1343 clock-names = "bus";
1344 operating-points-v2 = <&bus_gscl_opp_table>;
1345 status = "disabled";
1346 };
1347
1348 bus_mscl: bus_mscl {
1349 compatible = "samsung,exynos-bus";
1350 clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
1351 clock-names = "bus";
1352 operating-points-v2 = <&bus_mscl_opp_table>;
1353 status = "disabled";
1354 };
1355
1356 bus_wcore_opp_table: opp_table2 {
1357 compatible = "operating-points-v2";
1358
1359 opp00 {
1360 opp-hz = /bits/ 64 <84000000>;
1361 opp-microvolt = <925000>;
1362 };
1363 opp01 {
1364 opp-hz = /bits/ 64 <111000000>;
1365 opp-microvolt = <950000>;
1366 };
1367 opp02 {
1368 opp-hz = /bits/ 64 <222000000>;
1369 opp-microvolt = <950000>;
1370 };
1371 opp03 {
1372 opp-hz = /bits/ 64 <333000000>;
1373 opp-microvolt = <950000>;
1374 };
1375 opp04 {
1376 opp-hz = /bits/ 64 <400000000>;
1377 opp-microvolt = <987500>;
1378 };
1379 };
1380
1381 bus_noc_opp_table: opp_table3 {
1382 compatible = "operating-points-v2";
1383
1384 opp00 {
1385 opp-hz = /bits/ 64 <67000000>;
1386 };
1387 opp01 {
1388 opp-hz = /bits/ 64 <75000000>;
1389 };
1390 opp02 {
1391 opp-hz = /bits/ 64 <86000000>;
1392 };
1393 opp03 {
1394 opp-hz = /bits/ 64 <100000000>;
1395 };
1396 };
1397
1398 bus_fsys_apb_opp_table: opp_table4 {
1399 compatible = "operating-points-v2";
1400 opp-shared;
1401
1402 opp00 {
1403 opp-hz = /bits/ 64 <100000000>;
1404 };
1405 opp01 {
1406 opp-hz = /bits/ 64 <200000000>;
1407 };
1408 };
1409
1410 bus_fsys2_opp_table: opp_table5 {
1411 compatible = "operating-points-v2";
1412
1413 opp00 {
1414 opp-hz = /bits/ 64 <75000000>;
1415 };
1416 opp01 {
1417 opp-hz = /bits/ 64 <100000000>;
1418 };
1419 opp02 {
1420 opp-hz = /bits/ 64 <150000000>;
1421 };
1422 };
1423
1424 bus_mfc_opp_table: opp_table6 {
1425 compatible = "operating-points-v2";
1426
1427 opp00 {
1428 opp-hz = /bits/ 64 <96000000>;
1429 };
1430 opp01 {
1431 opp-hz = /bits/ 64 <111000000>;
1432 };
1433 opp02 {
1434 opp-hz = /bits/ 64 <167000000>;
1435 };
1436 opp03 {
1437 opp-hz = /bits/ 64 <222000000>;
1438 };
1439 opp04 {
1440 opp-hz = /bits/ 64 <333000000>;
1441 };
1442 };
1443
1444 bus_gen_opp_table: opp_table7 {
1445 compatible = "operating-points-v2";
1446
1447 opp00 {
1448 opp-hz = /bits/ 64 <89000000>;
1449 };
1450 opp01 {
1451 opp-hz = /bits/ 64 <133000000>;
1452 };
1453 opp02 {
1454 opp-hz = /bits/ 64 <178000000>;
1455 };
1456 opp03 {
1457 opp-hz = /bits/ 64 <267000000>;
1458 };
1459 };
1460
1461 bus_peri_opp_table: opp_table8 {
1462 compatible = "operating-points-v2";
1463
1464 opp00 {
1465 opp-hz = /bits/ 64 <67000000>;
1466 };
1467 };
1468
1469 bus_g2d_opp_table: opp_table9 {
1470 compatible = "operating-points-v2";
1471
1472 opp00 {
1473 opp-hz = /bits/ 64 <84000000>;
1474 };
1475 opp01 {
1476 opp-hz = /bits/ 64 <167000000>;
1477 };
1478 opp02 {
1479 opp-hz = /bits/ 64 <222000000>;
1480 };
1481 opp03 {
1482 opp-hz = /bits/ 64 <300000000>;
1483 };
1484 opp04 {
1485 opp-hz = /bits/ 64 <333000000>;
1486 };
1487 };
1488
1489 bus_g2d_acp_opp_table: opp_table10 {
1490 compatible = "operating-points-v2";
1491
1492 opp00 {
1493 opp-hz = /bits/ 64 <67000000>;
1494 };
1495 opp01 {
1496 opp-hz = /bits/ 64 <133000000>;
1497 };
1498 opp02 {
1499 opp-hz = /bits/ 64 <178000000>;
1500 };
1501 opp03 {
1502 opp-hz = /bits/ 64 <267000000>;
1503 };
1504 };
1505
1506 bus_jpeg_opp_table: opp_table11 {
1507 compatible = "operating-points-v2";
1508
1509 opp00 {
1510 opp-hz = /bits/ 64 <75000000>;
1511 };
1512 opp01 {
1513 opp-hz = /bits/ 64 <150000000>;
1514 };
1515 opp02 {
1516 opp-hz = /bits/ 64 <200000000>;
1517 };
1518 opp03 {
1519 opp-hz = /bits/ 64 <300000000>;
1520 };
1521 };
1522
1523 bus_jpeg_apb_opp_table: opp_table12 {
1524 compatible = "operating-points-v2";
1525
1526 opp00 {
1527 opp-hz = /bits/ 64 <84000000>;
1528 };
1529 opp01 {
1530 opp-hz = /bits/ 64 <111000000>;
1531 };
1532 opp02 {
1533 opp-hz = /bits/ 64 <134000000>;
1534 };
1535 opp03 {
1536 opp-hz = /bits/ 64 <167000000>;
1537 };
1538 };
1539
1540 bus_disp1_fimd_opp_table: opp_table13 {
1541 compatible = "operating-points-v2";
1542
1543 opp00 {
1544 opp-hz = /bits/ 64 <120000000>;
1545 };
1546 opp01 {
1547 opp-hz = /bits/ 64 <200000000>;
1548 };
1549 };
1550
1551 bus_disp1_opp_table: opp_table14 {
1552 compatible = "operating-points-v2";
1553
1554 opp00 {
1555 opp-hz = /bits/ 64 <120000000>;
1556 };
1557 opp01 {
1558 opp-hz = /bits/ 64 <200000000>;
1559 };
1560 opp02 {
1561 opp-hz = /bits/ 64 <300000000>;
1562 };
1563 };
1564
1565 bus_gscl_opp_table: opp_table15 {
1566 compatible = "operating-points-v2";
1567
1568 opp00 {
1569 opp-hz = /bits/ 64 <150000000>;
1570 };
1571 opp01 {
1572 opp-hz = /bits/ 64 <200000000>;
1573 };
1574 opp02 {
1575 opp-hz = /bits/ 64 <300000000>;
1576 };
1577 };
1578
1579 bus_mscl_opp_table: opp_table16 {
1580 compatible = "operating-points-v2";
1581
1582 opp00 {
1583 opp-hz = /bits/ 64 <84000000>;
1584 };
1585 opp01 {
1586 opp-hz = /bits/ 64 <167000000>;
1587 };
1588 opp02 {
1589 opp-hz = /bits/ 64 <222000000>;
1590 };
1591 opp03 {
1592 opp-hz = /bits/ 64 <333000000>;
1593 };
1594 opp04 {
1595 opp-hz = /bits/ 64 <400000000>;
1596 };
1597 };
1191}; 1598};
1192 1599
1193&dp { 1600&dp {
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
index 20fa7612080d..2a4e10bc8801 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
@@ -56,6 +56,89 @@
56 }; 56 };
57}; 57};
58 58
59&bus_wcore {
60 devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>,
61 <&nocp_mem1_0>, <&nocp_mem1_1>;
62 vdd-supply = <&buck3_reg>;
63 exynos,saturation-ratio = <100>;
64 status = "okay";
65};
66
67&bus_noc {
68 devfreq = <&bus_wcore>;
69 status = "okay";
70};
71
72&bus_fsys_apb {
73 devfreq = <&bus_wcore>;
74 status = "okay";
75};
76
77&bus_fsys {
78 devfreq = <&bus_wcore>;
79 status = "okay";
80};
81
82&bus_fsys2 {
83 devfreq = <&bus_wcore>;
84 status = "okay";
85};
86
87&bus_mfc {
88 devfreq = <&bus_wcore>;
89 status = "okay";
90};
91
92&bus_gen {
93 devfreq = <&bus_wcore>;
94 status = "okay";
95};
96
97&bus_peri {
98 devfreq = <&bus_wcore>;
99 status = "okay";
100};
101
102&bus_g2d {
103 devfreq = <&bus_wcore>;
104 status = "okay";
105};
106
107&bus_g2d_acp {
108 devfreq = <&bus_wcore>;
109 status = "okay";
110};
111
112&bus_jpeg {
113 devfreq = <&bus_wcore>;
114 status = "okay";
115};
116
117&bus_jpeg_apb {
118 devfreq = <&bus_wcore>;
119 status = "okay";
120};
121
122&bus_disp1_fimd {
123 devfreq = <&bus_wcore>;
124 status = "okay";
125};
126
127&bus_disp1 {
128 devfreq = <&bus_wcore>;
129 status = "okay";
130};
131
132&bus_gscl_scaler {
133 devfreq = <&bus_wcore>;
134 status = "okay";
135};
136
137&bus_mscl {
138 devfreq = <&bus_wcore>;
139 status = "okay";
140};
141
59&clock_audss { 142&clock_audss {
60 assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, 143 assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
61 <&clock_audss EXYNOS_MOUT_I2S>, 144 <&clock_audss EXYNOS_MOUT_I2S>,
@@ -361,6 +444,22 @@
361 vqmmc-supply = <&ldo13_reg>; 444 vqmmc-supply = <&ldo13_reg>;
362}; 445};
363 446
447&nocp_mem0_0 {
448 status = "okay";
449};
450
451&nocp_mem0_1 {
452 status = "okay";
453};
454
455&nocp_mem1_0 {
456 status = "okay";
457};
458
459&nocp_mem1_1 {
460 status = "okay";
461};
462
364&pinctrl_0 { 463&pinctrl_0 {
365 hdmi_hpd_irq: hdmi-hpd-irq { 464 hdmi_hpd_irq: hdmi-hpd-irq {
366 samsung,pins = "gpx3-7"; 465 samsung,pins = "gpx3-7";
diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts b/arch/arm/boot/dts/imx7d-nitrogen7.dts
new file mode 100644
index 000000000000..1ce97800f0c5
--- /dev/null
+++ b/arch/arm/boot/dts/imx7d-nitrogen7.dts
@@ -0,0 +1,745 @@
1/*
2 * Copyright 2016 Boundary Devices, Inc.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43/dts-v1/;
44
45#include <dt-bindings/input/input.h>
46#include "imx7d.dtsi"
47
48/ {
49 model = "Boundary Devices i.MX7 Nitrogen7 Board";
50 compatible = "boundary,imx7d-nitrogen7", "fsl,imx7d";
51
52 aliases {
53 fb_lcd = &lcdif;
54 t_lcd = &t_lcd;
55 };
56
57 memory {
58 reg = <0x80000000 0x40000000>;
59 };
60
61 backlight-j9 {
62 compatible = "gpio-backlight";
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_backlight_j9>;
65 gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
66 default-on;
67 };
68
69 backlight-j20 {
70 compatible = "pwm-backlight";
71 pwms = <&pwm1 0 5000000>;
72 brightness-levels = <0 4 8 16 32 64 128 255>;
73 default-brightness-level = <6>;
74 status = "okay";
75 };
76
77 reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
78 compatible = "regulator-fixed";
79 regulator-name = "usb_otg1_vbus";
80 regulator-min-microvolt = <5000000>;
81 regulator-max-microvolt = <5000000>;
82 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
83 enable-active-high;
84 };
85
86 reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
87 compatible = "regulator-fixed";
88 regulator-name = "usb_otg2_vbus";
89 regulator-min-microvolt = <5000000>;
90 regulator-max-microvolt = <5000000>;
91 gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
92 enable-active-high;
93 };
94
95 reg_can2_3v3: regulator-can2-3v3 {
96 compatible = "regulator-fixed";
97 regulator-name = "can2-3v3";
98 regulator-min-microvolt = <3300000>;
99 regulator-max-microvolt = <3300000>;
100 gpio = <&gpio2 14 GPIO_ACTIVE_LOW>;
101 };
102
103 reg_vref_1v8: regulator-vref-1v8 {
104 compatible = "regulator-fixed";
105 regulator-name = "vref-1v8";
106 regulator-min-microvolt = <1800000>;
107 regulator-max-microvolt = <1800000>;
108 };
109
110 reg_vref_3v3: regulator-vref-3v3 {
111 compatible = "regulator-fixed";
112 regulator-name = "vref-3v3";
113 regulator-min-microvolt = <3300000>;
114 regulator-max-microvolt = <3300000>;
115 };
116
117 reg_wlan: regulator-wlan {
118 compatible = "regulator-fixed";
119 regulator-min-microvolt = <3300000>;
120 regulator-max-microvolt = <3300000>;
121 clocks = <&clks IMX7D_CLKO2_ROOT_DIV>;
122 clock-names = "slow";
123 regulator-name = "reg_wlan";
124 startup-delay-us = <70000>;
125 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
126 enable-active-high;
127 };
128};
129
130&adc1 {
131 vref-supply = <&reg_vref_1v8>;
132 status = "okay";
133};
134
135&adc2 {
136 vref-supply = <&reg_vref_1v8>;
137 status = "okay";
138};
139
140&clks {
141 assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
142 <&clks IMX7D_CLKO2_ROOT_DIV>;
143 assigned-clock-parents = <&clks IMX7D_CKIL>;
144 assigned-clock-rates = <0>, <32768>;
145};
146
147&cpu0 {
148 arm-supply = <&sw1a_reg>;
149};
150
151&fec1 {
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_enet1>;
154 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
155 <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
156 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
157 assigned-clock-rates = <0>, <100000000>;
158 phy-mode = "rgmii";
159 phy-handle = <&ethphy0>;
160 fsl,magic-packet;
161 status = "okay";
162
163 mdio {
164 #address-cells = <1>;
165 #size-cells = <0>;
166
167 ethphy0: ethernet-phy@4 {
168 reg = <4>;
169 };
170 };
171};
172
173&flexcan2 {
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_flexcan2>;
176 xceiver-supply = <&reg_can2_3v3>;
177 status = "okay";
178};
179
180&i2c1 {
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_i2c1>;
183 status = "okay";
184
185 pmic: pfuze3000@08 {
186 compatible = "fsl,pfuze3000";
187 reg = <0x08>;
188
189 regulators {
190 sw1a_reg: sw1a {
191 regulator-min-microvolt = <700000>;
192 regulator-max-microvolt = <1475000>;
193 regulator-boot-on;
194 regulator-always-on;
195 regulator-ramp-delay = <6250>;
196 };
197
198 /* use sw1c_reg to align with pfuze100/pfuze200 */
199 sw1c_reg: sw1b {
200 regulator-min-microvolt = <700000>;
201 regulator-max-microvolt = <1475000>;
202 regulator-boot-on;
203 regulator-always-on;
204 regulator-ramp-delay = <6250>;
205 };
206
207 sw2_reg: sw2 {
208 regulator-min-microvolt = <1500000>;
209 regulator-max-microvolt = <1850000>;
210 regulator-boot-on;
211 regulator-always-on;
212 };
213
214 sw3a_reg: sw3 {
215 regulator-min-microvolt = <900000>;
216 regulator-max-microvolt = <1650000>;
217 regulator-boot-on;
218 regulator-always-on;
219 };
220
221 swbst_reg: swbst {
222 regulator-min-microvolt = <5000000>;
223 regulator-max-microvolt = <5150000>;
224 };
225
226 snvs_reg: vsnvs {
227 regulator-min-microvolt = <1000000>;
228 regulator-max-microvolt = <3000000>;
229 regulator-boot-on;
230 regulator-always-on;
231 };
232
233 vref_reg: vrefddr {
234 regulator-boot-on;
235 regulator-always-on;
236 };
237
238 vgen1_reg: vldo1 {
239 regulator-min-microvolt = <1800000>;
240 regulator-max-microvolt = <3300000>;
241 regulator-always-on;
242 };
243
244 vgen2_reg: vldo2 {
245 regulator-min-microvolt = <800000>;
246 regulator-max-microvolt = <1550000>;
247 regulator-always-on;
248 };
249
250 vgen3_reg: vccsd {
251 regulator-min-microvolt = <2850000>;
252 regulator-max-microvolt = <3300000>;
253 regulator-always-on;
254 };
255
256 vgen4_reg: v33 {
257 regulator-min-microvolt = <2850000>;
258 regulator-max-microvolt = <3300000>;
259 regulator-always-on;
260 };
261
262 vgen5_reg: vldo3 {
263 regulator-min-microvolt = <1800000>;
264 regulator-max-microvolt = <3300000>;
265 regulator-always-on;
266 };
267
268 vgen6_reg: vldo4 {
269 regulator-min-microvolt = <1800000>;
270 regulator-max-microvolt = <3300000>;
271 regulator-always-on;
272 };
273 };
274 };
275};
276
277&i2c2 {
278 pinctrl-names = "default";
279 pinctrl-0 = <&pinctrl_i2c2>;
280 status = "okay";
281
282 rtc@68 {
283 compatible = "rv4162";
284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_i2c2_rv4162>;
286 reg = <0x68>;
287 interrupts-extended = <&gpio2 15 IRQ_TYPE_LEVEL_LOW>;
288 };
289};
290
291&i2c3 {
292 pinctrl-names = "default";
293 pinctrl-0 = <&pinctrl_i2c3>;
294 status = "okay";
295
296 touch@48 {
297 compatible = "ti,tsc2004";
298 reg = <0x48>;
299 pinctrl-names = "default";
300 pinctrl-0 = <&pinctrl_i2c3_tsc2004>;
301 interrupts-extended = <&gpio3 4 IRQ_TYPE_EDGE_FALLING>;
302 wakeup-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
303 };
304};
305
306&i2c4 {
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_i2c4>;
309 status = "okay";
310
311 codec: wm8960@1a {
312 compatible = "wlf,wm8960";
313 reg = <0x1a>;
314 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
315 clock-names = "mclk";
316 wlf,shared-lrclk;
317 };
318};
319
320&lcdif {
321 pinctrl-names = "default";
322 pinctrl-0 = <&pinctrl_lcdif_dat
323 &pinctrl_lcdif_ctrl>;
324 lcd-supply = <&reg_vref_3v3>;
325 display = <&display0>;
326 status = "okay";
327
328 display0: lcd-display {
329 bits-per-pixel = <16>;
330 bus-width = <18>;
331
332 display-timings {
333 native-mode = <&t_lcd>;
334 t_lcd: t_lcd_default {
335 /* default to Okaya display */
336 clock-frequency = <30000000>;
337 hactive = <800>;
338 vactive = <480>;
339 hfront-porch = <40>;
340 hback-porch = <40>;
341 hsync-len = <48>;
342 vback-porch = <29>;
343 vfront-porch = <13>;
344 vsync-len = <3>;
345 hsync-active = <0>;
346 vsync-active = <0>;
347 de-active = <1>;
348 pixelclk-active = <0>;
349 };
350 };
351 };
352};
353
354&pwm1 {
355 pinctrl-names = "default";
356 pinctrl-0 = <&pinctrl_pwm1>;
357 status = "okay";
358};
359
360&pwm2 {
361 pinctrl-names = "default";
362 pinctrl-0 = <&pinctrl_pwm2>;
363 status = "okay";
364};
365
366&uart1 {
367 pinctrl-names = "default";
368 pinctrl-0 = <&pinctrl_uart1>;
369 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
370 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
371 status = "okay";
372};
373
374&uart2 {
375 pinctrl-names = "default";
376 pinctrl-0 = <&pinctrl_uart2>;
377 assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
378 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
379 status = "okay";
380};
381
382&uart3 {
383 pinctrl-names = "default";
384 pinctrl-0 = <&pinctrl_uart3>;
385 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
386 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
387 status = "okay";
388};
389
390&uart6 {
391 pinctrl-names = "default";
392 pinctrl-0 = <&pinctrl_uart6>;
393 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
394 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
395 fsl,uart-has-rtscts;
396 status = "okay";
397};
398
399&usbotg1 {
400 vbus-supply = <&reg_usb_otg1_vbus>;
401 pinctrl-names = "default";
402 pinctrl-0 = <&pinctrl_usbotg1>;
403 status = "okay";
404};
405
406&usbotg2 {
407 vbus-supply = <&reg_usb_otg2_vbus>;
408 pinctrl-names = "default";
409 pinctrl-0 = <&pinctrl_usbotg2>;
410 dr_mode = "host";
411 status = "okay";
412};
413
414&usdhc1 {
415 pinctrl-names = "default";
416 pinctrl-0 = <&pinctrl_usdhc1>;
417 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
418 vmmc-supply = <&vgen3_reg>;
419 bus-width = <4>;
420 fsl,tuning-step = <2>;
421 wakeup-source;
422 keep-power-in-suspend;
423 status = "okay";
424};
425
426&usdhc2 {
427 #address-cells = <1>;
428 #size-cells = <0>;
429 pinctrl-names = "default";
430 pinctrl-0 = <&pinctrl_usdhc2>;
431 bus-width = <4>;
432 non-removable;
433 vmmc-supply = <&reg_wlan>;
434 cap-power-off-card;
435 keep-power-in-suspend;
436 status = "okay";
437
438 wlcore: wlcore@2 {
439 compatible = "ti,wl1271";
440 reg = <2>;
441 interrupt-parent = <&gpio4>;
442 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
443 ref-clock-frequency = <38400000>;
444 };
445};
446
447&usdhc3 {
448 pinctrl-names = "default";
449 pinctrl-0 = <&pinctrl_usdhc3>;
450 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
451 assigned-clock-rates = <400000000>;
452 bus-width = <8>;
453 fsl,tuning-step = <2>;
454 non-removable;
455 status = "okay";
456};
457
458&wdog1 {
459 pinctrl-names = "default";
460 pinctrl-0 = <&pinctrl_wdog1>;
461 status = "okay";
462};
463
464&iomuxc {
465 pinctrl-names = "default";
466 pinctrl-0 = <&pinctrl_hog_1 &pinctrl_j2>;
467
468 pinctrl_hog_1: hoggrp-1 {
469 fsl,pins = <
470 MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x5d
471 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x7d
472 MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x7d
473 >;
474 };
475
476 pinctrl_enet1: enet1grp {
477 fsl,pins = <
478 MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3
479 MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3
480 MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x3
481 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71
482 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71
483 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71
484 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71
485 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71
486 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71
487 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x71
488 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x11
489 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x11
490 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x11
491 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x71
492 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x11
493 MX7D_PAD_SD3_STROBE__GPIO6_IO10 0x75
494 >;
495 };
496
497 pinctrl_flexcan2: flexcan2grp {
498 fsl,pins = <
499 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x7d
500 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x7d
501 MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x7d
502 >;
503 };
504
505 pinctrl_i2c1: i2c1grp {
506 fsl,pins = <
507 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
508 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
509 >;
510 };
511
512 pinctrl_i2c2: i2c2grp {
513 fsl,pins = <
514 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
515 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
516 >;
517 };
518
519 pinctrl_i2c2_rv4162: i2c2-rv4162grp {
520 fsl,pins = <
521 MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x7d
522 >;
523 };
524
525 pinctrl_i2c3: i2c3grp {
526 fsl,pins = <
527 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
528 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
529 >;
530 };
531
532 pinctrl_i2c3_tsc2004: i2c3tsc2004grp {
533 fsl,pins = <
534 MX7D_PAD_LCD_RESET__GPIO3_IO4 0x79
535 MX7D_PAD_SD2_WP__GPIO5_IO10 0x7d
536 >;
537 };
538
539 pinctrl_i2c4: i2c4grp {
540 fsl,pins = <
541 MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f
542 MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f
543 >;
544 };
545
546 pinctrl_j2: j2grp {
547 fsl,pins = <
548 MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x7d
549 MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x7d
550 MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x7d
551 MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x7d
552 MX7D_PAD_SD1_WP__GPIO5_IO1 0x7d
553 MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x7d
554 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x7d
555 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x7d
556 MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x7d
557 MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x7d
558 MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x7d
559 MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x7d
560 MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x7d
561 MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x7d
562 MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 0x7d
563 MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x7d
564 MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x7d
565 MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x7d
566 MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x7d
567 MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x7d
568 MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x7d
569 MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x7d
570 MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 0x7d
571 MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x7d
572 MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20 0x7d
573 MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x7d
574 MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 0x7d
575 MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x7d
576 MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x7d
577 MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x7d
578 MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x7d
579 MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x7d
580 MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x7d
581 MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x7d
582 MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x7d
583 >;
584 };
585
586 pinctrl_lcdif_dat: lcdifdatgrp {
587 fsl,pins = <
588 MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
589 MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
590 MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
591 MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
592 MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
593 MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
594 MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
595 MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
596 MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
597 MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
598 MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
599 MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
600 MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
601 MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
602 MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
603 MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
604 MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
605 MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
606 MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79
607 MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79
608 MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79
609 MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79
610 MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79
611 MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79
612 >;
613 };
614
615 pinctrl_lcdif_ctrl: lcdifctrlgrp {
616 fsl,pins = <
617 MX7D_PAD_LCD_CLK__LCD_CLK 0x79
618 MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79
619 MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79
620 MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79
621 >;
622 };
623
624 pinctrl_pwm2: pwm2grp {
625 fsl,pins = <
626 MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7d
627 >;
628 };
629
630 pinctrl_uart1: uart1grp {
631 fsl,pins = <
632 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
633 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
634 >;
635 };
636
637 pinctrl_uart2: uart2grp {
638 fsl,pins = <
639 MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79
640 MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79
641 >;
642 };
643
644 pinctrl_uart3: uart3grp {
645 fsl,pins = <
646 MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79
647 MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79
648 MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x7d
649 >;
650 };
651
652 pinctrl_uart6: uart6grp {
653 fsl,pins = <
654 MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79
655 MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79
656 MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79
657 MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79
658 >;
659 };
660
661 pinctrl_usbotg2: usbotg2grp {
662 fsl,pins = <
663 MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x7d
664 MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14
665 >;
666 };
667
668 pinctrl_usdhc1: usdhc1grp {
669 fsl,pins = <
670 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
671 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
672 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
673 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
674 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
675 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
676 MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x75
677 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x75
678 >;
679 };
680
681 pinctrl_usdhc2: usdhc2grp {
682 fsl,pins = <
683 MX7D_PAD_SD2_CMD__SD2_CMD 0x59
684 MX7D_PAD_SD2_CLK__SD2_CLK 0x19
685 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
686 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
687 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
688 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
689 MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x59
690 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x59
691 >;
692 };
693
694 pinctrl_usdhc3: usdhc3grp {
695 fsl,pins = <
696 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
697 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
698 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
699 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
700 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
701 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
702 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
703 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
704 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
705 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
706 >;
707 };
708};
709
710&iomuxc_lpsr {
711 pinctrl-names = "default";
712 pinctrl-0 = <&pinctrl_hog_2>;
713
714 pinctrl_hog_2: hoggrp-2 {
715 fsl,pins = <
716 MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x7d
717 MX7D_PAD_GPIO1_IO03__CCM_CLKO2 0x7d
718 >;
719 };
720
721 pinctrl_backlight_j9: backlightj9grp {
722 fsl,pins = <
723 MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x7d
724 >;
725 };
726
727 pinctrl_pwm1: pwm1grp {
728 fsl,pins = <
729 MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x7d
730 >;
731 };
732
733 pinctrl_usbotg1: usbotg1grp {
734 fsl,pins = <
735 MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x7d
736 MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14
737 >;
738 };
739
740 pinctrl_wdog1: wdog1grp {
741 fsl,pins = <
742 MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x75
743 >;
744 };
745};
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index b5a50e0e7ff1..6b3faa298417 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -651,6 +651,17 @@
651 #pwm-cells = <2>; 651 #pwm-cells = <2>;
652 status = "disabled"; 652 status = "disabled";
653 }; 653 };
654
655 lcdif: lcdif@30730000 {
656 compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
657 reg = <0x30730000 0x10000>;
658 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
659 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
660 <&clks IMX7D_CLK_DUMMY>,
661 <&clks IMX7D_CLK_DUMMY>;
662 clock-names = "pix", "axi", "disp_axi";
663 status = "disabled";
664 };
654 }; 665 };
655 666
656 aips3: aips-bus@30800000 { 667 aips3: aips-bus@30800000 {
@@ -693,6 +704,26 @@
693 status = "disabled"; 704 status = "disabled";
694 }; 705 };
695 706
707 flexcan1: can@30a00000 {
708 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
709 reg = <0x30a00000 0x10000>;
710 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
711 clocks = <&clks IMX7D_CLK_DUMMY>,
712 <&clks IMX7D_CAN1_ROOT_CLK>;
713 clock-names = "ipg", "per";
714 status = "disabled";
715 };
716
717 flexcan2: can@30a10000 {
718 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
719 reg = <0x30a10000 0x10000>;
720 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&clks IMX7D_CLK_DUMMY>,
722 <&clks IMX7D_CAN2_ROOT_CLK>;
723 clock-names = "ipg", "per";
724 status = "disabled";
725 };
726
696 i2c1: i2c@30a20000 { 727 i2c1: i2c@30a20000 {
697 #address-cells = <1>; 728 #address-cells = <1>;
698 #size-cells = <0>; 729 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index 0c82097daffc..b9bbcce69dfb 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -14,6 +14,7 @@
14#include <dt-bindings/clock/r8a7779-clock.h> 14#include <dt-bindings/clock/r8a7779-clock.h>
15#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h>
16#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/interrupt-controller/irq.h>
17#include <dt-bindings/power/r8a7779-sysc.h>
17 18
18/ { 19/ {
19 compatible = "renesas,r8a7779"; 20 compatible = "renesas,r8a7779";
@@ -34,18 +35,21 @@
34 compatible = "arm,cortex-a9"; 35 compatible = "arm,cortex-a9";
35 reg = <1>; 36 reg = <1>;
36 clock-frequency = <1000000000>; 37 clock-frequency = <1000000000>;
38 power-domains = <&sysc R8A7779_PD_ARM1>;
37 }; 39 };
38 cpu@2 { 40 cpu@2 {
39 device_type = "cpu"; 41 device_type = "cpu";
40 compatible = "arm,cortex-a9"; 42 compatible = "arm,cortex-a9";
41 reg = <2>; 43 reg = <2>;
42 clock-frequency = <1000000000>; 44 clock-frequency = <1000000000>;
45 power-domains = <&sysc R8A7779_PD_ARM2>;
43 }; 46 };
44 cpu@3 { 47 cpu@3 {
45 device_type = "cpu"; 48 device_type = "cpu";
46 compatible = "arm,cortex-a9"; 49 compatible = "arm,cortex-a9";
47 reg = <3>; 50 reg = <3>;
48 clock-frequency = <1000000000>; 51 clock-frequency = <1000000000>;
52 power-domains = <&sysc R8A7779_PD_ARM3>;
49 }; 53 };
50 }; 54 };
51 55
@@ -173,7 +177,7 @@
173 reg = <0xffc70000 0x1000>; 177 reg = <0xffc70000 0x1000>;
174 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 178 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
175 clocks = <&mstp0_clks R8A7779_CLK_I2C0>; 179 clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
176 power-domains = <&cpg_clocks>; 180 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
177 status = "disabled"; 181 status = "disabled";
178 }; 182 };
179 183
@@ -184,7 +188,7 @@
184 reg = <0xffc71000 0x1000>; 188 reg = <0xffc71000 0x1000>;
185 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 189 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
186 clocks = <&mstp0_clks R8A7779_CLK_I2C1>; 190 clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
187 power-domains = <&cpg_clocks>; 191 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
188 status = "disabled"; 192 status = "disabled";
189 }; 193 };
190 194
@@ -195,7 +199,7 @@
195 reg = <0xffc72000 0x1000>; 199 reg = <0xffc72000 0x1000>;
196 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 200 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&mstp0_clks R8A7779_CLK_I2C2>; 201 clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
198 power-domains = <&cpg_clocks>; 202 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
199 status = "disabled"; 203 status = "disabled";
200 }; 204 };
201 205
@@ -206,7 +210,7 @@
206 reg = <0xffc73000 0x1000>; 210 reg = <0xffc73000 0x1000>;
207 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 211 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
208 clocks = <&mstp0_clks R8A7779_CLK_I2C3>; 212 clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
209 power-domains = <&cpg_clocks>; 213 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
210 status = "disabled"; 214 status = "disabled";
211 }; 215 };
212 216
@@ -218,7 +222,7 @@
218 clocks = <&mstp0_clks R8A7779_CLK_SCIF0>, 222 clocks = <&mstp0_clks R8A7779_CLK_SCIF0>,
219 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; 223 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
220 clock-names = "fck", "brg_int", "scif_clk"; 224 clock-names = "fck", "brg_int", "scif_clk";
221 power-domains = <&cpg_clocks>; 225 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
222 status = "disabled"; 226 status = "disabled";
223 }; 227 };
224 228
@@ -230,7 +234,7 @@
230 clocks = <&mstp0_clks R8A7779_CLK_SCIF1>, 234 clocks = <&mstp0_clks R8A7779_CLK_SCIF1>,
231 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; 235 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
232 clock-names = "fck", "brg_int", "scif_clk"; 236 clock-names = "fck", "brg_int", "scif_clk";
233 power-domains = <&cpg_clocks>; 237 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
234 status = "disabled"; 238 status = "disabled";
235 }; 239 };
236 240
@@ -242,7 +246,7 @@
242 clocks = <&mstp0_clks R8A7779_CLK_SCIF2>, 246 clocks = <&mstp0_clks R8A7779_CLK_SCIF2>,
243 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; 247 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
244 clock-names = "fck", "brg_int", "scif_clk"; 248 clock-names = "fck", "brg_int", "scif_clk";
245 power-domains = <&cpg_clocks>; 249 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
246 status = "disabled"; 250 status = "disabled";
247 }; 251 };
248 252
@@ -254,7 +258,7 @@
254 clocks = <&mstp0_clks R8A7779_CLK_SCIF3>, 258 clocks = <&mstp0_clks R8A7779_CLK_SCIF3>,
255 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; 259 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
256 clock-names = "fck", "brg_int", "scif_clk"; 260 clock-names = "fck", "brg_int", "scif_clk";
257 power-domains = <&cpg_clocks>; 261 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
258 status = "disabled"; 262 status = "disabled";
259 }; 263 };
260 264
@@ -266,7 +270,7 @@
266 clocks = <&mstp0_clks R8A7779_CLK_SCIF4>, 270 clocks = <&mstp0_clks R8A7779_CLK_SCIF4>,
267 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; 271 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
268 clock-names = "fck", "brg_int", "scif_clk"; 272 clock-names = "fck", "brg_int", "scif_clk";
269 power-domains = <&cpg_clocks>; 273 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
270 status = "disabled"; 274 status = "disabled";
271 }; 275 };
272 276
@@ -278,7 +282,7 @@
278 clocks = <&mstp0_clks R8A7779_CLK_SCIF5>, 282 clocks = <&mstp0_clks R8A7779_CLK_SCIF5>,
279 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; 283 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
280 clock-names = "fck", "brg_int", "scif_clk"; 284 clock-names = "fck", "brg_int", "scif_clk";
281 power-domains = <&cpg_clocks>; 285 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
282 status = "disabled"; 286 status = "disabled";
283 }; 287 };
284 288
@@ -300,7 +304,7 @@
300 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 304 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
301 clocks = <&mstp0_clks R8A7779_CLK_TMU0>; 305 clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
302 clock-names = "fck"; 306 clock-names = "fck";
303 power-domains = <&cpg_clocks>; 307 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
304 308
305 #renesas,channels = <3>; 309 #renesas,channels = <3>;
306 310
@@ -315,7 +319,7 @@
315 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 319 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&mstp0_clks R8A7779_CLK_TMU1>; 320 clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
317 clock-names = "fck"; 321 clock-names = "fck";
318 power-domains = <&cpg_clocks>; 322 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
319 323
320 #renesas,channels = <3>; 324 #renesas,channels = <3>;
321 325
@@ -330,7 +334,7 @@
330 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 334 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
331 clocks = <&mstp0_clks R8A7779_CLK_TMU2>; 335 clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
332 clock-names = "fck"; 336 clock-names = "fck";
333 power-domains = <&cpg_clocks>; 337 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
334 338
335 #renesas,channels = <3>; 339 #renesas,channels = <3>;
336 340
@@ -342,7 +346,7 @@
342 reg = <0xfc600000 0x2000>; 346 reg = <0xfc600000 0x2000>;
343 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 347 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&mstp1_clks R8A7779_CLK_SATA>; 348 clocks = <&mstp1_clks R8A7779_CLK_SATA>;
345 power-domains = <&cpg_clocks>; 349 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
346 }; 350 };
347 351
348 sdhi0: sd@ffe4c000 { 352 sdhi0: sd@ffe4c000 {
@@ -350,7 +354,7 @@
350 reg = <0xffe4c000 0x100>; 354 reg = <0xffe4c000 0x100>;
351 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 355 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&mstp3_clks R8A7779_CLK_SDHI0>; 356 clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
353 power-domains = <&cpg_clocks>; 357 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
354 status = "disabled"; 358 status = "disabled";
355 }; 359 };
356 360
@@ -359,7 +363,7 @@
359 reg = <0xffe4d000 0x100>; 363 reg = <0xffe4d000 0x100>;
360 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 364 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&mstp3_clks R8A7779_CLK_SDHI1>; 365 clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
362 power-domains = <&cpg_clocks>; 366 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
363 status = "disabled"; 367 status = "disabled";
364 }; 368 };
365 369
@@ -368,7 +372,7 @@
368 reg = <0xffe4e000 0x100>; 372 reg = <0xffe4e000 0x100>;
369 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 373 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&mstp3_clks R8A7779_CLK_SDHI2>; 374 clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
371 power-domains = <&cpg_clocks>; 375 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
372 status = "disabled"; 376 status = "disabled";
373 }; 377 };
374 378
@@ -377,7 +381,7 @@
377 reg = <0xffe4f000 0x100>; 381 reg = <0xffe4f000 0x100>;
378 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 382 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&mstp3_clks R8A7779_CLK_SDHI3>; 383 clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
380 power-domains = <&cpg_clocks>; 384 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
381 status = "disabled"; 385 status = "disabled";
382 }; 386 };
383 387
@@ -388,7 +392,7 @@
388 #address-cells = <1>; 392 #address-cells = <1>;
389 #size-cells = <0>; 393 #size-cells = <0>;
390 clocks = <&mstp0_clks R8A7779_CLK_HSPI>; 394 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
391 power-domains = <&cpg_clocks>; 395 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
392 status = "disabled"; 396 status = "disabled";
393 }; 397 };
394 398
@@ -399,7 +403,7 @@
399 #address-cells = <1>; 403 #address-cells = <1>;
400 #size-cells = <0>; 404 #size-cells = <0>;
401 clocks = <&mstp0_clks R8A7779_CLK_HSPI>; 405 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
402 power-domains = <&cpg_clocks>; 406 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
403 status = "disabled"; 407 status = "disabled";
404 }; 408 };
405 409
@@ -410,7 +414,7 @@
410 #address-cells = <1>; 414 #address-cells = <1>;
411 #size-cells = <0>; 415 #size-cells = <0>;
412 clocks = <&mstp0_clks R8A7779_CLK_HSPI>; 416 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
413 power-domains = <&cpg_clocks>; 417 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
414 status = "disabled"; 418 status = "disabled";
415 }; 419 };
416 420
@@ -419,7 +423,7 @@
419 reg = <0 0xfff80000 0 0x40000>; 423 reg = <0 0xfff80000 0 0x40000>;
420 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 424 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&mstp1_clks R8A7779_CLK_DU>; 425 clocks = <&mstp1_clks R8A7779_CLK_DU>;
422 power-domains = <&cpg_clocks>; 426 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
423 status = "disabled"; 427 status = "disabled";
424 428
425 ports { 429 ports {
@@ -585,4 +589,10 @@
585 "mmc1", "mmc0"; 589 "mmc1", "mmc0";
586 }; 590 };
587 }; 591 };
592
593 sysc: system-controller@ffd85000 {
594 compatible = "renesas,r8a7779-sysc";
595 reg = <0xffd85000 0x0200>;
596 #power-domain-cells = <1>;
597 };
588}; 598};
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 935064fe7b13..83cf23cd26bb 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -13,6 +13,7 @@
13#include <dt-bindings/clock/r8a7790-clock.h> 13#include <dt-bindings/clock/r8a7790-clock.h>
14#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/interrupt-controller/irq.h> 15#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/power/r8a7790-sysc.h>
16 17
17/ { 18/ {
18 compatible = "renesas,r8a7790"; 19 compatible = "renesas,r8a7790";
@@ -52,6 +53,7 @@
52 voltage-tolerance = <1>; /* 1% */ 53 voltage-tolerance = <1>; /* 1% */
53 clocks = <&cpg_clocks R8A7790_CLK_Z>; 54 clocks = <&cpg_clocks R8A7790_CLK_Z>;
54 clock-latency = <300000>; /* 300 us */ 55 clock-latency = <300000>; /* 300 us */
56 power-domains = <&sysc R8A7790_PD_CA15_CPU0>;
55 next-level-cache = <&L2_CA15>; 57 next-level-cache = <&L2_CA15>;
56 58
57 /* kHz - uV - OPPs unknown yet */ 59 /* kHz - uV - OPPs unknown yet */
@@ -68,6 +70,7 @@
68 compatible = "arm,cortex-a15"; 70 compatible = "arm,cortex-a15";
69 reg = <1>; 71 reg = <1>;
70 clock-frequency = <1300000000>; 72 clock-frequency = <1300000000>;
73 power-domains = <&sysc R8A7790_PD_CA15_CPU1>;
71 next-level-cache = <&L2_CA15>; 74 next-level-cache = <&L2_CA15>;
72 }; 75 };
73 76
@@ -76,6 +79,7 @@
76 compatible = "arm,cortex-a15"; 79 compatible = "arm,cortex-a15";
77 reg = <2>; 80 reg = <2>;
78 clock-frequency = <1300000000>; 81 clock-frequency = <1300000000>;
82 power-domains = <&sysc R8A7790_PD_CA15_CPU2>;
79 next-level-cache = <&L2_CA15>; 83 next-level-cache = <&L2_CA15>;
80 }; 84 };
81 85
@@ -84,6 +88,7 @@
84 compatible = "arm,cortex-a15"; 88 compatible = "arm,cortex-a15";
85 reg = <3>; 89 reg = <3>;
86 clock-frequency = <1300000000>; 90 clock-frequency = <1300000000>;
91 power-domains = <&sysc R8A7790_PD_CA15_CPU3>;
87 next-level-cache = <&L2_CA15>; 92 next-level-cache = <&L2_CA15>;
88 }; 93 };
89 94
@@ -92,6 +97,7 @@
92 compatible = "arm,cortex-a7"; 97 compatible = "arm,cortex-a7";
93 reg = <0x100>; 98 reg = <0x100>;
94 clock-frequency = <780000000>; 99 clock-frequency = <780000000>;
100 power-domains = <&sysc R8A7790_PD_CA7_CPU0>;
95 next-level-cache = <&L2_CA7>; 101 next-level-cache = <&L2_CA7>;
96 }; 102 };
97 103
@@ -100,6 +106,7 @@
100 compatible = "arm,cortex-a7"; 106 compatible = "arm,cortex-a7";
101 reg = <0x101>; 107 reg = <0x101>;
102 clock-frequency = <780000000>; 108 clock-frequency = <780000000>;
109 power-domains = <&sysc R8A7790_PD_CA7_CPU1>;
103 next-level-cache = <&L2_CA7>; 110 next-level-cache = <&L2_CA7>;
104 }; 111 };
105 112
@@ -108,6 +115,7 @@
108 compatible = "arm,cortex-a7"; 115 compatible = "arm,cortex-a7";
109 reg = <0x102>; 116 reg = <0x102>;
110 clock-frequency = <780000000>; 117 clock-frequency = <780000000>;
118 power-domains = <&sysc R8A7790_PD_CA7_CPU2>;
111 next-level-cache = <&L2_CA7>; 119 next-level-cache = <&L2_CA7>;
112 }; 120 };
113 121
@@ -116,6 +124,7 @@
116 compatible = "arm,cortex-a7"; 124 compatible = "arm,cortex-a7";
117 reg = <0x103>; 125 reg = <0x103>;
118 clock-frequency = <780000000>; 126 clock-frequency = <780000000>;
127 power-domains = <&sysc R8A7790_PD_CA7_CPU3>;
119 next-level-cache = <&L2_CA7>; 128 next-level-cache = <&L2_CA7>;
120 }; 129 };
121 }; 130 };
@@ -141,12 +150,14 @@
141 150
142 L2_CA15: cache-controller@0 { 151 L2_CA15: cache-controller@0 {
143 compatible = "cache"; 152 compatible = "cache";
153 power-domains = <&sysc R8A7790_PD_CA15_SCU>;
144 cache-unified; 154 cache-unified;
145 cache-level = <2>; 155 cache-level = <2>;
146 }; 156 };
147 157
148 L2_CA7: cache-controller@1 { 158 L2_CA7: cache-controller@1 {
149 compatible = "cache"; 159 compatible = "cache";
160 power-domains = <&sysc R8A7790_PD_CA7_SCU>;
150 cache-unified; 161 cache-unified;
151 cache-level = <2>; 162 cache-level = <2>;
152 }; 163 };
@@ -173,7 +184,7 @@
173 #interrupt-cells = <2>; 184 #interrupt-cells = <2>;
174 interrupt-controller; 185 interrupt-controller;
175 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>; 186 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
176 power-domains = <&cpg_clocks>; 187 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
177 }; 188 };
178 189
179 gpio1: gpio@e6051000 { 190 gpio1: gpio@e6051000 {
@@ -186,7 +197,7 @@
186 #interrupt-cells = <2>; 197 #interrupt-cells = <2>;
187 interrupt-controller; 198 interrupt-controller;
188 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>; 199 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
189 power-domains = <&cpg_clocks>; 200 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
190 }; 201 };
191 202
192 gpio2: gpio@e6052000 { 203 gpio2: gpio@e6052000 {
@@ -199,7 +210,7 @@
199 #interrupt-cells = <2>; 210 #interrupt-cells = <2>;
200 interrupt-controller; 211 interrupt-controller;
201 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>; 212 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
202 power-domains = <&cpg_clocks>; 213 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
203 }; 214 };
204 215
205 gpio3: gpio@e6053000 { 216 gpio3: gpio@e6053000 {
@@ -212,7 +223,7 @@
212 #interrupt-cells = <2>; 223 #interrupt-cells = <2>;
213 interrupt-controller; 224 interrupt-controller;
214 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>; 225 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
215 power-domains = <&cpg_clocks>; 226 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
216 }; 227 };
217 228
218 gpio4: gpio@e6054000 { 229 gpio4: gpio@e6054000 {
@@ -225,7 +236,7 @@
225 #interrupt-cells = <2>; 236 #interrupt-cells = <2>;
226 interrupt-controller; 237 interrupt-controller;
227 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>; 238 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
228 power-domains = <&cpg_clocks>; 239 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
229 }; 240 };
230 241
231 gpio5: gpio@e6055000 { 242 gpio5: gpio@e6055000 {
@@ -238,7 +249,7 @@
238 #interrupt-cells = <2>; 249 #interrupt-cells = <2>;
239 interrupt-controller; 250 interrupt-controller;
240 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>; 251 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
241 power-domains = <&cpg_clocks>; 252 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
242 }; 253 };
243 254
244 thermal: thermal@e61f0000 { 255 thermal: thermal@e61f0000 {
@@ -248,7 +259,7 @@
248 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; 259 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
249 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 260 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>; 261 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
251 power-domains = <&cpg_clocks>; 262 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
252 #thermal-sensor-cells = <0>; 263 #thermal-sensor-cells = <0>;
253 }; 264 };
254 265
@@ -267,7 +278,7 @@
267 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 278 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&mstp1_clks R8A7790_CLK_CMT0>; 279 clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
269 clock-names = "fck"; 280 clock-names = "fck";
270 power-domains = <&cpg_clocks>; 281 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
271 282
272 renesas,channels-mask = <0x60>; 283 renesas,channels-mask = <0x60>;
273 284
@@ -287,7 +298,7 @@
287 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 298 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&mstp3_clks R8A7790_CLK_CMT1>; 299 clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
289 clock-names = "fck"; 300 clock-names = "fck";
290 power-domains = <&cpg_clocks>; 301 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
291 302
292 renesas,channels-mask = <0xff>; 303 renesas,channels-mask = <0xff>;
293 304
@@ -304,7 +315,7 @@
304 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 315 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 316 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&mstp4_clks R8A7790_CLK_IRQC>; 317 clocks = <&mstp4_clks R8A7790_CLK_IRQC>;
307 power-domains = <&cpg_clocks>; 318 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
308 }; 319 };
309 320
310 dmac0: dma-controller@e6700000 { 321 dmac0: dma-controller@e6700000 {
@@ -333,7 +344,7 @@
333 "ch12", "ch13", "ch14"; 344 "ch12", "ch13", "ch14";
334 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>; 345 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
335 clock-names = "fck"; 346 clock-names = "fck";
336 power-domains = <&cpg_clocks>; 347 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
337 #dma-cells = <1>; 348 #dma-cells = <1>;
338 dma-channels = <15>; 349 dma-channels = <15>;
339 }; 350 };
@@ -364,7 +375,7 @@
364 "ch12", "ch13", "ch14"; 375 "ch12", "ch13", "ch14";
365 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>; 376 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
366 clock-names = "fck"; 377 clock-names = "fck";
367 power-domains = <&cpg_clocks>; 378 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
368 #dma-cells = <1>; 379 #dma-cells = <1>;
369 dma-channels = <15>; 380 dma-channels = <15>;
370 }; 381 };
@@ -393,7 +404,7 @@
393 "ch12"; 404 "ch12";
394 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>; 405 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
395 clock-names = "fck"; 406 clock-names = "fck";
396 power-domains = <&cpg_clocks>; 407 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
397 #dma-cells = <1>; 408 #dma-cells = <1>;
398 dma-channels = <13>; 409 dma-channels = <13>;
399 }; 410 };
@@ -422,7 +433,7 @@
422 "ch12"; 433 "ch12";
423 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>; 434 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
424 clock-names = "fck"; 435 clock-names = "fck";
425 power-domains = <&cpg_clocks>; 436 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
426 #dma-cells = <1>; 437 #dma-cells = <1>;
427 dma-channels = <13>; 438 dma-channels = <13>;
428 }; 439 };
@@ -434,7 +445,7 @@
434 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 445 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
435 interrupt-names = "ch0", "ch1"; 446 interrupt-names = "ch0", "ch1";
436 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>; 447 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>;
437 power-domains = <&cpg_clocks>; 448 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
438 #dma-cells = <1>; 449 #dma-cells = <1>;
439 dma-channels = <2>; 450 dma-channels = <2>;
440 }; 451 };
@@ -446,7 +457,7 @@
446 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 457 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
447 interrupt-names = "ch0", "ch1"; 458 interrupt-names = "ch0", "ch1";
448 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>; 459 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>;
449 power-domains = <&cpg_clocks>; 460 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
450 #dma-cells = <1>; 461 #dma-cells = <1>;
451 dma-channels = <2>; 462 dma-channels = <2>;
452 }; 463 };
@@ -458,7 +469,7 @@
458 reg = <0 0xe6508000 0 0x40>; 469 reg = <0 0xe6508000 0 0x40>;
459 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 470 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&mstp9_clks R8A7790_CLK_I2C0>; 471 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
461 power-domains = <&cpg_clocks>; 472 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
462 i2c-scl-internal-delay-ns = <110>; 473 i2c-scl-internal-delay-ns = <110>;
463 status = "disabled"; 474 status = "disabled";
464 }; 475 };
@@ -470,7 +481,7 @@
470 reg = <0 0xe6518000 0 0x40>; 481 reg = <0 0xe6518000 0 0x40>;
471 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 482 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&mstp9_clks R8A7790_CLK_I2C1>; 483 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
473 power-domains = <&cpg_clocks>; 484 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
474 i2c-scl-internal-delay-ns = <6>; 485 i2c-scl-internal-delay-ns = <6>;
475 status = "disabled"; 486 status = "disabled";
476 }; 487 };
@@ -482,7 +493,7 @@
482 reg = <0 0xe6530000 0 0x40>; 493 reg = <0 0xe6530000 0 0x40>;
483 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 494 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&mstp9_clks R8A7790_CLK_I2C2>; 495 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
485 power-domains = <&cpg_clocks>; 496 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
486 i2c-scl-internal-delay-ns = <6>; 497 i2c-scl-internal-delay-ns = <6>;
487 status = "disabled"; 498 status = "disabled";
488 }; 499 };
@@ -494,7 +505,7 @@
494 reg = <0 0xe6540000 0 0x40>; 505 reg = <0 0xe6540000 0 0x40>;
495 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 506 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&mstp9_clks R8A7790_CLK_I2C3>; 507 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
497 power-domains = <&cpg_clocks>; 508 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
498 i2c-scl-internal-delay-ns = <110>; 509 i2c-scl-internal-delay-ns = <110>;
499 status = "disabled"; 510 status = "disabled";
500 }; 511 };
@@ -508,7 +519,7 @@
508 clocks = <&mstp3_clks R8A7790_CLK_IIC0>; 519 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
509 dmas = <&dmac0 0x61>, <&dmac0 0x62>; 520 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
510 dma-names = "tx", "rx"; 521 dma-names = "tx", "rx";
511 power-domains = <&cpg_clocks>; 522 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
512 status = "disabled"; 523 status = "disabled";
513 }; 524 };
514 525
@@ -521,7 +532,7 @@
521 clocks = <&mstp3_clks R8A7790_CLK_IIC1>; 532 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
522 dmas = <&dmac0 0x65>, <&dmac0 0x66>; 533 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
523 dma-names = "tx", "rx"; 534 dma-names = "tx", "rx";
524 power-domains = <&cpg_clocks>; 535 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
525 status = "disabled"; 536 status = "disabled";
526 }; 537 };
527 538
@@ -534,7 +545,7 @@
534 clocks = <&mstp3_clks R8A7790_CLK_IIC2>; 545 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
535 dmas = <&dmac0 0x69>, <&dmac0 0x6a>; 546 dmas = <&dmac0 0x69>, <&dmac0 0x6a>;
536 dma-names = "tx", "rx"; 547 dma-names = "tx", "rx";
537 power-domains = <&cpg_clocks>; 548 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
538 status = "disabled"; 549 status = "disabled";
539 }; 550 };
540 551
@@ -547,7 +558,7 @@
547 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>; 558 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
548 dmas = <&dmac0 0x77>, <&dmac0 0x78>; 559 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
549 dma-names = "tx", "rx"; 560 dma-names = "tx", "rx";
550 power-domains = <&cpg_clocks>; 561 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
551 status = "disabled"; 562 status = "disabled";
552 }; 563 };
553 564
@@ -558,7 +569,7 @@
558 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>; 569 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
559 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; 570 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
560 dma-names = "tx", "rx"; 571 dma-names = "tx", "rx";
561 power-domains = <&cpg_clocks>; 572 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
562 reg-io-width = <4>; 573 reg-io-width = <4>;
563 status = "disabled"; 574 status = "disabled";
564 max-frequency = <97500000>; 575 max-frequency = <97500000>;
@@ -571,7 +582,7 @@
571 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>; 582 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
572 dmas = <&dmac0 0xe1>, <&dmac0 0xe2>; 583 dmas = <&dmac0 0xe1>, <&dmac0 0xe2>;
573 dma-names = "tx", "rx"; 584 dma-names = "tx", "rx";
574 power-domains = <&cpg_clocks>; 585 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
575 reg-io-width = <4>; 586 reg-io-width = <4>;
576 status = "disabled"; 587 status = "disabled";
577 max-frequency = <97500000>; 588 max-frequency = <97500000>;
@@ -590,7 +601,7 @@
590 dmas = <&dmac1 0xcd>, <&dmac1 0xce>; 601 dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
591 dma-names = "tx", "rx"; 602 dma-names = "tx", "rx";
592 max-frequency = <195000000>; 603 max-frequency = <195000000>;
593 power-domains = <&cpg_clocks>; 604 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
594 status = "disabled"; 605 status = "disabled";
595 }; 606 };
596 607
@@ -602,7 +613,7 @@
602 dmas = <&dmac1 0xc9>, <&dmac1 0xca>; 613 dmas = <&dmac1 0xc9>, <&dmac1 0xca>;
603 dma-names = "tx", "rx"; 614 dma-names = "tx", "rx";
604 max-frequency = <195000000>; 615 max-frequency = <195000000>;
605 power-domains = <&cpg_clocks>; 616 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
606 status = "disabled"; 617 status = "disabled";
607 }; 618 };
608 619
@@ -614,7 +625,7 @@
614 dmas = <&dmac1 0xc1>, <&dmac1 0xc2>; 625 dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
615 dma-names = "tx", "rx"; 626 dma-names = "tx", "rx";
616 max-frequency = <97500000>; 627 max-frequency = <97500000>;
617 power-domains = <&cpg_clocks>; 628 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
618 status = "disabled"; 629 status = "disabled";
619 }; 630 };
620 631
@@ -626,7 +637,7 @@
626 dmas = <&dmac1 0xd3>, <&dmac1 0xd4>; 637 dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
627 dma-names = "tx", "rx"; 638 dma-names = "tx", "rx";
628 max-frequency = <97500000>; 639 max-frequency = <97500000>;
629 power-domains = <&cpg_clocks>; 640 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
630 status = "disabled"; 641 status = "disabled";
631 }; 642 };
632 643
@@ -639,7 +650,7 @@
639 clock-names = "fck"; 650 clock-names = "fck";
640 dmas = <&dmac0 0x21>, <&dmac0 0x22>; 651 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
641 dma-names = "tx", "rx"; 652 dma-names = "tx", "rx";
642 power-domains = <&cpg_clocks>; 653 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
643 status = "disabled"; 654 status = "disabled";
644 }; 655 };
645 656
@@ -652,7 +663,7 @@
652 clock-names = "fck"; 663 clock-names = "fck";
653 dmas = <&dmac0 0x25>, <&dmac0 0x26>; 664 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
654 dma-names = "tx", "rx"; 665 dma-names = "tx", "rx";
655 power-domains = <&cpg_clocks>; 666 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
656 status = "disabled"; 667 status = "disabled";
657 }; 668 };
658 669
@@ -665,7 +676,7 @@
665 clock-names = "fck"; 676 clock-names = "fck";
666 dmas = <&dmac0 0x27>, <&dmac0 0x28>; 677 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
667 dma-names = "tx", "rx"; 678 dma-names = "tx", "rx";
668 power-domains = <&cpg_clocks>; 679 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
669 status = "disabled"; 680 status = "disabled";
670 }; 681 };
671 682
@@ -678,7 +689,7 @@
678 clock-names = "fck"; 689 clock-names = "fck";
679 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>; 690 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
680 dma-names = "tx", "rx"; 691 dma-names = "tx", "rx";
681 power-domains = <&cpg_clocks>; 692 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
682 status = "disabled"; 693 status = "disabled";
683 }; 694 };
684 695
@@ -691,7 +702,7 @@
691 clock-names = "fck"; 702 clock-names = "fck";
692 dmas = <&dmac0 0x19>, <&dmac0 0x1a>; 703 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
693 dma-names = "tx", "rx"; 704 dma-names = "tx", "rx";
694 power-domains = <&cpg_clocks>; 705 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
695 status = "disabled"; 706 status = "disabled";
696 }; 707 };
697 708
@@ -704,7 +715,7 @@
704 clock-names = "fck"; 715 clock-names = "fck";
705 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>; 716 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
706 dma-names = "tx", "rx"; 717 dma-names = "tx", "rx";
707 power-domains = <&cpg_clocks>; 718 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
708 status = "disabled"; 719 status = "disabled";
709 }; 720 };
710 721
@@ -718,7 +729,7 @@
718 clock-names = "fck", "brg_int", "scif_clk"; 729 clock-names = "fck", "brg_int", "scif_clk";
719 dmas = <&dmac0 0x29>, <&dmac0 0x2a>; 730 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
720 dma-names = "tx", "rx"; 731 dma-names = "tx", "rx";
721 power-domains = <&cpg_clocks>; 732 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
722 status = "disabled"; 733 status = "disabled";
723 }; 734 };
724 735
@@ -732,7 +743,7 @@
732 clock-names = "fck", "brg_int", "scif_clk"; 743 clock-names = "fck", "brg_int", "scif_clk";
733 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>; 744 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
734 dma-names = "tx", "rx"; 745 dma-names = "tx", "rx";
735 power-domains = <&cpg_clocks>; 746 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
736 status = "disabled"; 747 status = "disabled";
737 }; 748 };
738 749
@@ -746,7 +757,7 @@
746 clock-names = "fck", "brg_int", "scif_clk"; 757 clock-names = "fck", "brg_int", "scif_clk";
747 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>; 758 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
748 dma-names = "tx", "rx"; 759 dma-names = "tx", "rx";
749 power-domains = <&cpg_clocks>; 760 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
750 status = "disabled"; 761 status = "disabled";
751 }; 762 };
752 763
@@ -760,7 +771,7 @@
760 clock-names = "fck", "brg_int", "scif_clk"; 771 clock-names = "fck", "brg_int", "scif_clk";
761 dmas = <&dmac0 0x39>, <&dmac0 0x3a>; 772 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
762 dma-names = "tx", "rx"; 773 dma-names = "tx", "rx";
763 power-domains = <&cpg_clocks>; 774 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
764 status = "disabled"; 775 status = "disabled";
765 }; 776 };
766 777
@@ -774,7 +785,7 @@
774 clock-names = "fck", "brg_int", "scif_clk"; 785 clock-names = "fck", "brg_int", "scif_clk";
775 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>; 786 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
776 dma-names = "tx", "rx"; 787 dma-names = "tx", "rx";
777 power-domains = <&cpg_clocks>; 788 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
778 status = "disabled"; 789 status = "disabled";
779 }; 790 };
780 791
@@ -783,7 +794,7 @@
783 reg = <0 0xee700000 0 0x400>; 794 reg = <0 0xee700000 0 0x400>;
784 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 795 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
785 clocks = <&mstp8_clks R8A7790_CLK_ETHER>; 796 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
786 power-domains = <&cpg_clocks>; 797 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
787 phy-mode = "rmii"; 798 phy-mode = "rmii";
788 #address-cells = <1>; 799 #address-cells = <1>;
789 #size-cells = <0>; 800 #size-cells = <0>;
@@ -796,7 +807,7 @@
796 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; 807 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
797 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 808 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
798 clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>; 809 clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>;
799 power-domains = <&cpg_clocks>; 810 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
800 #address-cells = <1>; 811 #address-cells = <1>;
801 #size-cells = <0>; 812 #size-cells = <0>;
802 status = "disabled"; 813 status = "disabled";
@@ -807,7 +818,7 @@
807 reg = <0 0xee300000 0 0x2000>; 818 reg = <0 0xee300000 0 0x2000>;
808 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 819 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
809 clocks = <&mstp8_clks R8A7790_CLK_SATA0>; 820 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
810 power-domains = <&cpg_clocks>; 821 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
811 status = "disabled"; 822 status = "disabled";
812 }; 823 };
813 824
@@ -816,7 +827,7 @@
816 reg = <0 0xee500000 0 0x2000>; 827 reg = <0 0xee500000 0 0x2000>;
817 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 828 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
818 clocks = <&mstp8_clks R8A7790_CLK_SATA1>; 829 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
819 power-domains = <&cpg_clocks>; 830 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
820 status = "disabled"; 831 status = "disabled";
821 }; 832 };
822 833
@@ -828,7 +839,7 @@
828 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 839 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
829 <&usb_dmac1 0>, <&usb_dmac1 1>; 840 <&usb_dmac1 0>, <&usb_dmac1 1>;
830 dma-names = "ch0", "ch1", "ch2", "ch3"; 841 dma-names = "ch0", "ch1", "ch2", "ch3";
831 power-domains = <&cpg_clocks>; 842 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
832 renesas,buswait = <4>; 843 renesas,buswait = <4>;
833 phys = <&usb0 1>; 844 phys = <&usb0 1>;
834 phy-names = "usb"; 845 phy-names = "usb";
@@ -842,7 +853,7 @@
842 #size-cells = <0>; 853 #size-cells = <0>;
843 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>; 854 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
844 clock-names = "usbhs"; 855 clock-names = "usbhs";
845 power-domains = <&cpg_clocks>; 856 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
846 status = "disabled"; 857 status = "disabled";
847 858
848 usb0: usb-channel@0 { 859 usb0: usb-channel@0 {
@@ -860,7 +871,7 @@
860 reg = <0 0xe6ef0000 0 0x1000>; 871 reg = <0 0xe6ef0000 0 0x1000>;
861 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 872 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
862 clocks = <&mstp8_clks R8A7790_CLK_VIN0>; 873 clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
863 power-domains = <&cpg_clocks>; 874 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
864 status = "disabled"; 875 status = "disabled";
865 }; 876 };
866 877
@@ -869,7 +880,7 @@
869 reg = <0 0xe6ef1000 0 0x1000>; 880 reg = <0 0xe6ef1000 0 0x1000>;
870 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 881 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&mstp8_clks R8A7790_CLK_VIN1>; 882 clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
872 power-domains = <&cpg_clocks>; 883 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
873 status = "disabled"; 884 status = "disabled";
874 }; 885 };
875 886
@@ -878,7 +889,7 @@
878 reg = <0 0xe6ef2000 0 0x1000>; 889 reg = <0 0xe6ef2000 0 0x1000>;
879 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 890 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
880 clocks = <&mstp8_clks R8A7790_CLK_VIN2>; 891 clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
881 power-domains = <&cpg_clocks>; 892 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
882 status = "disabled"; 893 status = "disabled";
883 }; 894 };
884 895
@@ -887,7 +898,7 @@
887 reg = <0 0xe6ef3000 0 0x1000>; 898 reg = <0 0xe6ef3000 0 0x1000>;
888 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 899 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
889 clocks = <&mstp8_clks R8A7790_CLK_VIN3>; 900 clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
890 power-domains = <&cpg_clocks>; 901 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
891 status = "disabled"; 902 status = "disabled";
892 }; 903 };
893 904
@@ -896,7 +907,7 @@
896 reg = <0 0xfe920000 0 0x8000>; 907 reg = <0 0xfe920000 0 0x8000>;
897 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 908 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
898 clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>; 909 clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
899 power-domains = <&cpg_clocks>; 910 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
900 911
901 renesas,has-sru; 912 renesas,has-sru;
902 renesas,#rpf = <5>; 913 renesas,#rpf = <5>;
@@ -909,7 +920,7 @@
909 reg = <0 0xfe928000 0 0x8000>; 920 reg = <0 0xfe928000 0 0x8000>;
910 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 921 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
911 clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>; 922 clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
912 power-domains = <&cpg_clocks>; 923 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
913 924
914 renesas,has-lut; 925 renesas,has-lut;
915 renesas,has-sru; 926 renesas,has-sru;
@@ -923,7 +934,7 @@
923 reg = <0 0xfe930000 0 0x8000>; 934 reg = <0 0xfe930000 0 0x8000>;
924 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 935 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
925 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>; 936 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
926 power-domains = <&cpg_clocks>; 937 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
927 938
928 renesas,has-lif; 939 renesas,has-lif;
929 renesas,has-lut; 940 renesas,has-lut;
@@ -937,7 +948,7 @@
937 reg = <0 0xfe938000 0 0x8000>; 948 reg = <0 0xfe938000 0 0x8000>;
938 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 949 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
939 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>; 950 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
940 power-domains = <&cpg_clocks>; 951 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
941 952
942 renesas,has-lif; 953 renesas,has-lif;
943 renesas,has-lut; 954 renesas,has-lut;
@@ -992,7 +1003,7 @@
992 clocks = <&mstp9_clks R8A7790_CLK_RCAN0>, 1003 clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
993 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>; 1004 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
994 clock-names = "clkp1", "clkp2", "can_clk"; 1005 clock-names = "clkp1", "clkp2", "can_clk";
995 power-domains = <&cpg_clocks>; 1006 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
996 status = "disabled"; 1007 status = "disabled";
997 }; 1008 };
998 1009
@@ -1003,7 +1014,7 @@
1003 clocks = <&mstp9_clks R8A7790_CLK_RCAN1>, 1014 clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
1004 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>; 1015 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
1005 clock-names = "clkp1", "clkp2", "can_clk"; 1016 clock-names = "clkp1", "clkp2", "can_clk";
1006 power-domains = <&cpg_clocks>; 1017 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1007 status = "disabled"; 1018 status = "disabled";
1008 }; 1019 };
1009 1020
@@ -1012,7 +1023,7 @@
1012 reg = <0 0xfe980000 0 0x10300>; 1023 reg = <0 0xfe980000 0 0x10300>;
1013 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1024 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
1014 clocks = <&mstp1_clks R8A7790_CLK_JPU>; 1025 clocks = <&mstp1_clks R8A7790_CLK_JPU>;
1015 power-domains = <&cpg_clocks>; 1026 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1016 }; 1027 };
1017 1028
1018 clocks { 1029 clocks {
@@ -1447,6 +1458,12 @@
1447 }; 1458 };
1448 }; 1459 };
1449 1460
1461 sysc: system-controller@e6180000 {
1462 compatible = "renesas,r8a7790-sysc";
1463 reg = <0 0xe6180000 0 0x0200>;
1464 #power-domain-cells = <1>;
1465 };
1466
1450 qspi: spi@e6b10000 { 1467 qspi: spi@e6b10000 {
1451 compatible = "renesas,qspi-r8a7790", "renesas,qspi"; 1468 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
1452 reg = <0 0xe6b10000 0 0x2c>; 1469 reg = <0 0xe6b10000 0 0x2c>;
@@ -1454,7 +1471,7 @@
1454 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>; 1471 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
1455 dmas = <&dmac0 0x17>, <&dmac0 0x18>; 1472 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1456 dma-names = "tx", "rx"; 1473 dma-names = "tx", "rx";
1457 power-domains = <&cpg_clocks>; 1474 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1458 num-cs = <1>; 1475 num-cs = <1>;
1459 #address-cells = <1>; 1476 #address-cells = <1>;
1460 #size-cells = <0>; 1477 #size-cells = <0>;
@@ -1468,7 +1485,7 @@
1468 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>; 1485 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
1469 dmas = <&dmac0 0x51>, <&dmac0 0x52>; 1486 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1470 dma-names = "tx", "rx"; 1487 dma-names = "tx", "rx";
1471 power-domains = <&cpg_clocks>; 1488 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1472 #address-cells = <1>; 1489 #address-cells = <1>;
1473 #size-cells = <0>; 1490 #size-cells = <0>;
1474 status = "disabled"; 1491 status = "disabled";
@@ -1481,7 +1498,7 @@
1481 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>; 1498 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
1482 dmas = <&dmac0 0x55>, <&dmac0 0x56>; 1499 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1483 dma-names = "tx", "rx"; 1500 dma-names = "tx", "rx";
1484 power-domains = <&cpg_clocks>; 1501 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1485 #address-cells = <1>; 1502 #address-cells = <1>;
1486 #size-cells = <0>; 1503 #size-cells = <0>;
1487 status = "disabled"; 1504 status = "disabled";
@@ -1494,7 +1511,7 @@
1494 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>; 1511 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
1495 dmas = <&dmac0 0x41>, <&dmac0 0x42>; 1512 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1496 dma-names = "tx", "rx"; 1513 dma-names = "tx", "rx";
1497 power-domains = <&cpg_clocks>; 1514 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1498 #address-cells = <1>; 1515 #address-cells = <1>;
1499 #size-cells = <0>; 1516 #size-cells = <0>;
1500 status = "disabled"; 1517 status = "disabled";
@@ -1507,7 +1524,7 @@
1507 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>; 1524 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
1508 dmas = <&dmac0 0x45>, <&dmac0 0x46>; 1525 dmas = <&dmac0 0x45>, <&dmac0 0x46>;
1509 dma-names = "tx", "rx"; 1526 dma-names = "tx", "rx";
1510 power-domains = <&cpg_clocks>; 1527 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1511 #address-cells = <1>; 1528 #address-cells = <1>;
1512 #size-cells = <0>; 1529 #size-cells = <0>;
1513 status = "disabled"; 1530 status = "disabled";
@@ -1518,7 +1535,7 @@
1518 reg = <0 0xee000000 0 0xc00>; 1535 reg = <0 0xee000000 0 0xc00>;
1519 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1536 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1520 clocks = <&mstp3_clks R8A7790_CLK_SSUSB>; 1537 clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
1521 power-domains = <&cpg_clocks>; 1538 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1522 phys = <&usb2 1>; 1539 phys = <&usb2 1>;
1523 phy-names = "usb"; 1540 phy-names = "usb";
1524 status = "disabled"; 1541 status = "disabled";
@@ -1531,7 +1548,7 @@
1531 <0 0xee080000 0 0x1100>; 1548 <0 0xee080000 0 0x1100>;
1532 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1549 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1533 clocks = <&mstp7_clks R8A7790_CLK_EHCI>; 1550 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1534 power-domains = <&cpg_clocks>; 1551 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1535 status = "disabled"; 1552 status = "disabled";
1536 1553
1537 bus-range = <0 0>; 1554 bus-range = <0 0>;
@@ -1566,7 +1583,7 @@
1566 <0 0xee0a0000 0 0x1100>; 1583 <0 0xee0a0000 0 0x1100>;
1567 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1584 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1568 clocks = <&mstp7_clks R8A7790_CLK_EHCI>; 1585 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1569 power-domains = <&cpg_clocks>; 1586 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1570 status = "disabled"; 1587 status = "disabled";
1571 1588
1572 bus-range = <1 1>; 1589 bus-range = <1 1>;
@@ -1584,7 +1601,7 @@
1584 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2"; 1601 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
1585 device_type = "pci"; 1602 device_type = "pci";
1586 clocks = <&mstp7_clks R8A7790_CLK_EHCI>; 1603 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1587 power-domains = <&cpg_clocks>; 1604 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1588 reg = <0 0xee0d0000 0 0xc00>, 1605 reg = <0 0xee0d0000 0 0xc00>,
1589 <0 0xee0c0000 0 0x1100>; 1606 <0 0xee0c0000 0 0x1100>;
1590 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1607 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
@@ -1637,7 +1654,7 @@
1637 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1654 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1638 clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>; 1655 clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
1639 clock-names = "pcie", "pcie_bus"; 1656 clock-names = "pcie", "pcie_bus";
1640 power-domains = <&cpg_clocks>; 1657 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1641 status = "disabled"; 1658 status = "disabled";
1642 }; 1659 };
1643 1660
@@ -1680,7 +1697,7 @@
1680 "mix.0", "mix.1", 1697 "mix.0", "mix.1",
1681 "dvc.0", "dvc.1", 1698 "dvc.0", "dvc.1",
1682 "clk_a", "clk_b", "clk_c", "clk_i"; 1699 "clk_a", "clk_b", "clk_c", "clk_i";
1683 power-domains = <&cpg_clocks>; 1700 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
1684 1701
1685 status = "disabled"; 1702 status = "disabled";
1686 1703
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 565c270e549d..db67e342c585 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -13,6 +13,7 @@
13#include <dt-bindings/clock/r8a7791-clock.h> 13#include <dt-bindings/clock/r8a7791-clock.h>
14#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/interrupt-controller/irq.h> 15#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/power/r8a7791-sysc.h>
16 17
17/ { 18/ {
18 compatible = "renesas,r8a7791"; 19 compatible = "renesas,r8a7791";
@@ -51,6 +52,7 @@
51 voltage-tolerance = <1>; /* 1% */ 52 voltage-tolerance = <1>; /* 1% */
52 clocks = <&cpg_clocks R8A7791_CLK_Z>; 53 clocks = <&cpg_clocks R8A7791_CLK_Z>;
53 clock-latency = <300000>; /* 300 us */ 54 clock-latency = <300000>; /* 300 us */
55 power-domains = <&sysc R8A7791_PD_CA15_CPU0>;
54 next-level-cache = <&L2_CA15>; 56 next-level-cache = <&L2_CA15>;
55 57
56 /* kHz - uV - OPPs unknown yet */ 58 /* kHz - uV - OPPs unknown yet */
@@ -67,6 +69,7 @@
67 compatible = "arm,cortex-a15"; 69 compatible = "arm,cortex-a15";
68 reg = <1>; 70 reg = <1>;
69 clock-frequency = <1500000000>; 71 clock-frequency = <1500000000>;
72 power-domains = <&sysc R8A7791_PD_CA15_CPU1>;
70 next-level-cache = <&L2_CA15>; 73 next-level-cache = <&L2_CA15>;
71 }; 74 };
72 }; 75 };
@@ -92,6 +95,7 @@
92 95
93 L2_CA15: cache-controller@0 { 96 L2_CA15: cache-controller@0 {
94 compatible = "cache"; 97 compatible = "cache";
98 power-domains = <&sysc R8A7791_PD_CA15_SCU>;
95 cache-unified; 99 cache-unified;
96 cache-level = <2>; 100 cache-level = <2>;
97 }; 101 };
@@ -118,7 +122,7 @@
118 #interrupt-cells = <2>; 122 #interrupt-cells = <2>;
119 interrupt-controller; 123 interrupt-controller;
120 clocks = <&mstp9_clks R8A7791_CLK_GPIO0>; 124 clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
121 power-domains = <&cpg_clocks>; 125 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
122 }; 126 };
123 127
124 gpio1: gpio@e6051000 { 128 gpio1: gpio@e6051000 {
@@ -131,7 +135,7 @@
131 #interrupt-cells = <2>; 135 #interrupt-cells = <2>;
132 interrupt-controller; 136 interrupt-controller;
133 clocks = <&mstp9_clks R8A7791_CLK_GPIO1>; 137 clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
134 power-domains = <&cpg_clocks>; 138 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
135 }; 139 };
136 140
137 gpio2: gpio@e6052000 { 141 gpio2: gpio@e6052000 {
@@ -144,7 +148,7 @@
144 #interrupt-cells = <2>; 148 #interrupt-cells = <2>;
145 interrupt-controller; 149 interrupt-controller;
146 clocks = <&mstp9_clks R8A7791_CLK_GPIO2>; 150 clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
147 power-domains = <&cpg_clocks>; 151 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
148 }; 152 };
149 153
150 gpio3: gpio@e6053000 { 154 gpio3: gpio@e6053000 {
@@ -157,7 +161,7 @@
157 #interrupt-cells = <2>; 161 #interrupt-cells = <2>;
158 interrupt-controller; 162 interrupt-controller;
159 clocks = <&mstp9_clks R8A7791_CLK_GPIO3>; 163 clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
160 power-domains = <&cpg_clocks>; 164 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
161 }; 165 };
162 166
163 gpio4: gpio@e6054000 { 167 gpio4: gpio@e6054000 {
@@ -170,7 +174,7 @@
170 #interrupt-cells = <2>; 174 #interrupt-cells = <2>;
171 interrupt-controller; 175 interrupt-controller;
172 clocks = <&mstp9_clks R8A7791_CLK_GPIO4>; 176 clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
173 power-domains = <&cpg_clocks>; 177 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
174 }; 178 };
175 179
176 gpio5: gpio@e6055000 { 180 gpio5: gpio@e6055000 {
@@ -183,7 +187,7 @@
183 #interrupt-cells = <2>; 187 #interrupt-cells = <2>;
184 interrupt-controller; 188 interrupt-controller;
185 clocks = <&mstp9_clks R8A7791_CLK_GPIO5>; 189 clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
186 power-domains = <&cpg_clocks>; 190 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
187 }; 191 };
188 192
189 gpio6: gpio@e6055400 { 193 gpio6: gpio@e6055400 {
@@ -196,7 +200,7 @@
196 #interrupt-cells = <2>; 200 #interrupt-cells = <2>;
197 interrupt-controller; 201 interrupt-controller;
198 clocks = <&mstp9_clks R8A7791_CLK_GPIO6>; 202 clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
199 power-domains = <&cpg_clocks>; 203 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
200 }; 204 };
201 205
202 gpio7: gpio@e6055800 { 206 gpio7: gpio@e6055800 {
@@ -209,7 +213,7 @@
209 #interrupt-cells = <2>; 213 #interrupt-cells = <2>;
210 interrupt-controller; 214 interrupt-controller;
211 clocks = <&mstp9_clks R8A7791_CLK_GPIO7>; 215 clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
212 power-domains = <&cpg_clocks>; 216 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
213 }; 217 };
214 218
215 thermal: thermal@e61f0000 { 219 thermal: thermal@e61f0000 {
@@ -219,7 +223,7 @@
219 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; 223 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
220 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 224 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>; 225 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
222 power-domains = <&cpg_clocks>; 226 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
223 #thermal-sensor-cells = <0>; 227 #thermal-sensor-cells = <0>;
224 }; 228 };
225 229
@@ -238,7 +242,7 @@
238 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 242 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
239 clocks = <&mstp1_clks R8A7791_CLK_CMT0>; 243 clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
240 clock-names = "fck"; 244 clock-names = "fck";
241 power-domains = <&cpg_clocks>; 245 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
242 246
243 renesas,channels-mask = <0x60>; 247 renesas,channels-mask = <0x60>;
244 248
@@ -258,7 +262,7 @@
258 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 262 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&mstp3_clks R8A7791_CLK_CMT1>; 263 clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
260 clock-names = "fck"; 264 clock-names = "fck";
261 power-domains = <&cpg_clocks>; 265 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
262 266
263 renesas,channels-mask = <0xff>; 267 renesas,channels-mask = <0xff>;
264 268
@@ -281,7 +285,7 @@
281 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 286 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&mstp4_clks R8A7791_CLK_IRQC>; 287 clocks = <&mstp4_clks R8A7791_CLK_IRQC>;
284 power-domains = <&cpg_clocks>; 288 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
285 }; 289 };
286 290
287 dmac0: dma-controller@e6700000 { 291 dmac0: dma-controller@e6700000 {
@@ -310,7 +314,7 @@
310 "ch12", "ch13", "ch14"; 314 "ch12", "ch13", "ch14";
311 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>; 315 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
312 clock-names = "fck"; 316 clock-names = "fck";
313 power-domains = <&cpg_clocks>; 317 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
314 #dma-cells = <1>; 318 #dma-cells = <1>;
315 dma-channels = <15>; 319 dma-channels = <15>;
316 }; 320 };
@@ -341,7 +345,7 @@
341 "ch12", "ch13", "ch14"; 345 "ch12", "ch13", "ch14";
342 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>; 346 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
343 clock-names = "fck"; 347 clock-names = "fck";
344 power-domains = <&cpg_clocks>; 348 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
345 #dma-cells = <1>; 349 #dma-cells = <1>;
346 dma-channels = <15>; 350 dma-channels = <15>;
347 }; 351 };
@@ -370,7 +374,7 @@
370 "ch12"; 374 "ch12";
371 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>; 375 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>;
372 clock-names = "fck"; 376 clock-names = "fck";
373 power-domains = <&cpg_clocks>; 377 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
374 #dma-cells = <1>; 378 #dma-cells = <1>;
375 dma-channels = <13>; 379 dma-channels = <13>;
376 }; 380 };
@@ -399,7 +403,7 @@
399 "ch12"; 403 "ch12";
400 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>; 404 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>;
401 clock-names = "fck"; 405 clock-names = "fck";
402 power-domains = <&cpg_clocks>; 406 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
403 #dma-cells = <1>; 407 #dma-cells = <1>;
404 dma-channels = <13>; 408 dma-channels = <13>;
405 }; 409 };
@@ -411,7 +415,7 @@
411 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 415 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
412 interrupt-names = "ch0", "ch1"; 416 interrupt-names = "ch0", "ch1";
413 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>; 417 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>;
414 power-domains = <&cpg_clocks>; 418 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
415 #dma-cells = <1>; 419 #dma-cells = <1>;
416 dma-channels = <2>; 420 dma-channels = <2>;
417 }; 421 };
@@ -423,7 +427,7 @@
423 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 427 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
424 interrupt-names = "ch0", "ch1"; 428 interrupt-names = "ch0", "ch1";
425 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>; 429 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>;
426 power-domains = <&cpg_clocks>; 430 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
427 #dma-cells = <1>; 431 #dma-cells = <1>;
428 dma-channels = <2>; 432 dma-channels = <2>;
429 }; 433 };
@@ -436,7 +440,7 @@
436 reg = <0 0xe6508000 0 0x40>; 440 reg = <0 0xe6508000 0 0x40>;
437 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 441 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&mstp9_clks R8A7791_CLK_I2C0>; 442 clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
439 power-domains = <&cpg_clocks>; 443 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
440 i2c-scl-internal-delay-ns = <6>; 444 i2c-scl-internal-delay-ns = <6>;
441 status = "disabled"; 445 status = "disabled";
442 }; 446 };
@@ -448,7 +452,7 @@
448 reg = <0 0xe6518000 0 0x40>; 452 reg = <0 0xe6518000 0 0x40>;
449 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 453 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
450 clocks = <&mstp9_clks R8A7791_CLK_I2C1>; 454 clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
451 power-domains = <&cpg_clocks>; 455 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
452 i2c-scl-internal-delay-ns = <6>; 456 i2c-scl-internal-delay-ns = <6>;
453 status = "disabled"; 457 status = "disabled";
454 }; 458 };
@@ -460,7 +464,7 @@
460 reg = <0 0xe6530000 0 0x40>; 464 reg = <0 0xe6530000 0 0x40>;
461 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 465 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&mstp9_clks R8A7791_CLK_I2C2>; 466 clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
463 power-domains = <&cpg_clocks>; 467 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
464 i2c-scl-internal-delay-ns = <6>; 468 i2c-scl-internal-delay-ns = <6>;
465 status = "disabled"; 469 status = "disabled";
466 }; 470 };
@@ -472,7 +476,7 @@
472 reg = <0 0xe6540000 0 0x40>; 476 reg = <0 0xe6540000 0 0x40>;
473 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 477 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&mstp9_clks R8A7791_CLK_I2C3>; 478 clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
475 power-domains = <&cpg_clocks>; 479 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
476 i2c-scl-internal-delay-ns = <6>; 480 i2c-scl-internal-delay-ns = <6>;
477 status = "disabled"; 481 status = "disabled";
478 }; 482 };
@@ -484,7 +488,7 @@
484 reg = <0 0xe6520000 0 0x40>; 488 reg = <0 0xe6520000 0 0x40>;
485 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 489 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&mstp9_clks R8A7791_CLK_I2C4>; 490 clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
487 power-domains = <&cpg_clocks>; 491 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
488 i2c-scl-internal-delay-ns = <6>; 492 i2c-scl-internal-delay-ns = <6>;
489 status = "disabled"; 493 status = "disabled";
490 }; 494 };
@@ -497,7 +501,7 @@
497 reg = <0 0xe6528000 0 0x40>; 501 reg = <0 0xe6528000 0 0x40>;
498 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 502 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
499 clocks = <&mstp9_clks R8A7791_CLK_I2C5>; 503 clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
500 power-domains = <&cpg_clocks>; 504 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
501 i2c-scl-internal-delay-ns = <110>; 505 i2c-scl-internal-delay-ns = <110>;
502 status = "disabled"; 506 status = "disabled";
503 }; 507 };
@@ -512,7 +516,7 @@
512 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>; 516 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
513 dmas = <&dmac0 0x77>, <&dmac0 0x78>; 517 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
514 dma-names = "tx", "rx"; 518 dma-names = "tx", "rx";
515 power-domains = <&cpg_clocks>; 519 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
516 status = "disabled"; 520 status = "disabled";
517 }; 521 };
518 522
@@ -525,7 +529,7 @@
525 clocks = <&mstp3_clks R8A7791_CLK_IIC0>; 529 clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
526 dmas = <&dmac0 0x61>, <&dmac0 0x62>; 530 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
527 dma-names = "tx", "rx"; 531 dma-names = "tx", "rx";
528 power-domains = <&cpg_clocks>; 532 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
529 status = "disabled"; 533 status = "disabled";
530 }; 534 };
531 535
@@ -538,7 +542,7 @@
538 clocks = <&mstp3_clks R8A7791_CLK_IIC1>; 542 clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
539 dmas = <&dmac0 0x65>, <&dmac0 0x66>; 543 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
540 dma-names = "tx", "rx"; 544 dma-names = "tx", "rx";
541 power-domains = <&cpg_clocks>; 545 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
542 status = "disabled"; 546 status = "disabled";
543 }; 547 };
544 548
@@ -554,7 +558,7 @@
554 clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>; 558 clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
555 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; 559 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
556 dma-names = "tx", "rx"; 560 dma-names = "tx", "rx";
557 power-domains = <&cpg_clocks>; 561 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
558 reg-io-width = <4>; 562 reg-io-width = <4>;
559 status = "disabled"; 563 status = "disabled";
560 max-frequency = <97500000>; 564 max-frequency = <97500000>;
@@ -567,7 +571,7 @@
567 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>; 571 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
568 dmas = <&dmac1 0xcd>, <&dmac1 0xce>; 572 dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
569 dma-names = "tx", "rx"; 573 dma-names = "tx", "rx";
570 power-domains = <&cpg_clocks>; 574 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
571 status = "disabled"; 575 status = "disabled";
572 }; 576 };
573 577
@@ -578,7 +582,7 @@
578 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>; 582 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
579 dmas = <&dmac1 0xc1>, <&dmac1 0xc2>; 583 dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
580 dma-names = "tx", "rx"; 584 dma-names = "tx", "rx";
581 power-domains = <&cpg_clocks>; 585 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
582 status = "disabled"; 586 status = "disabled";
583 }; 587 };
584 588
@@ -589,7 +593,7 @@
589 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>; 593 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
590 dmas = <&dmac1 0xd3>, <&dmac1 0xd4>; 594 dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
591 dma-names = "tx", "rx"; 595 dma-names = "tx", "rx";
592 power-domains = <&cpg_clocks>; 596 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
593 status = "disabled"; 597 status = "disabled";
594 }; 598 };
595 599
@@ -602,7 +606,7 @@
602 clock-names = "fck"; 606 clock-names = "fck";
603 dmas = <&dmac0 0x21>, <&dmac0 0x22>; 607 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
604 dma-names = "tx", "rx"; 608 dma-names = "tx", "rx";
605 power-domains = <&cpg_clocks>; 609 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
606 status = "disabled"; 610 status = "disabled";
607 }; 611 };
608 612
@@ -615,7 +619,7 @@
615 clock-names = "fck"; 619 clock-names = "fck";
616 dmas = <&dmac0 0x25>, <&dmac0 0x26>; 620 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
617 dma-names = "tx", "rx"; 621 dma-names = "tx", "rx";
618 power-domains = <&cpg_clocks>; 622 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
619 status = "disabled"; 623 status = "disabled";
620 }; 624 };
621 625
@@ -628,7 +632,7 @@
628 clock-names = "fck"; 632 clock-names = "fck";
629 dmas = <&dmac0 0x27>, <&dmac0 0x28>; 633 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
630 dma-names = "tx", "rx"; 634 dma-names = "tx", "rx";
631 power-domains = <&cpg_clocks>; 635 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
632 status = "disabled"; 636 status = "disabled";
633 }; 637 };
634 638
@@ -641,7 +645,7 @@
641 clock-names = "fck"; 645 clock-names = "fck";
642 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>; 646 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
643 dma-names = "tx", "rx"; 647 dma-names = "tx", "rx";
644 power-domains = <&cpg_clocks>; 648 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
645 status = "disabled"; 649 status = "disabled";
646 }; 650 };
647 651
@@ -654,7 +658,7 @@
654 clock-names = "fck"; 658 clock-names = "fck";
655 dmas = <&dmac0 0x1f>, <&dmac0 0x20>; 659 dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
656 dma-names = "tx", "rx"; 660 dma-names = "tx", "rx";
657 power-domains = <&cpg_clocks>; 661 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
658 status = "disabled"; 662 status = "disabled";
659 }; 663 };
660 664
@@ -667,7 +671,7 @@
667 clock-names = "fck"; 671 clock-names = "fck";
668 dmas = <&dmac0 0x23>, <&dmac0 0x24>; 672 dmas = <&dmac0 0x23>, <&dmac0 0x24>;
669 dma-names = "tx", "rx"; 673 dma-names = "tx", "rx";
670 power-domains = <&cpg_clocks>; 674 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
671 status = "disabled"; 675 status = "disabled";
672 }; 676 };
673 677
@@ -680,7 +684,7 @@
680 clock-names = "fck"; 684 clock-names = "fck";
681 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>; 685 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
682 dma-names = "tx", "rx"; 686 dma-names = "tx", "rx";
683 power-domains = <&cpg_clocks>; 687 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
684 status = "disabled"; 688 status = "disabled";
685 }; 689 };
686 690
@@ -693,7 +697,7 @@
693 clock-names = "fck"; 697 clock-names = "fck";
694 dmas = <&dmac0 0x19>, <&dmac0 0x1a>; 698 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
695 dma-names = "tx", "rx"; 699 dma-names = "tx", "rx";
696 power-domains = <&cpg_clocks>; 700 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
697 status = "disabled"; 701 status = "disabled";
698 }; 702 };
699 703
@@ -706,7 +710,7 @@
706 clock-names = "fck"; 710 clock-names = "fck";
707 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>; 711 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
708 dma-names = "tx", "rx"; 712 dma-names = "tx", "rx";
709 power-domains = <&cpg_clocks>; 713 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
710 status = "disabled"; 714 status = "disabled";
711 }; 715 };
712 716
@@ -720,7 +724,7 @@
720 clock-names = "fck", "brg_int", "scif_clk"; 724 clock-names = "fck", "brg_int", "scif_clk";
721 dmas = <&dmac0 0x29>, <&dmac0 0x2a>; 725 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
722 dma-names = "tx", "rx"; 726 dma-names = "tx", "rx";
723 power-domains = <&cpg_clocks>; 727 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
724 status = "disabled"; 728 status = "disabled";
725 }; 729 };
726 730
@@ -734,7 +738,7 @@
734 clock-names = "fck", "brg_int", "scif_clk"; 738 clock-names = "fck", "brg_int", "scif_clk";
735 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>; 739 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
736 dma-names = "tx", "rx"; 740 dma-names = "tx", "rx";
737 power-domains = <&cpg_clocks>; 741 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
738 status = "disabled"; 742 status = "disabled";
739 }; 743 };
740 744
@@ -748,7 +752,7 @@
748 clock-names = "fck", "brg_int", "scif_clk"; 752 clock-names = "fck", "brg_int", "scif_clk";
749 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>; 753 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
750 dma-names = "tx", "rx"; 754 dma-names = "tx", "rx";
751 power-domains = <&cpg_clocks>; 755 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
752 status = "disabled"; 756 status = "disabled";
753 }; 757 };
754 758
@@ -762,7 +766,7 @@
762 clock-names = "fck", "brg_int", "scif_clk"; 766 clock-names = "fck", "brg_int", "scif_clk";
763 dmas = <&dmac0 0x2f>, <&dmac0 0x30>; 767 dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
764 dma-names = "tx", "rx"; 768 dma-names = "tx", "rx";
765 power-domains = <&cpg_clocks>; 769 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
766 status = "disabled"; 770 status = "disabled";
767 }; 771 };
768 772
@@ -776,7 +780,7 @@
776 clock-names = "fck", "brg_int", "scif_clk"; 780 clock-names = "fck", "brg_int", "scif_clk";
777 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>; 781 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
778 dma-names = "tx", "rx"; 782 dma-names = "tx", "rx";
779 power-domains = <&cpg_clocks>; 783 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
780 status = "disabled"; 784 status = "disabled";
781 }; 785 };
782 786
@@ -790,7 +794,7 @@
790 clock-names = "fck", "brg_int", "scif_clk"; 794 clock-names = "fck", "brg_int", "scif_clk";
791 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>; 795 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
792 dma-names = "tx", "rx"; 796 dma-names = "tx", "rx";
793 power-domains = <&cpg_clocks>; 797 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
794 status = "disabled"; 798 status = "disabled";
795 }; 799 };
796 800
@@ -804,7 +808,7 @@
804 clock-names = "fck", "brg_int", "scif_clk"; 808 clock-names = "fck", "brg_int", "scif_clk";
805 dmas = <&dmac0 0x39>, <&dmac0 0x3a>; 809 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
806 dma-names = "tx", "rx"; 810 dma-names = "tx", "rx";
807 power-domains = <&cpg_clocks>; 811 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
808 status = "disabled"; 812 status = "disabled";
809 }; 813 };
810 814
@@ -818,7 +822,7 @@
818 clock-names = "fck", "brg_int", "scif_clk"; 822 clock-names = "fck", "brg_int", "scif_clk";
819 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>; 823 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
820 dma-names = "tx", "rx"; 824 dma-names = "tx", "rx";
821 power-domains = <&cpg_clocks>; 825 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
822 status = "disabled"; 826 status = "disabled";
823 }; 827 };
824 828
@@ -832,7 +836,7 @@
832 clock-names = "fck", "brg_int", "scif_clk"; 836 clock-names = "fck", "brg_int", "scif_clk";
833 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>; 837 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
834 dma-names = "tx", "rx"; 838 dma-names = "tx", "rx";
835 power-domains = <&cpg_clocks>; 839 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
836 status = "disabled"; 840 status = "disabled";
837 }; 841 };
838 842
@@ -841,7 +845,7 @@
841 reg = <0 0xee700000 0 0x400>; 845 reg = <0 0xee700000 0 0x400>;
842 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 846 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
843 clocks = <&mstp8_clks R8A7791_CLK_ETHER>; 847 clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
844 power-domains = <&cpg_clocks>; 848 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
845 phy-mode = "rmii"; 849 phy-mode = "rmii";
846 #address-cells = <1>; 850 #address-cells = <1>;
847 #size-cells = <0>; 851 #size-cells = <0>;
@@ -854,7 +858,7 @@
854 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; 858 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
855 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 859 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
856 clocks = <&mstp8_clks R8A7791_CLK_ETHERAVB>; 860 clocks = <&mstp8_clks R8A7791_CLK_ETHERAVB>;
857 power-domains = <&cpg_clocks>; 861 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
858 #address-cells = <1>; 862 #address-cells = <1>;
859 #size-cells = <0>; 863 #size-cells = <0>;
860 status = "disabled"; 864 status = "disabled";
@@ -865,7 +869,7 @@
865 reg = <0 0xee300000 0 0x2000>; 869 reg = <0 0xee300000 0 0x2000>;
866 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 870 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
867 clocks = <&mstp8_clks R8A7791_CLK_SATA0>; 871 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
868 power-domains = <&cpg_clocks>; 872 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
869 status = "disabled"; 873 status = "disabled";
870 }; 874 };
871 875
@@ -874,7 +878,7 @@
874 reg = <0 0xee500000 0 0x2000>; 878 reg = <0 0xee500000 0 0x2000>;
875 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 879 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
876 clocks = <&mstp8_clks R8A7791_CLK_SATA1>; 880 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
877 power-domains = <&cpg_clocks>; 881 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
878 status = "disabled"; 882 status = "disabled";
879 }; 883 };
880 884
@@ -886,7 +890,7 @@
886 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 890 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
887 <&usb_dmac1 0>, <&usb_dmac1 1>; 891 <&usb_dmac1 0>, <&usb_dmac1 1>;
888 dma-names = "ch0", "ch1", "ch2", "ch3"; 892 dma-names = "ch0", "ch1", "ch2", "ch3";
889 power-domains = <&cpg_clocks>; 893 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
890 renesas,buswait = <4>; 894 renesas,buswait = <4>;
891 phys = <&usb0 1>; 895 phys = <&usb0 1>;
892 phy-names = "usb"; 896 phy-names = "usb";
@@ -900,7 +904,7 @@
900 #size-cells = <0>; 904 #size-cells = <0>;
901 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>; 905 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
902 clock-names = "usbhs"; 906 clock-names = "usbhs";
903 power-domains = <&cpg_clocks>; 907 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
904 status = "disabled"; 908 status = "disabled";
905 909
906 usb0: usb-channel@0 { 910 usb0: usb-channel@0 {
@@ -918,7 +922,7 @@
918 reg = <0 0xe6ef0000 0 0x1000>; 922 reg = <0 0xe6ef0000 0 0x1000>;
919 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 923 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
920 clocks = <&mstp8_clks R8A7791_CLK_VIN0>; 924 clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
921 power-domains = <&cpg_clocks>; 925 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
922 status = "disabled"; 926 status = "disabled";
923 }; 927 };
924 928
@@ -927,7 +931,7 @@
927 reg = <0 0xe6ef1000 0 0x1000>; 931 reg = <0 0xe6ef1000 0 0x1000>;
928 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 932 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
929 clocks = <&mstp8_clks R8A7791_CLK_VIN1>; 933 clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
930 power-domains = <&cpg_clocks>; 934 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
931 status = "disabled"; 935 status = "disabled";
932 }; 936 };
933 937
@@ -936,7 +940,7 @@
936 reg = <0 0xe6ef2000 0 0x1000>; 940 reg = <0 0xe6ef2000 0 0x1000>;
937 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 941 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
938 clocks = <&mstp8_clks R8A7791_CLK_VIN2>; 942 clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
939 power-domains = <&cpg_clocks>; 943 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
940 status = "disabled"; 944 status = "disabled";
941 }; 945 };
942 946
@@ -945,7 +949,7 @@
945 reg = <0 0xfe928000 0 0x8000>; 949 reg = <0 0xfe928000 0 0x8000>;
946 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 950 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
947 clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>; 951 clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>;
948 power-domains = <&cpg_clocks>; 952 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
949 953
950 renesas,has-lut; 954 renesas,has-lut;
951 renesas,has-sru; 955 renesas,has-sru;
@@ -959,7 +963,7 @@
959 reg = <0 0xfe930000 0 0x8000>; 963 reg = <0 0xfe930000 0 0x8000>;
960 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 964 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
961 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>; 965 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>;
962 power-domains = <&cpg_clocks>; 966 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
963 967
964 renesas,has-lif; 968 renesas,has-lif;
965 renesas,has-lut; 969 renesas,has-lut;
@@ -973,7 +977,7 @@
973 reg = <0 0xfe938000 0 0x8000>; 977 reg = <0 0xfe938000 0 0x8000>;
974 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 978 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
975 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>; 979 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>;
976 power-domains = <&cpg_clocks>; 980 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
977 981
978 renesas,has-lif; 982 renesas,has-lif;
979 renesas,has-lut; 983 renesas,has-lut;
@@ -1019,7 +1023,7 @@
1019 clocks = <&mstp9_clks R8A7791_CLK_RCAN0>, 1023 clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
1020 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>; 1024 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
1021 clock-names = "clkp1", "clkp2", "can_clk"; 1025 clock-names = "clkp1", "clkp2", "can_clk";
1022 power-domains = <&cpg_clocks>; 1026 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1023 status = "disabled"; 1027 status = "disabled";
1024 }; 1028 };
1025 1029
@@ -1030,7 +1034,7 @@
1030 clocks = <&mstp9_clks R8A7791_CLK_RCAN1>, 1034 clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
1031 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>; 1035 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
1032 clock-names = "clkp1", "clkp2", "can_clk"; 1036 clock-names = "clkp1", "clkp2", "can_clk";
1033 power-domains = <&cpg_clocks>; 1037 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1034 status = "disabled"; 1038 status = "disabled";
1035 }; 1039 };
1036 1040
@@ -1039,7 +1043,7 @@
1039 reg = <0 0xfe980000 0 0x10300>; 1043 reg = <0 0xfe980000 0 0x10300>;
1040 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1044 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
1041 clocks = <&mstp1_clks R8A7791_CLK_JPU>; 1045 clocks = <&mstp1_clks R8A7791_CLK_JPU>;
1042 power-domains = <&cpg_clocks>; 1046 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1043 }; 1047 };
1044 1048
1045 clocks { 1049 clocks {
@@ -1463,6 +1467,12 @@
1463 }; 1467 };
1464 }; 1468 };
1465 1469
1470 sysc: system-controller@e6180000 {
1471 compatible = "renesas,r8a7791-sysc";
1472 reg = <0 0xe6180000 0 0x0200>;
1473 #power-domain-cells = <1>;
1474 };
1475
1466 qspi: spi@e6b10000 { 1476 qspi: spi@e6b10000 {
1467 compatible = "renesas,qspi-r8a7791", "renesas,qspi"; 1477 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
1468 reg = <0 0xe6b10000 0 0x2c>; 1478 reg = <0 0xe6b10000 0 0x2c>;
@@ -1470,7 +1480,7 @@
1470 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>; 1480 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
1471 dmas = <&dmac0 0x17>, <&dmac0 0x18>; 1481 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1472 dma-names = "tx", "rx"; 1482 dma-names = "tx", "rx";
1473 power-domains = <&cpg_clocks>; 1483 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1474 num-cs = <1>; 1484 num-cs = <1>;
1475 #address-cells = <1>; 1485 #address-cells = <1>;
1476 #size-cells = <0>; 1486 #size-cells = <0>;
@@ -1484,7 +1494,7 @@
1484 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; 1494 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
1485 dmas = <&dmac0 0x51>, <&dmac0 0x52>; 1495 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1486 dma-names = "tx", "rx"; 1496 dma-names = "tx", "rx";
1487 power-domains = <&cpg_clocks>; 1497 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1488 #address-cells = <1>; 1498 #address-cells = <1>;
1489 #size-cells = <0>; 1499 #size-cells = <0>;
1490 status = "disabled"; 1500 status = "disabled";
@@ -1497,7 +1507,7 @@
1497 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>; 1507 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
1498 dmas = <&dmac0 0x55>, <&dmac0 0x56>; 1508 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1499 dma-names = "tx", "rx"; 1509 dma-names = "tx", "rx";
1500 power-domains = <&cpg_clocks>; 1510 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1501 #address-cells = <1>; 1511 #address-cells = <1>;
1502 #size-cells = <0>; 1512 #size-cells = <0>;
1503 status = "disabled"; 1513 status = "disabled";
@@ -1510,7 +1520,7 @@
1510 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>; 1520 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
1511 dmas = <&dmac0 0x41>, <&dmac0 0x42>; 1521 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1512 dma-names = "tx", "rx"; 1522 dma-names = "tx", "rx";
1513 power-domains = <&cpg_clocks>; 1523 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1514 #address-cells = <1>; 1524 #address-cells = <1>;
1515 #size-cells = <0>; 1525 #size-cells = <0>;
1516 status = "disabled"; 1526 status = "disabled";
@@ -1521,7 +1531,7 @@
1521 reg = <0 0xee000000 0 0xc00>; 1531 reg = <0 0xee000000 0 0xc00>;
1522 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1532 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1523 clocks = <&mstp3_clks R8A7791_CLK_SSUSB>; 1533 clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
1524 power-domains = <&cpg_clocks>; 1534 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1525 phys = <&usb2 1>; 1535 phys = <&usb2 1>;
1526 phy-names = "usb"; 1536 phy-names = "usb";
1527 status = "disabled"; 1537 status = "disabled";
@@ -1534,7 +1544,7 @@
1534 <0 0xee080000 0 0x1100>; 1544 <0 0xee080000 0 0x1100>;
1535 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1545 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1536 clocks = <&mstp7_clks R8A7791_CLK_EHCI>; 1546 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1537 power-domains = <&cpg_clocks>; 1547 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1538 status = "disabled"; 1548 status = "disabled";
1539 1549
1540 bus-range = <0 0>; 1550 bus-range = <0 0>;
@@ -1569,7 +1579,7 @@
1569 <0 0xee0c0000 0 0x1100>; 1579 <0 0xee0c0000 0 0x1100>;
1570 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1580 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1571 clocks = <&mstp7_clks R8A7791_CLK_EHCI>; 1581 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1572 power-domains = <&cpg_clocks>; 1582 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1573 status = "disabled"; 1583 status = "disabled";
1574 1584
1575 bus-range = <1 1>; 1585 bus-range = <1 1>;
@@ -1619,7 +1629,7 @@
1619 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1629 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1620 clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>; 1630 clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
1621 clock-names = "pcie", "pcie_bus"; 1631 clock-names = "pcie", "pcie_bus";
1622 power-domains = <&cpg_clocks>; 1632 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1623 status = "disabled"; 1633 status = "disabled";
1624 }; 1634 };
1625 1635
@@ -1722,7 +1732,7 @@
1722 "mix.0", "mix.1", 1732 "mix.0", "mix.1",
1723 "dvc.0", "dvc.1", 1733 "dvc.0", "dvc.1",
1724 "clk_a", "clk_b", "clk_c", "clk_i"; 1734 "clk_a", "clk_b", "clk_c", "clk_i";
1725 power-domains = <&cpg_clocks>; 1735 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
1726 1736
1727 status = "disabled"; 1737 status = "disabled";
1728 1738
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index cf6dc2aeef20..1dd6d202cd4c 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -11,6 +11,7 @@
11#include <dt-bindings/clock/r8a7793-clock.h> 11#include <dt-bindings/clock/r8a7793-clock.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/interrupt-controller/irq.h>
14#include <dt-bindings/power/r8a7793-sysc.h>
14 15
15/ { 16/ {
16 compatible = "renesas,r8a7793"; 17 compatible = "renesas,r8a7793";
@@ -43,6 +44,7 @@
43 voltage-tolerance = <1>; /* 1% */ 44 voltage-tolerance = <1>; /* 1% */
44 clocks = <&cpg_clocks R8A7793_CLK_Z>; 45 clocks = <&cpg_clocks R8A7793_CLK_Z>;
45 clock-latency = <300000>; /* 300 us */ 46 clock-latency = <300000>; /* 300 us */
47 power-domains = <&sysc R8A7793_PD_CA15_CPU0>;
46 48
47 /* kHz - uV - OPPs unknown yet */ 49 /* kHz - uV - OPPs unknown yet */
48 operating-points = <1500000 1000000>, 50 operating-points = <1500000 1000000>,
@@ -76,6 +78,7 @@
76 78
77 L2_CA15: cache-controller@0 { 79 L2_CA15: cache-controller@0 {
78 compatible = "cache"; 80 compatible = "cache";
81 power-domains = <&sysc R8A7793_PD_CA15_SCU>;
79 cache-unified; 82 cache-unified;
80 cache-level = <2>; 83 cache-level = <2>;
81 }; 84 };
@@ -102,7 +105,7 @@
102 #interrupt-cells = <2>; 105 #interrupt-cells = <2>;
103 interrupt-controller; 106 interrupt-controller;
104 clocks = <&mstp9_clks R8A7793_CLK_GPIO0>; 107 clocks = <&mstp9_clks R8A7793_CLK_GPIO0>;
105 power-domains = <&cpg_clocks>; 108 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
106 }; 109 };
107 110
108 gpio1: gpio@e6051000 { 111 gpio1: gpio@e6051000 {
@@ -115,7 +118,7 @@
115 #interrupt-cells = <2>; 118 #interrupt-cells = <2>;
116 interrupt-controller; 119 interrupt-controller;
117 clocks = <&mstp9_clks R8A7793_CLK_GPIO1>; 120 clocks = <&mstp9_clks R8A7793_CLK_GPIO1>;
118 power-domains = <&cpg_clocks>; 121 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
119 }; 122 };
120 123
121 gpio2: gpio@e6052000 { 124 gpio2: gpio@e6052000 {
@@ -128,7 +131,7 @@
128 #interrupt-cells = <2>; 131 #interrupt-cells = <2>;
129 interrupt-controller; 132 interrupt-controller;
130 clocks = <&mstp9_clks R8A7793_CLK_GPIO2>; 133 clocks = <&mstp9_clks R8A7793_CLK_GPIO2>;
131 power-domains = <&cpg_clocks>; 134 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
132 }; 135 };
133 136
134 gpio3: gpio@e6053000 { 137 gpio3: gpio@e6053000 {
@@ -141,7 +144,7 @@
141 #interrupt-cells = <2>; 144 #interrupt-cells = <2>;
142 interrupt-controller; 145 interrupt-controller;
143 clocks = <&mstp9_clks R8A7793_CLK_GPIO3>; 146 clocks = <&mstp9_clks R8A7793_CLK_GPIO3>;
144 power-domains = <&cpg_clocks>; 147 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
145 }; 148 };
146 149
147 gpio4: gpio@e6054000 { 150 gpio4: gpio@e6054000 {
@@ -154,7 +157,7 @@
154 #interrupt-cells = <2>; 157 #interrupt-cells = <2>;
155 interrupt-controller; 158 interrupt-controller;
156 clocks = <&mstp9_clks R8A7793_CLK_GPIO4>; 159 clocks = <&mstp9_clks R8A7793_CLK_GPIO4>;
157 power-domains = <&cpg_clocks>; 160 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
158 }; 161 };
159 162
160 gpio5: gpio@e6055000 { 163 gpio5: gpio@e6055000 {
@@ -167,7 +170,7 @@
167 #interrupt-cells = <2>; 170 #interrupt-cells = <2>;
168 interrupt-controller; 171 interrupt-controller;
169 clocks = <&mstp9_clks R8A7793_CLK_GPIO5>; 172 clocks = <&mstp9_clks R8A7793_CLK_GPIO5>;
170 power-domains = <&cpg_clocks>; 173 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
171 }; 174 };
172 175
173 gpio6: gpio@e6055400 { 176 gpio6: gpio@e6055400 {
@@ -180,7 +183,7 @@
180 #interrupt-cells = <2>; 183 #interrupt-cells = <2>;
181 interrupt-controller; 184 interrupt-controller;
182 clocks = <&mstp9_clks R8A7793_CLK_GPIO6>; 185 clocks = <&mstp9_clks R8A7793_CLK_GPIO6>;
183 power-domains = <&cpg_clocks>; 186 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
184 }; 187 };
185 188
186 gpio7: gpio@e6055800 { 189 gpio7: gpio@e6055800 {
@@ -193,7 +196,7 @@
193 #interrupt-cells = <2>; 196 #interrupt-cells = <2>;
194 interrupt-controller; 197 interrupt-controller;
195 clocks = <&mstp9_clks R8A7793_CLK_GPIO7>; 198 clocks = <&mstp9_clks R8A7793_CLK_GPIO7>;
196 power-domains = <&cpg_clocks>; 199 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
197 }; 200 };
198 201
199 thermal: thermal@e61f0000 { 202 thermal: thermal@e61f0000 {
@@ -203,7 +206,7 @@
203 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; 206 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
204 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 207 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&mstp5_clks R8A7793_CLK_THERMAL>; 208 clocks = <&mstp5_clks R8A7793_CLK_THERMAL>;
206 power-domains = <&cpg_clocks>; 209 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
207 #thermal-sensor-cells = <0>; 210 #thermal-sensor-cells = <0>;
208 }; 211 };
209 212
@@ -222,7 +225,7 @@
222 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 225 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&mstp1_clks R8A7793_CLK_CMT0>; 226 clocks = <&mstp1_clks R8A7793_CLK_CMT0>;
224 clock-names = "fck"; 227 clock-names = "fck";
225 power-domains = <&cpg_clocks>; 228 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
226 229
227 renesas,channels-mask = <0x60>; 230 renesas,channels-mask = <0x60>;
228 231
@@ -242,7 +245,7 @@
242 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 245 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
243 clocks = <&mstp3_clks R8A7793_CLK_CMT1>; 246 clocks = <&mstp3_clks R8A7793_CLK_CMT1>;
244 clock-names = "fck"; 247 clock-names = "fck";
245 power-domains = <&cpg_clocks>; 248 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
246 249
247 renesas,channels-mask = <0xff>; 250 renesas,channels-mask = <0xff>;
248 251
@@ -265,7 +268,7 @@
265 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 268 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 269 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&mstp4_clks R8A7793_CLK_IRQC>; 270 clocks = <&mstp4_clks R8A7793_CLK_IRQC>;
268 power-domains = <&cpg_clocks>; 271 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
269 }; 272 };
270 273
271 dmac0: dma-controller@e6700000 { 274 dmac0: dma-controller@e6700000 {
@@ -294,7 +297,7 @@
294 "ch12", "ch13", "ch14"; 297 "ch12", "ch13", "ch14";
295 clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC0>; 298 clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC0>;
296 clock-names = "fck"; 299 clock-names = "fck";
297 power-domains = <&cpg_clocks>; 300 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
298 #dma-cells = <1>; 301 #dma-cells = <1>;
299 dma-channels = <15>; 302 dma-channels = <15>;
300 }; 303 };
@@ -325,7 +328,7 @@
325 "ch12", "ch13", "ch14"; 328 "ch12", "ch13", "ch14";
326 clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC1>; 329 clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC1>;
327 clock-names = "fck"; 330 clock-names = "fck";
328 power-domains = <&cpg_clocks>; 331 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
329 #dma-cells = <1>; 332 #dma-cells = <1>;
330 dma-channels = <15>; 333 dma-channels = <15>;
331 }; 334 };
@@ -354,7 +357,7 @@
354 "ch12"; 357 "ch12";
355 clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC0>; 358 clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC0>;
356 clock-names = "fck"; 359 clock-names = "fck";
357 power-domains = <&cpg_clocks>; 360 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
358 #dma-cells = <1>; 361 #dma-cells = <1>;
359 dma-channels = <13>; 362 dma-channels = <13>;
360 }; 363 };
@@ -383,7 +386,7 @@
383 "ch12"; 386 "ch12";
384 clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC1>; 387 clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC1>;
385 clock-names = "fck"; 388 clock-names = "fck";
386 power-domains = <&cpg_clocks>; 389 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
387 #dma-cells = <1>; 390 #dma-cells = <1>;
388 dma-channels = <13>; 391 dma-channels = <13>;
389 }; 392 };
@@ -396,7 +399,7 @@
396 reg = <0 0xe6508000 0 0x40>; 399 reg = <0 0xe6508000 0 0x40>;
397 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 400 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&mstp9_clks R8A7793_CLK_I2C0>; 401 clocks = <&mstp9_clks R8A7793_CLK_I2C0>;
399 power-domains = <&cpg_clocks>; 402 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
400 i2c-scl-internal-delay-ns = <6>; 403 i2c-scl-internal-delay-ns = <6>;
401 status = "disabled"; 404 status = "disabled";
402 }; 405 };
@@ -408,7 +411,7 @@
408 reg = <0 0xe6518000 0 0x40>; 411 reg = <0 0xe6518000 0 0x40>;
409 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 412 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&mstp9_clks R8A7793_CLK_I2C1>; 413 clocks = <&mstp9_clks R8A7793_CLK_I2C1>;
411 power-domains = <&cpg_clocks>; 414 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
412 i2c-scl-internal-delay-ns = <6>; 415 i2c-scl-internal-delay-ns = <6>;
413 status = "disabled"; 416 status = "disabled";
414 }; 417 };
@@ -420,7 +423,7 @@
420 reg = <0 0xe6530000 0 0x40>; 423 reg = <0 0xe6530000 0 0x40>;
421 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 424 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&mstp9_clks R8A7793_CLK_I2C2>; 425 clocks = <&mstp9_clks R8A7793_CLK_I2C2>;
423 power-domains = <&cpg_clocks>; 426 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
424 i2c-scl-internal-delay-ns = <6>; 427 i2c-scl-internal-delay-ns = <6>;
425 status = "disabled"; 428 status = "disabled";
426 }; 429 };
@@ -432,7 +435,7 @@
432 reg = <0 0xe6540000 0 0x40>; 435 reg = <0 0xe6540000 0 0x40>;
433 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 436 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
434 clocks = <&mstp9_clks R8A7793_CLK_I2C3>; 437 clocks = <&mstp9_clks R8A7793_CLK_I2C3>;
435 power-domains = <&cpg_clocks>; 438 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
436 i2c-scl-internal-delay-ns = <6>; 439 i2c-scl-internal-delay-ns = <6>;
437 status = "disabled"; 440 status = "disabled";
438 }; 441 };
@@ -444,7 +447,7 @@
444 reg = <0 0xe6520000 0 0x40>; 447 reg = <0 0xe6520000 0 0x40>;
445 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 448 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&mstp9_clks R8A7793_CLK_I2C4>; 449 clocks = <&mstp9_clks R8A7793_CLK_I2C4>;
447 power-domains = <&cpg_clocks>; 450 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
448 i2c-scl-internal-delay-ns = <6>; 451 i2c-scl-internal-delay-ns = <6>;
449 status = "disabled"; 452 status = "disabled";
450 }; 453 };
@@ -457,7 +460,7 @@
457 reg = <0 0xe6528000 0 0x40>; 460 reg = <0 0xe6528000 0 0x40>;
458 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 461 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
459 clocks = <&mstp9_clks R8A7793_CLK_I2C5>; 462 clocks = <&mstp9_clks R8A7793_CLK_I2C5>;
460 power-domains = <&cpg_clocks>; 463 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
461 i2c-scl-internal-delay-ns = <110>; 464 i2c-scl-internal-delay-ns = <110>;
462 status = "disabled"; 465 status = "disabled";
463 }; 466 };
@@ -472,7 +475,7 @@
472 clocks = <&mstp9_clks R8A7793_CLK_IICDVFS>; 475 clocks = <&mstp9_clks R8A7793_CLK_IICDVFS>;
473 dmas = <&dmac0 0x77>, <&dmac0 0x78>; 476 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
474 dma-names = "tx", "rx"; 477 dma-names = "tx", "rx";
475 power-domains = <&cpg_clocks>; 478 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
476 status = "disabled"; 479 status = "disabled";
477 }; 480 };
478 481
@@ -485,7 +488,7 @@
485 clocks = <&mstp3_clks R8A7793_CLK_IIC0>; 488 clocks = <&mstp3_clks R8A7793_CLK_IIC0>;
486 dmas = <&dmac0 0x61>, <&dmac0 0x62>; 489 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
487 dma-names = "tx", "rx"; 490 dma-names = "tx", "rx";
488 power-domains = <&cpg_clocks>; 491 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
489 status = "disabled"; 492 status = "disabled";
490 }; 493 };
491 494
@@ -498,7 +501,7 @@
498 clocks = <&mstp3_clks R8A7793_CLK_IIC1>; 501 clocks = <&mstp3_clks R8A7793_CLK_IIC1>;
499 dmas = <&dmac0 0x65>, <&dmac0 0x66>; 502 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
500 dma-names = "tx", "rx"; 503 dma-names = "tx", "rx";
501 power-domains = <&cpg_clocks>; 504 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
502 status = "disabled"; 505 status = "disabled";
503 }; 506 };
504 507
@@ -514,7 +517,7 @@
514 clocks = <&mstp3_clks R8A7793_CLK_SDHI0>; 517 clocks = <&mstp3_clks R8A7793_CLK_SDHI0>;
515 dmas = <&dmac0 0xcd>, <&dmac0 0xce>; 518 dmas = <&dmac0 0xcd>, <&dmac0 0xce>;
516 dma-names = "tx", "rx"; 519 dma-names = "tx", "rx";
517 power-domains = <&cpg_clocks>; 520 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
518 status = "disabled"; 521 status = "disabled";
519 }; 522 };
520 523
@@ -525,7 +528,7 @@
525 clocks = <&mstp3_clks R8A7793_CLK_SDHI1>; 528 clocks = <&mstp3_clks R8A7793_CLK_SDHI1>;
526 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>; 529 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>;
527 dma-names = "tx", "rx"; 530 dma-names = "tx", "rx";
528 power-domains = <&cpg_clocks>; 531 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
529 status = "disabled"; 532 status = "disabled";
530 }; 533 };
531 534
@@ -536,7 +539,7 @@
536 clocks = <&mstp3_clks R8A7793_CLK_SDHI2>; 539 clocks = <&mstp3_clks R8A7793_CLK_SDHI2>;
537 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>; 540 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>;
538 dma-names = "tx", "rx"; 541 dma-names = "tx", "rx";
539 power-domains = <&cpg_clocks>; 542 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
540 status = "disabled"; 543 status = "disabled";
541 }; 544 };
542 545
@@ -549,7 +552,7 @@
549 clock-names = "fck"; 552 clock-names = "fck";
550 dmas = <&dmac0 0x21>, <&dmac0 0x22>; 553 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
551 dma-names = "tx", "rx"; 554 dma-names = "tx", "rx";
552 power-domains = <&cpg_clocks>; 555 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
553 status = "disabled"; 556 status = "disabled";
554 }; 557 };
555 558
@@ -562,7 +565,7 @@
562 clock-names = "fck"; 565 clock-names = "fck";
563 dmas = <&dmac0 0x25>, <&dmac0 0x26>; 566 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
564 dma-names = "tx", "rx"; 567 dma-names = "tx", "rx";
565 power-domains = <&cpg_clocks>; 568 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
566 status = "disabled"; 569 status = "disabled";
567 }; 570 };
568 571
@@ -575,7 +578,7 @@
575 clock-names = "fck"; 578 clock-names = "fck";
576 dmas = <&dmac0 0x27>, <&dmac0 0x28>; 579 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
577 dma-names = "tx", "rx"; 580 dma-names = "tx", "rx";
578 power-domains = <&cpg_clocks>; 581 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
579 status = "disabled"; 582 status = "disabled";
580 }; 583 };
581 584
@@ -588,7 +591,7 @@
588 clock-names = "fck"; 591 clock-names = "fck";
589 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>; 592 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
590 dma-names = "tx", "rx"; 593 dma-names = "tx", "rx";
591 power-domains = <&cpg_clocks>; 594 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
592 status = "disabled"; 595 status = "disabled";
593 }; 596 };
594 597
@@ -601,7 +604,7 @@
601 clock-names = "fck"; 604 clock-names = "fck";
602 dmas = <&dmac0 0x1f>, <&dmac0 0x20>; 605 dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
603 dma-names = "tx", "rx"; 606 dma-names = "tx", "rx";
604 power-domains = <&cpg_clocks>; 607 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
605 status = "disabled"; 608 status = "disabled";
606 }; 609 };
607 610
@@ -614,7 +617,7 @@
614 clock-names = "fck"; 617 clock-names = "fck";
615 dmas = <&dmac0 0x23>, <&dmac0 0x24>; 618 dmas = <&dmac0 0x23>, <&dmac0 0x24>;
616 dma-names = "tx", "rx"; 619 dma-names = "tx", "rx";
617 power-domains = <&cpg_clocks>; 620 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
618 status = "disabled"; 621 status = "disabled";
619 }; 622 };
620 623
@@ -627,7 +630,7 @@
627 clock-names = "fck"; 630 clock-names = "fck";
628 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>; 631 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
629 dma-names = "tx", "rx"; 632 dma-names = "tx", "rx";
630 power-domains = <&cpg_clocks>; 633 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
631 status = "disabled"; 634 status = "disabled";
632 }; 635 };
633 636
@@ -640,7 +643,7 @@
640 clock-names = "fck"; 643 clock-names = "fck";
641 dmas = <&dmac0 0x19>, <&dmac0 0x1a>; 644 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
642 dma-names = "tx", "rx"; 645 dma-names = "tx", "rx";
643 power-domains = <&cpg_clocks>; 646 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
644 status = "disabled"; 647 status = "disabled";
645 }; 648 };
646 649
@@ -653,7 +656,7 @@
653 clock-names = "fck"; 656 clock-names = "fck";
654 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>; 657 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
655 dma-names = "tx", "rx"; 658 dma-names = "tx", "rx";
656 power-domains = <&cpg_clocks>; 659 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
657 status = "disabled"; 660 status = "disabled";
658 }; 661 };
659 662
@@ -667,7 +670,7 @@
667 clock-names = "fck", "brg_int", "scif_clk"; 670 clock-names = "fck", "brg_int", "scif_clk";
668 dmas = <&dmac0 0x29>, <&dmac0 0x2a>; 671 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
669 dma-names = "tx", "rx"; 672 dma-names = "tx", "rx";
670 power-domains = <&cpg_clocks>; 673 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
671 status = "disabled"; 674 status = "disabled";
672 }; 675 };
673 676
@@ -681,7 +684,7 @@
681 clock-names = "fck", "brg_int", "scif_clk"; 684 clock-names = "fck", "brg_int", "scif_clk";
682 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>; 685 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
683 dma-names = "tx", "rx"; 686 dma-names = "tx", "rx";
684 power-domains = <&cpg_clocks>; 687 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
685 status = "disabled"; 688 status = "disabled";
686 }; 689 };
687 690
@@ -695,7 +698,7 @@
695 clock-names = "fck", "brg_int", "scif_clk"; 698 clock-names = "fck", "brg_int", "scif_clk";
696 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>; 699 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
697 dma-names = "tx", "rx"; 700 dma-names = "tx", "rx";
698 power-domains = <&cpg_clocks>; 701 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
699 status = "disabled"; 702 status = "disabled";
700 }; 703 };
701 704
@@ -709,7 +712,7 @@
709 clock-names = "fck", "brg_int", "scif_clk"; 712 clock-names = "fck", "brg_int", "scif_clk";
710 dmas = <&dmac0 0x2f>, <&dmac0 0x30>; 713 dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
711 dma-names = "tx", "rx"; 714 dma-names = "tx", "rx";
712 power-domains = <&cpg_clocks>; 715 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
713 status = "disabled"; 716 status = "disabled";
714 }; 717 };
715 718
@@ -723,7 +726,7 @@
723 clock-names = "fck", "brg_int", "scif_clk"; 726 clock-names = "fck", "brg_int", "scif_clk";
724 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>; 727 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
725 dma-names = "tx", "rx"; 728 dma-names = "tx", "rx";
726 power-domains = <&cpg_clocks>; 729 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
727 status = "disabled"; 730 status = "disabled";
728 }; 731 };
729 732
@@ -737,7 +740,7 @@
737 clock-names = "fck", "brg_int", "scif_clk"; 740 clock-names = "fck", "brg_int", "scif_clk";
738 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>; 741 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
739 dma-names = "tx", "rx"; 742 dma-names = "tx", "rx";
740 power-domains = <&cpg_clocks>; 743 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
741 status = "disabled"; 744 status = "disabled";
742 }; 745 };
743 746
@@ -751,7 +754,7 @@
751 clock-names = "fck", "brg_int", "scif_clk"; 754 clock-names = "fck", "brg_int", "scif_clk";
752 dmas = <&dmac0 0x39>, <&dmac0 0x3a>; 755 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
753 dma-names = "tx", "rx"; 756 dma-names = "tx", "rx";
754 power-domains = <&cpg_clocks>; 757 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
755 status = "disabled"; 758 status = "disabled";
756 }; 759 };
757 760
@@ -765,7 +768,7 @@
765 clock-names = "fck", "brg_int", "scif_clk"; 768 clock-names = "fck", "brg_int", "scif_clk";
766 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>; 769 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
767 dma-names = "tx", "rx"; 770 dma-names = "tx", "rx";
768 power-domains = <&cpg_clocks>; 771 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
769 status = "disabled"; 772 status = "disabled";
770 }; 773 };
771 774
@@ -779,7 +782,7 @@
779 clock-names = "fck", "brg_int", "scif_clk"; 782 clock-names = "fck", "brg_int", "scif_clk";
780 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>; 783 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
781 dma-names = "tx", "rx"; 784 dma-names = "tx", "rx";
782 power-domains = <&cpg_clocks>; 785 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
783 status = "disabled"; 786 status = "disabled";
784 }; 787 };
785 788
@@ -788,7 +791,7 @@
788 reg = <0 0xee700000 0 0x400>; 791 reg = <0 0xee700000 0 0x400>;
789 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 792 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
790 clocks = <&mstp8_clks R8A7793_CLK_ETHER>; 793 clocks = <&mstp8_clks R8A7793_CLK_ETHER>;
791 power-domains = <&cpg_clocks>; 794 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
792 phy-mode = "rmii"; 795 phy-mode = "rmii";
793 #address-cells = <1>; 796 #address-cells = <1>;
794 #size-cells = <0>; 797 #size-cells = <0>;
@@ -802,7 +805,7 @@
802 clocks = <&mstp9_clks R8A7793_CLK_QSPI_MOD>; 805 clocks = <&mstp9_clks R8A7793_CLK_QSPI_MOD>;
803 dmas = <&dmac0 0x17>, <&dmac0 0x18>; 806 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
804 dma-names = "tx", "rx"; 807 dma-names = "tx", "rx";
805 power-domains = <&cpg_clocks>; 808 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
806 num-cs = <1>; 809 num-cs = <1>;
807 #address-cells = <1>; 810 #address-cells = <1>;
808 #size-cells = <0>; 811 #size-cells = <0>;
@@ -846,7 +849,7 @@
846 clocks = <&mstp9_clks R8A7793_CLK_RCAN0>, 849 clocks = <&mstp9_clks R8A7793_CLK_RCAN0>,
847 <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>; 850 <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>;
848 clock-names = "clkp1", "clkp2", "can_clk"; 851 clock-names = "clkp1", "clkp2", "can_clk";
849 power-domains = <&cpg_clocks>; 852 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
850 status = "disabled"; 853 status = "disabled";
851 }; 854 };
852 855
@@ -857,7 +860,7 @@
857 clocks = <&mstp9_clks R8A7793_CLK_RCAN1>, 860 clocks = <&mstp9_clks R8A7793_CLK_RCAN1>,
858 <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>; 861 <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>;
859 clock-names = "clkp1", "clkp2", "can_clk"; 862 clock-names = "clkp1", "clkp2", "can_clk";
860 power-domains = <&cpg_clocks>; 863 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
861 status = "disabled"; 864 status = "disabled";
862 }; 865 };
863 866
@@ -1221,6 +1224,12 @@
1221 }; 1224 };
1222 }; 1225 };
1223 1226
1227 sysc: system-controller@e6180000 {
1228 compatible = "renesas,r8a7793-sysc";
1229 reg = <0 0xe6180000 0 0x0200>;
1230 #power-domain-cells = <1>;
1231 };
1232
1224 ipmmu_sy0: mmu@e6280000 { 1233 ipmmu_sy0: mmu@e6280000 {
1225 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; 1234 compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa";
1226 reg = <0 0xe6280000 0 0x1000>; 1235 reg = <0 0xe6280000 0 0x1000>;
@@ -1316,7 +1325,7 @@
1316 "src.4", "src.3", "src.2", "src.1", "src.0", 1325 "src.4", "src.3", "src.2", "src.1", "src.0",
1317 "dvc.0", "dvc.1", 1326 "dvc.0", "dvc.1",
1318 "clk_a", "clk_b", "clk_c", "clk_i"; 1327 "clk_a", "clk_b", "clk_c", "clk_i";
1319 power-domains = <&cpg_clocks>; 1328 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
1320 1329
1321 status = "disabled"; 1330 status = "disabled";
1322 1331
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index e45b23f31149..f334a3a715f2 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -12,6 +12,7 @@
12#include <dt-bindings/clock/r8a7794-clock.h> 12#include <dt-bindings/clock/r8a7794-clock.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/power/r8a7794-sysc.h>
15 16
16/ { 17/ {
17 compatible = "renesas,r8a7794"; 18 compatible = "renesas,r8a7794";
@@ -42,6 +43,7 @@
42 compatible = "arm,cortex-a7"; 43 compatible = "arm,cortex-a7";
43 reg = <0>; 44 reg = <0>;
44 clock-frequency = <1000000000>; 45 clock-frequency = <1000000000>;
46 power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
45 next-level-cache = <&L2_CA7>; 47 next-level-cache = <&L2_CA7>;
46 }; 48 };
47 49
@@ -50,12 +52,14 @@
50 compatible = "arm,cortex-a7"; 52 compatible = "arm,cortex-a7";
51 reg = <1>; 53 reg = <1>;
52 clock-frequency = <1000000000>; 54 clock-frequency = <1000000000>;
55 power-domains = <&sysc R8A7794_PD_CA7_CPU1>;
53 next-level-cache = <&L2_CA7>; 56 next-level-cache = <&L2_CA7>;
54 }; 57 };
55 }; 58 };
56 59
57 L2_CA7: cache-controller@1 { 60 L2_CA7: cache-controller@1 {
58 compatible = "cache"; 61 compatible = "cache";
62 power-domains = <&sysc R8A7794_PD_CA7_SCU>;
59 cache-unified; 63 cache-unified;
60 cache-level = <2>; 64 cache-level = <2>;
61 }; 65 };
@@ -82,7 +86,7 @@
82 #interrupt-cells = <2>; 86 #interrupt-cells = <2>;
83 interrupt-controller; 87 interrupt-controller;
84 clocks = <&mstp9_clks R8A7794_CLK_GPIO0>; 88 clocks = <&mstp9_clks R8A7794_CLK_GPIO0>;
85 power-domains = <&cpg_clocks>; 89 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
86 }; 90 };
87 91
88 gpio1: gpio@e6051000 { 92 gpio1: gpio@e6051000 {
@@ -95,7 +99,7 @@
95 #interrupt-cells = <2>; 99 #interrupt-cells = <2>;
96 interrupt-controller; 100 interrupt-controller;
97 clocks = <&mstp9_clks R8A7794_CLK_GPIO1>; 101 clocks = <&mstp9_clks R8A7794_CLK_GPIO1>;
98 power-domains = <&cpg_clocks>; 102 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
99 }; 103 };
100 104
101 gpio2: gpio@e6052000 { 105 gpio2: gpio@e6052000 {
@@ -108,7 +112,7 @@
108 #interrupt-cells = <2>; 112 #interrupt-cells = <2>;
109 interrupt-controller; 113 interrupt-controller;
110 clocks = <&mstp9_clks R8A7794_CLK_GPIO2>; 114 clocks = <&mstp9_clks R8A7794_CLK_GPIO2>;
111 power-domains = <&cpg_clocks>; 115 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
112 }; 116 };
113 117
114 gpio3: gpio@e6053000 { 118 gpio3: gpio@e6053000 {
@@ -121,7 +125,7 @@
121 #interrupt-cells = <2>; 125 #interrupt-cells = <2>;
122 interrupt-controller; 126 interrupt-controller;
123 clocks = <&mstp9_clks R8A7794_CLK_GPIO3>; 127 clocks = <&mstp9_clks R8A7794_CLK_GPIO3>;
124 power-domains = <&cpg_clocks>; 128 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
125 }; 129 };
126 130
127 gpio4: gpio@e6054000 { 131 gpio4: gpio@e6054000 {
@@ -134,7 +138,7 @@
134 #interrupt-cells = <2>; 138 #interrupt-cells = <2>;
135 interrupt-controller; 139 interrupt-controller;
136 clocks = <&mstp9_clks R8A7794_CLK_GPIO4>; 140 clocks = <&mstp9_clks R8A7794_CLK_GPIO4>;
137 power-domains = <&cpg_clocks>; 141 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
138 }; 142 };
139 143
140 gpio5: gpio@e6055000 { 144 gpio5: gpio@e6055000 {
@@ -147,7 +151,7 @@
147 #interrupt-cells = <2>; 151 #interrupt-cells = <2>;
148 interrupt-controller; 152 interrupt-controller;
149 clocks = <&mstp9_clks R8A7794_CLK_GPIO5>; 153 clocks = <&mstp9_clks R8A7794_CLK_GPIO5>;
150 power-domains = <&cpg_clocks>; 154 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
151 }; 155 };
152 156
153 gpio6: gpio@e6055400 { 157 gpio6: gpio@e6055400 {
@@ -160,7 +164,7 @@
160 #interrupt-cells = <2>; 164 #interrupt-cells = <2>;
161 interrupt-controller; 165 interrupt-controller;
162 clocks = <&mstp9_clks R8A7794_CLK_GPIO6>; 166 clocks = <&mstp9_clks R8A7794_CLK_GPIO6>;
163 power-domains = <&cpg_clocks>; 167 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
164 }; 168 };
165 169
166 cmt0: timer@ffca0000 { 170 cmt0: timer@ffca0000 {
@@ -170,7 +174,7 @@
170 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 174 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
171 clocks = <&mstp1_clks R8A7794_CLK_CMT0>; 175 clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
172 clock-names = "fck"; 176 clock-names = "fck";
173 power-domains = <&cpg_clocks>; 177 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
174 178
175 renesas,channels-mask = <0x60>; 179 renesas,channels-mask = <0x60>;
176 180
@@ -190,7 +194,7 @@
190 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 194 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
191 clocks = <&mstp3_clks R8A7794_CLK_CMT1>; 195 clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
192 clock-names = "fck"; 196 clock-names = "fck";
193 power-domains = <&cpg_clocks>; 197 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
194 198
195 renesas,channels-mask = <0xff>; 199 renesas,channels-mask = <0xff>;
196 200
@@ -221,7 +225,7 @@
221 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 226 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&mstp4_clks R8A7794_CLK_IRQC>; 227 clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
224 power-domains = <&cpg_clocks>; 228 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
225 }; 229 };
226 230
227 pfc: pin-controller@e6060000 { 231 pfc: pin-controller@e6060000 {
@@ -255,7 +259,7 @@
255 "ch12", "ch13", "ch14"; 259 "ch12", "ch13", "ch14";
256 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>; 260 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
257 clock-names = "fck"; 261 clock-names = "fck";
258 power-domains = <&cpg_clocks>; 262 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
259 #dma-cells = <1>; 263 #dma-cells = <1>;
260 dma-channels = <15>; 264 dma-channels = <15>;
261 }; 265 };
@@ -286,7 +290,7 @@
286 "ch12", "ch13", "ch14"; 290 "ch12", "ch13", "ch14";
287 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>; 291 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
288 clock-names = "fck"; 292 clock-names = "fck";
289 power-domains = <&cpg_clocks>; 293 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
290 #dma-cells = <1>; 294 #dma-cells = <1>;
291 dma-channels = <15>; 295 dma-channels = <15>;
292 }; 296 };
@@ -300,7 +304,7 @@
300 clock-names = "fck"; 304 clock-names = "fck";
301 dmas = <&dmac0 0x21>, <&dmac0 0x22>; 305 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
302 dma-names = "tx", "rx"; 306 dma-names = "tx", "rx";
303 power-domains = <&cpg_clocks>; 307 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
304 status = "disabled"; 308 status = "disabled";
305 }; 309 };
306 310
@@ -313,7 +317,7 @@
313 clock-names = "fck"; 317 clock-names = "fck";
314 dmas = <&dmac0 0x25>, <&dmac0 0x26>; 318 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
315 dma-names = "tx", "rx"; 319 dma-names = "tx", "rx";
316 power-domains = <&cpg_clocks>; 320 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
317 status = "disabled"; 321 status = "disabled";
318 }; 322 };
319 323
@@ -326,7 +330,7 @@
326 clock-names = "fck"; 330 clock-names = "fck";
327 dmas = <&dmac0 0x27>, <&dmac0 0x28>; 331 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
328 dma-names = "tx", "rx"; 332 dma-names = "tx", "rx";
329 power-domains = <&cpg_clocks>; 333 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
330 status = "disabled"; 334 status = "disabled";
331 }; 335 };
332 336
@@ -339,7 +343,7 @@
339 clock-names = "fck"; 343 clock-names = "fck";
340 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>; 344 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
341 dma-names = "tx", "rx"; 345 dma-names = "tx", "rx";
342 power-domains = <&cpg_clocks>; 346 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
343 status = "disabled"; 347 status = "disabled";
344 }; 348 };
345 349
@@ -352,7 +356,7 @@
352 clock-names = "fck"; 356 clock-names = "fck";
353 dmas = <&dmac0 0x1f>, <&dmac0 0x20>; 357 dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
354 dma-names = "tx", "rx"; 358 dma-names = "tx", "rx";
355 power-domains = <&cpg_clocks>; 359 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
356 status = "disabled"; 360 status = "disabled";
357 }; 361 };
358 362
@@ -365,7 +369,7 @@
365 clock-names = "fck"; 369 clock-names = "fck";
366 dmas = <&dmac0 0x23>, <&dmac0 0x24>; 370 dmas = <&dmac0 0x23>, <&dmac0 0x24>;
367 dma-names = "tx", "rx"; 371 dma-names = "tx", "rx";
368 power-domains = <&cpg_clocks>; 372 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
369 status = "disabled"; 373 status = "disabled";
370 }; 374 };
371 375
@@ -378,7 +382,7 @@
378 clock-names = "fck"; 382 clock-names = "fck";
379 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>; 383 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
380 dma-names = "tx", "rx"; 384 dma-names = "tx", "rx";
381 power-domains = <&cpg_clocks>; 385 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
382 status = "disabled"; 386 status = "disabled";
383 }; 387 };
384 388
@@ -391,7 +395,7 @@
391 clock-names = "fck"; 395 clock-names = "fck";
392 dmas = <&dmac0 0x19>, <&dmac0 0x1a>; 396 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
393 dma-names = "tx", "rx"; 397 dma-names = "tx", "rx";
394 power-domains = <&cpg_clocks>; 398 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
395 status = "disabled"; 399 status = "disabled";
396 }; 400 };
397 401
@@ -404,7 +408,7 @@
404 clock-names = "fck"; 408 clock-names = "fck";
405 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>; 409 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
406 dma-names = "tx", "rx"; 410 dma-names = "tx", "rx";
407 power-domains = <&cpg_clocks>; 411 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
408 status = "disabled"; 412 status = "disabled";
409 }; 413 };
410 414
@@ -418,7 +422,7 @@
418 clock-names = "fck", "brg_int", "scif_clk"; 422 clock-names = "fck", "brg_int", "scif_clk";
419 dmas = <&dmac0 0x29>, <&dmac0 0x2a>; 423 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
420 dma-names = "tx", "rx"; 424 dma-names = "tx", "rx";
421 power-domains = <&cpg_clocks>; 425 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
422 status = "disabled"; 426 status = "disabled";
423 }; 427 };
424 428
@@ -432,7 +436,7 @@
432 clock-names = "fck", "brg_int", "scif_clk"; 436 clock-names = "fck", "brg_int", "scif_clk";
433 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>; 437 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
434 dma-names = "tx", "rx"; 438 dma-names = "tx", "rx";
435 power-domains = <&cpg_clocks>; 439 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
436 status = "disabled"; 440 status = "disabled";
437 }; 441 };
438 442
@@ -446,7 +450,7 @@
446 clock-names = "fck", "brg_int", "scif_clk"; 450 clock-names = "fck", "brg_int", "scif_clk";
447 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>; 451 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
448 dma-names = "tx", "rx"; 452 dma-names = "tx", "rx";
449 power-domains = <&cpg_clocks>; 453 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
450 status = "disabled"; 454 status = "disabled";
451 }; 455 };
452 456
@@ -460,7 +464,7 @@
460 clock-names = "fck", "brg_int", "scif_clk"; 464 clock-names = "fck", "brg_int", "scif_clk";
461 dmas = <&dmac0 0x2f>, <&dmac0 0x30>; 465 dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
462 dma-names = "tx", "rx"; 466 dma-names = "tx", "rx";
463 power-domains = <&cpg_clocks>; 467 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
464 status = "disabled"; 468 status = "disabled";
465 }; 469 };
466 470
@@ -474,7 +478,7 @@
474 clock-names = "fck", "brg_int", "scif_clk"; 478 clock-names = "fck", "brg_int", "scif_clk";
475 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>; 479 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
476 dma-names = "tx", "rx"; 480 dma-names = "tx", "rx";
477 power-domains = <&cpg_clocks>; 481 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
478 status = "disabled"; 482 status = "disabled";
479 }; 483 };
480 484
@@ -488,7 +492,7 @@
488 clock-names = "fck", "brg_int", "scif_clk"; 492 clock-names = "fck", "brg_int", "scif_clk";
489 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>; 493 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
490 dma-names = "tx", "rx"; 494 dma-names = "tx", "rx";
491 power-domains = <&cpg_clocks>; 495 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
492 status = "disabled"; 496 status = "disabled";
493 }; 497 };
494 498
@@ -502,7 +506,7 @@
502 clock-names = "fck", "brg_int", "scif_clk"; 506 clock-names = "fck", "brg_int", "scif_clk";
503 dmas = <&dmac0 0x39>, <&dmac0 0x3a>; 507 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
504 dma-names = "tx", "rx"; 508 dma-names = "tx", "rx";
505 power-domains = <&cpg_clocks>; 509 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
506 status = "disabled"; 510 status = "disabled";
507 }; 511 };
508 512
@@ -516,7 +520,7 @@
516 clock-names = "fck", "brg_int", "scif_clk"; 520 clock-names = "fck", "brg_int", "scif_clk";
517 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>; 521 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
518 dma-names = "tx", "rx"; 522 dma-names = "tx", "rx";
519 power-domains = <&cpg_clocks>; 523 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
520 status = "disabled"; 524 status = "disabled";
521 }; 525 };
522 526
@@ -530,7 +534,7 @@
530 clock-names = "fck", "brg_int", "scif_clk"; 534 clock-names = "fck", "brg_int", "scif_clk";
531 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>; 535 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
532 dma-names = "tx", "rx"; 536 dma-names = "tx", "rx";
533 power-domains = <&cpg_clocks>; 537 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
534 status = "disabled"; 538 status = "disabled";
535 }; 539 };
536 540
@@ -539,7 +543,7 @@
539 reg = <0 0xee700000 0 0x400>; 543 reg = <0 0xee700000 0 0x400>;
540 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 544 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
541 clocks = <&mstp8_clks R8A7794_CLK_ETHER>; 545 clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
542 power-domains = <&cpg_clocks>; 546 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
543 phy-mode = "rmii"; 547 phy-mode = "rmii";
544 #address-cells = <1>; 548 #address-cells = <1>;
545 #size-cells = <0>; 549 #size-cells = <0>;
@@ -552,7 +556,7 @@
552 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; 556 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
553 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 557 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
554 clocks = <&mstp8_clks R8A7794_CLK_ETHERAVB>; 558 clocks = <&mstp8_clks R8A7794_CLK_ETHERAVB>;
555 power-domains = <&cpg_clocks>; 559 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
556 #address-cells = <1>; 560 #address-cells = <1>;
557 #size-cells = <0>; 561 #size-cells = <0>;
558 status = "disabled"; 562 status = "disabled";
@@ -564,7 +568,7 @@
564 reg = <0 0xe6508000 0 0x40>; 568 reg = <0 0xe6508000 0 0x40>;
565 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 569 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&mstp9_clks R8A7794_CLK_I2C0>; 570 clocks = <&mstp9_clks R8A7794_CLK_I2C0>;
567 power-domains = <&cpg_clocks>; 571 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
568 #address-cells = <1>; 572 #address-cells = <1>;
569 #size-cells = <0>; 573 #size-cells = <0>;
570 i2c-scl-internal-delay-ns = <6>; 574 i2c-scl-internal-delay-ns = <6>;
@@ -576,7 +580,7 @@
576 reg = <0 0xe6518000 0 0x40>; 580 reg = <0 0xe6518000 0 0x40>;
577 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 581 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&mstp9_clks R8A7794_CLK_I2C1>; 582 clocks = <&mstp9_clks R8A7794_CLK_I2C1>;
579 power-domains = <&cpg_clocks>; 583 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
580 #address-cells = <1>; 584 #address-cells = <1>;
581 #size-cells = <0>; 585 #size-cells = <0>;
582 i2c-scl-internal-delay-ns = <6>; 586 i2c-scl-internal-delay-ns = <6>;
@@ -588,7 +592,7 @@
588 reg = <0 0xe6530000 0 0x40>; 592 reg = <0 0xe6530000 0 0x40>;
589 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 593 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&mstp9_clks R8A7794_CLK_I2C2>; 594 clocks = <&mstp9_clks R8A7794_CLK_I2C2>;
591 power-domains = <&cpg_clocks>; 595 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
592 #address-cells = <1>; 596 #address-cells = <1>;
593 #size-cells = <0>; 597 #size-cells = <0>;
594 i2c-scl-internal-delay-ns = <6>; 598 i2c-scl-internal-delay-ns = <6>;
@@ -600,7 +604,7 @@
600 reg = <0 0xe6540000 0 0x40>; 604 reg = <0 0xe6540000 0 0x40>;
601 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 605 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&mstp9_clks R8A7794_CLK_I2C3>; 606 clocks = <&mstp9_clks R8A7794_CLK_I2C3>;
603 power-domains = <&cpg_clocks>; 607 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
604 #address-cells = <1>; 608 #address-cells = <1>;
605 #size-cells = <0>; 609 #size-cells = <0>;
606 i2c-scl-internal-delay-ns = <6>; 610 i2c-scl-internal-delay-ns = <6>;
@@ -612,7 +616,7 @@
612 reg = <0 0xe6520000 0 0x40>; 616 reg = <0 0xe6520000 0 0x40>;
613 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 617 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
614 clocks = <&mstp9_clks R8A7794_CLK_I2C4>; 618 clocks = <&mstp9_clks R8A7794_CLK_I2C4>;
615 power-domains = <&cpg_clocks>; 619 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
616 #address-cells = <1>; 620 #address-cells = <1>;
617 #size-cells = <0>; 621 #size-cells = <0>;
618 i2c-scl-internal-delay-ns = <6>; 622 i2c-scl-internal-delay-ns = <6>;
@@ -624,7 +628,7 @@
624 reg = <0 0xe6528000 0 0x40>; 628 reg = <0 0xe6528000 0 0x40>;
625 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 629 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
626 clocks = <&mstp9_clks R8A7794_CLK_I2C5>; 630 clocks = <&mstp9_clks R8A7794_CLK_I2C5>;
627 power-domains = <&cpg_clocks>; 631 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
628 #address-cells = <1>; 632 #address-cells = <1>;
629 #size-cells = <0>; 633 #size-cells = <0>;
630 i2c-scl-internal-delay-ns = <6>; 634 i2c-scl-internal-delay-ns = <6>;
@@ -638,7 +642,7 @@
638 clocks = <&mstp3_clks R8A7794_CLK_IIC0>; 642 clocks = <&mstp3_clks R8A7794_CLK_IIC0>;
639 dmas = <&dmac0 0x61>, <&dmac0 0x62>; 643 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
640 dma-names = "tx", "rx"; 644 dma-names = "tx", "rx";
641 power-domains = <&cpg_clocks>; 645 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
642 #address-cells = <1>; 646 #address-cells = <1>;
643 #size-cells = <0>; 647 #size-cells = <0>;
644 status = "disabled"; 648 status = "disabled";
@@ -651,7 +655,7 @@
651 clocks = <&mstp3_clks R8A7794_CLK_IIC1>; 655 clocks = <&mstp3_clks R8A7794_CLK_IIC1>;
652 dmas = <&dmac0 0x65>, <&dmac0 0x66>; 656 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
653 dma-names = "tx", "rx"; 657 dma-names = "tx", "rx";
654 power-domains = <&cpg_clocks>; 658 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
655 #address-cells = <1>; 659 #address-cells = <1>;
656 #size-cells = <0>; 660 #size-cells = <0>;
657 status = "disabled"; 661 status = "disabled";
@@ -664,7 +668,7 @@
664 clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>; 668 clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>;
665 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; 669 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
666 dma-names = "tx", "rx"; 670 dma-names = "tx", "rx";
667 power-domains = <&cpg_clocks>; 671 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
668 reg-io-width = <4>; 672 reg-io-width = <4>;
669 status = "disabled"; 673 status = "disabled";
670 }; 674 };
@@ -674,7 +678,7 @@
674 reg = <0 0xee100000 0 0x200>; 678 reg = <0 0xee100000 0 0x200>;
675 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 679 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
676 clocks = <&mstp3_clks R8A7794_CLK_SDHI0>; 680 clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
677 power-domains = <&cpg_clocks>; 681 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
678 status = "disabled"; 682 status = "disabled";
679 }; 683 };
680 684
@@ -683,7 +687,7 @@
683 reg = <0 0xee140000 0 0x100>; 687 reg = <0 0xee140000 0 0x100>;
684 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 688 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
685 clocks = <&mstp3_clks R8A7794_CLK_SDHI1>; 689 clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
686 power-domains = <&cpg_clocks>; 690 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
687 status = "disabled"; 691 status = "disabled";
688 }; 692 };
689 693
@@ -692,7 +696,7 @@
692 reg = <0 0xee160000 0 0x100>; 696 reg = <0 0xee160000 0 0x100>;
693 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 697 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
694 clocks = <&mstp3_clks R8A7794_CLK_SDHI2>; 698 clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
695 power-domains = <&cpg_clocks>; 699 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
696 status = "disabled"; 700 status = "disabled";
697 }; 701 };
698 702
@@ -703,7 +707,7 @@
703 clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>; 707 clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>;
704 dmas = <&dmac0 0x17>, <&dmac0 0x18>; 708 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
705 dma-names = "tx", "rx"; 709 dma-names = "tx", "rx";
706 power-domains = <&cpg_clocks>; 710 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
707 num-cs = <1>; 711 num-cs = <1>;
708 #address-cells = <1>; 712 #address-cells = <1>;
709 #size-cells = <0>; 713 #size-cells = <0>;
@@ -715,7 +719,7 @@
715 reg = <0 0xe6ef0000 0 0x1000>; 719 reg = <0 0xe6ef0000 0 0x1000>;
716 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 720 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
717 clocks = <&mstp8_clks R8A7794_CLK_VIN0>; 721 clocks = <&mstp8_clks R8A7794_CLK_VIN0>;
718 power-domains = <&cpg_clocks>; 722 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
719 status = "disabled"; 723 status = "disabled";
720 }; 724 };
721 725
@@ -724,7 +728,7 @@
724 reg = <0 0xe6ef1000 0 0x1000>; 728 reg = <0 0xe6ef1000 0 0x1000>;
725 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 729 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&mstp8_clks R8A7794_CLK_VIN1>; 730 clocks = <&mstp8_clks R8A7794_CLK_VIN1>;
727 power-domains = <&cpg_clocks>; 731 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
728 status = "disabled"; 732 status = "disabled";
729 }; 733 };
730 734
@@ -735,7 +739,7 @@
735 <0 0xee080000 0 0x1100>; 739 <0 0xee080000 0 0x1100>;
736 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 740 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&mstp7_clks R8A7794_CLK_EHCI>; 741 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
738 power-domains = <&cpg_clocks>; 742 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
739 status = "disabled"; 743 status = "disabled";
740 744
741 bus-range = <0 0>; 745 bus-range = <0 0>;
@@ -770,7 +774,7 @@
770 <0 0xee0c0000 0 0x1100>; 774 <0 0xee0c0000 0 0x1100>;
771 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 775 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
772 clocks = <&mstp7_clks R8A7794_CLK_EHCI>; 776 clocks = <&mstp7_clks R8A7794_CLK_EHCI>;
773 power-domains = <&cpg_clocks>; 777 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
774 status = "disabled"; 778 status = "disabled";
775 779
776 bus-range = <1 1>; 780 bus-range = <1 1>;
@@ -803,7 +807,7 @@
803 reg = <0 0xe6590000 0 0x100>; 807 reg = <0 0xe6590000 0 0x100>;
804 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 808 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
805 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>; 809 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
806 power-domains = <&cpg_clocks>; 810 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
807 renesas,buswait = <4>; 811 renesas,buswait = <4>;
808 phys = <&usb0 1>; 812 phys = <&usb0 1>;
809 phy-names = "usb"; 813 phy-names = "usb";
@@ -817,7 +821,7 @@
817 #size-cells = <0>; 821 #size-cells = <0>;
818 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>; 822 clocks = <&mstp7_clks R8A7794_CLK_HSUSB>;
819 clock-names = "usbhs"; 823 clock-names = "usbhs";
820 power-domains = <&cpg_clocks>; 824 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
821 status = "disabled"; 825 status = "disabled";
822 826
823 usb0: usb-channel@0 { 827 usb0: usb-channel@0 {
@@ -865,7 +869,7 @@
865 clocks = <&mstp9_clks R8A7794_CLK_RCAN0>, 869 clocks = <&mstp9_clks R8A7794_CLK_RCAN0>,
866 <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>; 870 <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
867 clock-names = "clkp1", "clkp2", "can_clk"; 871 clock-names = "clkp1", "clkp2", "can_clk";
868 power-domains = <&cpg_clocks>; 872 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
869 status = "disabled"; 873 status = "disabled";
870 }; 874 };
871 875
@@ -876,7 +880,7 @@
876 clocks = <&mstp9_clks R8A7794_CLK_RCAN1>, 880 clocks = <&mstp9_clks R8A7794_CLK_RCAN1>,
877 <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>; 881 <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
878 clock-names = "clkp1", "clkp2", "can_clk"; 882 clock-names = "clkp1", "clkp2", "can_clk";
879 power-domains = <&cpg_clocks>; 883 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
880 status = "disabled"; 884 status = "disabled";
881 }; 885 };
882 886
@@ -1213,6 +1217,12 @@
1213 }; 1217 };
1214 }; 1218 };
1215 1219
1220 sysc: system-controller@e6180000 {
1221 compatible = "renesas,r8a7794-sysc";
1222 reg = <0 0xe6180000 0 0x0200>;
1223 #power-domain-cells = <1>;
1224 };
1225
1216 ipmmu_sy0: mmu@e6280000 { 1226 ipmmu_sy0: mmu@e6280000 {
1217 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; 1227 compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa";
1218 reg = <0 0xe6280000 0 0x1000>; 1228 reg = <0 0xe6280000 0 0x1000>;
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index a99f07ad6312..941f36263c8f 100644
--- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
@@ -38,11 +38,17 @@
38 vddio-pex-ctl-supply = <&vdd_3v3_lp0>; 38 vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
39 avdd-pll-erefe-supply = <&avdd_1v05_run>; 39 avdd-pll-erefe-supply = <&avdd_1v05_run>;
40 40
41 /* Mini PCIe */
41 pci@1,0 { 42 pci@1,0 {
43 phys = <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-4}>;
44 phy-names = "pcie-0";
42 status = "okay"; 45 status = "okay";
43 }; 46 };
44 47
48 /* Gigabit Ethernet */
45 pci@2,0 { 49 pci@2,0 {
50 phys = <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-2}>;
51 phy-names = "pcie-0";
46 status = "okay"; 52 status = "okay";
47 }; 53 };
48 }; 54 };
@@ -1677,6 +1683,9 @@
1677 sata@0,70020000 { 1683 sata@0,70020000 {
1678 status = "okay"; 1684 status = "okay";
1679 1685
1686 phys = <&{/padctl@0,7009f000/pads/sata/lanes/sata-0}>;
1687 phy-names = "sata-0";
1688
1680 hvdd-supply = <&vdd_3v3_lp0>; 1689 hvdd-supply = <&vdd_3v3_lp0>;
1681 vddio-supply = <&vdd_1v05_run>; 1690 vddio-supply = <&vdd_1v05_run>;
1682 avdd-supply = <&vdd_1v05_run>; 1691 avdd-supply = <&vdd_1v05_run>;
@@ -1689,28 +1698,107 @@
1689 status = "okay"; 1698 status = "okay";
1690 }; 1699 };
1691 1700
1701 usb@0,70090000 {
1702 phys = <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-0}>, /* Micro A/B */
1703 <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-1}>, /* Mini PCIe */
1704 <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-2}>, /* USB3 */
1705 <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-0}>; /* USB3 */
1706 phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0";
1707
1708 avddio-pex-supply = <&vdd_1v05_run>;
1709 dvddio-pex-supply = <&vdd_1v05_run>;
1710 avdd-usb-supply = <&vdd_3v3_lp0>;
1711 avdd-pll-utmip-supply = <&vddio_1v8>;
1712 avdd-pll-erefe-supply = <&avdd_1v05_run>;
1713 avdd-usb-ss-pll-supply = <&vdd_1v05_run>;
1714 hvdd-usb-ss-supply = <&vdd_3v3_lp0>;
1715 hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>;
1716
1717 status = "okay";
1718 };
1719
1692 padctl@0,7009f000 { 1720 padctl@0,7009f000 {
1693 pinctrl-0 = <&padctl_default>; 1721 status = "okay";
1694 pinctrl-names = "default";
1695 1722
1696 padctl_default: pinmux { 1723 pads {
1697 usb3 { 1724 usb2 {
1698 nvidia,lanes = "pcie-0", "pcie-1"; 1725 status = "okay";
1699 nvidia,function = "usb3"; 1726
1700 nvidia,iddq = <0>; 1727 lanes {
1728 usb2-0 {
1729 nvidia,function = "xusb";
1730 status = "okay";
1731 };
1732
1733 usb2-1 {
1734 nvidia,function = "xusb";
1735 status = "okay";
1736 };
1737
1738 usb2-2 {
1739 nvidia,function = "xusb";
1740 status = "okay";
1741 };
1742 };
1701 }; 1743 };
1702 1744
1703 pcie { 1745 pcie {
1704 nvidia,lanes = "pcie-2", "pcie-3", 1746 status = "okay";
1705 "pcie-4"; 1747
1706 nvidia,function = "pcie"; 1748 lanes {
1707 nvidia,iddq = <0>; 1749 pcie-0 {
1750 nvidia,function = "usb3-ss";
1751 status = "okay";
1752 };
1753
1754 pcie-2 {
1755 nvidia,function = "pcie";
1756 status = "okay";
1757 };
1758
1759 pcie-4 {
1760 nvidia,function = "pcie";
1761 status = "okay";
1762 };
1763 };
1708 }; 1764 };
1709 1765
1710 sata { 1766 sata {
1711 nvidia,lanes = "sata-0"; 1767 status = "okay";
1712 nvidia,function = "sata"; 1768
1713 nvidia,iddq = <0>; 1769 lanes {
1770 sata-0 {
1771 nvidia,function = "sata";
1772 status = "okay";
1773 };
1774 };
1775 };
1776 };
1777
1778 ports {
1779 /* Micro A/B */
1780 usb2-0 {
1781 status = "okay";
1782 mode = "otg";
1783 };
1784
1785 /* Mini PCIe */
1786 usb2-1 {
1787 status = "okay";
1788 mode = "host";
1789 };
1790
1791 /* USB3 */
1792 usb2-2 {
1793 status = "okay";
1794 mode = "host";
1795
1796 vbus-supply = <&vdd_usb3_vbus>;
1797 };
1798
1799 usb3-0 {
1800 nvidia,usb2-companion = <2>;
1801 status = "okay";
1714 }; 1802 };
1715 }; 1803 };
1716 }; 1804 };
diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi
index 5f1fc1410bd0..0710a600cc69 100644
--- a/arch/arm/boot/dts/tegra124-nyan.dtsi
+++ b/arch/arm/boot/dts/tegra124-nyan.dtsi
@@ -224,7 +224,7 @@
224 regulator-always-on; 224 regulator-always-on;
225 }; 225 };
226 226
227 ldo0 { 227 avdd_1v05_run: ldo0 {
228 regulator-name = "+1.05V_RUN_AVDD"; 228 regulator-name = "+1.05V_RUN_AVDD";
229 regulator-min-microvolt = <1050000>; 229 regulator-min-microvolt = <1050000>;
230 regulator-max-microvolt = <1050000>; 230 regulator-max-microvolt = <1050000>;
@@ -368,6 +368,99 @@
368 status = "okay"; 368 status = "okay";
369 }; 369 };
370 370
371 usb@0,70090000 {
372 phys = <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */
373 <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */
374 <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */
375 <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */
376 <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */
377 phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1";
378
379 avddio-pex-supply = <&vdd_1v05_run>;
380 dvddio-pex-supply = <&vdd_1v05_run>;
381 avdd-usb-supply = <&vdd_3v3_lp0>;
382 avdd-pll-utmip-supply = <&vddio_1v8>;
383 avdd-pll-erefe-supply = <&avdd_1v05_run>;
384 avdd-usb-ss-pll-supply = <&vdd_1v05_run>;
385 hvdd-usb-ss-supply = <&vdd_3v3_lp0>;
386 hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>;
387
388 status = "okay";
389 };
390
391 padctl@0,7009f000 {
392 status = "okay";
393
394 pads {
395 usb2 {
396 status = "okay";
397
398 lanes {
399 usb2-0 {
400 nvidia,function = "xusb";
401 status = "okay";
402 };
403
404 usb2-1 {
405 nvidia,function = "xusb";
406 status = "okay";
407 };
408
409 usb2-2 {
410 nvidia,function = "xusb";
411 status = "okay";
412 };
413 };
414 };
415
416 pcie {
417 status = "okay";
418
419 lanes {
420 pcie-0 {
421 nvidia,function = "usb3-ss";
422 status = "okay";
423 };
424
425 pcie-1 {
426 nvidia,function = "usb3-ss";
427 status = "okay";
428 };
429 };
430 };
431 };
432
433 ports {
434 usb2-0 {
435 vbus-supply = <&vdd_usb1_vbus>;
436 status = "okay";
437 mode = "otg";
438 };
439
440 usb2-1 {
441 vbus-supply = <&vdd_run_cam>;
442 status = "okay";
443 mode = "host";
444 };
445
446 usb2-2 {
447 vbus-supply = <&vdd_usb3_vbus>;
448 status = "okay";
449 mode = "host";
450 };
451
452 usb3-0 {
453 nvidia,usb2-companion = <0>;
454 status = "okay";
455 };
456
457 usb3-1 {
458 nvidia,usb2-companion = <1>;
459 status = "okay";
460 };
461 };
462 };
463
371 sdhci0_pwrseq: sdhci0_pwrseq { 464 sdhci0_pwrseq: sdhci0_pwrseq {
372 compatible = "mmc-pwrseq-simple"; 465 compatible = "mmc-pwrseq-simple";
373 466
@@ -414,33 +507,6 @@
414 }; 507 };
415 }; 508 };
416 509
417 usb@0,7d000000 { /* Rear external USB port. */
418 status = "okay";
419 };
420
421 usb-phy@0,7d000000 {
422 status = "okay";
423 vbus-supply = <&vdd_usb1_vbus>;
424 };
425
426 usb@0,7d004000 { /* Internal webcam. */
427 status = "okay";
428 };
429
430 usb-phy@0,7d004000 {
431 status = "okay";
432 vbus-supply = <&vdd_run_cam>;
433 };
434
435 usb@0,7d008000 { /* Left external USB port. */
436 status = "okay";
437 };
438
439 usb-phy@0,7d008000 {
440 status = "okay";
441 vbus-supply = <&vdd_usb3_vbus>;
442 };
443
444 backlight: backlight { 510 backlight: backlight {
445 compatible = "pwm-backlight"; 511 compatible = "pwm-backlight";
446 512
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts
index 0318258dde3e..973446d07182 100644
--- a/arch/arm/boot/dts/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -757,7 +757,7 @@
757 regulator-always-on; 757 regulator-always-on;
758 }; 758 };
759 759
760 ldo0 { 760 avdd_1v05_run: ldo0 {
761 regulator-name = "+1.05V_RUN_AVDD"; 761 regulator-name = "+1.05V_RUN_AVDD";
762 regulator-min-microvolt = <1050000>; 762 regulator-min-microvolt = <1050000>;
763 regulator-max-microvolt = <1050000>; 763 regulator-max-microvolt = <1050000>;
@@ -899,6 +899,105 @@
899 status = "okay"; 899 status = "okay";
900 }; 900 };
901 901
902 usb@0,70090000 {
903 phys = <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */
904 <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */
905 <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */
906 <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */
907 <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */
908 phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1";
909
910 avddio-pex-supply = <&vdd_1v05_run>;
911 dvddio-pex-supply = <&vdd_1v05_run>;
912 avdd-usb-supply = <&vdd_3v3_lp0>;
913 avdd-pll-utmip-supply = <&vddio_1v8>;
914 avdd-pll-erefe-supply = <&avdd_1v05_run>;
915 avdd-usb-ss-pll-supply = <&vdd_1v05_run>;
916 hvdd-usb-ss-supply = <&vdd_3v3_lp0>;
917 hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>;
918
919 status = "okay";
920 };
921
922 padctl@0,7009f000 {
923 pads {
924 usb2 {
925 status = "okay";
926
927 lanes {
928 usb2-0 {
929 nvidia,function = "xusb";
930 status = "okay";
931 };
932
933 usb2-1 {
934 nvidia,function = "xusb";
935 status = "okay";
936 };
937
938 usb2-2 {
939 nvidia,function = "xusb";
940 status = "okay";
941 };
942 };
943 };
944
945 pcie {
946 status = "okay";
947
948 lanes {
949 pcie-0 {
950 nvidia,function = "usb3-ss";
951 status = "okay";
952 };
953
954 pcie-1 {
955 nvidia,function = "usb3-ss";
956 status = "okay";
957 };
958
959 pcie-1 {
960 nvidia,function = "usb3-ss";
961 status = "okay";
962 };
963 };
964 };
965 };
966
967 ports {
968 usb2-0 {
969 status = "okay";
970 mode = "otg";
971
972 vbus-supply = <&vdd_usb1_vbus>;
973 };
974
975 usb2-1 {
976 status = "okay";
977 mode = "host";
978
979 vbus-supply = <&vdd_run_cam>;
980 };
981
982 usb2-2 {
983 status = "okay";
984 mode = "host";
985
986 vbus-supply = <&vdd_usb3_vbus>;
987 };
988
989 usb3-0 {
990 nvidia,usb2-companion = <0>;
991 status = "okay";
992 };
993
994 usb3-1 {
995 nvidia,usb2-companion = <2>;
996 status = "okay";
997 };
998 };
999 };
1000
902 sdhci@0,700b0400 { 1001 sdhci@0,700b0400 {
903 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; 1002 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
904 power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; 1003 power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index e4eac1f01e64..ea4811870de2 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -2,7 +2,6 @@
2#include <dt-bindings/gpio/tegra-gpio.h> 2#include <dt-bindings/gpio/tegra-gpio.h>
3#include <dt-bindings/memory/tegra124-mc.h> 3#include <dt-bindings/memory/tegra124-mc.h>
4#include <dt-bindings/pinctrl/pinctrl-tegra.h> 4#include <dt-bindings/pinctrl/pinctrl-tegra.h>
5#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
6#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/reset/tegra124-car.h> 6#include <dt-bindings/reset/tegra124-car.h>
8#include <dt-bindings/thermal/tegra124-soctherm.h> 7#include <dt-bindings/thermal/tegra124-soctherm.h>
@@ -51,9 +50,6 @@
51 reset-names = "pex", "afi", "pcie_x"; 50 reset-names = "pex", "afi", "pcie_x";
52 status = "disabled"; 51 status = "disabled";
53 52
54 phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
55 phy-names = "pcie";
56
57 pci@1,0 { 53 pci@1,0 {
58 device_type = "pci"; 54 device_type = "pci";
59 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 55 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
@@ -622,8 +618,6 @@
622 <&tegra_car 123>, 618 <&tegra_car 123>,
623 <&tegra_car 129>; 619 <&tegra_car 129>;
624 reset-names = "sata", "sata-oob", "sata-cold"; 620 reset-names = "sata", "sata-oob", "sata-cold";
625 phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
626 phy-names = "sata-phy";
627 status = "disabled"; 621 status = "disabled";
628 }; 622 };
629 623
@@ -642,13 +636,172 @@
642 status = "disabled"; 636 status = "disabled";
643 }; 637 };
644 638
639 usb@0,70090000 {
640 compatible = "nvidia,tegra124-xusb";
641 reg = <0x0 0x70090000 0x0 0x8000>,
642 <0x0 0x70098000 0x0 0x1000>,
643 <0x0 0x70099000 0x0 0x1000>;
644 reg-names = "hcd", "fpci", "ipfs";
645
646 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
647 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
648
649 clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
650 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
651 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
652 <&tegra_car TEGRA124_CLK_XUSB_SS>,
653 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
654 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
655 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
656 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
657 <&tegra_car TEGRA124_CLK_PLL_U_480M>,
658 <&tegra_car TEGRA124_CLK_CLK_M>,
659 <&tegra_car TEGRA124_CLK_PLL_E>;
660 clock-names = "xusb_host", "xusb_host_src",
661 "xusb_falcon_src", "xusb_ss",
662 "xusb_ss_div2", "xusb_ss_src",
663 "xusb_hs_src", "xusb_fs_src",
664 "pll_u_480m", "clk_m", "pll_e";
665 resets = <&tegra_car 89>, <&tegra_car 156>,
666 <&tegra_car 143>;
667 reset-names = "xusb_host", "xusb_ss", "xusb_src";
668
669 nvidia,xusb-padctl = <&padctl>;
670
671 status = "disabled";
672 };
673
645 padctl: padctl@0,7009f000 { 674 padctl: padctl@0,7009f000 {
646 compatible = "nvidia,tegra124-xusb-padctl"; 675 compatible = "nvidia,tegra124-xusb-padctl";
647 reg = <0x0 0x7009f000 0x0 0x1000>; 676 reg = <0x0 0x7009f000 0x0 0x1000>;
648 resets = <&tegra_car 142>; 677 resets = <&tegra_car 142>;
649 reset-names = "padctl"; 678 reset-names = "padctl";
650 679
651 #phy-cells = <1>; 680 pads {
681 usb2 {
682 status = "disabled";
683
684 lanes {
685 usb2-0 {
686 status = "disabled";
687 #phy-cells = <0>;
688 };
689
690 usb2-1 {
691 status = "disabled";
692 #phy-cells = <0>;
693 };
694
695 usb2-2 {
696 status = "disabled";
697 #phy-cells = <0>;
698 };
699 };
700 };
701
702 ulpi {
703 status = "disabled";
704
705 lanes {
706 ulpi-0 {
707 status = "disabled";
708 #phy-cells = <0>;
709 };
710 };
711 };
712
713 hsic {
714 status = "disabled";
715
716 lanes {
717 hsic-0 {
718 status = "disabled";
719 #phy-cells = <0>;
720 };
721
722 hsic-1 {
723 status = "disabled";
724 #phy-cells = <0>;
725 };
726 };
727 };
728
729 pcie {
730 status = "disabled";
731
732 lanes {
733 pcie-0 {
734 status = "disabled";
735 #phy-cells = <0>;
736 };
737
738 pcie-1 {
739 status = "disabled";
740 #phy-cells = <0>;
741 };
742
743 pcie-2 {
744 status = "disabled";
745 #phy-cells = <0>;
746 };
747
748 pcie-3 {
749 status = "disabled";
750 #phy-cells = <0>;
751 };
752
753 pcie-4 {
754 status = "disabled";
755 #phy-cells = <0>;
756 };
757 };
758 };
759
760 sata {
761 status = "disabled";
762
763 lanes {
764 sata-0 {
765 status = "disabled";
766 #phy-cells = <0>;
767 };
768 };
769 };
770 };
771
772 ports {
773 usb2-0 {
774 status = "disabled";
775 };
776
777 usb2-1 {
778 status = "disabled";
779 };
780
781 usb2-2 {
782 status = "disabled";
783 };
784
785 ulpi-0 {
786 status = "disabled";
787 };
788
789 hsic-0 {
790 status = "disabled";
791 };
792
793 hsic-1 {
794 status = "disabled";
795 };
796
797 usb3-0 {
798 status = "disabled";
799 };
800
801 usb3-1 {
802 status = "disabled";
803 };
804 };
652 }; 805 };
653 806
654 sdhci@0,700b0000 { 807 sdhci@0,700b0000 {
diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
index 4d8b7f693535..a8a8e434fb27 100644
--- a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
@@ -50,6 +50,11 @@
50 clock-frequency = <16000000>; 50 clock-frequency = <16000000>;
51 }; 51 };
52 52
53 panel: panel {
54 compatible = "edt,et057090dhu";
55 backlight = <&bl>;
56 };
57
53 reg_3v3: regulator-3v3 { 58 reg_3v3: regulator-3v3 {
54 compatible = "regulator-fixed"; 59 compatible = "regulator-fixed";
55 regulator-name = "3.3V"; 60 regulator-name = "3.3V";
@@ -83,6 +88,13 @@
83 status = "okay"; 88 status = "okay";
84}; 89};
85 90
91&dcu0 {
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_dcu0_1>;
94 fsl,panel = <&panel>;
95 status = "okay";
96};
97
86&dspi1 { 98&dspi1 {
87 status = "okay"; 99 status = "okay";
88 100
@@ -134,6 +146,10 @@
134 vin-supply = <&reg_3v3>; 146 vin-supply = <&reg_3v3>;
135}; 147};
136 148
149&tcon0 {
150 status = "okay";
151};
152
137&uart0 { 153&uart0 {
138 status = "okay"; 154 status = "okay";
139}; 155};
diff --git a/arch/arm/boot/dts/vf-colibri.dtsi b/arch/arm/boot/dts/vf-colibri.dtsi
index 226a86ffd3c9..b7417094dc11 100644
--- a/arch/arm/boot/dts/vf-colibri.dtsi
+++ b/arch/arm/boot/dts/vf-colibri.dtsi
@@ -222,6 +222,39 @@
222 >; 222 >;
223 }; 223 };
224 224
225 pinctrl_dcu0_1: dcu0grp_1 {
226 fsl,pins = <
227 VF610_PAD_PTE0__DCU0_HSYNC 0x1902
228 VF610_PAD_PTE1__DCU0_VSYNC 0x1902
229 VF610_PAD_PTE2__DCU0_PCLK 0x1902
230 VF610_PAD_PTE4__DCU0_DE 0x1902
231 VF610_PAD_PTE5__DCU0_R0 0x1902
232 VF610_PAD_PTE6__DCU0_R1 0x1902
233 VF610_PAD_PTE7__DCU0_R2 0x1902
234 VF610_PAD_PTE8__DCU0_R3 0x1902
235 VF610_PAD_PTE9__DCU0_R4 0x1902
236 VF610_PAD_PTE10__DCU0_R5 0x1902
237 VF610_PAD_PTE11__DCU0_R6 0x1902
238 VF610_PAD_PTE12__DCU0_R7 0x1902
239 VF610_PAD_PTE13__DCU0_G0 0x1902
240 VF610_PAD_PTE14__DCU0_G1 0x1902
241 VF610_PAD_PTE15__DCU0_G2 0x1902
242 VF610_PAD_PTE16__DCU0_G3 0x1902
243 VF610_PAD_PTE17__DCU0_G4 0x1902
244 VF610_PAD_PTE18__DCU0_G5 0x1902
245 VF610_PAD_PTE19__DCU0_G6 0x1902
246 VF610_PAD_PTE20__DCU0_G7 0x1902
247 VF610_PAD_PTE21__DCU0_B0 0x1902
248 VF610_PAD_PTE22__DCU0_B1 0x1902
249 VF610_PAD_PTE23__DCU0_B2 0x1902
250 VF610_PAD_PTE24__DCU0_B3 0x1902
251 VF610_PAD_PTE25__DCU0_B4 0x1902
252 VF610_PAD_PTE26__DCU0_B5 0x1902
253 VF610_PAD_PTE27__DCU0_B6 0x1902
254 VF610_PAD_PTE28__DCU0_B7 0x1902
255 >;
256 };
257
225 pinctrl_dspi1: dspi1grp { 258 pinctrl_dspi1: dspi1grp {
226 fsl,pins = < 259 fsl,pins = <
227 VF610_PAD_PTD5__DSPI1_CS0 0x33e2 260 VF610_PAD_PTD5__DSPI1_CS0 0x33e2
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
index 04ef54d45a91..2c13ec696ac5 100644
--- a/arch/arm/boot/dts/vfxxx.dtsi
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -311,6 +311,14 @@
311 <20000000>; 311 <20000000>;
312 }; 312 };
313 313
314 tcon0: timing-controller@4003d000 {
315 compatible = "fsl,vf610-tcon";
316 reg = <0x4003d000 0x1000>;
317 clocks = <&clks VF610_CLK_TCON0>;
318 clock-names = "ipg";
319 status = "disabled";
320 };
321
314 wdoga5: wdog@4003e000 { 322 wdoga5: wdog@4003e000 {
315 compatible = "fsl,vf610-wdt", "fsl,imx21-wdt"; 323 compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
316 reg = <0x4003e000 0x1000>; 324 reg = <0x4003e000 0x1000>;
@@ -416,6 +424,17 @@
416 status = "disabled"; 424 status = "disabled";
417 }; 425 };
418 426
427 dcu0: dcu@40058000 {
428 compatible = "fsl,vf610-dcu";
429 reg = <0x40058000 0x1200>;
430 interrupts = <30 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&clks VF610_CLK_DCU0>,
432 <&clks VF610_CLK_DCU0_DIV>;
433 clock-names = "dcu", "pix";
434 fsl,tcon = <&tcon0>;
435 status = "disabled";
436 };
437
419 i2c0: i2c@40066000 { 438 i2c0: i2c@40066000 {
420 #address-cells = <1>; 439 #address-cells = <1>;
421 #size-cells = <0>; 440 #size-cells = <0>;
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 7cb2d72e7378..3285a9286786 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -10,6 +10,7 @@
10 10
11#include <dt-bindings/clock/r8a7795-cpg-mssr.h> 11#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/power/r8a7795-sysc.h>
13 14
14/ { 15/ {
15 compatible = "renesas,r8a7795"; 16 compatible = "renesas,r8a7795";
@@ -39,6 +40,7 @@
39 compatible = "arm,cortex-a57", "arm,armv8"; 40 compatible = "arm,cortex-a57", "arm,armv8";
40 reg = <0x0>; 41 reg = <0x0>;
41 device_type = "cpu"; 42 device_type = "cpu";
43 power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
42 next-level-cache = <&L2_CA57>; 44 next-level-cache = <&L2_CA57>;
43 enable-method = "psci"; 45 enable-method = "psci";
44 }; 46 };
@@ -47,6 +49,7 @@
47 compatible = "arm,cortex-a57","arm,armv8"; 49 compatible = "arm,cortex-a57","arm,armv8";
48 reg = <0x1>; 50 reg = <0x1>;
49 device_type = "cpu"; 51 device_type = "cpu";
52 power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
50 next-level-cache = <&L2_CA57>; 53 next-level-cache = <&L2_CA57>;
51 enable-method = "psci"; 54 enable-method = "psci";
52 }; 55 };
@@ -54,6 +57,7 @@
54 compatible = "arm,cortex-a57","arm,armv8"; 57 compatible = "arm,cortex-a57","arm,armv8";
55 reg = <0x2>; 58 reg = <0x2>;
56 device_type = "cpu"; 59 device_type = "cpu";
60 power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
57 next-level-cache = <&L2_CA57>; 61 next-level-cache = <&L2_CA57>;
58 enable-method = "psci"; 62 enable-method = "psci";
59 }; 63 };
@@ -61,6 +65,7 @@
61 compatible = "arm,cortex-a57","arm,armv8"; 65 compatible = "arm,cortex-a57","arm,armv8";
62 reg = <0x3>; 66 reg = <0x3>;
63 device_type = "cpu"; 67 device_type = "cpu";
68 power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
64 next-level-cache = <&L2_CA57>; 69 next-level-cache = <&L2_CA57>;
65 enable-method = "psci"; 70 enable-method = "psci";
66 }; 71 };
@@ -68,12 +73,14 @@
68 73
69 L2_CA57: cache-controller@0 { 74 L2_CA57: cache-controller@0 {
70 compatible = "cache"; 75 compatible = "cache";
76 power-domains = <&sysc R8A7795_PD_CA57_SCU>;
71 cache-unified; 77 cache-unified;
72 cache-level = <2>; 78 cache-level = <2>;
73 }; 79 };
74 80
75 L2_CA53: cache-controller@1 { 81 L2_CA53: cache-controller@1 {
76 compatible = "cache"; 82 compatible = "cache";
83 power-domains = <&sysc R8A7795_PD_CA53_SCU>;
77 cache-unified; 84 cache-unified;
78 cache-level = <2>; 85 cache-level = <2>;
79 }; 86 };
@@ -168,7 +175,7 @@
168 #interrupt-cells = <2>; 175 #interrupt-cells = <2>;
169 interrupt-controller; 176 interrupt-controller;
170 clocks = <&cpg CPG_MOD 912>; 177 clocks = <&cpg CPG_MOD 912>;
171 power-domains = <&cpg>; 178 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
172 }; 179 };
173 180
174 gpio1: gpio@e6051000 { 181 gpio1: gpio@e6051000 {
@@ -182,7 +189,7 @@
182 #interrupt-cells = <2>; 189 #interrupt-cells = <2>;
183 interrupt-controller; 190 interrupt-controller;
184 clocks = <&cpg CPG_MOD 911>; 191 clocks = <&cpg CPG_MOD 911>;
185 power-domains = <&cpg>; 192 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
186 }; 193 };
187 194
188 gpio2: gpio@e6052000 { 195 gpio2: gpio@e6052000 {
@@ -196,7 +203,7 @@
196 #interrupt-cells = <2>; 203 #interrupt-cells = <2>;
197 interrupt-controller; 204 interrupt-controller;
198 clocks = <&cpg CPG_MOD 910>; 205 clocks = <&cpg CPG_MOD 910>;
199 power-domains = <&cpg>; 206 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
200 }; 207 };
201 208
202 gpio3: gpio@e6053000 { 209 gpio3: gpio@e6053000 {
@@ -210,7 +217,7 @@
210 #interrupt-cells = <2>; 217 #interrupt-cells = <2>;
211 interrupt-controller; 218 interrupt-controller;
212 clocks = <&cpg CPG_MOD 909>; 219 clocks = <&cpg CPG_MOD 909>;
213 power-domains = <&cpg>; 220 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
214 }; 221 };
215 222
216 gpio4: gpio@e6054000 { 223 gpio4: gpio@e6054000 {
@@ -224,7 +231,7 @@
224 #interrupt-cells = <2>; 231 #interrupt-cells = <2>;
225 interrupt-controller; 232 interrupt-controller;
226 clocks = <&cpg CPG_MOD 908>; 233 clocks = <&cpg CPG_MOD 908>;
227 power-domains = <&cpg>; 234 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
228 }; 235 };
229 236
230 gpio5: gpio@e6055000 { 237 gpio5: gpio@e6055000 {
@@ -238,7 +245,7 @@
238 #interrupt-cells = <2>; 245 #interrupt-cells = <2>;
239 interrupt-controller; 246 interrupt-controller;
240 clocks = <&cpg CPG_MOD 907>; 247 clocks = <&cpg CPG_MOD 907>;
241 power-domains = <&cpg>; 248 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
242 }; 249 };
243 250
244 gpio6: gpio@e6055400 { 251 gpio6: gpio@e6055400 {
@@ -252,7 +259,7 @@
252 #interrupt-cells = <2>; 259 #interrupt-cells = <2>;
253 interrupt-controller; 260 interrupt-controller;
254 clocks = <&cpg CPG_MOD 906>; 261 clocks = <&cpg CPG_MOD 906>;
255 power-domains = <&cpg>; 262 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
256 }; 263 };
257 264
258 gpio7: gpio@e6055800 { 265 gpio7: gpio@e6055800 {
@@ -266,7 +273,7 @@
266 #interrupt-cells = <2>; 273 #interrupt-cells = <2>;
267 interrupt-controller; 274 interrupt-controller;
268 clocks = <&cpg CPG_MOD 905>; 275 clocks = <&cpg CPG_MOD 905>;
269 power-domains = <&cpg>; 276 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
270 }; 277 };
271 278
272 pmu_a57 { 279 pmu_a57 {
@@ -302,6 +309,12 @@
302 #power-domain-cells = <0>; 309 #power-domain-cells = <0>;
303 }; 310 };
304 311
312 sysc: system-controller@e6180000 {
313 compatible = "renesas,r8a7795-sysc";
314 reg = <0 0xe6180000 0 0x0400>;
315 #power-domain-cells = <1>;
316 };
317
305 audma0: dma-controller@ec700000 { 318 audma0: dma-controller@ec700000 {
306 compatible = "renesas,rcar-dmac"; 319 compatible = "renesas,rcar-dmac";
307 reg = <0 0xec700000 0 0x10000>; 320 reg = <0 0xec700000 0 0x10000>;
@@ -329,7 +342,7 @@
329 "ch12", "ch13", "ch14", "ch15"; 342 "ch12", "ch13", "ch14", "ch15";
330 clocks = <&cpg CPG_MOD 502>; 343 clocks = <&cpg CPG_MOD 502>;
331 clock-names = "fck"; 344 clock-names = "fck";
332 power-domains = <&cpg>; 345 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
333 #dma-cells = <1>; 346 #dma-cells = <1>;
334 dma-channels = <16>; 347 dma-channels = <16>;
335 }; 348 };
@@ -361,7 +374,7 @@
361 "ch12", "ch13", "ch14", "ch15"; 374 "ch12", "ch13", "ch14", "ch15";
362 clocks = <&cpg CPG_MOD 501>; 375 clocks = <&cpg CPG_MOD 501>;
363 clock-names = "fck"; 376 clock-names = "fck";
364 power-domains = <&cpg>; 377 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
365 #dma-cells = <1>; 378 #dma-cells = <1>;
366 dma-channels = <16>; 379 dma-channels = <16>;
367 }; 380 };
@@ -383,7 +396,7 @@
383 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 396 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
384 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 397 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&cpg CPG_MOD 407>; 398 clocks = <&cpg CPG_MOD 407>;
386 power-domains = <&cpg>; 399 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
387 }; 400 };
388 401
389 dmac0: dma-controller@e6700000 { 402 dmac0: dma-controller@e6700000 {
@@ -414,7 +427,7 @@
414 "ch12", "ch13", "ch14", "ch15"; 427 "ch12", "ch13", "ch14", "ch15";
415 clocks = <&cpg CPG_MOD 219>; 428 clocks = <&cpg CPG_MOD 219>;
416 clock-names = "fck"; 429 clock-names = "fck";
417 power-domains = <&cpg>; 430 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
418 #dma-cells = <1>; 431 #dma-cells = <1>;
419 dma-channels = <16>; 432 dma-channels = <16>;
420 }; 433 };
@@ -447,7 +460,7 @@
447 "ch12", "ch13", "ch14", "ch15"; 460 "ch12", "ch13", "ch14", "ch15";
448 clocks = <&cpg CPG_MOD 218>; 461 clocks = <&cpg CPG_MOD 218>;
449 clock-names = "fck"; 462 clock-names = "fck";
450 power-domains = <&cpg>; 463 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
451 #dma-cells = <1>; 464 #dma-cells = <1>;
452 dma-channels = <16>; 465 dma-channels = <16>;
453 }; 466 };
@@ -480,7 +493,7 @@
480 "ch12", "ch13", "ch14", "ch15"; 493 "ch12", "ch13", "ch14", "ch15";
481 clocks = <&cpg CPG_MOD 217>; 494 clocks = <&cpg CPG_MOD 217>;
482 clock-names = "fck"; 495 clock-names = "fck";
483 power-domains = <&cpg>; 496 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
484 #dma-cells = <1>; 497 #dma-cells = <1>;
485 dma-channels = <16>; 498 dma-channels = <16>;
486 }; 499 };
@@ -522,7 +535,7 @@
522 "ch20", "ch21", "ch22", "ch23", 535 "ch20", "ch21", "ch22", "ch23",
523 "ch24"; 536 "ch24";
524 clocks = <&cpg CPG_MOD 812>; 537 clocks = <&cpg CPG_MOD 812>;
525 power-domains = <&cpg>; 538 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
526 phy-mode = "rgmii-id"; 539 phy-mode = "rgmii-id";
527 #address-cells = <1>; 540 #address-cells = <1>;
528 #size-cells = <0>; 541 #size-cells = <0>;
@@ -539,7 +552,7 @@
539 clock-names = "clkp1", "clkp2", "can_clk"; 552 clock-names = "clkp1", "clkp2", "can_clk";
540 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; 553 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
541 assigned-clock-rates = <40000000>; 554 assigned-clock-rates = <40000000>;
542 power-domains = <&cpg>; 555 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
543 status = "disabled"; 556 status = "disabled";
544 }; 557 };
545 558
@@ -554,7 +567,7 @@
554 clock-names = "clkp1", "clkp2", "can_clk"; 567 clock-names = "clkp1", "clkp2", "can_clk";
555 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; 568 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
556 assigned-clock-rates = <40000000>; 569 assigned-clock-rates = <40000000>;
557 power-domains = <&cpg>; 570 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
558 status = "disabled"; 571 status = "disabled";
559 }; 572 };
560 573
@@ -570,7 +583,7 @@
570 clock-names = "fck", "brg_int", "scif_clk"; 583 clock-names = "fck", "brg_int", "scif_clk";
571 dmas = <&dmac1 0x31>, <&dmac1 0x30>; 584 dmas = <&dmac1 0x31>, <&dmac1 0x30>;
572 dma-names = "tx", "rx"; 585 dma-names = "tx", "rx";
573 power-domains = <&cpg>; 586 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
574 status = "disabled"; 587 status = "disabled";
575 }; 588 };
576 589
@@ -586,7 +599,7 @@
586 clock-names = "fck", "brg_int", "scif_clk"; 599 clock-names = "fck", "brg_int", "scif_clk";
587 dmas = <&dmac1 0x33>, <&dmac1 0x32>; 600 dmas = <&dmac1 0x33>, <&dmac1 0x32>;
588 dma-names = "tx", "rx"; 601 dma-names = "tx", "rx";
589 power-domains = <&cpg>; 602 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
590 status = "disabled"; 603 status = "disabled";
591 }; 604 };
592 605
@@ -602,7 +615,7 @@
602 clock-names = "fck", "brg_int", "scif_clk"; 615 clock-names = "fck", "brg_int", "scif_clk";
603 dmas = <&dmac1 0x35>, <&dmac1 0x34>; 616 dmas = <&dmac1 0x35>, <&dmac1 0x34>;
604 dma-names = "tx", "rx"; 617 dma-names = "tx", "rx";
605 power-domains = <&cpg>; 618 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
606 status = "disabled"; 619 status = "disabled";
607 }; 620 };
608 621
@@ -618,7 +631,7 @@
618 clock-names = "fck", "brg_int", "scif_clk"; 631 clock-names = "fck", "brg_int", "scif_clk";
619 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 632 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
620 dma-names = "tx", "rx"; 633 dma-names = "tx", "rx";
621 power-domains = <&cpg>; 634 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
622 status = "disabled"; 635 status = "disabled";
623 }; 636 };
624 637
@@ -634,7 +647,7 @@
634 clock-names = "fck", "brg_int", "scif_clk"; 647 clock-names = "fck", "brg_int", "scif_clk";
635 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 648 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
636 dma-names = "tx", "rx"; 649 dma-names = "tx", "rx";
637 power-domains = <&cpg>; 650 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
638 status = "disabled"; 651 status = "disabled";
639 }; 652 };
640 653
@@ -649,7 +662,7 @@
649 clock-names = "fck", "brg_int", "scif_clk"; 662 clock-names = "fck", "brg_int", "scif_clk";
650 dmas = <&dmac1 0x51>, <&dmac1 0x50>; 663 dmas = <&dmac1 0x51>, <&dmac1 0x50>;
651 dma-names = "tx", "rx"; 664 dma-names = "tx", "rx";
652 power-domains = <&cpg>; 665 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
653 status = "disabled"; 666 status = "disabled";
654 }; 667 };
655 668
@@ -664,7 +677,7 @@
664 clock-names = "fck", "brg_int", "scif_clk"; 677 clock-names = "fck", "brg_int", "scif_clk";
665 dmas = <&dmac1 0x53>, <&dmac1 0x52>; 678 dmas = <&dmac1 0x53>, <&dmac1 0x52>;
666 dma-names = "tx", "rx"; 679 dma-names = "tx", "rx";
667 power-domains = <&cpg>; 680 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
668 status = "disabled"; 681 status = "disabled";
669 }; 682 };
670 683
@@ -679,7 +692,7 @@
679 clock-names = "fck", "brg_int", "scif_clk"; 692 clock-names = "fck", "brg_int", "scif_clk";
680 dmas = <&dmac1 0x13>, <&dmac1 0x12>; 693 dmas = <&dmac1 0x13>, <&dmac1 0x12>;
681 dma-names = "tx", "rx"; 694 dma-names = "tx", "rx";
682 power-domains = <&cpg>; 695 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
683 status = "disabled"; 696 status = "disabled";
684 }; 697 };
685 698
@@ -694,7 +707,7 @@
694 clock-names = "fck", "brg_int", "scif_clk"; 707 clock-names = "fck", "brg_int", "scif_clk";
695 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 708 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
696 dma-names = "tx", "rx"; 709 dma-names = "tx", "rx";
697 power-domains = <&cpg>; 710 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
698 status = "disabled"; 711 status = "disabled";
699 }; 712 };
700 713
@@ -709,7 +722,7 @@
709 clock-names = "fck", "brg_int", "scif_clk"; 722 clock-names = "fck", "brg_int", "scif_clk";
710 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 723 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
711 dma-names = "tx", "rx"; 724 dma-names = "tx", "rx";
712 power-domains = <&cpg>; 725 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
713 status = "disabled"; 726 status = "disabled";
714 }; 727 };
715 728
@@ -724,7 +737,7 @@
724 clock-names = "fck", "brg_int", "scif_clk"; 737 clock-names = "fck", "brg_int", "scif_clk";
725 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>; 738 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>;
726 dma-names = "tx", "rx"; 739 dma-names = "tx", "rx";
727 power-domains = <&cpg>; 740 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
728 status = "disabled"; 741 status = "disabled";
729 }; 742 };
730 743
@@ -735,7 +748,7 @@
735 reg = <0 0xe6500000 0 0x40>; 748 reg = <0 0xe6500000 0 0x40>;
736 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 749 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&cpg CPG_MOD 931>; 750 clocks = <&cpg CPG_MOD 931>;
738 power-domains = <&cpg>; 751 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
739 i2c-scl-internal-delay-ns = <110>; 752 i2c-scl-internal-delay-ns = <110>;
740 status = "disabled"; 753 status = "disabled";
741 }; 754 };
@@ -747,7 +760,7 @@
747 reg = <0 0xe6508000 0 0x40>; 760 reg = <0 0xe6508000 0 0x40>;
748 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 761 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
749 clocks = <&cpg CPG_MOD 930>; 762 clocks = <&cpg CPG_MOD 930>;
750 power-domains = <&cpg>; 763 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
751 i2c-scl-internal-delay-ns = <6>; 764 i2c-scl-internal-delay-ns = <6>;
752 status = "disabled"; 765 status = "disabled";
753 }; 766 };
@@ -759,7 +772,7 @@
759 reg = <0 0xe6510000 0 0x40>; 772 reg = <0 0xe6510000 0 0x40>;
760 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 773 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
761 clocks = <&cpg CPG_MOD 929>; 774 clocks = <&cpg CPG_MOD 929>;
762 power-domains = <&cpg>; 775 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
763 i2c-scl-internal-delay-ns = <6>; 776 i2c-scl-internal-delay-ns = <6>;
764 status = "disabled"; 777 status = "disabled";
765 }; 778 };
@@ -771,7 +784,7 @@
771 reg = <0 0xe66d0000 0 0x40>; 784 reg = <0 0xe66d0000 0 0x40>;
772 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 785 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
773 clocks = <&cpg CPG_MOD 928>; 786 clocks = <&cpg CPG_MOD 928>;
774 power-domains = <&cpg>; 787 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
775 i2c-scl-internal-delay-ns = <110>; 788 i2c-scl-internal-delay-ns = <110>;
776 status = "disabled"; 789 status = "disabled";
777 }; 790 };
@@ -783,7 +796,7 @@
783 reg = <0 0xe66d8000 0 0x40>; 796 reg = <0 0xe66d8000 0 0x40>;
784 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 797 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
785 clocks = <&cpg CPG_MOD 927>; 798 clocks = <&cpg CPG_MOD 927>;
786 power-domains = <&cpg>; 799 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
787 i2c-scl-internal-delay-ns = <110>; 800 i2c-scl-internal-delay-ns = <110>;
788 status = "disabled"; 801 status = "disabled";
789 }; 802 };
@@ -795,7 +808,7 @@
795 reg = <0 0xe66e0000 0 0x40>; 808 reg = <0 0xe66e0000 0 0x40>;
796 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 809 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
797 clocks = <&cpg CPG_MOD 919>; 810 clocks = <&cpg CPG_MOD 919>;
798 power-domains = <&cpg>; 811 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
799 i2c-scl-internal-delay-ns = <110>; 812 i2c-scl-internal-delay-ns = <110>;
800 status = "disabled"; 813 status = "disabled";
801 }; 814 };
@@ -807,7 +820,7 @@
807 reg = <0 0xe66e8000 0 0x40>; 820 reg = <0 0xe66e8000 0 0x40>;
808 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 821 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
809 clocks = <&cpg CPG_MOD 918>; 822 clocks = <&cpg CPG_MOD 918>;
810 power-domains = <&cpg>; 823 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
811 i2c-scl-internal-delay-ns = <6>; 824 i2c-scl-internal-delay-ns = <6>;
812 status = "disabled"; 825 status = "disabled";
813 }; 826 };
@@ -857,7 +870,7 @@
857 "src.1", "src.0", 870 "src.1", "src.0",
858 "dvc.0", "dvc.1", 871 "dvc.0", "dvc.1",
859 "clk_a", "clk_b", "clk_c", "clk_i"; 872 "clk_a", "clk_b", "clk_c", "clk_i";
860 power-domains = <&cpg>; 873 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
861 status = "disabled"; 874 status = "disabled";
862 875
863 rcar_sound,dvc { 876 rcar_sound,dvc {
@@ -991,7 +1004,7 @@
991 reg = <0 0xee000000 0 0xc00>; 1004 reg = <0 0xee000000 0 0xc00>;
992 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1005 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
993 clocks = <&cpg CPG_MOD 328>; 1006 clocks = <&cpg CPG_MOD 328>;
994 power-domains = <&cpg>; 1007 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
995 status = "disabled"; 1008 status = "disabled";
996 }; 1009 };
997 1010
@@ -1000,7 +1013,7 @@
1000 reg = <0 0xee040000 0 0xc00>; 1013 reg = <0 0xee040000 0 0xc00>;
1001 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1014 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1002 clocks = <&cpg CPG_MOD 327>; 1015 clocks = <&cpg CPG_MOD 327>;
1003 power-domains = <&cpg>; 1016 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1004 status = "disabled"; 1017 status = "disabled";
1005 }; 1018 };
1006 1019
@@ -1012,7 +1025,7 @@
1012 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 1025 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1013 interrupt-names = "ch0", "ch1"; 1026 interrupt-names = "ch0", "ch1";
1014 clocks = <&cpg CPG_MOD 330>; 1027 clocks = <&cpg CPG_MOD 330>;
1015 power-domains = <&cpg>; 1028 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1016 #dma-cells = <1>; 1029 #dma-cells = <1>;
1017 dma-channels = <2>; 1030 dma-channels = <2>;
1018 }; 1031 };
@@ -1025,7 +1038,7 @@
1025 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 1038 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
1026 interrupt-names = "ch0", "ch1"; 1039 interrupt-names = "ch0", "ch1";
1027 clocks = <&cpg CPG_MOD 331>; 1040 clocks = <&cpg CPG_MOD 331>;
1028 power-domains = <&cpg>; 1041 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1029 #dma-cells = <1>; 1042 #dma-cells = <1>;
1030 dma-channels = <2>; 1043 dma-channels = <2>;
1031 }; 1044 };
@@ -1035,7 +1048,7 @@
1035 reg = <0 0xee100000 0 0x2000>; 1048 reg = <0 0xee100000 0 0x2000>;
1036 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1049 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1037 clocks = <&cpg CPG_MOD 314>; 1050 clocks = <&cpg CPG_MOD 314>;
1038 power-domains = <&cpg>; 1051 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1039 status = "disabled"; 1052 status = "disabled";
1040 }; 1053 };
1041 1054
@@ -1044,7 +1057,7 @@
1044 reg = <0 0xee120000 0 0x2000>; 1057 reg = <0 0xee120000 0 0x2000>;
1045 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1058 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1046 clocks = <&cpg CPG_MOD 313>; 1059 clocks = <&cpg CPG_MOD 313>;
1047 power-domains = <&cpg>; 1060 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1048 status = "disabled"; 1061 status = "disabled";
1049 }; 1062 };
1050 1063
@@ -1053,7 +1066,7 @@
1053 reg = <0 0xee140000 0 0x2000>; 1066 reg = <0 0xee140000 0 0x2000>;
1054 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1067 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1055 clocks = <&cpg CPG_MOD 312>; 1068 clocks = <&cpg CPG_MOD 312>;
1056 power-domains = <&cpg>; 1069 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1057 cap-mmc-highspeed; 1070 cap-mmc-highspeed;
1058 status = "disabled"; 1071 status = "disabled";
1059 }; 1072 };
@@ -1063,7 +1076,7 @@
1063 reg = <0 0xee160000 0 0x2000>; 1076 reg = <0 0xee160000 0 0x2000>;
1064 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1077 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1065 clocks = <&cpg CPG_MOD 311>; 1078 clocks = <&cpg CPG_MOD 311>;
1066 power-domains = <&cpg>; 1079 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1067 cap-mmc-highspeed; 1080 cap-mmc-highspeed;
1068 status = "disabled"; 1081 status = "disabled";
1069 }; 1082 };
@@ -1073,7 +1086,7 @@
1073 reg = <0 0xee080200 0 0x700>; 1086 reg = <0 0xee080200 0 0x700>;
1074 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1087 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1075 clocks = <&cpg CPG_MOD 703>; 1088 clocks = <&cpg CPG_MOD 703>;
1076 power-domains = <&cpg>; 1089 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1077 #phy-cells = <0>; 1090 #phy-cells = <0>;
1078 status = "disabled"; 1091 status = "disabled";
1079 }; 1092 };
@@ -1082,7 +1095,7 @@
1082 compatible = "renesas,usb2-phy-r8a7795"; 1095 compatible = "renesas,usb2-phy-r8a7795";
1083 reg = <0 0xee0a0200 0 0x700>; 1096 reg = <0 0xee0a0200 0 0x700>;
1084 clocks = <&cpg CPG_MOD 702>; 1097 clocks = <&cpg CPG_MOD 702>;
1085 power-domains = <&cpg>; 1098 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1086 #phy-cells = <0>; 1099 #phy-cells = <0>;
1087 status = "disabled"; 1100 status = "disabled";
1088 }; 1101 };
@@ -1091,7 +1104,7 @@
1091 compatible = "renesas,usb2-phy-r8a7795"; 1104 compatible = "renesas,usb2-phy-r8a7795";
1092 reg = <0 0xee0c0200 0 0x700>; 1105 reg = <0 0xee0c0200 0 0x700>;
1093 clocks = <&cpg CPG_MOD 701>; 1106 clocks = <&cpg CPG_MOD 701>;
1094 power-domains = <&cpg>; 1107 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1095 #phy-cells = <0>; 1108 #phy-cells = <0>;
1096 status = "disabled"; 1109 status = "disabled";
1097 }; 1110 };
@@ -1103,7 +1116,7 @@
1103 clocks = <&cpg CPG_MOD 703>; 1116 clocks = <&cpg CPG_MOD 703>;
1104 phys = <&usb2_phy0>; 1117 phys = <&usb2_phy0>;
1105 phy-names = "usb"; 1118 phy-names = "usb";
1106 power-domains = <&cpg>; 1119 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1107 status = "disabled"; 1120 status = "disabled";
1108 }; 1121 };
1109 1122
@@ -1114,7 +1127,7 @@
1114 clocks = <&cpg CPG_MOD 702>; 1127 clocks = <&cpg CPG_MOD 702>;
1115 phys = <&usb2_phy1>; 1128 phys = <&usb2_phy1>;
1116 phy-names = "usb"; 1129 phy-names = "usb";
1117 power-domains = <&cpg>; 1130 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1118 status = "disabled"; 1131 status = "disabled";
1119 }; 1132 };
1120 1133
@@ -1125,7 +1138,7 @@
1125 clocks = <&cpg CPG_MOD 701>; 1138 clocks = <&cpg CPG_MOD 701>;
1126 phys = <&usb2_phy2>; 1139 phys = <&usb2_phy2>;
1127 phy-names = "usb"; 1140 phy-names = "usb";
1128 power-domains = <&cpg>; 1141 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1129 status = "disabled"; 1142 status = "disabled";
1130 }; 1143 };
1131 1144
@@ -1136,7 +1149,7 @@
1136 clocks = <&cpg CPG_MOD 703>; 1149 clocks = <&cpg CPG_MOD 703>;
1137 phys = <&usb2_phy0>; 1150 phys = <&usb2_phy0>;
1138 phy-names = "usb"; 1151 phy-names = "usb";
1139 power-domains = <&cpg>; 1152 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1140 status = "disabled"; 1153 status = "disabled";
1141 }; 1154 };
1142 1155
@@ -1147,7 +1160,7 @@
1147 clocks = <&cpg CPG_MOD 702>; 1160 clocks = <&cpg CPG_MOD 702>;
1148 phys = <&usb2_phy1>; 1161 phys = <&usb2_phy1>;
1149 phy-names = "usb"; 1162 phy-names = "usb";
1150 power-domains = <&cpg>; 1163 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1151 status = "disabled"; 1164 status = "disabled";
1152 }; 1165 };
1153 1166
@@ -1158,7 +1171,7 @@
1158 clocks = <&cpg CPG_MOD 701>; 1171 clocks = <&cpg CPG_MOD 701>;
1159 phys = <&usb2_phy2>; 1172 phys = <&usb2_phy2>;
1160 phy-names = "usb"; 1173 phy-names = "usb";
1161 power-domains = <&cpg>; 1174 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1162 status = "disabled"; 1175 status = "disabled";
1163 }; 1176 };
1164 pciec0: pcie@fe000000 { 1177 pciec0: pcie@fe000000 {
@@ -1182,7 +1195,7 @@
1182 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1195 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1183 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 1196 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1184 clock-names = "pcie", "pcie_bus"; 1197 clock-names = "pcie", "pcie_bus";
1185 power-domains = <&cpg>; 1198 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1186 status = "disabled"; 1199 status = "disabled";
1187 }; 1200 };
1188 1201
@@ -1207,7 +1220,7 @@
1207 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1220 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1208 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; 1221 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
1209 clock-names = "pcie", "pcie_bus"; 1222 clock-names = "pcie", "pcie_bus";
1210 power-domains = <&cpg>; 1223 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
1211 status = "disabled"; 1224 status = "disabled";
1212 }; 1225 };
1213 }; 1226 };
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-30 19:05:27 -0400