Merge tag 'samsung-dt-devfreq-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/late

Merge "ARM: dts: exynos: Devfreq for v4.7: from Krzysztof Kozłowski:

Topic branch for Device Tree changes adding new generic devfreq driver, for
v4.7:
1. Add bus nodes for Exynos3250, Exynos4x12, Exynos4210 and Exynos542x.
2. Split out common PPMU (Performance Monitoring Unit) nodes into separate
   DTSI. The PPMU provides performance data for devfreq.
3. Add NoCP (Network on Chip Probe) node for Exynos542x. On this SoC, like PPMU
   on older designs, provides performance data for devfreq.
4. Enable DFVS (Dynamic Voltage and Frequency Scaling) on boards:
   - Exynos3250 Rinato,
   - Exynos4412 Odroid-X/X2/U3 and Trats2,
   - Exynos5422 Odroid XU3/XU3-Lite/XU4.

* tag 'samsung-dt-devfreq-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  ARM: dts: exynos: Add support of Bus frequency using VDD_INT for exynos5422-odroidxu3
  ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos542x SoC
  ARM: dts: exynos: Add NoC Probe dt node for Exynos542x SoC
  ARM: dts: exynos: Add support of bus frequency for exynos4412-trats/odroidu3
  ARM: dts: exynos: Expand the voltage range of buck1/3 regulator for exynos4412-odroidu3
  ARM: dts: exynos: Add support of bus frequency using VDD_INT for exynos3250-rinato
  ARM: dts: exynos: Add exynos4412-ppmu-common dtsi to delete duplicate PPMU nodes
  ARM: dts: exynos: Add bus nodes using VDD_MIF for Exynos4210
  ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos4x12
  ARM: dts: exynos: Add bus nodes using VDD_MIF for Exynos4x12
  ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos3250
  ARM: dts: exynos: Add DMC bus frequency for exynos3250-rinato/monk
  ARM: dts: exynos: Add DMC bus node for Exynos3250
  clk: samsung: exynos542x: Add the clock id for ACLK
  dt-bindings: clock: Add the clock id for ACLK clock of Exynos542x SoC

12 files changed, 1295 insertions, 155 deletions

diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts
index 9e2840b59ae8..fbe09d640c9a 100644
--- a/arch/arm/boot/dts/exynos3250-monk.dts
+++ b/arch/arm/boot/dts/exynos3250-monk.dts
@@ -14,6 +14,7 @@
 
 /dts-v1/;
 #include "exynos3250.dtsi"
+#include "exynos4412-ppmu-common.dtsi"
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/clock/samsung,s2mps11.h>
@@ -156,6 +157,12 @@
         };
 };
 
+&bus_dmc {
+        devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
+        vdd-supply = <&buck1_reg>;
+        status = "okay";
+};
+
 &cpu0 {
         cpu0-supply = <&buck2_reg>;
 };
@@ -458,46 +465,6 @@
         status = "okay";
 };
 
-&ppmu_dmc0 {
-        status = "okay";
-
-        events {
-                ppmu_dmc0_3: ppmu-event3-dmc0 {
-                        event-name = "ppmu-event3-dmc0";
-                };
-        };
-};
-
-&ppmu_dmc1 {
-        status = "okay";
-
-        events {
-                ppmu_dmc1_3: ppmu-event3-dmc1 {
-                        event-name = "ppmu-event3-dmc1";
-                };
-        };
-};
-
-&ppmu_leftbus {
-        status = "okay";
-
-        events {
-                ppmu_leftbus_3: ppmu-event3-leftbus {
-                        event-name = "ppmu-event3-leftbus";
-                };
-        };
-};
-
-&ppmu_rightbus {
-        status = "okay";
-
-        events {
-                ppmu_rightbus_3: ppmu-event3-rightbus {
-                        event-name = "ppmu-event3-rightbus";
-                };
-        };
-};
-
 &xusbxti {
         clock-frequency = <24000000>;
 };
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts
index 1f102f3a1ab1..09444897b416 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -14,6 +14,7 @@
 
 /dts-v1/;
 #include "exynos3250.dtsi"
+#include "exynos4412-ppmu-common.dtsi"
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/clock/samsung,s2mps11.h>
@@ -147,6 +148,53 @@
         };
 };
 
+&bus_dmc {
+        devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
+        vdd-supply = <&buck1_reg>;
+        status = "okay";
+};
+
+&bus_leftbus {
+        devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
+        vdd-supply = <&buck3_reg>;
+        status = "okay";
+};
+
+&bus_rightbus {
+        devfreq = <&bus_leftbus>;
+        status = "okay";
+};
+
+&bus_lcd0 {
+        devfreq = <&bus_leftbus>;
+        status = "okay";
+};
+
+&bus_fsys {
+        devfreq = <&bus_leftbus>;
+        status = "okay";
+};
+
+&bus_mcuisp {
+        devfreq = <&bus_leftbus>;
+        status = "okay";
+};
+
+&bus_isp {
+        devfreq = <&bus_leftbus>;
+        status = "okay";
+};
+
+&bus_peril {
+        devfreq = <&bus_leftbus>;
+        status = "okay";
+};
+
+&bus_mfc {
+        devfreq = <&bus_leftbus>;
+        status = "okay";
+};
+
 &cpu0 {
         cpu0-supply = <&buck2_reg>;
 };
@@ -635,46 +683,6 @@
         status = "okay";
 };
 
-&ppmu_dmc0 {
-        status = "okay";
-
-        events {
-                ppmu_dmc0_3: ppmu-event3-dmc0 {
-                        event-name = "ppmu-event3-dmc0";
-                };
-        };
-};
-
-&ppmu_dmc1 {
-        status = "okay";
-
-        events {
-                ppmu_dmc1_3: ppmu-event3-dmc1 {
-                        event-name = "ppmu-event3-dmc1";
-                };
-        };
-};
-
-&ppmu_leftbus {
-        status = "okay";
-
-        events {
-                ppmu_leftbus_3: ppmu-event3-leftbus {
-                        event-name = "ppmu-event3-leftbus";
-                };
-        };
-};
-
-&ppmu_rightbus {
-        status = "okay";
-
-        events {
-                ppmu_rightbus_3: ppmu-event3-rightbus {
-                        event-name = "ppmu-event3-rightbus";
-                };
-        };
-};
-
 &xusbxti {
         clock-frequency = <24000000>;
 };
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 137f9015d4e8..b5157492a422 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -688,6 +688,187 @@
                         clock-names = "ppmu";
                         status = "disabled";
                 };
+
+                bus_dmc: bus_dmc {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&cmu_dmc CLK_DIV_DMC>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_dmc_opp_table>;
+                        status = "disabled";
+                };
+
+                bus_dmc_opp_table: opp_table1 {
+                        compatible = "operating-points-v2";
+                        opp-shared;
+
+                        opp@50000000 {
+                                opp-hz = /bits/ 64 <50000000>;
+                                opp-microvolt = <800000>;
+                        };
+                        opp@100000000 {
+                                opp-hz = /bits/ 64 <100000000>;
+                                opp-microvolt = <800000>;
+                        };
+                        opp@134000000 {
+                                opp-hz = /bits/ 64 <134000000>;
+                                opp-microvolt = <800000>;
+                        };
+                        opp@200000000 {
+                                opp-hz = /bits/ 64 <200000000>;
+                                opp-microvolt = <825000>;
+                        };
+                        opp@400000000 {
+                                opp-hz = /bits/ 64 <400000000>;
+                                opp-microvolt = <875000>;
+                        };
+                };
+
+                bus_leftbus: bus_leftbus {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&cmu CLK_DIV_GDL>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_leftbus_opp_table>;
+                        status = "disabled";
+                };
+
+                bus_rightbus: bus_rightbus {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&cmu CLK_DIV_GDR>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_leftbus_opp_table>;
+                        status = "disabled";
+                };
+
+                bus_lcd0: bus_lcd0 {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&cmu CLK_DIV_ACLK_160>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_leftbus_opp_table>;
+                        status = "disabled";
+                };
+
+                bus_fsys: bus_fsys {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&cmu CLK_DIV_ACLK_200>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_leftbus_opp_table>;
+                        status = "disabled";
+                };
+
+                bus_mcuisp: bus_mcuisp {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_mcuisp_opp_table>;
+                        status = "disabled";
+                };
+
+                bus_isp: bus_isp {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&cmu CLK_DIV_ACLK_266>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_isp_opp_table>;
+                        status = "disabled";
+                };
+
+                bus_peril: bus_peril {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&cmu CLK_DIV_ACLK_100>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_peril_opp_table>;
+                        status = "disabled";
+                };
+
+                bus_mfc: bus_mfc {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&cmu CLK_SCLK_MFC>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_leftbus_opp_table>;
+                        status = "disabled";
+                };
+
+                bus_leftbus_opp_table: opp_table2 {
+                        compatible = "operating-points-v2";
+                        opp-shared;
+
+                        opp@50000000 {
+                                opp-hz = /bits/ 64 <50000000>;
+                                opp-microvolt = <900000>;
+                        };
+                        opp@80000000 {
+                                opp-hz = /bits/ 64 <80000000>;
+                                opp-microvolt = <900000>;
+                        };
+                        opp@100000000 {
+                                opp-hz = /bits/ 64 <100000000>;
+                                opp-microvolt = <1000000>;
+                        };
+                        opp@134000000 {
+                                opp-hz = /bits/ 64 <134000000>;
+                                opp-microvolt = <1000000>;
+                        };
+                        opp@200000000 {
+                                opp-hz = /bits/ 64 <200000000>;
+                                opp-microvolt = <1000000>;
+                        };
+                };
+
+                bus_mcuisp_opp_table: opp_table3 {
+                        compatible = "operating-points-v2";
+                        opp-shared;
+
+                        opp@50000000 {
+                                opp-hz = /bits/ 64 <50000000>;
+                        };
+                        opp@80000000 {
+                                opp-hz = /bits/ 64 <80000000>;
+                        };
+                        opp@100000000 {
+                                opp-hz = /bits/ 64 <100000000>;
+                        };
+                        opp@200000000 {
+                                opp-hz = /bits/ 64 <200000000>;
+                        };
+                        opp@400000000 {
+                                opp-hz = /bits/ 64 <400000000>;
+                        };
+                };
+
+                bus_isp_opp_table: opp_table4 {
+                        compatible = "operating-points-v2";
+                        opp-shared;
+
+                        opp@50000000 {
+                                opp-hz = /bits/ 64 <50000000>;
+                        };
+                        opp@80000000 {
+                                opp-hz = /bits/ 64 <80000000>;
+                        };
+                        opp@100000000 {
+                                opp-hz = /bits/ 64 <100000000>;
+                        };
+                        opp@200000000 {
+                                opp-hz = /bits/ 64 <200000000>;
+                        };
+                        opp@300000000 {
+                                opp-hz = /bits/ 64 <300000000>;
+                        };
+                };
+
+                bus_peril_opp_table: opp_table5 {
+                        compatible = "operating-points-v2";
+                        opp-shared;
+
+                        opp@50000000 {
+                                opp-hz = /bits/ 64 <50000000>;
+                        };
+                        opp@80000000 {
+                                opp-hz = /bits/ 64 <80000000>;
+                        };
+                        opp@100000000 {
+                                opp-hz = /bits/ 64 <100000000>;
+                        };
+                };
         };
 };
 
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index c1cb8df6da07..2d9b02967105 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -257,6 +257,165 @@
                 power-domains = <&pd_lcd1>;
                 #iommu-cells = <0>;
         };
+
+        bus_dmc: bus_dmc {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_DIV_DMC>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_dmc_opp_table>;
+                status = "disabled";
+        };
+
+        bus_acp: bus_acp {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_DIV_ACP>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_acp_opp_table>;
+                status = "disabled";
+        };
+
+        bus_peri: bus_peri {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_ACLK100>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_peri_opp_table>;
+                status = "disabled";
+        };
+
+        bus_fsys: bus_fsys {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_ACLK133>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_fsys_opp_table>;
+                status = "disabled";
+        };
+
+        bus_display: bus_display {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_ACLK160>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_display_opp_table>;
+                status = "disabled";
+        };
+
+        bus_lcd0: bus_lcd0 {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_ACLK200>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_leftbus_opp_table>;
+                status = "disabled";
+        };
+
+        bus_leftbus: bus_leftbus {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_DIV_GDL>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_leftbus_opp_table>;
+                status = "disabled";
+        };
+
+        bus_rightbus: bus_rightbus {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_DIV_GDR>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_leftbus_opp_table>;
+                status = "disabled";
+        };
+
+        bus_mfc: bus_mfc {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_SCLK_MFC>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_leftbus_opp_table>;
+                status = "disabled";
+        };
+
+        bus_dmc_opp_table: opp_table1 {
+                compatible = "operating-points-v2";
+                opp-shared;
+
+                opp@134000000 {
+                        opp-hz = /bits/ 64 <134000000>;
+                        opp-microvolt = <1025000>;
+                };
+                opp@267000000 {
+                        opp-hz = /bits/ 64 <267000000>;
+                        opp-microvolt = <1050000>;
+                };
+                opp@400000000 {
+                        opp-hz = /bits/ 64 <400000000>;
+                        opp-microvolt = <1150000>;
+                };
+        };
+
+        bus_acp_opp_table: opp_table2 {
+                compatible = "operating-points-v2";
+                opp-shared;
+
+                opp@134000000 {
+                        opp-hz = /bits/ 64 <134000000>;
+                };
+                opp@160000000 {
+                        opp-hz = /bits/ 64 <160000000>;
+                };
+                opp@200000000 {
+                        opp-hz = /bits/ 64 <200000000>;
+                };
+        };
+
+        bus_peri_opp_table: opp_table3 {
+                compatible = "operating-points-v2";
+                opp-shared;
+
+                opp@5000000 {
+                        opp-hz = /bits/ 64 <5000000>;
+                };
+                opp@100000000 {
+                        opp-hz = /bits/ 64 <100000000>;
+                };
+        };
+
+        bus_fsys_opp_table: opp_table4 {
+                compatible = "operating-points-v2";
+                opp-shared;
+
+                opp@10000000 {
+                        opp-hz = /bits/ 64 <10000000>;
+                };
+                opp@134000000 {
+                        opp-hz = /bits/ 64 <134000000>;
+                };
+        };
+
+        bus_display_opp_table: opp_table5 {
+                compatible = "operating-points-v2";
+                opp-shared;
+
+                opp@100000000 {
+                        opp-hz = /bits/ 64 <100000000>;
+                };
+                opp@134000000 {
+                        opp-hz = /bits/ 64 <134000000>;
+                };
+                opp@160000000 {
+                        opp-hz = /bits/ 64 <160000000>;
+                };
+        };
+
+        bus_leftbus_opp_table: opp_table6 {
+                compatible = "operating-points-v2";
+                opp-shared;
+
+                opp@100000000 {
+                        opp-hz = /bits/ 64 <100000000>;
+                };
+                opp@160000000 {
+                        opp-hz = /bits/ 64 <160000000>;
+                };
+                opp@200000000 {
+                        opp-hz = /bits/ 64 <200000000>;
+                };
+        };
 };
 
 &gic {
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index 5e5d3fecb04c..2015f10071f9 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -11,6 +11,7 @@
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/clock/maxim,max77686.h>
 #include "exynos4412.dtsi"
+#include "exynos4412-ppmu-common.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 
 / {
@@ -108,6 +109,53 @@
         };
 };
 
+&bus_dmc {
+        devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
+        vdd-supply = <&buck1_reg>;
+        status = "okay";
+};
+
+&bus_acp {
+        devfreq = <&bus_dmc>;
+        status = "okay";
+};
+
+&bus_c2c {
+        devfreq = <&bus_dmc>;
+        status = "okay";
+};
+
+&bus_leftbus {
+        devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
+        vdd-supply = <&buck3_reg>;
+        status = "okay";
+};
+
+&bus_rightbus {
+        devfreq = <&bus_leftbus>;
+        status = "okay";
+};
+
+&bus_display {
+        devfreq = <&bus_leftbus>;
+        status = "okay";
+};
+
+&bus_fsys {
+        devfreq = <&bus_leftbus>;
+        status = "okay";
+};
+
+&bus_peri {
+        devfreq = <&bus_leftbus>;
+        status = "okay";
+};
+
+&bus_mfc {
+        devfreq = <&bus_leftbus>;
+        status = "okay";
+};
+
 &cpu0 {
         cpu0-supply = <&buck2_reg>;
 };
@@ -355,8 +403,8 @@
 
                         buck1_reg: BUCK1 {
                                 regulator-name = "vdd_mif";
-                                regulator-min-microvolt = <1000000>;
-                                regulator-max-microvolt = <1000000>;
+                                regulator-min-microvolt = <900000>;
+                                regulator-max-microvolt = <1100000>;
                                 regulator-always-on;
                                 regulator-boot-on;
                         };
@@ -371,8 +419,8 @@
 
                         buck3_reg: BUCK3 {
                                 regulator-name = "vdd_int";
-                                regulator-min-microvolt = <1000000>;
-                                regulator-max-microvolt = <1000000>;
+                                regulator-min-microvolt = <900000>;
+                                regulator-max-microvolt = <1050000>;
                                 regulator-always-on;
                                 regulator-boot-on;
                         };
diff --git a/arch/arm/boot/dts/exynos4412-ppmu-common.dtsi b/arch/arm/boot/dts/exynos4412-ppmu-common.dtsi
new file mode 100644
index 000000000000..16e4b77d8cb1
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-ppmu-common.dtsi
@@ -0,0 +1,50 @@
+/*
+ * Device tree sources for Exynos4412 PPMU common device tree
+ *
+ * Copyright (C) 2015 Samsung Electronics
+ * Author: Chanwoo Choi <cw00.choi@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+&ppmu_dmc0 {
+       status = "okay";
+
+       events {
+               ppmu_dmc0_3: ppmu-event3-dmc0 {
+                       event-name = "ppmu-event3-dmc0";
+               };
+       };
+};
+
+&ppmu_dmc1 {
+       status = "okay";
+
+       events {
+               ppmu_dmc1_3: ppmu-event3-dmc1 {
+                       event-name = "ppmu-event3-dmc1";
+               };
+       };
+};
+
+&ppmu_leftbus {
+       status = "okay";
+
+       events {
+               ppmu_leftbus_3: ppmu-event3-leftbus {
+                       event-name = "ppmu-event3-leftbus";
+               };
+       };
+};
+
+&ppmu_rightbus {
+       status = "okay";
+
+       events {
+               ppmu_rightbus_3: ppmu-event3-rightbus {
+                       event-name = "ppmu-event3-rightbus";
+               };
+       };
+};
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index ed017cc7b14f..9f3fb9a7f5f4 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -14,6 +14,7 @@
 
 /dts-v1/;
 #include "exynos4412.dtsi"
+#include "exynos4412-ppmu-common.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/clock/maxim,max77686.h>
@@ -288,6 +289,53 @@
         status = "okay";
 };
 
+&bus_dmc {
+        devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
+        vdd-supply = <&buck1_reg>;
+        status = "okay";
+};
+
+&bus_acp {
+        devfreq = <&bus_dmc>;
+        status = "okay";
+};
+
+&bus_c2c {
+        devfreq = <&bus_dmc>;
+        status = "okay";
+};
+
+&bus_leftbus {
+        devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
+        vdd-supply = <&buck3_reg>;
+        status = "okay";
+};
+
+&bus_rightbus {
+        devfreq = <&bus_leftbus>;
+        status = "okay";
+};
+
+&bus_display {
+        devfreq = <&bus_leftbus>;
+        status = "okay";
+};
+
+&bus_fsys {
+        devfreq = <&bus_leftbus>;
+        status = "okay";
+};
+
+&bus_peri {
+        devfreq = <&bus_leftbus>;
+        status = "okay";
+};
+
+&bus_mfc {
+        devfreq = <&bus_leftbus>;
+        status = "okay";
+};
+
 &cpu0 {
         cpu0-supply = <&buck2_reg>;
 };
@@ -871,46 +919,6 @@
         assigned-clock-parents =  <&clock CLK_XUSBXTI>;
 };
 
-&ppmu_dmc0 {
-        status = "okay";
-
-        events {
-                ppmu_dmc0_3: ppmu-event3-dmc0 {
-                        event-name = "ppmu-event3-dmc0";
-                };
-        };
-};
-
-&ppmu_dmc1 {
-        status = "okay";
-
-        events {
-                ppmu_dmc1_3: ppmu-event3-dmc1 {
-                        event-name = "ppmu-event3-dmc1";
-                };
-        };
-};
-
-&ppmu_leftbus {
-        status = "okay";
-
-        events {
-                ppmu_leftbus_3: ppmu-event3-leftbus {
-                        event-name = "ppmu-event3-leftbus";
-                };
-        };
-};
-
-&ppmu_rightbus {
-        status = "okay";
-
-        events {
-                ppmu_rightbus_3: ppmu-event3-rightbus {
-                        event-name = "ppmu-event3-rightbus";
-                };
-        };
-};
-
 &pinctrl_0 {
         pinctrl-names = "default";
         pinctrl-0 = <&sleep0>;
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 84a23f962946..e5173107ed44 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -281,6 +281,180 @@
                 clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>;
                 #iommu-cells = <0>;
         };
+
+        bus_dmc: bus_dmc {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_DIV_DMC>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_dmc_opp_table>;
+                status = "disabled";
+        };
+
+        bus_acp: bus_acp {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_DIV_ACP>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_acp_opp_table>;
+                status = "disabled";
+        };
+
+        bus_c2c: bus_c2c {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_DIV_C2C>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_dmc_opp_table>;
+                status = "disabled";
+        };
+
+        bus_dmc_opp_table: opp_table1 {
+                compatible = "operating-points-v2";
+                opp-shared;
+
+                opp@100000000 {
+                        opp-hz = /bits/ 64 <100000000>;
+                        opp-microvolt = <900000>;
+                };
+                opp@134000000 {
+                        opp-hz = /bits/ 64 <134000000>;
+                        opp-microvolt = <900000>;
+                };
+                opp@160000000 {
+                        opp-hz = /bits/ 64 <160000000>;
+                        opp-microvolt = <900000>;
+                };
+                opp@267000000 {
+                        opp-hz = /bits/ 64 <267000000>;
+                        opp-microvolt = <950000>;
+                };
+                opp@400000000 {
+                        opp-hz = /bits/ 64 <400000000>;
+                        opp-microvolt = <1050000>;
+                };
+        };
+
+        bus_acp_opp_table: opp_table2 {
+                compatible = "operating-points-v2";
+                opp-shared;
+
+                opp@100000000 {
+                        opp-hz = /bits/ 64 <100000000>;
+                };
+                opp@134000000 {
+                        opp-hz = /bits/ 64 <134000000>;
+                };
+                opp@160000000 {
+                        opp-hz = /bits/ 64 <160000000>;
+                };
+                opp@267000000 {
+                        opp-hz = /bits/ 64 <267000000>;
+                };
+        };
+
+        bus_leftbus: bus_leftbus {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_DIV_GDL>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_leftbus_opp_table>;
+                status = "disabled";
+        };
+
+        bus_rightbus: bus_rightbus {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_DIV_GDR>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_leftbus_opp_table>;
+                status = "disabled";
+        };
+
+        bus_display: bus_display {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_ACLK160>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_display_opp_table>;
+                status = "disabled";
+        };
+
+        bus_fsys: bus_fsys {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_ACLK133>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_fsys_opp_table>;
+                status = "disabled";
+        };
+
+        bus_peri: bus_peri {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_ACLK100>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_peri_opp_table>;
+                status = "disabled";
+        };
+
+        bus_mfc: bus_mfc {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_SCLK_MFC>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_leftbus_opp_table>;
+                status = "disabled";
+        };
+
+        bus_leftbus_opp_table: opp_table3 {
+                compatible = "operating-points-v2";
+                opp-shared;
+
+                opp@100000000 {
+                        opp-hz = /bits/ 64 <100000000>;
+                        opp-microvolt = <900000>;
+                };
+                opp@134000000 {
+                        opp-hz = /bits/ 64 <134000000>;
+                        opp-microvolt = <925000>;
+                };
+                opp@160000000 {
+                        opp-hz = /bits/ 64 <160000000>;
+                        opp-microvolt = <950000>;
+                };
+                opp@200000000 {
+                        opp-hz = /bits/ 64 <200000000>;
+                        opp-microvolt = <1000000>;
+                };
+        };
+
+        bus_display_opp_table: opp_table4 {
+                compatible = "operating-points-v2";
+                opp-shared;
+
+                opp@160000000 {
+                        opp-hz = /bits/ 64 <160000000>;
+                };
+                opp@200000000 {
+                        opp-hz = /bits/ 64 <200000000>;
+                };
+        };
+
+        bus_fsys_opp_table: opp_table5 {
+                compatible = "operating-points-v2";
+                opp-shared;
+
+                opp@100000000 {
+                        opp-hz = /bits/ 64 <100000000>;
+                };
+                opp@134000000 {
+                        opp-hz = /bits/ 64 <134000000>;
+                };
+        };
+
+        bus_peri_opp_table: opp_table6 {
+                compatible = "operating-points-v2";
+                opp-shared;
+
+                opp@50000000 {
+                        opp-hz = /bits/ 64 <50000000>;
+                };
+                opp@100000000 {
+                        opp-hz = /bits/ 64 <100000000>;
+                };
+        };
 };
 
 &combiner {
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 7b99cb58d82d..18888b5d2f8c 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -294,6 +294,42 @@
                 };
         };
 
+        nocp_mem0_0: nocp@10CA1000 {
+                compatible = "samsung,exynos5420-nocp";
+                reg = <0x10CA1000 0x200>;
+                status = "disabled";
+        };
+
+        nocp_mem0_1: nocp@10CA1400 {
+                compatible = "samsung,exynos5420-nocp";
+                reg = <0x10CA1400 0x200>;
+                status = "disabled";
+        };
+
+        nocp_mem1_0: nocp@10CA1800 {
+                compatible = "samsung,exynos5420-nocp";
+                reg = <0x10CA1800 0x200>;
+                status = "disabled";
+        };
+
+        nocp_mem1_1: nocp@10CA1C00 {
+                compatible = "samsung,exynos5420-nocp";
+                reg = <0x10CA1C00 0x200>;
+                status = "disabled";
+        };
+
+        nocp_g3d_0: nocp@11A51000 {
+                compatible = "samsung,exynos5420-nocp";
+                reg = <0x11A51000 0x200>;
+                status = "disabled";
+        };
+
+        nocp_g3d_1: nocp@11A51400 {
+                compatible = "samsung,exynos5420-nocp";
+                reg = <0x11A51400 0x200>;
+                status = "disabled";
+        };
+
         gsc_pd: power-domain@10044000 {
                 compatible = "samsung,exynos4210-pd";
                 reg = <0x10044000 0x20>;
@@ -1188,6 +1224,377 @@
                 power-domains = <&disp_pd>;
                 #iommu-cells = <0>;
         };
+
+        bus_wcore: bus_wcore {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_wcore_opp_table>;
+                status = "disabled";
+        };
+
+        bus_noc: bus_noc {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_DOUT_ACLK100_NOC>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_noc_opp_table>;
+                status = "disabled";
+        };
+
+        bus_fsys_apb: bus_fsys_apb {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_fsys_apb_opp_table>;
+                status = "disabled";
+        };
+
+        bus_fsys: bus_fsys {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_fsys_apb_opp_table>;
+                status = "disabled";
+        };
+
+        bus_fsys2: bus_fsys2 {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_fsys2_opp_table>;
+                status = "disabled";
+        };
+
+        bus_mfc: bus_mfc {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_DOUT_ACLK333>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_mfc_opp_table>;
+                status = "disabled";
+        };
+
+        bus_gen: bus_gen {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_DOUT_ACLK266>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_gen_opp_table>;
+                status = "disabled";
+        };
+
+        bus_peri: bus_peri {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_DOUT_ACLK66>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_peri_opp_table>;
+                status = "disabled";
+        };
+
+        bus_g2d: bus_g2d {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_DOUT_ACLK333_G2D>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_g2d_opp_table>;
+                status = "disabled";
+        };
+
+        bus_g2d_acp: bus_g2d_acp {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_DOUT_ACLK266_G2D>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_g2d_acp_opp_table>;
+                status = "disabled";
+        };
+
+        bus_jpeg: bus_jpeg {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_jpeg_opp_table>;
+                status = "disabled";
+        };
+
+        bus_jpeg_apb: bus_jpeg_apb {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_DOUT_ACLK166>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_jpeg_apb_opp_table>;
+                status = "disabled";
+        };
+
+        bus_disp1_fimd: bus_disp1_fimd {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_disp1_fimd_opp_table>;
+                status = "disabled";
+        };
+
+        bus_disp1: bus_disp1 {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_disp1_opp_table>;
+                status = "disabled";
+        };
+
+        bus_gscl_scaler: bus_gscl_scaler {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_gscl_opp_table>;
+                status = "disabled";
+        };
+
+        bus_mscl: bus_mscl {
+                compatible = "samsung,exynos-bus";
+                clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
+                clock-names = "bus";
+                operating-points-v2 = <&bus_mscl_opp_table>;
+                status = "disabled";
+        };
+
+        bus_wcore_opp_table: opp_table2 {
+                compatible = "operating-points-v2";
+
+                opp00 {
+                        opp-hz = /bits/ 64 <84000000>;
+                        opp-microvolt = <925000>;
+                };
+                opp01 {
+                        opp-hz = /bits/ 64 <111000000>;
+                        opp-microvolt = <950000>;
+                };
+                opp02 {
+                        opp-hz = /bits/ 64 <222000000>;
+                        opp-microvolt = <950000>;
+                };
+                opp03 {
+                        opp-hz = /bits/ 64 <333000000>;
+                        opp-microvolt = <950000>;
+                };
+                opp04 {
+                        opp-hz = /bits/ 64 <400000000>;
+                        opp-microvolt = <987500>;
+                };
+        };
+
+        bus_noc_opp_table: opp_table3 {
+                compatible = "operating-points-v2";
+
+                opp00 {
+                        opp-hz = /bits/ 64 <67000000>;
+                };
+                opp01 {
+                        opp-hz = /bits/ 64 <75000000>;
+                };
+                opp02 {
+                        opp-hz = /bits/ 64 <86000000>;
+                };
+                opp03 {
+                        opp-hz = /bits/ 64 <100000000>;
+                };
+        };
+
+        bus_fsys_apb_opp_table: opp_table4 {
+                compatible = "operating-points-v2";
+                opp-shared;
+
+                opp00 {
+                        opp-hz = /bits/ 64 <100000000>;
+                };
+                opp01 {
+                        opp-hz = /bits/ 64 <200000000>;
+                };
+        };
+
+        bus_fsys2_opp_table: opp_table5 {
+                compatible = "operating-points-v2";
+
+                opp00 {
+                        opp-hz = /bits/ 64 <75000000>;
+                };
+                opp01 {
+                        opp-hz = /bits/ 64 <100000000>;
+                };
+                opp02 {
+                        opp-hz = /bits/ 64 <150000000>;
+                };
+        };
+
+        bus_mfc_opp_table: opp_table6 {
+                compatible = "operating-points-v2";
+
+                opp00 {
+                        opp-hz = /bits/ 64 <96000000>;
+                };
+                opp01 {
+                        opp-hz = /bits/ 64 <111000000>;
+                };
+                opp02 {
+                        opp-hz = /bits/ 64 <167000000>;
+                };
+                opp03 {
+                        opp-hz = /bits/ 64 <222000000>;
+                };
+                opp04 {
+                        opp-hz = /bits/ 64 <333000000>;
+                };
+        };
+
+        bus_gen_opp_table: opp_table7 {
+                compatible = "operating-points-v2";
+
+                opp00 {
+                        opp-hz = /bits/ 64 <89000000>;
+                };
+                opp01 {
+                        opp-hz = /bits/ 64 <133000000>;
+                };
+                opp02 {
+                        opp-hz = /bits/ 64 <178000000>;
+                };
+                opp03 {
+                        opp-hz = /bits/ 64 <267000000>;
+                };
+        };
+
+        bus_peri_opp_table: opp_table8 {
+                compatible = "operating-points-v2";
+
+                opp00 {
+                        opp-hz = /bits/ 64 <67000000>;
+                };
+        };
+
+        bus_g2d_opp_table: opp_table9 {
+                compatible = "operating-points-v2";
+
+                opp00 {
+                        opp-hz = /bits/ 64 <84000000>;
+                };
+                opp01 {
+                        opp-hz = /bits/ 64 <167000000>;
+                };
+                opp02 {
+                        opp-hz = /bits/ 64 <222000000>;
+                };
+                opp03 {
+                        opp-hz = /bits/ 64 <300000000>;
+                };
+                opp04 {
+                        opp-hz = /bits/ 64 <333000000>;
+                };
+        };
+
+        bus_g2d_acp_opp_table: opp_table10 {
+                compatible = "operating-points-v2";
+
+                opp00 {
+                        opp-hz = /bits/ 64 <67000000>;
+                };
+                opp01 {
+                        opp-hz = /bits/ 64 <133000000>;
+                };
+                opp02 {
+                        opp-hz = /bits/ 64 <178000000>;
+                };
+                opp03 {
+                        opp-hz = /bits/ 64 <267000000>;
+                };
+        };
+
+        bus_jpeg_opp_table: opp_table11 {
+                compatible = "operating-points-v2";
+
+                opp00 {
+                        opp-hz = /bits/ 64 <75000000>;
+                };
+                opp01 {
+                        opp-hz = /bits/ 64 <150000000>;
+                };
+                opp02 {
+                        opp-hz = /bits/ 64 <200000000>;
+                };
+                opp03 {
+                        opp-hz = /bits/ 64 <300000000>;
+                };
+        };
+
+        bus_jpeg_apb_opp_table: opp_table12 {
+                compatible = "operating-points-v2";
+
+                opp00 {
+                        opp-hz = /bits/ 64 <84000000>;
+                };
+                opp01 {
+                        opp-hz = /bits/ 64 <111000000>;
+                };
+                opp02 {
+                        opp-hz = /bits/ 64 <134000000>;
+                };
+                opp03 {
+                        opp-hz = /bits/ 64 <167000000>;
+                };
+        };
+
+        bus_disp1_fimd_opp_table: opp_table13 {
+                compatible = "operating-points-v2";
+
+                opp00 {
+                        opp-hz = /bits/ 64 <120000000>;
+                };
+                opp01 {
+                        opp-hz = /bits/ 64 <200000000>;
+                };
+        };
+
+        bus_disp1_opp_table: opp_table14 {
+                compatible = "operating-points-v2";
+
+                opp00 {
+                        opp-hz = /bits/ 64 <120000000>;
+                };
+                opp01 {
+                        opp-hz = /bits/ 64 <200000000>;
+                };
+                opp02 {
+                        opp-hz = /bits/ 64 <300000000>;
+                };
+        };
+
+        bus_gscl_opp_table: opp_table15 {
+                compatible = "operating-points-v2";
+
+                opp00 {
+                        opp-hz = /bits/ 64 <150000000>;
+                };
+                opp01 {
+                        opp-hz = /bits/ 64 <200000000>;
+                };
+                opp02 {
+                        opp-hz = /bits/ 64 <300000000>;
+                };
+        };
+
+        bus_mscl_opp_table: opp_table16 {
+                compatible = "operating-points-v2";
+
+                opp00 {
+                        opp-hz = /bits/ 64 <84000000>;
+                };
+                opp01 {
+                        opp-hz = /bits/ 64 <167000000>;
+                };
+                opp02 {
+                        opp-hz = /bits/ 64 <222000000>;
+                };
+                opp03 {
+                        opp-hz = /bits/ 64 <333000000>;
+                };
+                opp04 {
+                        opp-hz = /bits/ 64 <400000000>;
+                };
+        };
 };
 
 &dp {
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
index 1bd507bfa750..d32984c5ff93 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
@@ -56,6 +56,89 @@
         };
 };
 
+&bus_wcore {
+        devfreq-events = <&nocp_mem0_0>, <&nocp_mem0_1>,
+                        <&nocp_mem1_0>, <&nocp_mem1_1>;
+        vdd-supply = <&buck3_reg>;
+        exynos,saturation-ratio = <100>;
+        status = "okay";
+};
+
+&bus_noc {
+        devfreq = <&bus_wcore>;
+        status = "okay";
+};
+
+&bus_fsys_apb {
+        devfreq = <&bus_wcore>;
+        status = "okay";
+};
+
+&bus_fsys {
+        devfreq = <&bus_wcore>;
+        status = "okay";
+};
+
+&bus_fsys2 {
+        devfreq = <&bus_wcore>;
+        status = "okay";
+};
+
+&bus_mfc {
+        devfreq = <&bus_wcore>;
+        status = "okay";
+};
+
+&bus_gen {
+        devfreq = <&bus_wcore>;
+        status = "okay";
+};
+
+&bus_peri {
+        devfreq = <&bus_wcore>;
+        status = "okay";
+};
+
+&bus_g2d {
+        devfreq = <&bus_wcore>;
+        status = "okay";
+};
+
+&bus_g2d_acp {
+        devfreq = <&bus_wcore>;
+        status = "okay";
+};
+
+&bus_jpeg {
+        devfreq = <&bus_wcore>;
+        status = "okay";
+};
+
+&bus_jpeg_apb {
+        devfreq = <&bus_wcore>;
+        status = "okay";
+};
+
+&bus_disp1_fimd {
+        devfreq = <&bus_wcore>;
+        status = "okay";
+};
+
+&bus_disp1 {
+        devfreq = <&bus_wcore>;
+        status = "okay";
+};
+
+&bus_gscl_scaler {
+        devfreq = <&bus_wcore>;
+        status = "okay";
+};
+
+&bus_mscl {
+        devfreq = <&bus_wcore>;
+        status = "okay";
+};
+
 &clock_audss {
         assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
                         <&clock_audss EXYNOS_MOUT_I2S>,
@@ -361,6 +444,22 @@
         cap-sd-highspeed;
 };
 
+&nocp_mem0_0 {
+        status = "okay";
+};
+
+&nocp_mem0_1 {
+        status = "okay";
+};
+
+&nocp_mem1_0 {
+        status = "okay";
+};
+
+&nocp_mem1_1 {
+        status = "okay";
+};
+
 &pinctrl_0 {
         hdmi_hpd_irq: hdmi-hpd-irq {
                 samsung,pins = "gpx3-7";
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index be03ed0fcb6b..92382cef9f90 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -554,8 +554,8 @@ static struct samsung_mux_clock exynos5800_mux_clks[] __initdata = {
 };
 
 static struct samsung_div_clock exynos5800_div_clks[] __initdata = {
-        DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore", DIV_TOP0, 16, 3),
-
+        DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
+                        "mout_aclk400_wcore", DIV_TOP0, 16, 3),
         DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
                                 DIV_TOP8, 16, 3),
         DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam",
@@ -607,8 +607,8 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
 };
 
 static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
-        DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore_bpll",
-                        DIV_TOP0, 16, 3),
+        DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
+                        "mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3),
 };
 
 static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
@@ -785,31 +785,47 @@ static struct samsung_div_clock exynos5x_div_clks[] __initdata = {
         DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
         DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
 
-        DIV(0, "dout_aclk400_isp", "mout_aclk400_isp", DIV_TOP0, 0, 3),
-        DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3),
-        DIV(0, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3),
-        DIV(0, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3),
-        DIV(0, "dout_aclk100_noc", "mout_aclk100_noc", DIV_TOP0, 20, 3),
-        DIV(0, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3),
-        DIV(0, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3),
-
-        DIV(0, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl",
-                        DIV_TOP1, 0, 3),
-        DIV(0, "dout_aclk333_432_isp", "mout_aclk333_432_isp",
-                        DIV_TOP1, 4, 3),
-        DIV(0, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6),
-        DIV(0, "dout_aclk333_432_isp0", "mout_aclk333_432_isp0",
-                        DIV_TOP1, 16, 3),
-        DIV(0, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3),
-        DIV(0, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3),
-        DIV(0, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3),
-
-        DIV(0, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3),
-        DIV(0, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3),
-        DIV(0, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3),
-        DIV(0, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3),
-        DIV(0, "dout_aclk300_disp1", "mout_aclk300_disp1", DIV_TOP2, 24, 3),
-        DIV(0, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3),
+        DIV(CLK_DOUT_ACLK400_ISP, "dout_aclk400_isp", "mout_aclk400_isp",
+                        DIV_TOP0, 0, 3),
+        DIV(CLK_DOUT_ACLK400_MSCL, "dout_aclk400_mscl", "mout_aclk400_mscl",
+                        DIV_TOP0, 4, 3),
+        DIV(CLK_DOUT_ACLK200, "dout_aclk200", "mout_aclk200",
+                        DIV_TOP0, 8, 3),
+        DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2",
+                        DIV_TOP0, 12, 3),
+        DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc",
+                        DIV_TOP0, 20, 3),
+        DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys",
+                        DIV_TOP0, 24, 3),
+        DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys",
+                        DIV_TOP0, 28, 3),
+        DIV(CLK_DOUT_ACLK333_432_GSCL, "dout_aclk333_432_gscl",
+                        "mout_aclk333_432_gscl", DIV_TOP1, 0, 3),
+        DIV(CLK_DOUT_ACLK333_432_ISP, "dout_aclk333_432_isp",
+                        "mout_aclk333_432_isp", DIV_TOP1, 4, 3),
+        DIV(CLK_DOUT_ACLK66, "dout_aclk66", "mout_aclk66",
+                        DIV_TOP1, 8, 6),
+        DIV(CLK_DOUT_ACLK333_432_ISP0, "dout_aclk333_432_isp0",
+                        "mout_aclk333_432_isp0", DIV_TOP1, 16, 3),
+        DIV(CLK_DOUT_ACLK266, "dout_aclk266", "mout_aclk266",
+                        DIV_TOP1, 20, 3),
+        DIV(CLK_DOUT_ACLK166, "dout_aclk166", "mout_aclk166",
+                        DIV_TOP1, 24, 3),
+        DIV(CLK_DOUT_ACLK333, "dout_aclk333", "mout_aclk333",
+                        DIV_TOP1, 28, 3),
+
+        DIV(CLK_DOUT_ACLK333_G2D, "dout_aclk333_g2d", "mout_aclk333_g2d",
+                        DIV_TOP2, 8, 3),
+        DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d",
+                        DIV_TOP2, 12, 3),
+        DIV(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2,
+                        16, 3),
+        DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg",
+                        DIV_TOP2, 20, 3),
+        DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1",
+                        "mout_aclk300_disp1", DIV_TOP2, 24, 3),
+        DIV(CLK_DOUT_ACLK300_GSCL, "dout_aclk300_gscl", "mout_aclk300_gscl",
+                        DIV_TOP2, 28, 3),
 
         /* DISP1 Block */
         DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4),
@@ -817,7 +833,8 @@ static struct samsung_div_clock exynos5x_div_clks[] __initdata = {
         DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
         DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
         DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2),
-        DIV(0, "dout_aclk400_disp1", "mout_aclk400_disp1", DIV_TOP2, 4, 3),
+        DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1",
+                        "mout_aclk400_disp1", DIV_TOP2, 4, 3),
 
         /* Audio Block */
         DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 7699ee9c16c0..17ab8394bec7 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -217,8 +217,30 @@
 
 /* divider clocks */
 #define CLK_DOUT_PIXEL          768
+#define CLK_DOUT_ACLK400_WCORE  769
+#define CLK_DOUT_ACLK400_ISP    770
+#define CLK_DOUT_ACLK400_MSCL   771
+#define CLK_DOUT_ACLK200        772
+#define CLK_DOUT_ACLK200_FSYS2  773
+#define CLK_DOUT_ACLK100_NOC    774
+#define CLK_DOUT_PCLK200_FSYS   775
+#define CLK_DOUT_ACLK200_FSYS   776
+#define CLK_DOUT_ACLK333_432_GSCL       777
+#define CLK_DOUT_ACLK333_432_ISP        778
+#define CLK_DOUT_ACLK66         779
+#define CLK_DOUT_ACLK333_432_ISP0       780
+#define CLK_DOUT_ACLK266        781
+#define CLK_DOUT_ACLK166        782
+#define CLK_DOUT_ACLK333        783
+#define CLK_DOUT_ACLK333_G2D    784
+#define CLK_DOUT_ACLK266_G2D    785
+#define CLK_DOUT_ACLK_G3D       786
+#define CLK_DOUT_ACLK300_JPEG   787
+#define CLK_DOUT_ACLK300_DISP1  788
+#define CLK_DOUT_ACLK300_GSCL   789
+#define CLK_DOUT_ACLK400_DISP1  790
 
 /* must be greater than maximal clock id */
-#define CLK_NR_CLKS             769
+#define CLK_NR_CLKS             791
 
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */