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authorBjorn Helgaas <bhelgaas@google.com>2018-01-31 11:13:07 -0500
committerBjorn Helgaas <helgaas@kernel.org>2018-01-31 11:13:07 -0500
commit01f095e46ba3a91b06709170c19bc3936e872541 (patch)
tree8e4e3504b81b9ebee4561ac42f55b734449b73ae
parent6a436fa81252b3a302d61133c784472a237b6dd7 (diff)
parent0aa0f5d1084ca1cc302e3c2025065a2a2182bb08 (diff)
Merge branch 'pci/trivial' into next
* pci/trivial: PCI: Clean up whitespace in linux/pci.h, pci/pci.h PCI: Tidy up pci/probe.c comments
-rw-r--r--drivers/pci/pci.h54
-rw-r--r--drivers/pci/probe.c205
-rw-r--r--include/linux/pci.h411
3 files changed, 338 insertions, 332 deletions
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index e90009fff1a9..fcd81911b127 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -38,21 +38,21 @@ int pci_probe_reset_function(struct pci_dev *dev);
38 * struct pci_platform_pm_ops - Firmware PM callbacks 38 * struct pci_platform_pm_ops - Firmware PM callbacks
39 * 39 *
40 * @is_manageable: returns 'true' if given device is power manageable by the 40 * @is_manageable: returns 'true' if given device is power manageable by the
41 * platform firmware 41 * platform firmware
42 * 42 *
43 * @set_state: invokes the platform firmware to set the device's power state 43 * @set_state: invokes the platform firmware to set the device's power state
44 * 44 *
45 * @get_state: queries the platform firmware for a device's current power state 45 * @get_state: queries the platform firmware for a device's current power state
46 * 46 *
47 * @choose_state: returns PCI power state of given device preferred by the 47 * @choose_state: returns PCI power state of given device preferred by the
48 * platform; to be used during system-wide transitions from a 48 * platform; to be used during system-wide transitions from a
49 * sleeping state to the working state and vice versa 49 * sleeping state to the working state and vice versa
50 * 50 *
51 * @set_wakeup: enables/disables wakeup capability for the device 51 * @set_wakeup: enables/disables wakeup capability for the device
52 * 52 *
53 * @need_resume: returns 'true' if the given device (which is currently 53 * @need_resume: returns 'true' if the given device (which is currently
54 * suspended) needs to be resumed to be configured for system 54 * suspended) needs to be resumed to be configured for system
55 * wakeup. 55 * wakeup.
56 * 56 *
57 * If given platform is generally capable of power managing PCI devices, all of 57 * If given platform is generally capable of power managing PCI devices, all of
58 * these callbacks are mandatory. 58 * these callbacks are mandatory.
@@ -112,7 +112,7 @@ struct pci_vpd_ops {
112 112
113struct pci_vpd { 113struct pci_vpd {
114 const struct pci_vpd_ops *ops; 114 const struct pci_vpd_ops *ops;
115 struct bin_attribute *attr; /* descriptor for sysfs VPD entry */ 115 struct bin_attribute *attr; /* Descriptor for sysfs VPD entry */
116 struct mutex lock; 116 struct mutex lock;
117 unsigned int len; 117 unsigned int len;
118 u16 flag; 118 u16 flag;
@@ -199,7 +199,7 @@ extern const struct attribute_group *pci_bus_groups[];
199 199
200/** 200/**
201 * pci_match_one_device - Tell if a PCI device structure has a matching 201 * pci_match_one_device - Tell if a PCI device structure has a matching
202 * PCI device id structure 202 * PCI device id structure
203 * @id: single PCI device id structure to match 203 * @id: single PCI device id structure to match
204 * @dev: the PCI device structure to match against 204 * @dev: the PCI device structure to match against
205 * 205 *
@@ -231,7 +231,7 @@ struct pci_slot_attribute {
231 231
232enum pci_bar_type { 232enum pci_bar_type {
233 pci_bar_unknown, /* Standard PCI BAR probe */ 233 pci_bar_unknown, /* Standard PCI BAR probe */
234 pci_bar_io, /* An io port BAR */ 234 pci_bar_io, /* An I/O port BAR */
235 pci_bar_mem32, /* A 32-bit memory BAR */ 235 pci_bar_mem32, /* A 32-bit memory BAR */
236 pci_bar_mem64, /* A 64-bit memory BAR */ 236 pci_bar_mem64, /* A 64-bit memory BAR */
237}; 237};
@@ -255,24 +255,24 @@ void pci_disable_bridge_window(struct pci_dev *dev);
255 255
256/* Single Root I/O Virtualization */ 256/* Single Root I/O Virtualization */
257struct pci_sriov { 257struct pci_sriov {
258 int pos; /* capability position */ 258 int pos; /* Capability position */
259 int nres; /* number of resources */ 259 int nres; /* Number of resources */
260 u32 cap; /* SR-IOV Capabilities */ 260 u32 cap; /* SR-IOV Capabilities */
261 u16 ctrl; /* SR-IOV Control */ 261 u16 ctrl; /* SR-IOV Control */
262 u16 total_VFs; /* total VFs associated with the PF */ 262 u16 total_VFs; /* Total VFs associated with the PF */
263 u16 initial_VFs; /* initial VFs associated with the PF */ 263 u16 initial_VFs; /* Initial VFs associated with the PF */
264 u16 num_VFs; /* number of VFs available */ 264 u16 num_VFs; /* Number of VFs available */
265 u16 offset; /* first VF Routing ID offset */ 265 u16 offset; /* First VF Routing ID offset */
266 u16 stride; /* following VF stride */ 266 u16 stride; /* Following VF stride */
267 u16 vf_device; /* VF device ID */ 267 u16 vf_device; /* VF device ID */
268 u32 pgsz; /* page size for BAR alignment */ 268 u32 pgsz; /* Page size for BAR alignment */
269 u8 link; /* Function Dependency Link */ 269 u8 link; /* Function Dependency Link */
270 u8 max_VF_buses; /* max buses consumed by VFs */ 270 u8 max_VF_buses; /* Max buses consumed by VFs */
271 u16 driver_max_VFs; /* max num VFs driver supports */ 271 u16 driver_max_VFs; /* Max num VFs driver supports */
272 struct pci_dev *dev; /* lowest numbered PF */ 272 struct pci_dev *dev; /* Lowest numbered PF */
273 struct pci_dev *self; /* this PF */ 273 struct pci_dev *self; /* This PF */
274 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ 274 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
275 bool drivers_autoprobe; /* auto probing of VFs by driver */ 275 bool drivers_autoprobe; /* Auto probing of VFs by driver */
276}; 276};
277 277
278/* pci_dev priv_flags */ 278/* pci_dev priv_flags */
@@ -335,7 +335,7 @@ static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
335 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END) 335 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
336 return pci_sriov_resource_alignment(dev, resno); 336 return pci_sriov_resource_alignment(dev, resno);
337#endif 337#endif
338 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) 338 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
339 return pci_cardbus_resource_alignment(res); 339 return pci_cardbus_resource_alignment(res);
340 return resource_alignment(res); 340 return resource_alignment(res);
341} 341}
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 815c821fe950..2c673a65d5b0 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -69,8 +69,8 @@ static int find_anything(struct device *dev, void *data)
69} 69}
70 70
71/* 71/*
72 * Some device drivers need know if pci is initiated. 72 * Some device drivers need know if PCI is initiated.
73 * Basically, we think pci is not initiated when there 73 * Basically, we think PCI is not initiated when there
74 * is no device to be found on the pci_bus_type. 74 * is no device to be found on the pci_bus_type.
75 */ 75 */
76int no_pci_devices(void) 76int no_pci_devices(void)
@@ -116,12 +116,16 @@ static u64 pci_size(u64 base, u64 maxbase, u64 mask)
116 if (!size) 116 if (!size)
117 return 0; 117 return 0;
118 118
119 /* Get the lowest of them to find the decode size, and 119 /*
120 from that the extent. */ 120 * Get the lowest of them to find the decode size, and from that
121 * the extent.
122 */
121 size = (size & ~(size-1)) - 1; 123 size = (size & ~(size-1)) - 1;
122 124
123 /* base == maxbase can be valid only if the BAR has 125 /*
124 already been programmed with all 1s. */ 126 * base == maxbase can be valid only if the BAR has already been
127 * programmed with all 1s.
128 */
125 if (base == maxbase && ((base | size) & mask) != mask) 129 if (base == maxbase && ((base | size) & mask) != mask)
126 return 0; 130 return 0;
127 131
@@ -164,7 +168,7 @@ static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
164#define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO) 168#define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
165 169
166/** 170/**
167 * pci_read_base - read a PCI BAR 171 * pci_read_base - Read a PCI BAR
168 * @dev: the PCI device 172 * @dev: the PCI device
169 * @type: type of the BAR 173 * @type: type of the BAR
170 * @res: resource buffer to be filled in 174 * @res: resource buffer to be filled in
@@ -764,7 +768,7 @@ static int pci_register_host_bridge(struct pci_host_bridge *bridge)
764 768
765 bridge->bus = bus; 769 bridge->bus = bus;
766 770
767 /* temporarily move resources off the list */ 771 /* Temporarily move resources off the list */
768 list_splice_init(&bridge->windows, &resources); 772 list_splice_init(&bridge->windows, &resources);
769 bus->sysdata = bridge->sysdata; 773 bus->sysdata = bridge->sysdata;
770 bus->msi = bridge->msi; 774 bus->msi = bridge->msi;
@@ -776,7 +780,7 @@ static int pci_register_host_bridge(struct pci_host_bridge *bridge)
776 780
777 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr); 781 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
778 if (b) { 782 if (b) {
779 /* If we already got to this bus through a different bridge, ignore it */ 783 /* Ignore it if we already got here via a different bridge */
780 dev_dbg(&b->dev, "bus already known\n"); 784 dev_dbg(&b->dev, "bus already known\n");
781 err = -EEXIST; 785 err = -EEXIST;
782 goto free; 786 goto free;
@@ -869,9 +873,7 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
869 int i; 873 int i;
870 int ret; 874 int ret;
871 875
872 /* 876 /* Allocate a new bus and inherit stuff from the parent */
873 * Allocate a new bus, and inherit stuff from the parent..
874 */
875 child = pci_alloc_bus(parent); 877 child = pci_alloc_bus(parent);
876 if (!child) 878 if (!child)
877 return NULL; 879 return NULL;
@@ -882,16 +884,14 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
882 child->sysdata = parent->sysdata; 884 child->sysdata = parent->sysdata;
883 child->bus_flags = parent->bus_flags; 885 child->bus_flags = parent->bus_flags;
884 886
885 /* initialize some portions of the bus device, but don't register it 887 /*
886 * now as the parent is not properly set up yet. 888 * Initialize some portions of the bus device, but don't register
889 * it now as the parent is not properly set up yet.
887 */ 890 */
888 child->dev.class = &pcibus_class; 891 child->dev.class = &pcibus_class;
889 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); 892 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
890 893
891 /* 894 /* Set up the primary, secondary and subordinate bus numbers */
892 * Set up the primary, secondary and subordinate
893 * bus numbers.
894 */
895 child->number = child->busn_res.start = busnr; 895 child->number = child->busn_res.start = busnr;
896 child->primary = parent->busn_res.start; 896 child->primary = parent->busn_res.start;
897 child->busn_res.end = 0xff; 897 child->busn_res.end = 0xff;
@@ -907,7 +907,7 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
907 pci_set_bus_of_node(child); 907 pci_set_bus_of_node(child);
908 pci_set_bus_speed(child); 908 pci_set_bus_speed(child);
909 909
910 /* Set up default resource pointers and names.. */ 910 /* Set up default resource pointers and names */
911 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 911 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
912 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; 912 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
913 child->resource[i]->name = child->name; 913 child->resource[i]->name = child->name;
@@ -1022,8 +1022,10 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
1022 broken = 1; 1022 broken = 1;
1023 } 1023 }
1024 1024
1025 /* Disable MasterAbortMode during probing to avoid reporting 1025 /*
1026 of bus errors (in some architectures) */ 1026 * Disable Master-Abort Mode during probing to avoid reporting of
1027 * bus errors in some architectures.
1028 */
1027 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); 1029 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
1028 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, 1030 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
1029 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); 1031 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
@@ -1033,18 +1035,19 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
1033 if ((secondary || subordinate) && !pcibios_assign_all_busses() && 1035 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
1034 !is_cardbus && !broken) { 1036 !is_cardbus && !broken) {
1035 unsigned int cmax; 1037 unsigned int cmax;
1038
1036 /* 1039 /*
1037 * Bus already configured by firmware, process it in the first 1040 * Bus already configured by firmware, process it in the
1038 * pass and just note the configuration. 1041 * first pass and just note the configuration.
1039 */ 1042 */
1040 if (pass) 1043 if (pass)
1041 goto out; 1044 goto out;
1042 1045
1043 /* 1046 /*
1044 * The bus might already exist for two reasons: Either we are 1047 * The bus might already exist for two reasons: Either we
1045 * rescanning the bus or the bus is reachable through more than 1048 * are rescanning the bus or the bus is reachable through
1046 * one bridge. The second case can happen with the i450NX 1049 * more than one bridge. The second case can happen with
1047 * chipset. 1050 * the i450NX chipset.
1048 */ 1051 */
1049 child = pci_find_bus(pci_domain_nr(bus), secondary); 1052 child = pci_find_bus(pci_domain_nr(bus), secondary);
1050 if (!child) { 1053 if (!child) {
@@ -1060,22 +1063,27 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
1060 if (cmax > subordinate) 1063 if (cmax > subordinate)
1061 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n", 1064 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n",
1062 subordinate, cmax); 1065 subordinate, cmax);
1063 /* subordinate should equal child->busn_res.end */ 1066
1067 /* Subordinate should equal child->busn_res.end */
1064 if (subordinate > max) 1068 if (subordinate > max)
1065 max = subordinate; 1069 max = subordinate;
1066 } else { 1070 } else {
1071
1067 /* 1072 /*
1068 * We need to assign a number to this bus which we always 1073 * We need to assign a number to this bus which we always
1069 * do in the second pass. 1074 * do in the second pass.
1070 */ 1075 */
1071 if (!pass) { 1076 if (!pass) {
1072 if (pcibios_assign_all_busses() || broken || is_cardbus) 1077 if (pcibios_assign_all_busses() || broken || is_cardbus)
1073 /* Temporarily disable forwarding of the 1078
1074 configuration cycles on all bridges in 1079 /*
1075 this bus segment to avoid possible 1080 * Temporarily disable forwarding of the
1076 conflicts in the second pass between two 1081 * configuration cycles on all bridges in
1077 bridges programmed with overlapping 1082 * this bus segment to avoid possible
1078 bus ranges. */ 1083 * conflicts in the second pass between two
1084 * bridges programmed with overlapping bus
1085 * ranges.
1086 */
1079 pci_write_config_dword(dev, PCI_PRIMARY_BUS, 1087 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
1080 buses & ~0xffffff); 1088 buses & ~0xffffff);
1081 goto out; 1089 goto out;
@@ -1084,9 +1092,11 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
1084 /* Clear errors */ 1092 /* Clear errors */
1085 pci_write_config_word(dev, PCI_STATUS, 0xffff); 1093 pci_write_config_word(dev, PCI_STATUS, 0xffff);
1086 1094
1087 /* Prevent assigning a bus number that already exists. 1095 /*
1088 * This can happen when a bridge is hot-plugged, so in 1096 * Prevent assigning a bus number that already exists.
1089 * this case we only re-scan this bus. */ 1097 * This can happen when a bridge is hot-plugged, so in this
1098 * case we only re-scan this bus.
1099 */
1090 child = pci_find_bus(pci_domain_nr(bus), max+1); 1100 child = pci_find_bus(pci_domain_nr(bus), max+1);
1091 if (!child) { 1101 if (!child) {
1092 child = pci_add_new_bus(bus, dev, max+1); 1102 child = pci_add_new_bus(bus, dev, max+1);
@@ -1113,19 +1123,18 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
1113 buses |= CARDBUS_LATENCY_TIMER << 24; 1123 buses |= CARDBUS_LATENCY_TIMER << 24;
1114 } 1124 }
1115 1125
1116 /* 1126 /* We need to blast all three values with a single write */
1117 * We need to blast all three values with a single write.
1118 */
1119 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); 1127 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
1120 1128
1121 if (!is_cardbus) { 1129 if (!is_cardbus) {
1122 child->bridge_ctl = bctl; 1130 child->bridge_ctl = bctl;
1123 max = pci_scan_child_bus_extend(child, available_buses); 1131 max = pci_scan_child_bus_extend(child, available_buses);
1124 } else { 1132 } else {
1133
1125 /* 1134 /*
1126 * For CardBus bridges, we leave 4 bus numbers 1135 * For CardBus bridges, we leave 4 bus numbers as
1127 * as cards with a PCI-to-PCI bridge can be 1136 * cards with a PCI-to-PCI bridge can be inserted
1128 * inserted later. 1137 * later.
1129 */ 1138 */
1130 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) { 1139 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
1131 struct pci_bus *parent = bus; 1140 struct pci_bus *parent = bus;
@@ -1141,10 +1150,11 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
1141 parent = parent->parent; 1150 parent = parent->parent;
1142 } 1151 }
1143 if (j) { 1152 if (j) {
1153
1144 /* 1154 /*
1145 * Often, there are two cardbus bridges 1155 * Often, there are two CardBus
1146 * -- try to leave one valid bus number 1156 * bridges -- try to leave one
1147 * for each one. 1157 * valid bus number for each one.
1148 */ 1158 */
1149 i /= 2; 1159 i /= 2;
1150 break; 1160 break;
@@ -1152,9 +1162,8 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
1152 } 1162 }
1153 max += i; 1163 max += i;
1154 } 1164 }
1155 /* 1165
1156 * Set the subordinate bus number to its real value. 1166 /* Set subordinate bus number to its real value */
1157 */
1158 pci_bus_update_busn_res_end(child, max); 1167 pci_bus_update_busn_res_end(child, max);
1159 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); 1168 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
1160 } 1169 }
@@ -1295,7 +1304,7 @@ static void set_pcie_thunderbolt(struct pci_dev *dev)
1295} 1304}
1296 1305
1297/** 1306/**
1298 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config? 1307 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?
1299 * @dev: PCI device 1308 * @dev: PCI device
1300 * 1309 *
1301 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that 1310 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
@@ -1332,7 +1341,7 @@ static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1332} 1341}
1333 1342
1334/** 1343/**
1335 * pci_cfg_space_size - get the configuration space size of the PCI device. 1344 * pci_cfg_space_size - Get the configuration space size of the PCI device
1336 * @dev: PCI device 1345 * @dev: PCI device
1337 * 1346 *
1338 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices 1347 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
@@ -1398,7 +1407,7 @@ static void pci_msi_setup_pci_dev(struct pci_dev *dev)
1398} 1407}
1399 1408
1400/** 1409/**
1401 * pci_intx_mask_broken - test PCI_COMMAND_INTX_DISABLE writability 1410 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability
1402 * @dev: PCI device 1411 * @dev: PCI device
1403 * 1412 *
1404 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this 1413 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this
@@ -1426,11 +1435,11 @@ static int pci_intx_mask_broken(struct pci_dev *dev)
1426} 1435}
1427 1436
1428/** 1437/**
1429 * pci_setup_device - fill in class and map information of a device 1438 * pci_setup_device - Fill in class and map information of a device
1430 * @dev: the device structure to fill 1439 * @dev: the device structure to fill
1431 * 1440 *
1432 * Initialize the device structure with information about the device's 1441 * Initialize the device structure with information about the device's
1433 * vendor,class,memory and IO-space addresses,IRQ lines etc. 1442 * vendor,class,memory and IO-space addresses, IRQ lines etc.
1434 * Called at initialisation of the PCI subsystem and by CardBus services. 1443 * Called at initialisation of the PCI subsystem and by CardBus services.
1435 * Returns 0 on success and negative if unknown type of device (not normal, 1444 * Returns 0 on success and negative if unknown type of device (not normal,
1436 * bridge or CardBus). 1445 * bridge or CardBus).
@@ -1456,8 +1465,11 @@ int pci_setup_device(struct pci_dev *dev)
1456 set_pcie_port_type(dev); 1465 set_pcie_port_type(dev);
1457 1466
1458 pci_dev_assign_slot(dev); 1467 pci_dev_assign_slot(dev);
1459 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) 1468
1460 set this higher, assuming the system even supports it. */ 1469 /*
1470 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1471 * set this higher, assuming the system even supports it.
1472 */
1461 dev->dma_mask = 0xffffffff; 1473 dev->dma_mask = 0xffffffff;
1462 1474
1463 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), 1475 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
@@ -1471,10 +1483,10 @@ int pci_setup_device(struct pci_dev *dev)
1471 pci_printk(KERN_DEBUG, dev, "[%04x:%04x] type %02x class %#08x\n", 1483 pci_printk(KERN_DEBUG, dev, "[%04x:%04x] type %02x class %#08x\n",
1472 dev->vendor, dev->device, dev->hdr_type, dev->class); 1484 dev->vendor, dev->device, dev->hdr_type, dev->class);
1473 1485
1474 /* need to have dev->class ready */ 1486 /* Need to have dev->class ready */
1475 dev->cfg_size = pci_cfg_space_size(dev); 1487 dev->cfg_size = pci_cfg_space_size(dev);
1476 1488
1477 /* need to have dev->cfg_size ready */ 1489 /* Need to have dev->cfg_size ready */
1478 set_pcie_thunderbolt(dev); 1490 set_pcie_thunderbolt(dev);
1479 1491
1480 /* "Unknown power state" */ 1492 /* "Unknown power state" */
@@ -1482,7 +1494,8 @@ int pci_setup_device(struct pci_dev *dev)
1482 1494
1483 /* Early fixups, before probing the BARs */ 1495 /* Early fixups, before probing the BARs */
1484 pci_fixup_device(pci_fixup_early, dev); 1496 pci_fixup_device(pci_fixup_early, dev);
1485 /* device class may be changed after fixup */ 1497
1498 /* Device class may be changed after fixup */
1486 class = dev->class >> 8; 1499 class = dev->class >> 8;
1487 1500
1488 if (dev->non_compliant_bars) { 1501 if (dev->non_compliant_bars) {
@@ -1553,9 +1566,12 @@ int pci_setup_device(struct pci_dev *dev)
1553 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ 1566 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1554 if (class != PCI_CLASS_BRIDGE_PCI) 1567 if (class != PCI_CLASS_BRIDGE_PCI)
1555 goto bad; 1568 goto bad;
1556 /* The PCI-to-PCI bridge spec requires that subtractive 1569
1557 decoding (i.e. transparent) bridge must have programming 1570 /*
1558 interface code of 0x01. */ 1571 * The PCI-to-PCI bridge spec requires that subtractive
1572 * decoding (i.e. transparent) bridge must have programming
1573 * interface code of 0x01.
1574 */
1559 pci_read_irq(dev); 1575 pci_read_irq(dev);
1560 dev->transparent = ((dev->class & 0xff) == 1); 1576 dev->transparent = ((dev->class & 0xff) == 1);
1561 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); 1577 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
@@ -1771,6 +1787,7 @@ static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1771 /* Initialize Advanced Error Capabilities and Control Register */ 1787 /* Initialize Advanced Error Capabilities and Control Register */
1772 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &reg32); 1788 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &reg32);
1773 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or; 1789 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1790
1774 /* Don't enable ECRC generation or checking if unsupported */ 1791 /* Don't enable ECRC generation or checking if unsupported */
1775 if (!(reg32 & PCI_ERR_CAP_ECRC_GENC)) 1792 if (!(reg32 & PCI_ERR_CAP_ECRC_GENC))
1776 reg32 &= ~PCI_ERR_CAP_ECRC_GENE; 1793 reg32 &= ~PCI_ERR_CAP_ECRC_GENE;
@@ -1934,10 +1951,11 @@ static void pci_release_capabilities(struct pci_dev *dev)
1934} 1951}
1935 1952
1936/** 1953/**
1937 * pci_release_dev - free a pci device structure when all users of it are finished. 1954 * pci_release_dev - Free a PCI device structure when all users of it are
1955 * finished
1938 * @dev: device that's been disconnected 1956 * @dev: device that's been disconnected
1939 * 1957 *
1940 * Will be called only by the device core when all users of this pci device are 1958 * Will be called only by the device core when all users of this PCI device are
1941 * done. 1959 * done.
1942 */ 1960 */
1943static void pci_release_dev(struct device *dev) 1961static void pci_release_dev(struct device *dev)
@@ -2025,7 +2043,7 @@ bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2025 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) 2043 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2026 return false; 2044 return false;
2027 2045
2028 /* some broken boards return 0 or ~0 if a slot is empty: */ 2046 /* Some broken boards return 0 or ~0 if a slot is empty: */
2029 if (*l == 0xffffffff || *l == 0x00000000 || 2047 if (*l == 0xffffffff || *l == 0x00000000 ||
2030 *l == 0x0000ffff || *l == 0xffff0000) 2048 *l == 0x0000ffff || *l == 0xffff0000)
2031 return false; 2049 return false;
@@ -2038,8 +2056,8 @@ bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2038EXPORT_SYMBOL(pci_bus_read_dev_vendor_id); 2056EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
2039 2057
2040/* 2058/*
2041 * Read the config data for a PCI device, sanity-check it 2059 * Read the config data for a PCI device, sanity-check it,
2042 * and fill in the dev structure... 2060 * and fill in the dev structure.
2043 */ 2061 */
2044static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) 2062static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
2045{ 2063{
@@ -2105,7 +2123,7 @@ static void pci_init_capabilities(struct pci_dev *dev)
2105} 2123}
2106 2124
2107/* 2125/*
2108 * This is the equivalent of pci_host_bridge_msi_domain that acts on 2126 * This is the equivalent of pci_host_bridge_msi_domain() that acts on
2109 * devices. Firmware interfaces that can select the MSI domain on a 2127 * devices. Firmware interfaces that can select the MSI domain on a
2110 * per-device basis should be called from here. 2128 * per-device basis should be called from here.
2111 */ 2129 */
@@ -2114,7 +2132,7 @@ static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
2114 struct irq_domain *d; 2132 struct irq_domain *d;
2115 2133
2116 /* 2134 /*
2117 * If a domain has been set through the pcibios_add_device 2135 * If a domain has been set through the pcibios_add_device()
2118 * callback, then this is the one (platform code knows best). 2136 * callback, then this is the one (platform code knows best).
2119 */ 2137 */
2120 d = dev_get_msi_domain(&dev->dev); 2138 d = dev_get_msi_domain(&dev->dev);
@@ -2168,10 +2186,10 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
2168 /* Fix up broken headers */ 2186 /* Fix up broken headers */
2169 pci_fixup_device(pci_fixup_header, dev); 2187 pci_fixup_device(pci_fixup_header, dev);
2170 2188
2171 /* moved out from quirk header fixup code */ 2189 /* Moved out from quirk header fixup code */
2172 pci_reassigndev_resource_alignment(dev); 2190 pci_reassigndev_resource_alignment(dev);
2173 2191
2174 /* Clear the state_saved flag. */ 2192 /* Clear the state_saved flag */
2175 dev->state_saved = false; 2193 dev->state_saved = false;
2176 2194
2177 /* Initialize various capabilities */ 2195 /* Initialize various capabilities */
@@ -2188,7 +2206,7 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
2188 ret = pcibios_add_device(dev); 2206 ret = pcibios_add_device(dev);
2189 WARN_ON(ret < 0); 2207 WARN_ON(ret < 0);
2190 2208
2191 /* Setup MSI irq domain */ 2209 /* Set up MSI IRQ domain */
2192 pci_set_msi_domain(dev); 2210 pci_set_msi_domain(dev);
2193 2211
2194 /* Notifier could use PCI capabilities */ 2212 /* Notifier could use PCI capabilities */
@@ -2272,9 +2290,9 @@ static int only_one_child(struct pci_bus *bus)
2272} 2290}
2273 2291
2274/** 2292/**
2275 * pci_scan_slot - scan a PCI slot on a bus for devices. 2293 * pci_scan_slot - Scan a PCI slot on a bus for devices
2276 * @bus: PCI bus to scan 2294 * @bus: PCI bus to scan
2277 * @devfn: slot number to scan (must have zero function.) 2295 * @devfn: slot number to scan (must have zero function)
2278 * 2296 *
2279 * Scan a PCI slot on the specified PCI bus for devices, adding 2297 * Scan a PCI slot on the specified PCI bus for devices, adding
2280 * discovered devices to the @bus->devices list. New devices 2298 * discovered devices to the @bus->devices list. New devices
@@ -2305,7 +2323,7 @@ int pci_scan_slot(struct pci_bus *bus, int devfn)
2305 } 2323 }
2306 } 2324 }
2307 2325
2308 /* only one slot has pcie device */ 2326 /* Only one slot has PCIe device */
2309 if (bus->self && nr) 2327 if (bus->self && nr)
2310 pcie_aspm_init_link_state(bus->self); 2328 pcie_aspm_init_link_state(bus->self);
2311 2329
@@ -2354,7 +2372,9 @@ static void pcie_write_mps(struct pci_dev *dev, int mps)
2354 2372
2355 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT && 2373 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
2356 dev->bus->self) 2374 dev->bus->self)
2357 /* For "Performance", the assumption is made that 2375
2376 /*
2377 * For "Performance", the assumption is made that
2358 * downstream communication will never be larger than 2378 * downstream communication will never be larger than
2359 * the MRRS. So, the MPS only needs to be configured 2379 * the MRRS. So, the MPS only needs to be configured
2360 * for the upstream communication. This being the case, 2380 * for the upstream communication. This being the case,
@@ -2378,20 +2398,23 @@ static void pcie_write_mrrs(struct pci_dev *dev)
2378{ 2398{
2379 int rc, mrrs; 2399 int rc, mrrs;
2380 2400
2381 /* In the "safe" case, do not configure the MRRS. There appear to be 2401 /*
2402 * In the "safe" case, do not configure the MRRS. There appear to be
2382 * issues with setting MRRS to 0 on a number of devices. 2403 * issues with setting MRRS to 0 on a number of devices.
2383 */ 2404 */
2384 if (pcie_bus_config != PCIE_BUS_PERFORMANCE) 2405 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
2385 return; 2406 return;
2386 2407
2387 /* For Max performance, the MRRS must be set to the largest supported 2408 /*
2409 * For max performance, the MRRS must be set to the largest supported
2388 * value. However, it cannot be configured larger than the MPS the 2410 * value. However, it cannot be configured larger than the MPS the
2389 * device or the bus can support. This should already be properly 2411 * device or the bus can support. This should already be properly
2390 * configured by a prior call to pcie_write_mps. 2412 * configured by a prior call to pcie_write_mps().
2391 */ 2413 */
2392 mrrs = pcie_get_mps(dev); 2414 mrrs = pcie_get_mps(dev);
2393 2415
2394 /* MRRS is a R/W register. Invalid values can be written, but a 2416 /*
2417 * MRRS is a R/W register. Invalid values can be written, but a
2395 * subsequent read will verify if the value is acceptable or not. 2418 * subsequent read will verify if the value is acceptable or not.
2396 * If the MRRS value provided is not acceptable (e.g., too large), 2419 * If the MRRS value provided is not acceptable (e.g., too large),
2397 * shrink the value until it is acceptable to the HW. 2420 * shrink the value until it is acceptable to the HW.
@@ -2433,7 +2456,8 @@ static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
2433 return 0; 2456 return 0;
2434} 2457}
2435 2458
2436/* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down, 2459/*
2460 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,
2437 * parents then children fashion. If this changes, then this code will not 2461 * parents then children fashion. If this changes, then this code will not
2438 * work as designed. 2462 * work as designed.
2439 */ 2463 */
@@ -2447,7 +2471,8 @@ void pcie_bus_configure_settings(struct pci_bus *bus)
2447 if (!pci_is_pcie(bus->self)) 2471 if (!pci_is_pcie(bus->self))
2448 return; 2472 return;
2449 2473
2450 /* FIXME - Peer to peer DMA is possible, though the endpoint would need 2474 /*
2475 * FIXME - Peer to peer DMA is possible, though the endpoint would need
2451 * to be aware of the MPS of the destination. To work around this, 2476 * to be aware of the MPS of the destination. To work around this,
2452 * simply force the MPS of the entire system to the smallest possible. 2477 * simply force the MPS of the entire system to the smallest possible.
2453 */ 2478 */
@@ -2501,7 +2526,7 @@ static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
2501 for (devfn = 0; devfn < 0x100; devfn += 8) 2526 for (devfn = 0; devfn < 0x100; devfn += 8)
2502 pci_scan_slot(bus, devfn); 2527 pci_scan_slot(bus, devfn);
2503 2528
2504 /* Reserve buses for SR-IOV capability. */ 2529 /* Reserve buses for SR-IOV capability */
2505 used_buses = pci_iov_bus_range(bus); 2530 used_buses = pci_iov_bus_range(bus);
2506 max += used_buses; 2531 max += used_buses;
2507 2532
@@ -2543,6 +2568,7 @@ static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
2543 unsigned int buses = 0; 2568 unsigned int buses = 0;
2544 2569
2545 if (!hotplug_bridges && normal_bridges == 1) { 2570 if (!hotplug_bridges && normal_bridges == 1) {
2571
2546 /* 2572 /*
2547 * There is only one bridge on the bus (upstream 2573 * There is only one bridge on the bus (upstream
2548 * port) so it gets all available buses which it 2574 * port) so it gets all available buses which it
@@ -2551,6 +2577,7 @@ static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
2551 */ 2577 */
2552 buses = available_buses; 2578 buses = available_buses;
2553 } else if (dev->is_hotplug_bridge) { 2579 } else if (dev->is_hotplug_bridge) {
2580
2554 /* 2581 /*
2555 * Distribute the extra buses between hotplug 2582 * Distribute the extra buses between hotplug
2556 * bridges if any. 2583 * bridges if any.
@@ -2609,8 +2636,8 @@ unsigned int pci_scan_child_bus(struct pci_bus *bus)
2609EXPORT_SYMBOL_GPL(pci_scan_child_bus); 2636EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2610 2637
2611/** 2638/**
2612 * pcibios_root_bridge_prepare - Platform-specific host bridge setup. 2639 * pcibios_root_bridge_prepare - Platform-specific host bridge setup
2613 * @bridge: Host bridge to set up. 2640 * @bridge: Host bridge to set up
2614 * 2641 *
2615 * Default empty implementation. Replace with an architecture-specific setup 2642 * Default empty implementation. Replace with an architecture-specific setup
2616 * routine, if necessary. 2643 * routine, if necessary.
@@ -2813,7 +2840,7 @@ struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
2813EXPORT_SYMBOL(pci_scan_bus); 2840EXPORT_SYMBOL(pci_scan_bus);
2814 2841
2815/** 2842/**
2816 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices. 2843 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices
2817 * @bridge: PCI bridge for the bus to scan 2844 * @bridge: PCI bridge for the bus to scan
2818 * 2845 *
2819 * Scan a PCI bus and child buses for new devices, add them, 2846 * Scan a PCI bus and child buses for new devices, add them,
@@ -2838,11 +2865,11 @@ unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
2838} 2865}
2839 2866
2840/** 2867/**
2841 * pci_rescan_bus - scan a PCI bus for devices. 2868 * pci_rescan_bus - Scan a PCI bus for devices
2842 * @bus: PCI bus to scan 2869 * @bus: PCI bus to scan
2843 * 2870 *
2844 * Scan a PCI bus and child buses for new devices, adds them, 2871 * Scan a PCI bus and child buses for new devices, add them,
2845 * and enables them. 2872 * and enable them.
2846 * 2873 *
2847 * Returns the max number of subordinate bus discovered. 2874 * Returns the max number of subordinate bus discovered.
2848 */ 2875 */
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 656989b00666..a1e10ba7b612 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -48,17 +48,17 @@
48 * In the interest of not exposing interfaces to user-space unnecessarily, 48 * In the interest of not exposing interfaces to user-space unnecessarily,
49 * the following kernel-only defines are being added here. 49 * the following kernel-only defines are being added here.
50 */ 50 */
51#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 51#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
52/* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 52/* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
53#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 53#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
54 54
55/* pci_slot represents a physical slot */ 55/* pci_slot represents a physical slot */
56struct pci_slot { 56struct pci_slot {
57 struct pci_bus *bus; /* The bus this slot is on */ 57 struct pci_bus *bus; /* Bus this slot is on */
58 struct list_head list; /* node in list of slots on this bus */ 58 struct list_head list; /* Node in list of slots */
59 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ 59 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
60 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 60 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
61 struct kobject kobj; 61 struct kobject kobj;
62}; 62};
63 63
64static inline const char *pci_slot_name(const struct pci_slot *slot) 64static inline const char *pci_slot_name(const struct pci_slot *slot)
@@ -72,9 +72,7 @@ enum pci_mmap_state {
72 pci_mmap_mem 72 pci_mmap_mem
73}; 73};
74 74
75/* 75/* For PCI devices, the region numbers are assigned this way: */
76 * For PCI devices, the region numbers are assigned this way:
77 */
78enum { 76enum {
79 /* #0-5: standard PCI resources */ 77 /* #0-5: standard PCI resources */
80 PCI_STD_RESOURCES, 78 PCI_STD_RESOURCES,
@@ -83,23 +81,23 @@ enum {
83 /* #6: expansion ROM resource */ 81 /* #6: expansion ROM resource */
84 PCI_ROM_RESOURCE, 82 PCI_ROM_RESOURCE,
85 83
86 /* device specific resources */ 84 /* Device-specific resources */
87#ifdef CONFIG_PCI_IOV 85#ifdef CONFIG_PCI_IOV
88 PCI_IOV_RESOURCES, 86 PCI_IOV_RESOURCES,
89 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
90#endif 88#endif
91 89
92 /* resources assigned to buses behind the bridge */ 90 /* Resources assigned to buses behind the bridge */
93#define PCI_BRIDGE_RESOURCE_NUM 4 91#define PCI_BRIDGE_RESOURCE_NUM 4
94 92
95 PCI_BRIDGE_RESOURCES, 93 PCI_BRIDGE_RESOURCES,
96 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
97 PCI_BRIDGE_RESOURCE_NUM - 1, 95 PCI_BRIDGE_RESOURCE_NUM - 1,
98 96
99 /* total resources associated with a PCI device */ 97 /* Total resources associated with a PCI device */
100 PCI_NUM_RESOURCES, 98 PCI_NUM_RESOURCES,
101 99
102 /* preserve this for compatibility */ 100 /* Preserve this for compatibility */
103 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
104}; 102};
105 103
@@ -152,9 +150,10 @@ static inline const char *pci_power_name(pci_power_t state)
152#define PCI_PM_D3COLD_WAIT 100 150#define PCI_PM_D3COLD_WAIT 100
153#define PCI_PM_BUS_WAIT 50 151#define PCI_PM_BUS_WAIT 50
154 152
155/** The pci_channel state describes connectivity between the CPU and 153/**
156 * the pci device. If some PCI bus between here and the pci device 154 * The pci_channel state describes connectivity between the CPU and
157 * has crashed or locked up, this info is reflected here. 155 * the PCI device. If some PCI bus between here and the PCI device
156 * has crashed or locked up, this info is reflected here.
158 */ 157 */
159typedef unsigned int __bitwise pci_channel_state_t; 158typedef unsigned int __bitwise pci_channel_state_t;
160 159
@@ -184,9 +183,7 @@ enum pcie_reset_state {
184 183
185typedef unsigned short __bitwise pci_dev_flags_t; 184typedef unsigned short __bitwise pci_dev_flags_t;
186enum pci_dev_flags { 185enum pci_dev_flags {
187 /* INTX_DISABLE in PCI_COMMAND register disables MSI 186 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
188 * generation too.
189 */
190 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 187 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
191 /* Device configuration is irrevocably lost if disabled into D3 */ 188 /* Device configuration is irrevocably lost if disabled into D3 */
192 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 189 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
@@ -202,7 +199,7 @@ enum pci_dev_flags {
202 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 199 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
203 /* Get VPD from function 0 VPD */ 200 /* Get VPD from function 0 VPD */
204 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 201 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
205 /* a non-root bridge where translation occurs, stop alias search here */ 202 /* A non-root bridge where translation occurs, stop alias search here */
206 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), 203 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
207 /* Do not use FLR even if device advertises PCI_AF_CAP */ 204 /* Do not use FLR even if device advertises PCI_AF_CAP */
208 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), 205 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
@@ -222,17 +219,17 @@ enum pci_bus_flags {
222 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 219 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
223}; 220};
224 221
225/* These values come from the PCI Express Spec */ 222/* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
226enum pcie_link_width { 223enum pcie_link_width {
227 PCIE_LNK_WIDTH_RESRV = 0x00, 224 PCIE_LNK_WIDTH_RESRV = 0x00,
228 PCIE_LNK_X1 = 0x01, 225 PCIE_LNK_X1 = 0x01,
229 PCIE_LNK_X2 = 0x02, 226 PCIE_LNK_X2 = 0x02,
230 PCIE_LNK_X4 = 0x04, 227 PCIE_LNK_X4 = 0x04,
231 PCIE_LNK_X8 = 0x08, 228 PCIE_LNK_X8 = 0x08,
232 PCIE_LNK_X12 = 0x0C, 229 PCIE_LNK_X12 = 0x0c,
233 PCIE_LNK_X16 = 0x10, 230 PCIE_LNK_X16 = 0x10,
234 PCIE_LNK_X32 = 0x20, 231 PCIE_LNK_X32 = 0x20,
235 PCIE_LNK_WIDTH_UNKNOWN = 0xFF, 232 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
236}; 233};
237 234
238/* Based on the PCI Hotplug Spec, but some values are made up by us */ 235/* Based on the PCI Hotplug Spec, but some values are made up by us */
@@ -263,15 +260,15 @@ enum pci_bus_speed {
263}; 260};
264 261
265struct pci_cap_saved_data { 262struct pci_cap_saved_data {
266 u16 cap_nr; 263 u16 cap_nr;
267 bool cap_extended; 264 bool cap_extended;
268 unsigned int size; 265 unsigned int size;
269 u32 data[0]; 266 u32 data[0];
270}; 267};
271 268
272struct pci_cap_saved_state { 269struct pci_cap_saved_state {
273 struct hlist_node next; 270 struct hlist_node next;
274 struct pci_cap_saved_data cap; 271 struct pci_cap_saved_data cap;
275}; 272};
276 273
277struct irq_affinity; 274struct irq_affinity;
@@ -280,19 +277,17 @@ struct pci_vpd;
280struct pci_sriov; 277struct pci_sriov;
281struct pci_ats; 278struct pci_ats;
282 279
283/* 280/* The pci_dev structure describes PCI devices */
284 * The pci_dev structure is used to describe PCI devices.
285 */
286struct pci_dev { 281struct pci_dev {
287 struct list_head bus_list; /* node in per-bus list */ 282 struct list_head bus_list; /* Node in per-bus list */
288 struct pci_bus *bus; /* bus this device is on */ 283 struct pci_bus *bus; /* Bus this device is on */
289 struct pci_bus *subordinate; /* bus this device bridges to */ 284 struct pci_bus *subordinate; /* Bus this device bridges to */
290 285
291 void *sysdata; /* hook for sys-specific extension */ 286 void *sysdata; /* Hook for sys-specific extension */
292 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ 287 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
293 struct pci_slot *slot; /* Physical slot this device is in */ 288 struct pci_slot *slot; /* Physical slot this device is in */
294 289
295 unsigned int devfn; /* encoded device & function index */ 290 unsigned int devfn; /* Encoded device & function index */
296 unsigned short vendor; 291 unsigned short vendor;
297 unsigned short device; 292 unsigned short device;
298 unsigned short subsystem_vendor; 293 unsigned short subsystem_vendor;
@@ -307,12 +302,12 @@ struct pci_dev {
307 u8 msi_cap; /* MSI capability offset */ 302 u8 msi_cap; /* MSI capability offset */
308 u8 msix_cap; /* MSI-X capability offset */ 303 u8 msix_cap; /* MSI-X capability offset */
309 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 304 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
310 u8 rom_base_reg; /* which config register controls the ROM */ 305 u8 rom_base_reg; /* Config register controlling ROM */
311 u8 pin; /* which interrupt pin this device uses */ 306 u8 pin; /* Interrupt pin this device uses */
312 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */ 307 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
313 unsigned long *dma_alias_mask;/* mask of enabled devfn aliases */ 308 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
314 309
315 struct pci_driver *driver; /* which driver has allocated this device */ 310 struct pci_driver *driver; /* Driver bound to this device */
316 u64 dma_mask; /* Mask of the bits of bus address this 311 u64 dma_mask; /* Mask of the bits of bus address this
317 device implements. Normally this is 312 device implements. Normally this is
318 0xffffffff. You only need to change 313 0xffffffff. You only need to change
@@ -321,9 +316,9 @@ struct pci_dev {
321 316
322 struct device_dma_parameters dma_parms; 317 struct device_dma_parameters dma_parms;
323 318
324 pci_power_t current_state; /* Current operating state. In ACPI-speak, 319 pci_power_t current_state; /* Current operating state. In ACPI,
325 this is D0-D3, D0 being fully functional, 320 this is D0-D3, D0 being fully
326 and D3 being off. */ 321 functional, and D3 being off. */
327 u8 pm_cap; /* PM capability offset */ 322 u8 pm_cap; /* PM capability offset */
328 unsigned int pme_support:5; /* Bitmask of states from which PME# 323 unsigned int pme_support:5; /* Bitmask of states from which PME#
329 can be generated */ 324 can be generated */
@@ -334,10 +329,10 @@ struct pci_dev {
334 unsigned int no_d3cold:1; /* D3cold is forbidden */ 329 unsigned int no_d3cold:1; /* D3cold is forbidden */
335 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 330 unsigned int bridge_d3:1; /* Allow D3 for bridge */
336 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 331 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
337 unsigned int mmio_always_on:1; /* disallow turning off io/mem 332 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
338 decoding during bar sizing */ 333 decoding during BAR sizing */
339 unsigned int wakeup_prepared:1; 334 unsigned int wakeup_prepared:1;
340 unsigned int runtime_d3cold:1; /* whether go through runtime 335 unsigned int runtime_d3cold:1; /* Whether go through runtime
341 D3cold, not set for devices 336 D3cold, not set for devices
342 powered on/off by the 337 powered on/off by the
343 corresponding bridge */ 338 corresponding bridge */
@@ -354,10 +349,10 @@ struct pci_dev {
354 supported from root to here */ 349 supported from root to here */
355#endif 350#endif
356 351
357 pci_channel_state_t error_state; /* current connectivity state */ 352 pci_channel_state_t error_state; /* Current connectivity state */
358 struct device dev; /* Generic device interface */ 353 struct device dev; /* Generic device interface */
359 354
360 int cfg_size; /* Size of configuration space */ 355 int cfg_size; /* Size of config space */
361 356
362 /* 357 /*
363 * Instead of touching interrupt line and base address registers 358 * Instead of touching interrupt line and base address registers
@@ -366,47 +361,47 @@ struct pci_dev {
366 unsigned int irq; 361 unsigned int irq;
367 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 362 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
368 363
369 bool match_driver; /* Skip attaching driver */ 364 bool match_driver; /* Skip attaching driver */
370 /* These fields are used by common fixups */ 365
371 unsigned int transparent:1; /* Subtractive decode PCI bridge */ 366 unsigned int transparent:1; /* Subtractive decode bridge */
372 unsigned int multifunction:1;/* Part of multi-function device */ 367 unsigned int multifunction:1; /* Multi-function device */
373 /* keep track of device state */ 368
374 unsigned int is_added:1; 369 unsigned int is_added:1;
375 unsigned int is_busmaster:1; /* device is busmaster */ 370 unsigned int is_busmaster:1; /* Is busmaster */
376 unsigned int no_msi:1; /* device may not use msi */ 371 unsigned int no_msi:1; /* May not use MSI */
377 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */ 372 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
378 unsigned int block_cfg_access:1; /* config space access is blocked */ 373 unsigned int block_cfg_access:1; /* Config space access blocked */
379 unsigned int broken_parity_status:1; /* Device generates false positive parity */ 374 unsigned int broken_parity_status:1; /* Generates false positive parity */
380 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ 375 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
381 unsigned int msi_enabled:1; 376 unsigned int msi_enabled:1;
382 unsigned int msix_enabled:1; 377 unsigned int msix_enabled:1;
383 unsigned int ari_enabled:1; /* ARI forwarding */ 378 unsigned int ari_enabled:1; /* ARI forwarding */
384 unsigned int ats_enabled:1; /* Address Translation Service */ 379 unsigned int ats_enabled:1; /* Address Translation Svc */
385 unsigned int pasid_enabled:1; /* Process Address Space ID */ 380 unsigned int pasid_enabled:1; /* Process Address Space ID */
386 unsigned int pri_enabled:1; /* Page Request Interface */ 381 unsigned int pri_enabled:1; /* Page Request Interface */
387 unsigned int is_managed:1; 382 unsigned int is_managed:1;
388 unsigned int needs_freset:1; /* Dev requires fundamental reset */ 383 unsigned int needs_freset:1; /* Requires fundamental reset */
389 unsigned int state_saved:1; 384 unsigned int state_saved:1;
390 unsigned int is_physfn:1; 385 unsigned int is_physfn:1;
391 unsigned int is_virtfn:1; 386 unsigned int is_virtfn:1;
392 unsigned int reset_fn:1; 387 unsigned int reset_fn:1;
393 unsigned int is_hotplug_bridge:1; 388 unsigned int is_hotplug_bridge:1;
394 unsigned int is_thunderbolt:1; /* Thunderbolt controller */ 389 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
395 unsigned int __aer_firmware_first_valid:1; 390 unsigned int __aer_firmware_first_valid:1;
396 unsigned int __aer_firmware_first:1; 391 unsigned int __aer_firmware_first:1;
397 unsigned int broken_intx_masking:1; /* INTx masking can't be used */ 392 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
398 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */ 393 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
399 unsigned int irq_managed:1; 394 unsigned int irq_managed:1;
400 unsigned int has_secondary_link:1; 395 unsigned int has_secondary_link:1;
401 unsigned int non_compliant_bars:1; /* broken BARs; ignore them */ 396 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
402 unsigned int is_probed:1; /* device probing in progress */ 397 unsigned int is_probed:1; /* Device probing in progress */
403 pci_dev_flags_t dev_flags; 398 pci_dev_flags_t dev_flags;
404 atomic_t enable_cnt; /* pci_enable_device has been called */ 399 atomic_t enable_cnt; /* pci_enable_device has been called */
405 400
406 u32 saved_config_space[16]; /* config space saved at suspend time */ 401 u32 saved_config_space[16]; /* Config space saved at suspend time */
407 struct hlist_head saved_cap_space; 402 struct hlist_head saved_cap_space;
408 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ 403 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */
409 int rom_attr_enabled; /* has display of the rom attribute been enabled? */ 404 int rom_attr_enabled; /* Display of ROM attribute enabled? */
410 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 405 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
411 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 406 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
412 407
@@ -421,12 +416,12 @@ struct pci_dev {
421 struct pci_vpd *vpd; 416 struct pci_vpd *vpd;
422#ifdef CONFIG_PCI_ATS 417#ifdef CONFIG_PCI_ATS
423 union { 418 union {
424 struct pci_sriov *sriov; /* SR-IOV capability related */ 419 struct pci_sriov *sriov; /* PF: SR-IOV info */
425 struct pci_dev *physfn; /* the PF this VF is associated with */ 420 struct pci_dev *physfn; /* VF: related PF */
426 }; 421 };
427 u16 ats_cap; /* ATS Capability offset */ 422 u16 ats_cap; /* ATS Capability offset */
428 u8 ats_stu; /* ATS Smallest Translation Unit */ 423 u8 ats_stu; /* ATS Smallest Translation Unit */
429 atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */ 424 atomic_t ats_ref_cnt; /* Number of VFs with ATS enabled */
430#endif 425#endif
431#ifdef CONFIG_PCI_PRI 426#ifdef CONFIG_PCI_PRI
432 u32 pri_reqs_alloc; /* Number of PRI requests allocated */ 427 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
@@ -434,11 +429,11 @@ struct pci_dev {
434#ifdef CONFIG_PCI_PASID 429#ifdef CONFIG_PCI_PASID
435 u16 pasid_features; 430 u16 pasid_features;
436#endif 431#endif
437 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */ 432 phys_addr_t rom; /* Physical address if not from BAR */
438 size_t romlen; /* Length of ROM if it's not from the BAR */ 433 size_t romlen; /* Length if not from BAR */
439 char *driver_override; /* Driver name to force a match */ 434 char *driver_override; /* Driver name to force a match */
440 435
441 unsigned long priv_flags; /* Private flags for the pci driver */ 436 unsigned long priv_flags; /* Private flags for the PCI driver */
442}; 437};
443 438
444static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 439static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
@@ -461,26 +456,26 @@ static inline int pci_channel_offline(struct pci_dev *pdev)
461} 456}
462 457
463struct pci_host_bridge { 458struct pci_host_bridge {
464 struct device dev; 459 struct device dev;
465 struct pci_bus *bus; /* root bus */ 460 struct pci_bus *bus; /* Root bus */
466 struct pci_ops *ops; 461 struct pci_ops *ops;
467 void *sysdata; 462 void *sysdata;
468 int busnr; 463 int busnr;
469 struct list_head windows; /* resource_entry */ 464 struct list_head windows; /* resource_entry */
470 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* platform IRQ swizzler */ 465 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
471 int (*map_irq)(const struct pci_dev *, u8, u8); 466 int (*map_irq)(const struct pci_dev *, u8, u8);
472 void (*release_fn)(struct pci_host_bridge *); 467 void (*release_fn)(struct pci_host_bridge *);
473 void *release_data; 468 void *release_data;
474 struct msi_controller *msi; 469 struct msi_controller *msi;
475 unsigned int ignore_reset_delay:1; /* for entire hierarchy */ 470 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
476 unsigned int no_ext_tags:1; /* no Extended Tags */ 471 unsigned int no_ext_tags:1; /* No Extended Tags */
477 /* Resource alignment requirements */ 472 /* Resource alignment requirements */
478 resource_size_t (*align_resource)(struct pci_dev *dev, 473 resource_size_t (*align_resource)(struct pci_dev *dev,
479 const struct resource *res, 474 const struct resource *res,
480 resource_size_t start, 475 resource_size_t start,
481 resource_size_t size, 476 resource_size_t size,
482 resource_size_t align); 477 resource_size_t align);
483 unsigned long private[0] ____cacheline_aligned; 478 unsigned long private[0] ____cacheline_aligned;
484}; 479};
485 480
486#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 481#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
@@ -502,8 +497,8 @@ void pci_free_host_bridge(struct pci_host_bridge *bridge);
502struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 497struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
503 498
504void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 499void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
505 void (*release_fn)(struct pci_host_bridge *), 500 void (*release_fn)(struct pci_host_bridge *),
506 void *release_data); 501 void *release_data);
507 502
508int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 503int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
509 504
@@ -523,32 +518,32 @@ int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
523#define PCI_SUBTRACTIVE_DECODE 0x1 518#define PCI_SUBTRACTIVE_DECODE 0x1
524 519
525struct pci_bus_resource { 520struct pci_bus_resource {
526 struct list_head list; 521 struct list_head list;
527 struct resource *res; 522 struct resource *res;
528 unsigned int flags; 523 unsigned int flags;
529}; 524};
530 525
531#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 526#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
532 527
533struct pci_bus { 528struct pci_bus {
534 struct list_head node; /* node in list of buses */ 529 struct list_head node; /* Node in list of buses */
535 struct pci_bus *parent; /* parent bus this bridge is on */ 530 struct pci_bus *parent; /* Parent bus this bridge is on */
536 struct list_head children; /* list of child buses */ 531 struct list_head children; /* List of child buses */
537 struct list_head devices; /* list of devices on this bus */ 532 struct list_head devices; /* List of devices on this bus */
538 struct pci_dev *self; /* bridge device as seen by parent */ 533 struct pci_dev *self; /* Bridge device as seen by parent */
539 struct list_head slots; /* list of slots on this bus; 534 struct list_head slots; /* List of slots on this bus;
540 protected by pci_slot_mutex */ 535 protected by pci_slot_mutex */
541 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 536 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
542 struct list_head resources; /* address space routed to this bus */ 537 struct list_head resources; /* Address space routed to this bus */
543 struct resource busn_res; /* bus numbers routed to this bus */ 538 struct resource busn_res; /* Bus numbers routed to this bus */
544 539
545 struct pci_ops *ops; /* configuration access functions */ 540 struct pci_ops *ops; /* Configuration access functions */
546 struct msi_controller *msi; /* MSI controller */ 541 struct msi_controller *msi; /* MSI controller */
547 void *sysdata; /* hook for sys-specific extension */ 542 void *sysdata; /* Hook for sys-specific extension */
548 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ 543 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
549 544
550 unsigned char number; /* bus number */ 545 unsigned char number; /* Bus number */
551 unsigned char primary; /* number of primary bridge */ 546 unsigned char primary; /* Number of primary bridge */
552 unsigned char max_bus_speed; /* enum pci_bus_speed */ 547 unsigned char max_bus_speed; /* enum pci_bus_speed */
553 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 548 unsigned char cur_bus_speed; /* enum pci_bus_speed */
554#ifdef CONFIG_PCI_DOMAINS_GENERIC 549#ifdef CONFIG_PCI_DOMAINS_GENERIC
@@ -557,12 +552,12 @@ struct pci_bus {
557 552
558 char name[48]; 553 char name[48];
559 554
560 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ 555 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
561 pci_bus_flags_t bus_flags; /* inherited by child buses */ 556 pci_bus_flags_t bus_flags; /* Inherited by child buses */
562 struct device *bridge; 557 struct device *bridge;
563 struct device dev; 558 struct device dev;
564 struct bin_attribute *legacy_io; /* legacy I/O for this bus */ 559 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
565 struct bin_attribute *legacy_mem; /* legacy mem */ 560 struct bin_attribute *legacy_mem; /* Legacy mem */
566 unsigned int is_added:1; 561 unsigned int is_added:1;
567}; 562};
568 563
@@ -619,9 +614,7 @@ static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
619static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 614static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
620#endif 615#endif
621 616
622/* 617/* Error values that may be returned by PCI functions */
623 * Error values that may be returned by PCI functions.
624 */
625#define PCIBIOS_SUCCESSFUL 0x00 618#define PCIBIOS_SUCCESSFUL 0x00
626#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 619#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
627#define PCIBIOS_BAD_VENDOR_ID 0x83 620#define PCIBIOS_BAD_VENDOR_ID 0x83
@@ -630,9 +623,7 @@ static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false;
630#define PCIBIOS_SET_FAILED 0x88 623#define PCIBIOS_SET_FAILED 0x88
631#define PCIBIOS_BUFFER_TOO_SMALL 0x89 624#define PCIBIOS_BUFFER_TOO_SMALL 0x89
632 625
633/* 626/* Translate above to generic errno for passing back through non-PCI code */
634 * Translate above to generic errno for passing back through non-PCI code.
635 */
636static inline int pcibios_err_to_errno(int err) 627static inline int pcibios_err_to_errno(int err)
637{ 628{
638 if (err <= PCIBIOS_SUCCESSFUL) 629 if (err <= PCIBIOS_SUCCESSFUL)
@@ -682,13 +673,13 @@ typedef u32 pci_bus_addr_t;
682#endif 673#endif
683 674
684struct pci_bus_region { 675struct pci_bus_region {
685 pci_bus_addr_t start; 676 pci_bus_addr_t start;
686 pci_bus_addr_t end; 677 pci_bus_addr_t end;
687}; 678};
688 679
689struct pci_dynids { 680struct pci_dynids {
690 spinlock_t lock; /* protects list, index */ 681 spinlock_t lock; /* Protects list, index */
691 struct list_head list; /* for IDs added at runtime */ 682 struct list_head list; /* For IDs added at runtime */
692}; 683};
693 684
694 685
@@ -702,13 +693,13 @@ struct pci_dynids {
702typedef unsigned int __bitwise pci_ers_result_t; 693typedef unsigned int __bitwise pci_ers_result_t;
703 694
704enum pci_ers_result { 695enum pci_ers_result {
705 /* no result/none/not supported in device driver */ 696 /* No result/none/not supported in device driver */
706 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 697 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
707 698
708 /* Device driver can recover without slot reset */ 699 /* Device driver can recover without slot reset */
709 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 700 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
710 701
711 /* Device driver wants slot to be reset. */ 702 /* Device driver wants slot to be reset */
712 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 703 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
713 704
714 /* Device has completely failed, is unrecoverable */ 705 /* Device has completely failed, is unrecoverable */
@@ -744,27 +735,27 @@ struct pci_error_handlers {
744 735
745struct module; 736struct module;
746struct pci_driver { 737struct pci_driver {
747 struct list_head node; 738 struct list_head node;
748 const char *name; 739 const char *name;
749 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ 740 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
750 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 741 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
751 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 742 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
752 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 743 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
753 int (*suspend_late) (struct pci_dev *dev, pm_message_t state); 744 int (*suspend_late)(struct pci_dev *dev, pm_message_t state);
754 int (*resume_early) (struct pci_dev *dev); 745 int (*resume_early)(struct pci_dev *dev);
755 int (*resume) (struct pci_dev *dev); /* Device woken up */ 746 int (*resume) (struct pci_dev *dev); /* Device woken up */
756 void (*shutdown) (struct pci_dev *dev); 747 void (*shutdown) (struct pci_dev *dev);
757 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */ 748 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* On PF */
758 const struct pci_error_handlers *err_handler; 749 const struct pci_error_handlers *err_handler;
759 const struct attribute_group **groups; 750 const struct attribute_group **groups;
760 struct device_driver driver; 751 struct device_driver driver;
761 struct pci_dynids dynids; 752 struct pci_dynids dynids;
762}; 753};
763 754
764#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 755#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
765 756
766/** 757/**
767 * PCI_DEVICE - macro used to describe a specific pci device 758 * PCI_DEVICE - macro used to describe a specific PCI device
768 * @vend: the 16 bit PCI Vendor ID 759 * @vend: the 16 bit PCI Vendor ID
769 * @dev: the 16 bit PCI Device ID 760 * @dev: the 16 bit PCI Device ID
770 * 761 *
@@ -777,7 +768,7 @@ struct pci_driver {
777 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 768 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
778 769
779/** 770/**
780 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem 771 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
781 * @vend: the 16 bit PCI Vendor ID 772 * @vend: the 16 bit PCI Vendor ID
782 * @dev: the 16 bit PCI Device ID 773 * @dev: the 16 bit PCI Device ID
783 * @subvend: the 16 bit PCI Subvendor ID 774 * @subvend: the 16 bit PCI Subvendor ID
@@ -791,7 +782,7 @@ struct pci_driver {
791 .subvendor = (subvend), .subdevice = (subdev) 782 .subvendor = (subvend), .subdevice = (subdev)
792 783
793/** 784/**
794 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class 785 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
795 * @dev_class: the class, subclass, prog-if triple for this device 786 * @dev_class: the class, subclass, prog-if triple for this device
796 * @dev_class_mask: the class mask for this device 787 * @dev_class_mask: the class mask for this device
797 * 788 *
@@ -805,7 +796,7 @@ struct pci_driver {
805 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 796 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
806 797
807/** 798/**
808 * PCI_VDEVICE - macro used to describe a specific pci device in short form 799 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
809 * @vend: the vendor name 800 * @vend: the vendor name
810 * @dev: the 16 bit PCI Device ID 801 * @dev: the 16 bit PCI Device ID
811 * 802 *
@@ -814,22 +805,21 @@ struct pci_driver {
814 * to PCI_ANY_ID. The macro allows the next field to follow as the device 805 * to PCI_ANY_ID. The macro allows the next field to follow as the device
815 * private data. 806 * private data.
816 */ 807 */
817
818#define PCI_VDEVICE(vend, dev) \ 808#define PCI_VDEVICE(vend, dev) \
819 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 809 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
820 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 810 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
821 811
822enum { 812enum {
823 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* ignore firmware setup */ 813 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
824 PCI_REASSIGN_ALL_BUS = 0x00000002, /* reassign all bus numbers */ 814 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
825 PCI_PROBE_ONLY = 0x00000004, /* use existing setup */ 815 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
826 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* don't do ISA alignment */ 816 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
827 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* enable domains in /proc */ 817 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
828 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 818 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
829 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* scan all, not just dev 0 */ 819 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
830}; 820};
831 821
832/* these external functions are only available when PCI support is enabled */ 822/* These external functions are only available when PCI support is enabled */
833#ifdef CONFIG_PCI 823#ifdef CONFIG_PCI
834 824
835extern unsigned int pci_flags; 825extern unsigned int pci_flags;
@@ -842,11 +832,11 @@ static inline int pci_has_flag(int flag) { return pci_flags & flag; }
842void pcie_bus_configure_settings(struct pci_bus *bus); 832void pcie_bus_configure_settings(struct pci_bus *bus);
843 833
844enum pcie_bus_config_types { 834enum pcie_bus_config_types {
845 PCIE_BUS_TUNE_OFF, /* don't touch MPS at all */ 835 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
846 PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */ 836 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
847 PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */ 837 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
848 PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */ 838 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
849 PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */ 839 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
850}; 840};
851 841
852extern enum pcie_bus_config_types pcie_bus_config; 842extern enum pcie_bus_config_types pcie_bus_config;
@@ -855,7 +845,7 @@ extern struct bus_type pci_bus_type;
855 845
856/* Do NOT directly access these two variables, unless you are arch-specific PCI 846/* Do NOT directly access these two variables, unless you are arch-specific PCI
857 * code, or PCI core code. */ 847 * code, or PCI core code. */
858extern struct list_head pci_root_buses; /* list of all known PCI buses */ 848extern struct list_head pci_root_buses; /* List of all known PCI buses */
859/* Some device drivers need know if PCI is initiated */ 849/* Some device drivers need know if PCI is initiated */
860int no_pci_devices(void); 850int no_pci_devices(void);
861 851
@@ -893,8 +883,8 @@ int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
893int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 883int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
894void pci_bus_release_busn_res(struct pci_bus *b); 884void pci_bus_release_busn_res(struct pci_bus *b);
895struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 885struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
896 struct pci_ops *ops, void *sysdata, 886 struct pci_ops *ops, void *sysdata,
897 struct list_head *resources); 887 struct list_head *resources);
898int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); 888int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
899struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 889struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
900 int busnr); 890 int busnr);
@@ -951,10 +941,10 @@ int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
951struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 941struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
952 942
953struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 943struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
954 struct pci_dev *from); 944 struct pci_dev *from);
955struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 945struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
956 unsigned int ss_vendor, unsigned int ss_device, 946 unsigned int ss_vendor, unsigned int ss_device,
957 struct pci_dev *from); 947 struct pci_dev *from);
958struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 948struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
959struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 949struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
960 unsigned int devfn); 950 unsigned int devfn);
@@ -1030,7 +1020,7 @@ static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1030 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 1020 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1031} 1021}
1032 1022
1033/* user-space driven config access */ 1023/* User-space driven config access */
1034int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 1024int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1035int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 1025int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1036int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 1026int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
@@ -1172,7 +1162,7 @@ unsigned int pci_rescan_bus(struct pci_bus *bus);
1172void pci_lock_rescan_remove(void); 1162void pci_lock_rescan_remove(void);
1173void pci_unlock_rescan_remove(void); 1163void pci_unlock_rescan_remove(void);
1174 1164
1175/* Vital product data routines */ 1165/* Vital Product Data routines */
1176ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1166ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1177ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1167ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1178int pci_set_vpd_size(struct pci_dev *dev, size_t len); 1168int pci_set_vpd_size(struct pci_dev *dev, size_t len);
@@ -1257,9 +1247,7 @@ static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1257int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1247int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1258 const char *mod_name); 1248 const char *mod_name);
1259 1249
1260/* 1250/* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1261 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1262 */
1263#define pci_register_driver(driver) \ 1251#define pci_register_driver(driver) \
1264 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1252 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1265 1253
@@ -1274,8 +1262,7 @@ void pci_unregister_driver(struct pci_driver *dev);
1274 * use this macro once, and calling it replaces module_init() and module_exit() 1262 * use this macro once, and calling it replaces module_init() and module_exit()
1275 */ 1263 */
1276#define module_pci_driver(__pci_driver) \ 1264#define module_pci_driver(__pci_driver) \
1277 module_driver(__pci_driver, pci_register_driver, \ 1265 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1278 pci_unregister_driver)
1279 1266
1280/** 1267/**
1281 * builtin_pci_driver() - Helper macro for registering a PCI driver 1268 * builtin_pci_driver() - Helper macro for registering a PCI driver
@@ -1314,10 +1301,10 @@ resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
1314int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1301int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1315 unsigned int command_bits, u32 flags); 1302 unsigned int command_bits, u32 flags);
1316 1303
1317#define PCI_IRQ_LEGACY (1 << 0) /* allow legacy interrupts */ 1304#define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
1318#define PCI_IRQ_MSI (1 << 1) /* allow MSI interrupts */ 1305#define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1319#define PCI_IRQ_MSIX (1 << 2) /* allow MSI-X interrupts */ 1306#define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1320#define PCI_IRQ_AFFINITY (1 << 3) /* auto-assign affinity */ 1307#define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
1321#define PCI_IRQ_ALL_TYPES \ 1308#define PCI_IRQ_ALL_TYPES \
1322 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1309 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1323 1310
@@ -1336,8 +1323,8 @@ int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1336#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 1323#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1337 1324
1338struct msix_entry { 1325struct msix_entry {
1339 u32 vector; /* kernel uses to write allocated vector */ 1326 u32 vector; /* Kernel uses to write allocated vector */
1340 u16 entry; /* driver uses to specify entry, OS writes */ 1327 u16 entry; /* Driver uses to specify entry, OS writes */
1341}; 1328};
1342 1329
1343#ifdef CONFIG_PCI_MSI 1330#ifdef CONFIG_PCI_MSI
@@ -1377,10 +1364,10 @@ static inline int pci_msi_enabled(void) { return 0; }
1377static inline int pci_enable_msi(struct pci_dev *dev) 1364static inline int pci_enable_msi(struct pci_dev *dev)
1378{ return -ENOSYS; } 1365{ return -ENOSYS; }
1379static inline int pci_enable_msix_range(struct pci_dev *dev, 1366static inline int pci_enable_msix_range(struct pci_dev *dev,
1380 struct msix_entry *entries, int minvec, int maxvec) 1367 struct msix_entry *entries, int minvec, int maxvec)
1381{ return -ENOSYS; } 1368{ return -ENOSYS; }
1382static inline int pci_enable_msix_exact(struct pci_dev *dev, 1369static inline int pci_enable_msix_exact(struct pci_dev *dev,
1383 struct msix_entry *entries, int nvec) 1370 struct msix_entry *entries, int nvec)
1384{ return -ENOSYS; } 1371{ return -ENOSYS; }
1385 1372
1386static inline int 1373static inline int
@@ -1545,9 +1532,9 @@ static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1545int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 1532int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1546#endif 1533#endif
1547 1534
1548/* some architectures require additional setup to direct VGA traffic */ 1535/* Some architectures require additional setup to direct VGA traffic */
1549typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1536typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1550 unsigned int command_bits, u32 flags); 1537 unsigned int command_bits, u32 flags);
1551void pci_register_set_vga_state(arch_set_vga_state_t func); 1538void pci_register_set_vga_state(arch_set_vga_state_t func);
1552 1539
1553static inline int 1540static inline int
@@ -1586,10 +1573,9 @@ static inline void pci_clear_flags(int flags) { }
1586static inline int pci_has_flag(int flag) { return 0; } 1573static inline int pci_has_flag(int flag) { return 0; }
1587 1574
1588/* 1575/*
1589 * If the system does not have PCI, clearly these return errors. Define 1576 * If the system does not have PCI, clearly these return errors. Define
1590 * these as simple inline functions to avoid hair in drivers. 1577 * these as simple inline functions to avoid hair in drivers.
1591 */ 1578 */
1592
1593#define _PCI_NOP(o, s, t) \ 1579#define _PCI_NOP(o, s, t) \
1594 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1580 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1595 int where, t val) \ 1581 int where, t val) \
@@ -1735,8 +1721,10 @@ int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1735#define pci_root_bus_fwnode(bus) NULL 1721#define pci_root_bus_fwnode(bus) NULL
1736#endif 1722#endif
1737 1723
1738/* these helpers provide future and backwards compatibility 1724/*
1739 * for accessing popular PCI BAR info */ 1725 * These helpers provide future and backwards compatibility
1726 * for accessing popular PCI BAR info
1727 */
1740#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1728#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1741#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1729#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1742#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1730#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
@@ -1748,7 +1736,8 @@ int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1748 (pci_resource_end((dev), (bar)) - \ 1736 (pci_resource_end((dev), (bar)) - \
1749 pci_resource_start((dev), (bar)) + 1)) 1737 pci_resource_start((dev), (bar)) + 1))
1750 1738
1751/* Similar to the helpers above, these manipulate per-pci_dev 1739/*
1740 * Similar to the helpers above, these manipulate per-pci_dev
1752 * driver-specific data. They are really just a wrapper around 1741 * driver-specific data. They are really just a wrapper around
1753 * the generic device structure functions of these calls. 1742 * the generic device structure functions of these calls.
1754 */ 1743 */
@@ -1762,16 +1751,14 @@ static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1762 dev_set_drvdata(&pdev->dev, data); 1751 dev_set_drvdata(&pdev->dev, data);
1763} 1752}
1764 1753
1765/* If you want to know what to call your pci_dev, ask this function.
1766 * Again, it's a wrapper around the generic device.
1767 */
1768static inline const char *pci_name(const struct pci_dev *pdev) 1754static inline const char *pci_name(const struct pci_dev *pdev)
1769{ 1755{
1770 return dev_name(&pdev->dev); 1756 return dev_name(&pdev->dev);
1771} 1757}
1772 1758
1773 1759
1774/* Some archs don't want to expose struct resource to userland as-is 1760/*
1761 * Some archs don't want to expose struct resource to userland as-is
1775 * in sysfs and /proc 1762 * in sysfs and /proc
1776 */ 1763 */
1777#ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER 1764#ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
@@ -1790,16 +1777,16 @@ static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1790 1777
1791 1778
1792/* 1779/*
1793 * The world is not perfect and supplies us with broken PCI devices. 1780 * The world is not perfect and supplies us with broken PCI devices.
1794 * For at least a part of these bugs we need a work-around, so both 1781 * For at least a part of these bugs we need a work-around, so both
1795 * generic (drivers/pci/quirks.c) and per-architecture code can define 1782 * generic (drivers/pci/quirks.c) and per-architecture code can define
1796 * fixup hooks to be called for particular buggy devices. 1783 * fixup hooks to be called for particular buggy devices.
1797 */ 1784 */
1798 1785
1799struct pci_fixup { 1786struct pci_fixup {
1800 u16 vendor; /* You can use PCI_ANY_ID here of course */ 1787 u16 vendor; /* Or PCI_ANY_ID */
1801 u16 device; /* You can use PCI_ANY_ID here of course */ 1788 u16 device; /* Or PCI_ANY_ID */
1802 u32 class; /* You can use PCI_ANY_ID here too */ 1789 u32 class; /* Or PCI_ANY_ID */
1803 unsigned int class_shift; /* should be 0, 8, 16 */ 1790 unsigned int class_shift; /* should be 0, 8, 16 */
1804 void (*hook)(struct pci_dev *dev); 1791 void (*hook)(struct pci_dev *dev);
1805}; 1792};
@@ -1841,23 +1828,19 @@ enum pci_fixup_pass {
1841#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 1828#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1842 class_shift, hook) \ 1829 class_shift, hook) \
1843 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1830 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1844 resume##hook, vendor, device, class, \ 1831 resume##hook, vendor, device, class, class_shift, hook)
1845 class_shift, hook)
1846#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 1832#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1847 class_shift, hook) \ 1833 class_shift, hook) \
1848 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1834 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1849 resume_early##hook, vendor, device, \ 1835 resume_early##hook, vendor, device, class, class_shift, hook)
1850 class, class_shift, hook)
1851#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 1836#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1852 class_shift, hook) \ 1837 class_shift, hook) \
1853 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1838 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1854 suspend##hook, vendor, device, class, \ 1839 suspend##hook, vendor, device, class, class_shift, hook)
1855 class_shift, hook)
1856#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 1840#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1857 class_shift, hook) \ 1841 class_shift, hook) \
1858 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1842 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1859 suspend_late##hook, vendor, device, \ 1843 suspend_late##hook, vendor, device, class, class_shift, hook)
1860 class, class_shift, hook)
1861 1844
1862#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 1845#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1863 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1846 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
@@ -1873,20 +1856,16 @@ enum pci_fixup_pass {
1873 hook, vendor, device, PCI_ANY_ID, 0, hook) 1856 hook, vendor, device, PCI_ANY_ID, 0, hook)
1874#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 1857#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1875 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1858 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1876 resume##hook, vendor, device, \ 1859 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
1877 PCI_ANY_ID, 0, hook)
1878#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 1860#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1879 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1861 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1880 resume_early##hook, vendor, device, \ 1862 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
1881 PCI_ANY_ID, 0, hook)
1882#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 1863#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1883 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1864 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1884 suspend##hook, vendor, device, \ 1865 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
1885 PCI_ANY_ID, 0, hook)
1886#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 1866#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1887 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1867 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1888 suspend_late##hook, vendor, device, \ 1868 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
1889 PCI_ANY_ID, 0, hook)
1890 1869
1891#ifdef CONFIG_PCI_QUIRKS 1870#ifdef CONFIG_PCI_QUIRKS
1892void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1871void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
@@ -2122,7 +2101,7 @@ static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2122 */ 2101 */
2123static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt) 2102static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2124{ 2103{
2125 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK); 2104 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2126} 2105}
2127 2106
2128/** 2107/**
@@ -2207,7 +2186,7 @@ static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2207 return bus ? bus->dev.of_node : NULL; 2186 return bus ? bus->dev.of_node : NULL;
2208} 2187}
2209 2188
2210#else /* CONFIG_OF */ 2189#else /* CONFIG_OF */
2211static inline void pci_set_of_node(struct pci_dev *dev) { } 2190static inline void pci_set_of_node(struct pci_dev *dev) { }
2212static inline void pci_release_of_node(struct pci_dev *dev) { } 2191static inline void pci_release_of_node(struct pci_dev *dev) { }
2213static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 2192static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
@@ -2216,7 +2195,7 @@ static inline struct device_node *
2216pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; } 2195pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; }
2217static inline struct irq_domain * 2196static inline struct irq_domain *
2218pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2197pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2219#endif /* CONFIG_OF */ 2198#endif /* CONFIG_OF */
2220 2199
2221#ifdef CONFIG_ACPI 2200#ifdef CONFIG_ACPI
2222struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); 2201struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
@@ -2241,7 +2220,7 @@ int pci_for_each_dma_alias(struct pci_dev *pdev,
2241 int (*fn)(struct pci_dev *pdev, 2220 int (*fn)(struct pci_dev *pdev,
2242 u16 alias, void *data), void *data); 2221 u16 alias, void *data), void *data);
2243 2222
2244/* helper functions for operation of device flag */ 2223/* Helper functions for operation of device flag */
2245static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2224static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2246{ 2225{
2247 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2226 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
@@ -2288,7 +2267,7 @@ static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2288 return false; 2267 return false;
2289} 2268}
2290 2269
2291/* provide the legacy pci_dma_* API */ 2270/* Provide the legacy pci_dma_* API */
2292#include <linux/pci-dma-compat.h> 2271#include <linux/pci-dma-compat.h>
2293 2272
2294#define pci_printk(level, pdev, fmt, arg...) \ 2273#define pci_printk(level, pdev, fmt, arg...) \