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authorLinus Torvalds <torvalds@linux-foundation.org>2015-09-04 13:22:09 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2015-09-04 13:22:09 -0400
commit88a99886c26fec8bf662e7b6bc080431a8660326 (patch)
tree615b9a9a959ab093f6d8d0dd94d3bbc5299fc4c6 /drivers/pinctrl/qcom
parent8d2faea672606827c2018143ec7d88c760f2d6de (diff)
parent1ab36387ea4face01aac3560b396b1e2ce07c4ff (diff)
Merge tag 'pinctrl-v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v4.3 development cycle. Like with GPIO it's a lot of stuff. If my subsystems are any sign of the overall tempo of the kernel v4.3 will be a gigantic diff. [ It looks like 4.3 is calmer than 4.2 in most other subsystems, but we'll see - Linus ] Core changes: - It is possible configure groups in debugfs. - Consolidation of chained IRQ handler install/remove replacing all call sites where irq_set_handler_data() and irq_set_chained_handler() were done in succession with a combined call to irq_set_chained_handler_and_data(). This series was created by Thomas Gleixner after the problem was observed by Russell King. - Tglx also made another series of patches switching __irq_set_handler_locked() for irq_set_handler_locked() which is way cleaner. - Tglx also wrote a good bunch of patches to make use of irq_desc_get_xxx() accessors and avoid looking up irq_descs from IRQ numbers. The goal is to get rid of the irq number from the handlers in the IRQ flow which is nice. Driver feature enhancements: - Power management support for the SiRF SoC Atlas 7. - Power down support for the Qualcomm driver. - Intel Cherryview and Baytrail: switch drivers to use raw spinlocks in IRQ handlers to play nice with the realtime patch set. - Rework and new modes handling for Qualcomm SPMI-MPP. - Pinconf power source config for SH PFC. New drivers and subdrivers: - A new driver for Conexant Digicolor CX92755. - A new driver for UniPhier PH1-LD4, PH1-Pro4, PH1-sLD8, PH1-Pro5, ProXtream2 and PH1-LD6b SoC pin control support. - Reverse-egineered the S/PDIF settings for the Allwinner sun4i driver. - Support for Qualcomm Technologies QDF2xxx ARM64 SoCs - A new Freescale i.mx6ul subdriver. Cleanup: - Remove platform data support in a number of SH PFC subdrivers" * tag 'pinctrl-v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (95 commits) pinctrl: at91: fix null pointer dereference pinctrl: mediatek: Implement wake handler and suspend resume pinctrl: mediatek: Fix multiple registration issue. pinctrl: sh-pfc: r8a7794: add USB pin groups pinctrl: at91: Use generic irq_{request,release}_resources() pinctrl: cherryview: Use raw_spinlock for locking pinctrl: baytrail: Use raw_spinlock for locking pinctrl: imx6ul: Remove .owner field pinctrl: zynq: Fix typos in smc0_nand_grp and smc0_nor_grp pinctrl: sh-pfc: Implement pinconf power-source param for voltage switching clk: rockchip: add pclk_pd_pmu to the list of rk3288 critical clocks pinctrl: sun4i: add spdif to pin description. pinctrl: atlas7: clear ugly branch statements for pull and drivestrength pinctrl: baytrail: Serialize all register access pinctrl: baytrail: Drop FSF mailing address pinctrl: rockchip: only enable gpio clock when it setting pinctrl/mediatek: fix spelling mistake in dev_err error message pinctrl: cherryview: Serialize all register access pinctrl: UniPhier: PH1-Pro5: add I2C ch6 pin-mux setting pinctrl: nomadik: reflect current input value ...
Diffstat (limited to 'drivers/pinctrl/qcom')
-rw-r--r--drivers/pinctrl/qcom/Kconfig20
-rw-r--r--drivers/pinctrl/qcom/Makefile3
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm.c19
-rw-r--r--drivers/pinctrl/qcom/pinctrl-qdf2xxx.c122
-rw-r--r--drivers/pinctrl/qcom/pinctrl-spmi-mpp.c376
-rw-r--r--drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c791
-rw-r--r--drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c882
7 files changed, 2015 insertions, 198 deletions
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 58f5632b27f4..383263a92e59 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -63,6 +63,14 @@ config PINCTRL_MSM8916
63 This is the pinctrl, pinmux, pinconf and gpiolib driver for the 63 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
64 Qualcomm TLMM block found on the Qualcomm 8916 platform. 64 Qualcomm TLMM block found on the Qualcomm 8916 platform.
65 65
66config PINCTRL_QDF2XXX
67 tristate "Qualcomm Technologies QDF2xxx pin controller driver"
68 depends on GPIOLIB && ACPI
69 select PINCTRL_MSM
70 help
71 This is the GPIO driver for the TLMM block found on the
72 Qualcomm Technologies QDF2xxx SOCs.
73
66config PINCTRL_QCOM_SPMI_PMIC 74config PINCTRL_QCOM_SPMI_PMIC
67 tristate "Qualcomm SPMI PMIC pin controller driver" 75 tristate "Qualcomm SPMI PMIC pin controller driver"
68 depends on GPIOLIB && OF && SPMI 76 depends on GPIOLIB && OF && SPMI
@@ -76,4 +84,16 @@ config PINCTRL_QCOM_SPMI_PMIC
76 which are using SPMI for communication with SoC. Example PMIC's 84 which are using SPMI for communication with SoC. Example PMIC's
77 devices are pm8841, pm8941 and pma8084. 85 devices are pm8841, pm8941 and pma8084.
78 86
87config PINCTRL_QCOM_SSBI_PMIC
88 tristate "Qualcomm SSBI PMIC pin controller driver"
89 depends on GPIOLIB && OF
90 select PINMUX
91 select PINCONF
92 select GENERIC_PINCONF
93 help
94 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
95 Qualcomm GPIO and MPP blocks found in the Qualcomm PMIC's chips,
96 which are using SSBI for communication with SoC. Example PMIC's
97 devices are pm8058 and pm8921.
98
79endif 99endif
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 3666c703ce88..13b190e72c21 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -7,5 +7,8 @@ obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o
7obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o 7obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o
8obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o 8obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
9obj-$(CONFIG_PINCTRL_MSM8916) += pinctrl-msm8916.o 9obj-$(CONFIG_PINCTRL_MSM8916) += pinctrl-msm8916.o
10obj-$(CONFIG_PINCTRL_QDF2XXX) += pinctrl-qdf2xxx.o
10obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o 11obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o
11obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o 12obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o
13obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o
14obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index e457d52302a2..492cdd51dc5c 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -28,6 +28,7 @@
28#include <linux/interrupt.h> 28#include <linux/interrupt.h>
29#include <linux/spinlock.h> 29#include <linux/spinlock.h>
30#include <linux/reboot.h> 30#include <linux/reboot.h>
31#include <linux/pm.h>
31 32
32#include "../core.h" 33#include "../core.h"
33#include "../pinconf.h" 34#include "../pinconf.h"
@@ -733,9 +734,9 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
733 spin_unlock_irqrestore(&pctrl->lock, flags); 734 spin_unlock_irqrestore(&pctrl->lock, flags);
734 735
735 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 736 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
736 __irq_set_handler_locked(d->irq, handle_level_irq); 737 irq_set_handler_locked(d, handle_level_irq);
737 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 738 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
738 __irq_set_handler_locked(d->irq, handle_edge_irq); 739 irq_set_handler_locked(d, handle_edge_irq);
739 740
740 return 0; 741 return 0;
741} 742}
@@ -764,12 +765,13 @@ static struct irq_chip msm_gpio_irq_chip = {
764 .irq_set_wake = msm_gpio_irq_set_wake, 765 .irq_set_wake = msm_gpio_irq_set_wake,
765}; 766};
766 767
767static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) 768static void msm_gpio_irq_handler(unsigned int __irq, struct irq_desc *desc)
768{ 769{
770 unsigned int irq = irq_desc_get_irq(desc);
769 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 771 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
770 const struct msm_pingroup *g; 772 const struct msm_pingroup *g;
771 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); 773 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
772 struct irq_chip *chip = irq_get_chip(irq); 774 struct irq_chip *chip = irq_desc_get_chip(desc);
773 int irq_pin; 775 int irq_pin;
774 int handled = 0; 776 int handled = 0;
775 u32 val; 777 u32 val;
@@ -855,6 +857,13 @@ static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action,
855 return NOTIFY_DONE; 857 return NOTIFY_DONE;
856} 858}
857 859
860static struct msm_pinctrl *poweroff_pctrl;
861
862static void msm_ps_hold_poweroff(void)
863{
864 msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL);
865}
866
858static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) 867static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
859{ 868{
860 int i; 869 int i;
@@ -867,6 +876,8 @@ static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
867 if (register_restart_handler(&pctrl->restart_nb)) 876 if (register_restart_handler(&pctrl->restart_nb))
868 dev_err(pctrl->dev, 877 dev_err(pctrl->dev,
869 "failed to setup restart handler.\n"); 878 "failed to setup restart handler.\n");
879 poweroff_pctrl = pctrl;
880 pm_power_off = msm_ps_hold_poweroff;
870 break; 881 break;
871 } 882 }
872} 883}
diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
new file mode 100644
index 000000000000..e9ff3bc150bb
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
@@ -0,0 +1,122 @@
1/*
2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * GPIO and pin control functions on this SOC are handled by the "TLMM"
14 * device. The driver which controls this device is pinctrl-msm.c. Each
15 * SOC with a TLMM is expected to create a client driver that registers
16 * with pinctrl-msm.c. This means that all TLMM drivers are pin control
17 * drivers.
18 *
19 * This pin control driver is intended to be used only an ACPI-enabled
20 * system. As such, UEFI will handle all pin control configuration, so
21 * this driver does not provide pin control functions. It is effectively
22 * a GPIO-only driver. The alternative is to duplicate the GPIO code of
23 * pinctrl-msm.c into another driver.
24 */
25
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/pinctrl/pinctrl.h>
29#include <linux/acpi.h>
30
31#include "pinctrl-msm.h"
32
33static struct msm_pinctrl_soc_data qdf2xxx_pinctrl;
34
35static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
36{
37 struct pinctrl_pin_desc *pins;
38 struct msm_pingroup *groups;
39 unsigned int i;
40 u32 num_gpios;
41 int ret;
42
43 /* Query the number of GPIOs from ACPI */
44 ret = device_property_read_u32(&pdev->dev, "num-gpios", &num_gpios);
45 if (ret < 0)
46 return ret;
47
48 if (!num_gpios) {
49 dev_warn(&pdev->dev, "missing num-gpios property\n");
50 return -ENODEV;
51 }
52
53 pins = devm_kcalloc(&pdev->dev, num_gpios,
54 sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
55 groups = devm_kcalloc(&pdev->dev, num_gpios,
56 sizeof(struct msm_pingroup), GFP_KERNEL);
57
58 for (i = 0; i < num_gpios; i++) {
59 pins[i].number = i;
60
61 groups[i].npins = 1,
62 groups[i].pins = &pins[i].number;
63 groups[i].ctl_reg = 0x10000 * i;
64 groups[i].io_reg = 0x04 + 0x10000 * i;
65 groups[i].intr_cfg_reg = 0x08 + 0x10000 * i;
66 groups[i].intr_status_reg = 0x0c + 0x10000 * i;
67 groups[i].intr_target_reg = 0x08 + 0x10000 * i;
68
69 groups[i].mux_bit = 2;
70 groups[i].pull_bit = 0;
71 groups[i].drv_bit = 6;
72 groups[i].oe_bit = 9;
73 groups[i].in_bit = 0;
74 groups[i].out_bit = 1;
75 groups[i].intr_enable_bit = 0;
76 groups[i].intr_status_bit = 0;
77 groups[i].intr_target_bit = 5;
78 groups[i].intr_target_kpss_val = 1;
79 groups[i].intr_raw_status_bit = 4;
80 groups[i].intr_polarity_bit = 1;
81 groups[i].intr_detection_bit = 2;
82 groups[i].intr_detection_width = 2;
83 }
84
85 qdf2xxx_pinctrl.pins = pins;
86 qdf2xxx_pinctrl.groups = groups;
87 qdf2xxx_pinctrl.npins = num_gpios;
88 qdf2xxx_pinctrl.ngroups = num_gpios;
89 qdf2xxx_pinctrl.ngpios = num_gpios;
90
91 return msm_pinctrl_probe(pdev, &qdf2xxx_pinctrl);
92}
93
94static const struct acpi_device_id qdf2xxx_acpi_ids[] = {
95 {"QCOM8001"},
96 {},
97};
98MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids);
99
100static struct platform_driver qdf2xxx_pinctrl_driver = {
101 .driver = {
102 .name = "qdf2xxx-pinctrl",
103 .acpi_match_table = ACPI_PTR(qdf2xxx_acpi_ids),
104 },
105 .probe = qdf2xxx_pinctrl_probe,
106 .remove = msm_pinctrl_remove,
107};
108
109static int __init qdf2xxx_pinctrl_init(void)
110{
111 return platform_driver_register(&qdf2xxx_pinctrl_driver);
112}
113arch_initcall(qdf2xxx_pinctrl_init);
114
115static void __exit qdf2xxx_pinctrl_exit(void)
116{
117 platform_driver_unregister(&qdf2xxx_pinctrl_driver);
118}
119module_exit(qdf2xxx_pinctrl_exit);
120
121MODULE_DESCRIPTION("Qualcomm Technologies QDF2xxx pin control driver");
122MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
index 3121de9b6331..e3be3ce2cada 100644
--- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
+++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
@@ -61,7 +61,9 @@
61#define PMIC_MPP_REG_DIG_PULL_CTL 0x42 61#define PMIC_MPP_REG_DIG_PULL_CTL 0x42
62#define PMIC_MPP_REG_DIG_IN_CTL 0x43 62#define PMIC_MPP_REG_DIG_IN_CTL 0x43
63#define PMIC_MPP_REG_EN_CTL 0x46 63#define PMIC_MPP_REG_EN_CTL 0x46
64#define PMIC_MPP_REG_AOUT_CTL 0x48
64#define PMIC_MPP_REG_AIN_CTL 0x4a 65#define PMIC_MPP_REG_AIN_CTL 0x4a
66#define PMIC_MPP_REG_SINK_CTL 0x4c
65 67
66/* PMIC_MPP_REG_MODE_CTL */ 68/* PMIC_MPP_REG_MODE_CTL */
67#define PMIC_MPP_REG_MODE_VALUE_MASK 0x1 69#define PMIC_MPP_REG_MODE_VALUE_MASK 0x1
@@ -85,11 +87,25 @@
85#define PMIC_MPP_REG_AIN_ROUTE_SHIFT 0 87#define PMIC_MPP_REG_AIN_ROUTE_SHIFT 0
86#define PMIC_MPP_REG_AIN_ROUTE_MASK 0x7 88#define PMIC_MPP_REG_AIN_ROUTE_MASK 0x7
87 89
90#define PMIC_MPP_MODE_DIGITAL_INPUT 0
91#define PMIC_MPP_MODE_DIGITAL_OUTPUT 1
92#define PMIC_MPP_MODE_DIGITAL_BIDIR 2
93#define PMIC_MPP_MODE_ANALOG_BIDIR 3
94#define PMIC_MPP_MODE_ANALOG_INPUT 4
95#define PMIC_MPP_MODE_ANALOG_OUTPUT 5
96#define PMIC_MPP_MODE_CURRENT_SINK 6
97
98#define PMIC_MPP_SELECTOR_NORMAL 0
99#define PMIC_MPP_SELECTOR_PAIRED 1
100#define PMIC_MPP_SELECTOR_DTEST_FIRST 4
101
88#define PMIC_MPP_PHYSICAL_OFFSET 1 102#define PMIC_MPP_PHYSICAL_OFFSET 1
89 103
90/* Qualcomm specific pin configurations */ 104/* Qualcomm specific pin configurations */
91#define PMIC_MPP_CONF_AMUX_ROUTE (PIN_CONFIG_END + 1) 105#define PMIC_MPP_CONF_AMUX_ROUTE (PIN_CONFIG_END + 1)
92#define PMIC_MPP_CONF_ANALOG_MODE (PIN_CONFIG_END + 2) 106#define PMIC_MPP_CONF_ANALOG_LEVEL (PIN_CONFIG_END + 2)
107#define PMIC_MPP_CONF_DTEST_SELECTOR (PIN_CONFIG_END + 3)
108#define PMIC_MPP_CONF_PAIRED (PIN_CONFIG_END + 4)
93 109
94/** 110/**
95 * struct pmic_mpp_pad - keep current MPP settings 111 * struct pmic_mpp_pad - keep current MPP settings
@@ -99,13 +115,15 @@
99 * @out_value: Cached pin output value. 115 * @out_value: Cached pin output value.
100 * @output_enabled: Set to true if MPP output logic is enabled. 116 * @output_enabled: Set to true if MPP output logic is enabled.
101 * @input_enabled: Set to true if MPP input buffer logic is enabled. 117 * @input_enabled: Set to true if MPP input buffer logic is enabled.
102 * @analog_mode: Set to true when MPP should operate in Analog Input, Analog 118 * @paired: Pin operates in paired mode
103 * Output or Bidirectional Analog mode.
104 * @num_sources: Number of power-sources supported by this MPP. 119 * @num_sources: Number of power-sources supported by this MPP.
105 * @power_source: Current power-source used. 120 * @power_source: Current power-source used.
106 * @amux_input: Set the source for analog input. 121 * @amux_input: Set the source for analog input.
122 * @aout_level: Analog output level
107 * @pullup: Pullup resistor value. Valid in Bidirectional mode only. 123 * @pullup: Pullup resistor value. Valid in Bidirectional mode only.
108 * @function: See pmic_mpp_functions[]. 124 * @function: See pmic_mpp_functions[].
125 * @drive_strength: Amount of current in sink mode
126 * @dtest: DTEST route selector
109 */ 127 */
110struct pmic_mpp_pad { 128struct pmic_mpp_pad {
111 u16 base; 129 u16 base;
@@ -114,12 +132,15 @@ struct pmic_mpp_pad {
114 bool out_value; 132 bool out_value;
115 bool output_enabled; 133 bool output_enabled;
116 bool input_enabled; 134 bool input_enabled;
117 bool analog_mode; 135 bool paired;
118 unsigned int num_sources; 136 unsigned int num_sources;
119 unsigned int power_source; 137 unsigned int power_source;
120 unsigned int amux_input; 138 unsigned int amux_input;
139 unsigned int aout_level;
121 unsigned int pullup; 140 unsigned int pullup;
122 unsigned int function; 141 unsigned int function;
142 unsigned int drive_strength;
143 unsigned int dtest;
123}; 144};
124 145
125struct pmic_mpp_state { 146struct pmic_mpp_state {
@@ -129,25 +150,32 @@ struct pmic_mpp_state {
129 struct gpio_chip chip; 150 struct gpio_chip chip;
130}; 151};
131 152
132struct pmic_mpp_bindings { 153static const struct pinconf_generic_params pmic_mpp_bindings[] = {
133 const char *property; 154 {"qcom,amux-route", PMIC_MPP_CONF_AMUX_ROUTE, 0},
134 unsigned param; 155 {"qcom,analog-level", PMIC_MPP_CONF_ANALOG_LEVEL, 0},
156 {"qcom,dtest", PMIC_MPP_CONF_DTEST_SELECTOR, 0},
157 {"qcom,paired", PMIC_MPP_CONF_PAIRED, 0},
135}; 158};
136 159
137static struct pmic_mpp_bindings pmic_mpp_bindings[] = { 160#ifdef CONFIG_DEBUG_FS
138 {"qcom,amux-route", PMIC_MPP_CONF_AMUX_ROUTE}, 161static const struct pin_config_item pmic_conf_items[] = {
139 {"qcom,analog-mode", PMIC_MPP_CONF_ANALOG_MODE}, 162 PCONFDUMP(PMIC_MPP_CONF_AMUX_ROUTE, "analog mux", NULL, true),
163 PCONFDUMP(PMIC_MPP_CONF_ANALOG_LEVEL, "analog level", NULL, true),
164 PCONFDUMP(PMIC_MPP_CONF_DTEST_SELECTOR, "dtest", NULL, true),
165 PCONFDUMP(PMIC_MPP_CONF_PAIRED, "paired", NULL, false),
140}; 166};
167#endif
141 168
142static const char *const pmic_mpp_groups[] = { 169static const char *const pmic_mpp_groups[] = {
143 "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", 170 "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8",
144}; 171};
145 172
173#define PMIC_MPP_DIGITAL 0
174#define PMIC_MPP_ANALOG 1
175#define PMIC_MPP_SINK 2
176
146static const char *const pmic_mpp_functions[] = { 177static const char *const pmic_mpp_functions[] = {
147 PMIC_MPP_FUNC_NORMAL, PMIC_MPP_FUNC_PAIRED, 178 "digital", "analog", "sink"
148 "reserved1", "reserved2",
149 PMIC_MPP_FUNC_DTEST1, PMIC_MPP_FUNC_DTEST2,
150 PMIC_MPP_FUNC_DTEST3, PMIC_MPP_FUNC_DTEST4,
151}; 179};
152 180
153static inline struct pmic_mpp_state *to_mpp_state(struct gpio_chip *chip) 181static inline struct pmic_mpp_state *to_mpp_state(struct gpio_chip *chip)
@@ -204,118 +232,11 @@ static int pmic_mpp_get_group_pins(struct pinctrl_dev *pctldev,
204 return 0; 232 return 0;
205} 233}
206 234
207static int pmic_mpp_parse_dt_config(struct device_node *np,
208 struct pinctrl_dev *pctldev,
209 unsigned long **configs,
210 unsigned int *nconfs)
211{
212 struct pmic_mpp_bindings *par;
213 unsigned long cfg;
214 int ret, i;
215 u32 val;
216
217 for (i = 0; i < ARRAY_SIZE(pmic_mpp_bindings); i++) {
218 par = &pmic_mpp_bindings[i];
219 ret = of_property_read_u32(np, par->property, &val);
220
221 /* property not found */
222 if (ret == -EINVAL)
223 continue;
224
225 /* use zero as default value, when no value is specified */
226 if (ret)
227 val = 0;
228
229 dev_dbg(pctldev->dev, "found %s with value %u\n",
230 par->property, val);
231
232 cfg = pinconf_to_config_packed(par->param, val);
233
234 ret = pinctrl_utils_add_config(pctldev, configs, nconfs, cfg);
235 if (ret)
236 return ret;
237 }
238
239 return 0;
240}
241
242static int pmic_mpp_dt_subnode_to_map(struct pinctrl_dev *pctldev,
243 struct device_node *np,
244 struct pinctrl_map **map,
245 unsigned *reserv, unsigned *nmaps,
246 enum pinctrl_map_type type)
247{
248 unsigned long *configs = NULL;
249 unsigned nconfs = 0;
250 struct property *prop;
251 const char *group;
252 int ret;
253
254 ret = pmic_mpp_parse_dt_config(np, pctldev, &configs, &nconfs);
255 if (ret < 0)
256 return ret;
257
258 if (!nconfs)
259 return 0;
260
261 ret = of_property_count_strings(np, "pins");
262 if (ret < 0)
263 goto exit;
264
265 ret = pinctrl_utils_reserve_map(pctldev, map, reserv, nmaps, ret);
266 if (ret < 0)
267 goto exit;
268
269 of_property_for_each_string(np, "pins", prop, group) {
270 ret = pinctrl_utils_add_map_configs(pctldev, map,
271 reserv, nmaps, group,
272 configs, nconfs, type);
273 if (ret < 0)
274 break;
275 }
276exit:
277 kfree(configs);
278 return ret;
279}
280
281static int pmic_mpp_dt_node_to_map(struct pinctrl_dev *pctldev,
282 struct device_node *np_config,
283 struct pinctrl_map **map, unsigned *nmaps)
284{
285 struct device_node *np;
286 enum pinctrl_map_type type;
287 unsigned reserv;
288 int ret;
289
290 ret = 0;
291 *map = NULL;
292 *nmaps = 0;
293 reserv = 0;
294 type = PIN_MAP_TYPE_CONFIGS_GROUP;
295
296 for_each_child_of_node(np_config, np) {
297 ret = pinconf_generic_dt_subnode_to_map(pctldev, np, map,
298 &reserv, nmaps, type);
299 if (ret)
300 break;
301
302 ret = pmic_mpp_dt_subnode_to_map(pctldev, np, map, &reserv,
303 nmaps, type);
304 if (ret)
305 break;
306 }
307
308 if (ret < 0)
309 pinctrl_utils_dt_free_map(pctldev, *map, *nmaps);
310
311 return ret;
312}
313
314static const struct pinctrl_ops pmic_mpp_pinctrl_ops = { 235static const struct pinctrl_ops pmic_mpp_pinctrl_ops = {
315 .get_groups_count = pmic_mpp_get_groups_count, 236 .get_groups_count = pmic_mpp_get_groups_count,
316 .get_group_name = pmic_mpp_get_group_name, 237 .get_group_name = pmic_mpp_get_group_name,
317 .get_group_pins = pmic_mpp_get_group_pins, 238 .get_group_pins = pmic_mpp_get_group_pins,
318 .dt_node_to_map = pmic_mpp_dt_node_to_map, 239 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
319 .dt_free_map = pinctrl_utils_dt_free_map, 240 .dt_free_map = pinctrl_utils_dt_free_map,
320}; 241};
321 242
@@ -340,6 +261,53 @@ static int pmic_mpp_get_function_groups(struct pinctrl_dev *pctldev,
340 return 0; 261 return 0;
341} 262}
342 263
264static int pmic_mpp_write_mode_ctl(struct pmic_mpp_state *state,
265 struct pmic_mpp_pad *pad)
266{
267 unsigned int mode;
268 unsigned int sel;
269 unsigned int val;
270 unsigned int en;
271
272 switch (pad->function) {
273 case PMIC_MPP_ANALOG:
274 if (pad->input_enabled && pad->output_enabled)
275 mode = PMIC_MPP_MODE_ANALOG_BIDIR;
276 else if (pad->input_enabled)
277 mode = PMIC_MPP_MODE_ANALOG_INPUT;
278 else
279 mode = PMIC_MPP_MODE_ANALOG_OUTPUT;
280 break;
281 case PMIC_MPP_DIGITAL:
282 if (pad->input_enabled && pad->output_enabled)
283 mode = PMIC_MPP_MODE_DIGITAL_BIDIR;
284 else if (pad->input_enabled)
285 mode = PMIC_MPP_MODE_DIGITAL_INPUT;
286 else
287 mode = PMIC_MPP_MODE_DIGITAL_OUTPUT;
288 break;
289 case PMIC_MPP_SINK:
290 default:
291 mode = PMIC_MPP_MODE_CURRENT_SINK;
292 break;
293 }
294
295 if (pad->dtest)
296 sel = PMIC_MPP_SELECTOR_DTEST_FIRST + pad->dtest - 1;
297 else if (pad->paired)
298 sel = PMIC_MPP_SELECTOR_PAIRED;
299 else
300 sel = PMIC_MPP_SELECTOR_NORMAL;
301
302 en = !!pad->out_value;
303
304 val = mode << PMIC_MPP_REG_MODE_DIR_SHIFT |
305 sel << PMIC_MPP_REG_MODE_FUNCTION_SHIFT |
306 en;
307
308 return pmic_mpp_write(state, pad, PMIC_MPP_REG_MODE_CTL, val);
309}
310
343static int pmic_mpp_set_mux(struct pinctrl_dev *pctldev, unsigned function, 311static int pmic_mpp_set_mux(struct pinctrl_dev *pctldev, unsigned function,
344 unsigned pin) 312 unsigned pin)
345{ 313{
@@ -352,31 +320,7 @@ static int pmic_mpp_set_mux(struct pinctrl_dev *pctldev, unsigned function,
352 320
353 pad->function = function; 321 pad->function = function;
354 322
355 if (!pad->analog_mode) { 323 ret = pmic_mpp_write_mode_ctl(state, pad);
356 val = 0; /* just digital input */
357 if (pad->output_enabled) {
358 if (pad->input_enabled)
359 val = 2; /* digital input and output */
360 else
361 val = 1; /* just digital output */
362 }
363 } else {
364 val = 4; /* just analog input */
365 if (pad->output_enabled) {
366 if (pad->input_enabled)
367 val = 3; /* analog input and output */
368 else
369 val = 5; /* just analog output */
370 }
371 }
372
373 val = val << PMIC_MPP_REG_MODE_DIR_SHIFT;
374 val |= pad->function << PMIC_MPP_REG_MODE_FUNCTION_SHIFT;
375 val |= pad->out_value & PMIC_MPP_REG_MODE_VALUE_MASK;
376
377 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_MODE_CTL, val);
378 if (ret < 0)
379 return ret;
380 324
381 val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT; 325 val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT;
382 326
@@ -433,11 +377,20 @@ static int pmic_mpp_config_get(struct pinctrl_dev *pctldev,
433 case PIN_CONFIG_OUTPUT: 377 case PIN_CONFIG_OUTPUT:
434 arg = pad->out_value; 378 arg = pad->out_value;
435 break; 379 break;
380 case PMIC_MPP_CONF_DTEST_SELECTOR:
381 arg = pad->dtest;
382 break;
436 case PMIC_MPP_CONF_AMUX_ROUTE: 383 case PMIC_MPP_CONF_AMUX_ROUTE:
437 arg = pad->amux_input; 384 arg = pad->amux_input;
438 break; 385 break;
439 case PMIC_MPP_CONF_ANALOG_MODE: 386 case PMIC_MPP_CONF_PAIRED:
440 arg = pad->analog_mode; 387 arg = pad->paired;
388 break;
389 case PIN_CONFIG_DRIVE_STRENGTH:
390 arg = pad->drive_strength;
391 break;
392 case PMIC_MPP_CONF_ANALOG_LEVEL:
393 arg = pad->aout_level;
441 break; 394 break;
442 default: 395 default:
443 return -EINVAL; 396 return -EINVAL;
@@ -459,6 +412,9 @@ static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
459 412
460 pad = pctldev->desc->pins[pin].drv_data; 413 pad = pctldev->desc->pins[pin].drv_data;
461 414
415 /* Make it possible to enable the pin, by not setting high impedance */
416 pad->is_enabled = true;
417
462 for (i = 0; i < nconfs; i++) { 418 for (i = 0; i < nconfs; i++) {
463 param = pinconf_to_config_param(configs[i]); 419 param = pinconf_to_config_param(configs[i]);
464 arg = pinconf_to_config_argument(configs[i]); 420 arg = pinconf_to_config_argument(configs[i]);
@@ -497,13 +453,22 @@ static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
497 pad->output_enabled = true; 453 pad->output_enabled = true;
498 pad->out_value = arg; 454 pad->out_value = arg;
499 break; 455 break;
456 case PMIC_MPP_CONF_DTEST_SELECTOR:
457 pad->dtest = arg;
458 break;
459 case PIN_CONFIG_DRIVE_STRENGTH:
460 arg = pad->drive_strength;
461 break;
500 case PMIC_MPP_CONF_AMUX_ROUTE: 462 case PMIC_MPP_CONF_AMUX_ROUTE:
501 if (arg >= PMIC_MPP_AMUX_ROUTE_ABUS4) 463 if (arg >= PMIC_MPP_AMUX_ROUTE_ABUS4)
502 return -EINVAL; 464 return -EINVAL;
503 pad->amux_input = arg; 465 pad->amux_input = arg;
504 break; 466 break;
505 case PMIC_MPP_CONF_ANALOG_MODE: 467 case PMIC_MPP_CONF_ANALOG_LEVEL:
506 pad->analog_mode = true; 468 pad->aout_level = arg;
469 break;
470 case PMIC_MPP_CONF_PAIRED:
471 pad->paired = !!arg;
507 break; 472 break;
508 default: 473 default:
509 return -EINVAL; 474 return -EINVAL;
@@ -528,29 +493,17 @@ static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
528 if (ret < 0) 493 if (ret < 0)
529 return ret; 494 return ret;
530 495
531 if (!pad->analog_mode) { 496 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_AOUT_CTL, pad->aout_level);
532 val = 0; /* just digital input */ 497 if (ret < 0)
533 if (pad->output_enabled) { 498 return ret;
534 if (pad->input_enabled) 499
535 val = 2; /* digital input and output */ 500 ret = pmic_mpp_write_mode_ctl(state, pad);
536 else 501 if (ret < 0)
537 val = 1; /* just digital output */ 502 return ret;
538 }
539 } else {
540 val = 4; /* just analog input */
541 if (pad->output_enabled) {
542 if (pad->input_enabled)
543 val = 3; /* analog input and output */
544 else
545 val = 5; /* just analog output */
546 }
547 }
548 503
549 val = val << PMIC_MPP_REG_MODE_DIR_SHIFT; 504 val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT;
550 val |= pad->function << PMIC_MPP_REG_MODE_FUNCTION_SHIFT;
551 val |= pad->out_value & PMIC_MPP_REG_MODE_VALUE_MASK;
552 505
553 return pmic_mpp_write(state, pad, PMIC_MPP_REG_MODE_CTL, val); 506 return pmic_mpp_write(state, pad, PMIC_MPP_REG_EN_CTL, val);
554} 507}
555 508
556static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev, 509static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev,
@@ -558,20 +511,17 @@ static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev,
558{ 511{
559 struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev); 512 struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev);
560 struct pmic_mpp_pad *pad; 513 struct pmic_mpp_pad *pad;
561 int ret, val; 514 int ret;
562 515
563 static const char *const biases[] = { 516 static const char *const biases[] = {
564 "0.6kOhm", "10kOhm", "30kOhm", "Disabled" 517 "0.6kOhm", "10kOhm", "30kOhm", "Disabled"
565 }; 518 };
566 519
567
568 pad = pctldev->desc->pins[pin].drv_data; 520 pad = pctldev->desc->pins[pin].drv_data;
569 521
570 seq_printf(s, " mpp%-2d:", pin + PMIC_MPP_PHYSICAL_OFFSET); 522 seq_printf(s, " mpp%-2d:", pin + PMIC_MPP_PHYSICAL_OFFSET);
571 523
572 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_EN_CTL); 524 if (!pad->is_enabled) {
573
574 if (val < 0 || !(val >> PMIC_MPP_REG_MASTER_EN_SHIFT)) {
575 seq_puts(s, " ---"); 525 seq_puts(s, " ---");
576 } else { 526 } else {
577 527
@@ -585,15 +535,20 @@ static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev,
585 } 535 }
586 536
587 seq_printf(s, " %-4s", pad->output_enabled ? "out" : "in"); 537 seq_printf(s, " %-4s", pad->output_enabled ? "out" : "in");
588 seq_printf(s, " %-4s", pad->analog_mode ? "ana" : "dig");
589 seq_printf(s, " %-7s", pmic_mpp_functions[pad->function]); 538 seq_printf(s, " %-7s", pmic_mpp_functions[pad->function]);
590 seq_printf(s, " vin-%d", pad->power_source); 539 seq_printf(s, " vin-%d", pad->power_source);
540 seq_printf(s, " %d", pad->aout_level);
591 seq_printf(s, " %-8s", biases[pad->pullup]); 541 seq_printf(s, " %-8s", biases[pad->pullup]);
592 seq_printf(s, " %-4s", pad->out_value ? "high" : "low"); 542 seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
543 if (pad->dtest)
544 seq_printf(s, " dtest%d", pad->dtest);
545 if (pad->paired)
546 seq_puts(s, " paired");
593 } 547 }
594} 548}
595 549
596static const struct pinconf_ops pmic_mpp_pinconf_ops = { 550static const struct pinconf_ops pmic_mpp_pinconf_ops = {
551 .is_generic = true,
597 .pin_config_group_get = pmic_mpp_config_get, 552 .pin_config_group_get = pmic_mpp_config_get,
598 .pin_config_group_set = pmic_mpp_config_set, 553 .pin_config_group_set = pmic_mpp_config_set,
599 .pin_config_group_dbg_show = pmic_mpp_config_dbg_show, 554 .pin_config_group_dbg_show = pmic_mpp_config_dbg_show,
@@ -709,6 +664,7 @@ static int pmic_mpp_populate(struct pmic_mpp_state *state,
709 struct pmic_mpp_pad *pad) 664 struct pmic_mpp_pad *pad)
710{ 665{
711 int type, subtype, val, dir; 666 int type, subtype, val, dir;
667 unsigned int sel;
712 668
713 type = pmic_mpp_read(state, pad, PMIC_MPP_REG_TYPE); 669 type = pmic_mpp_read(state, pad, PMIC_MPP_REG_TYPE);
714 if (type < 0) 670 if (type < 0)
@@ -751,43 +707,53 @@ static int pmic_mpp_populate(struct pmic_mpp_state *state,
751 dir &= PMIC_MPP_REG_MODE_DIR_MASK; 707 dir &= PMIC_MPP_REG_MODE_DIR_MASK;
752 708
753 switch (dir) { 709 switch (dir) {
754 case 0: 710 case PMIC_MPP_MODE_DIGITAL_INPUT:
755 pad->input_enabled = true; 711 pad->input_enabled = true;
756 pad->output_enabled = false; 712 pad->output_enabled = false;
757 pad->analog_mode = false; 713 pad->function = PMIC_MPP_DIGITAL;
758 break; 714 break;
759 case 1: 715 case PMIC_MPP_MODE_DIGITAL_OUTPUT:
760 pad->input_enabled = false; 716 pad->input_enabled = false;
761 pad->output_enabled = true; 717 pad->output_enabled = true;
762 pad->analog_mode = false; 718 pad->function = PMIC_MPP_DIGITAL;
763 break; 719 break;
764 case 2: 720 case PMIC_MPP_MODE_DIGITAL_BIDIR:
765 pad->input_enabled = true; 721 pad->input_enabled = true;
766 pad->output_enabled = true; 722 pad->output_enabled = true;
767 pad->analog_mode = false; 723 pad->function = PMIC_MPP_DIGITAL;
768 break; 724 break;
769 case 3: 725 case PMIC_MPP_MODE_ANALOG_BIDIR:
770 pad->input_enabled = true; 726 pad->input_enabled = true;
771 pad->output_enabled = true; 727 pad->output_enabled = true;
772 pad->analog_mode = true; 728 pad->function = PMIC_MPP_ANALOG;
773 break; 729 break;
774 case 4: 730 case PMIC_MPP_MODE_ANALOG_INPUT:
775 pad->input_enabled = true; 731 pad->input_enabled = true;
776 pad->output_enabled = false; 732 pad->output_enabled = false;
777 pad->analog_mode = true; 733 pad->function = PMIC_MPP_ANALOG;
778 break; 734 break;
779 case 5: 735 case PMIC_MPP_MODE_ANALOG_OUTPUT:
780 pad->input_enabled = false; 736 pad->input_enabled = false;
781 pad->output_enabled = true; 737 pad->output_enabled = true;
782 pad->analog_mode = true; 738 pad->function = PMIC_MPP_ANALOG;
739 break;
740 case PMIC_MPP_MODE_CURRENT_SINK:
741 pad->input_enabled = false;
742 pad->output_enabled = true;
743 pad->function = PMIC_MPP_SINK;
783 break; 744 break;
784 default: 745 default:
785 dev_err(state->dev, "unknown MPP direction\n"); 746 dev_err(state->dev, "unknown MPP direction\n");
786 return -ENODEV; 747 return -ENODEV;
787 } 748 }
788 749
789 pad->function = val >> PMIC_MPP_REG_MODE_FUNCTION_SHIFT; 750 sel = val >> PMIC_MPP_REG_MODE_FUNCTION_SHIFT;
790 pad->function &= PMIC_MPP_REG_MODE_FUNCTION_MASK; 751 sel &= PMIC_MPP_REG_MODE_FUNCTION_MASK;
752
753 if (sel >= PMIC_MPP_SELECTOR_DTEST_FIRST)
754 pad->dtest = sel + 1;
755 else if (sel == PMIC_MPP_SELECTOR_PAIRED)
756 pad->paired = true;
791 757
792 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_VIN_CTL); 758 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_VIN_CTL);
793 if (val < 0) 759 if (val < 0)
@@ -810,8 +776,24 @@ static int pmic_mpp_populate(struct pmic_mpp_state *state,
810 pad->amux_input = val >> PMIC_MPP_REG_AIN_ROUTE_SHIFT; 776 pad->amux_input = val >> PMIC_MPP_REG_AIN_ROUTE_SHIFT;
811 pad->amux_input &= PMIC_MPP_REG_AIN_ROUTE_MASK; 777 pad->amux_input &= PMIC_MPP_REG_AIN_ROUTE_MASK;
812 778
813 /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */ 779 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_SINK_CTL);
814 pad->is_enabled = true; 780 if (val < 0)
781 return val;
782
783 pad->drive_strength = val;
784
785 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AOUT_CTL);
786 if (val < 0)
787 return val;
788
789 pad->aout_level = val;
790
791 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_EN_CTL);
792 if (val < 0)
793 return val;
794
795 pad->is_enabled = !!val;
796
815 return 0; 797 return 0;
816} 798}
817 799
@@ -866,6 +848,12 @@ static int pmic_mpp_probe(struct platform_device *pdev)
866 pctrldesc->pins = pindesc; 848 pctrldesc->pins = pindesc;
867 pctrldesc->npins = npins; 849 pctrldesc->npins = npins;
868 850
851 pctrldesc->num_custom_params = ARRAY_SIZE(pmic_mpp_bindings);
852 pctrldesc->custom_params = pmic_mpp_bindings;
853#ifdef CONFIG_DEBUG_FS
854 pctrldesc->custom_conf_items = pmic_conf_items;
855#endif
856
869 for (i = 0; i < npins; i++, pindesc++) { 857 for (i = 0; i < npins; i++, pindesc++) {
870 pad = &pads[i]; 858 pad = &pads[i];
871 pindesc->drv_data = pad; 859 pindesc->drv_data = pad;
diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c
new file mode 100644
index 000000000000..c978b311031b
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c
@@ -0,0 +1,791 @@
1/*
2 * Copyright (c) 2015, Sony Mobile Communications AB.
3 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 and
7 * only version 2 as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/module.h>
16#include <linux/platform_device.h>
17#include <linux/pinctrl/pinctrl.h>
18#include <linux/pinctrl/pinmux.h>
19#include <linux/pinctrl/pinconf.h>
20#include <linux/pinctrl/pinconf-generic.h>
21#include <linux/slab.h>
22#include <linux/regmap.h>
23#include <linux/gpio.h>
24#include <linux/interrupt.h>
25#include <linux/of_device.h>
26
27#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
28
29#include "../core.h"
30#include "../pinctrl-utils.h"
31
32/* mode */
33#define PM8XXX_GPIO_MODE_ENABLED BIT(0)
34#define PM8XXX_GPIO_MODE_INPUT 0
35#define PM8XXX_GPIO_MODE_OUTPUT 2
36
37/* output buffer */
38#define PM8XXX_GPIO_PUSH_PULL 0
39#define PM8XXX_GPIO_OPEN_DRAIN 1
40
41/* bias */
42#define PM8XXX_GPIO_BIAS_PU_30 0
43#define PM8XXX_GPIO_BIAS_PU_1P5 1
44#define PM8XXX_GPIO_BIAS_PU_31P5 2
45#define PM8XXX_GPIO_BIAS_PU_1P5_30 3
46#define PM8XXX_GPIO_BIAS_PD 4
47#define PM8XXX_GPIO_BIAS_NP 5
48
49/* GPIO registers */
50#define SSBI_REG_ADDR_GPIO_BASE 0x150
51#define SSBI_REG_ADDR_GPIO(n) (SSBI_REG_ADDR_GPIO_BASE + n)
52
53#define PM8XXX_BANK_WRITE BIT(7)
54
55#define PM8XXX_MAX_GPIOS 44
56
57/* custom pinconf parameters */
58#define PM8XXX_QCOM_DRIVE_STRENGH (PIN_CONFIG_END + 1)
59#define PM8XXX_QCOM_PULL_UP_STRENGTH (PIN_CONFIG_END + 2)
60
61/**
62 * struct pm8xxx_pin_data - dynamic configuration for a pin
63 * @reg: address of the control register
64 * @irq: IRQ from the PMIC interrupt controller
65 * @power_source: logical selected voltage source, mapping in static data
66 * is used translate to register values
67 * @mode: operating mode for the pin (input/output)
68 * @open_drain: output buffer configured as open-drain (vs push-pull)
69 * @output_value: configured output value
70 * @bias: register view of configured bias
71 * @pull_up_strength: placeholder for selected pull up strength
72 * only used to configure bias when pull up is selected
73 * @output_strength: selector of output-strength
74 * @disable: pin disabled / configured as tristate
75 * @function: pinmux selector
76 * @inverted: pin logic is inverted
77 */
78struct pm8xxx_pin_data {
79 unsigned reg;
80 int irq;
81 u8 power_source;
82 u8 mode;
83 bool open_drain;
84 bool output_value;
85 u8 bias;
86 u8 pull_up_strength;
87 u8 output_strength;
88 bool disable;
89 u8 function;
90 bool inverted;
91};
92
93struct pm8xxx_gpio {
94 struct device *dev;
95 struct regmap *regmap;
96 struct pinctrl_dev *pctrl;
97 struct gpio_chip chip;
98
99 struct pinctrl_desc desc;
100 unsigned npins;
101};
102
103static const struct pinconf_generic_params pm8xxx_gpio_bindings[] = {
104 {"qcom,drive-strength", PM8XXX_QCOM_DRIVE_STRENGH, 0},
105 {"qcom,pull-up-strength", PM8XXX_QCOM_PULL_UP_STRENGTH, 0},
106};
107
108#ifdef CONFIG_DEBUG_FS
109static const struct pin_config_item pm8xxx_conf_items[ARRAY_SIZE(pm8xxx_gpio_bindings)] = {
110 PCONFDUMP(PM8XXX_QCOM_DRIVE_STRENGH, "drive-strength", NULL, true),
111 PCONFDUMP(PM8XXX_QCOM_PULL_UP_STRENGTH, "pull up strength", NULL, true),
112};
113#endif
114
115static const char * const pm8xxx_groups[PM8XXX_MAX_GPIOS] = {
116 "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
117 "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
118 "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
119 "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
120 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
121 "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
122 "gpio44",
123};
124
125static const char * const pm8xxx_gpio_functions[] = {
126 PMIC_GPIO_FUNC_NORMAL, PMIC_GPIO_FUNC_PAIRED,
127 PMIC_GPIO_FUNC_FUNC1, PMIC_GPIO_FUNC_FUNC2,
128 PMIC_GPIO_FUNC_DTEST1, PMIC_GPIO_FUNC_DTEST2,
129 PMIC_GPIO_FUNC_DTEST3, PMIC_GPIO_FUNC_DTEST4,
130};
131
132static int pm8xxx_read_bank(struct pm8xxx_gpio *pctrl,
133 struct pm8xxx_pin_data *pin, int bank)
134{
135 unsigned int val = bank << 4;
136 int ret;
137
138 ret = regmap_write(pctrl->regmap, pin->reg, val);
139 if (ret) {
140 dev_err(pctrl->dev, "failed to select bank %d\n", bank);
141 return ret;
142 }
143
144 ret = regmap_read(pctrl->regmap, pin->reg, &val);
145 if (ret) {
146 dev_err(pctrl->dev, "failed to read register %d\n", bank);
147 return ret;
148 }
149
150 return val;
151}
152
153static int pm8xxx_write_bank(struct pm8xxx_gpio *pctrl,
154 struct pm8xxx_pin_data *pin,
155 int bank,
156 u8 val)
157{
158 int ret;
159
160 val |= PM8XXX_BANK_WRITE;
161 val |= bank << 4;
162
163 ret = regmap_write(pctrl->regmap, pin->reg, val);
164 if (ret)
165 dev_err(pctrl->dev, "failed to write register\n");
166
167 return ret;
168}
169
170static int pm8xxx_get_groups_count(struct pinctrl_dev *pctldev)
171{
172 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
173
174 return pctrl->npins;
175}
176
177static const char *pm8xxx_get_group_name(struct pinctrl_dev *pctldev,
178 unsigned group)
179{
180 return pm8xxx_groups[group];
181}
182
183
184static int pm8xxx_get_group_pins(struct pinctrl_dev *pctldev,
185 unsigned group,
186 const unsigned **pins,
187 unsigned *num_pins)
188{
189 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
190
191 *pins = &pctrl->desc.pins[group].number;
192 *num_pins = 1;
193
194 return 0;
195}
196
197static const struct pinctrl_ops pm8xxx_pinctrl_ops = {
198 .get_groups_count = pm8xxx_get_groups_count,
199 .get_group_name = pm8xxx_get_group_name,
200 .get_group_pins = pm8xxx_get_group_pins,
201 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
202 .dt_free_map = pinctrl_utils_dt_free_map,
203};
204
205static int pm8xxx_get_functions_count(struct pinctrl_dev *pctldev)
206{
207 return ARRAY_SIZE(pm8xxx_gpio_functions);
208}
209
210static const char *pm8xxx_get_function_name(struct pinctrl_dev *pctldev,
211 unsigned function)
212{
213 return pm8xxx_gpio_functions[function];
214}
215
216static int pm8xxx_get_function_groups(struct pinctrl_dev *pctldev,
217 unsigned function,
218 const char * const **groups,
219 unsigned * const num_groups)
220{
221 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
222
223 *groups = pm8xxx_groups;
224 *num_groups = pctrl->npins;
225 return 0;
226}
227
228static int pm8xxx_pinmux_set_mux(struct pinctrl_dev *pctldev,
229 unsigned function,
230 unsigned group)
231{
232 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
233 struct pm8xxx_pin_data *pin = pctrl->desc.pins[group].drv_data;
234 u8 val;
235
236 pin->function = function;
237 val = pin->function << 1;
238
239 pm8xxx_write_bank(pctrl, pin, 4, val);
240
241 return 0;
242}
243
244static const struct pinmux_ops pm8xxx_pinmux_ops = {
245 .get_functions_count = pm8xxx_get_functions_count,
246 .get_function_name = pm8xxx_get_function_name,
247 .get_function_groups = pm8xxx_get_function_groups,
248 .set_mux = pm8xxx_pinmux_set_mux,
249};
250
251static int pm8xxx_pin_config_get(struct pinctrl_dev *pctldev,
252 unsigned int offset,
253 unsigned long *config)
254{
255 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
256 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
257 unsigned param = pinconf_to_config_param(*config);
258 unsigned arg;
259
260 switch (param) {
261 case PIN_CONFIG_BIAS_DISABLE:
262 arg = pin->bias == PM8XXX_GPIO_BIAS_NP;
263 break;
264 case PIN_CONFIG_BIAS_PULL_DOWN:
265 arg = pin->bias == PM8XXX_GPIO_BIAS_PD;
266 break;
267 case PIN_CONFIG_BIAS_PULL_UP:
268 arg = pin->bias <= PM8XXX_GPIO_BIAS_PU_1P5_30;
269 break;
270 case PM8XXX_QCOM_PULL_UP_STRENGTH:
271 arg = pin->pull_up_strength;
272 break;
273 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
274 arg = pin->disable;
275 break;
276 case PIN_CONFIG_INPUT_ENABLE:
277 arg = pin->mode == PM8XXX_GPIO_MODE_INPUT;
278 break;
279 case PIN_CONFIG_OUTPUT:
280 if (pin->mode & PM8XXX_GPIO_MODE_OUTPUT)
281 arg = pin->output_value;
282 else
283 arg = 0;
284 break;
285 case PIN_CONFIG_POWER_SOURCE:
286 arg = pin->power_source;
287 break;
288 case PM8XXX_QCOM_DRIVE_STRENGH:
289 arg = pin->output_strength;
290 break;
291 case PIN_CONFIG_DRIVE_PUSH_PULL:
292 arg = !pin->open_drain;
293 break;
294 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
295 arg = pin->open_drain;
296 break;
297 default:
298 return -EINVAL;
299 }
300
301 *config = pinconf_to_config_packed(param, arg);
302
303 return 0;
304}
305
306static int pm8xxx_pin_config_set(struct pinctrl_dev *pctldev,
307 unsigned int offset,
308 unsigned long *configs,
309 unsigned num_configs)
310{
311 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
312 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
313 unsigned param;
314 unsigned arg;
315 unsigned i;
316 u8 banks = 0;
317 u8 val;
318
319 for (i = 0; i < num_configs; i++) {
320 param = pinconf_to_config_param(configs[i]);
321 arg = pinconf_to_config_argument(configs[i]);
322
323 switch (param) {
324 case PIN_CONFIG_BIAS_DISABLE:
325 pin->bias = PM8XXX_GPIO_BIAS_NP;
326 banks |= BIT(2);
327 pin->disable = 0;
328 banks |= BIT(3);
329 break;
330 case PIN_CONFIG_BIAS_PULL_DOWN:
331 pin->bias = PM8XXX_GPIO_BIAS_PD;
332 banks |= BIT(2);
333 pin->disable = 0;
334 banks |= BIT(3);
335 break;
336 case PM8XXX_QCOM_PULL_UP_STRENGTH:
337 if (arg > PM8XXX_GPIO_BIAS_PU_1P5_30) {
338 dev_err(pctrl->dev, "invalid pull-up strength\n");
339 return -EINVAL;
340 }
341 pin->pull_up_strength = arg;
342 /* FALLTHROUGH */
343 case PIN_CONFIG_BIAS_PULL_UP:
344 pin->bias = pin->pull_up_strength;
345 banks |= BIT(2);
346 pin->disable = 0;
347 banks |= BIT(3);
348 break;
349 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
350 pin->disable = 1;
351 banks |= BIT(3);
352 break;
353 case PIN_CONFIG_INPUT_ENABLE:
354 pin->mode = PM8XXX_GPIO_MODE_INPUT;
355 banks |= BIT(0) | BIT(1);
356 break;
357 case PIN_CONFIG_OUTPUT:
358 pin->mode = PM8XXX_GPIO_MODE_OUTPUT;
359 pin->output_value = !!arg;
360 banks |= BIT(0) | BIT(1);
361 break;
362 case PIN_CONFIG_POWER_SOURCE:
363 pin->power_source = arg;
364 banks |= BIT(0);
365 break;
366 case PM8XXX_QCOM_DRIVE_STRENGH:
367 if (arg > PMIC_GPIO_STRENGTH_LOW) {
368 dev_err(pctrl->dev, "invalid drive strength\n");
369 return -EINVAL;
370 }
371 pin->output_strength = arg;
372 banks |= BIT(3);
373 break;
374 case PIN_CONFIG_DRIVE_PUSH_PULL:
375 pin->open_drain = 0;
376 banks |= BIT(1);
377 break;
378 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
379 pin->open_drain = 1;
380 banks |= BIT(1);
381 break;
382 default:
383 dev_err(pctrl->dev,
384 "unsupported config parameter: %x\n",
385 param);
386 return -EINVAL;
387 }
388 }
389
390 if (banks & BIT(0)) {
391 val = pin->power_source << 1;
392 val |= PM8XXX_GPIO_MODE_ENABLED;
393 pm8xxx_write_bank(pctrl, pin, 0, val);
394 }
395
396 if (banks & BIT(1)) {
397 val = pin->mode << 2;
398 val |= pin->open_drain << 1;
399 val |= pin->output_value;
400 pm8xxx_write_bank(pctrl, pin, 1, val);
401 }
402
403 if (banks & BIT(2)) {
404 val = pin->bias << 1;
405 pm8xxx_write_bank(pctrl, pin, 2, val);
406 }
407
408 if (banks & BIT(3)) {
409 val = pin->output_strength << 2;
410 val |= pin->disable;
411 pm8xxx_write_bank(pctrl, pin, 3, val);
412 }
413
414 if (banks & BIT(4)) {
415 val = pin->function << 1;
416 pm8xxx_write_bank(pctrl, pin, 4, val);
417 }
418
419 if (banks & BIT(5)) {
420 val = 0;
421 if (!pin->inverted)
422 val |= BIT(3);
423 pm8xxx_write_bank(pctrl, pin, 5, val);
424 }
425
426 return 0;
427}
428
429static const struct pinconf_ops pm8xxx_pinconf_ops = {
430 .is_generic = true,
431 .pin_config_group_get = pm8xxx_pin_config_get,
432 .pin_config_group_set = pm8xxx_pin_config_set,
433};
434
435static struct pinctrl_desc pm8xxx_pinctrl_desc = {
436 .name = "pm8xxx_gpio",
437 .pctlops = &pm8xxx_pinctrl_ops,
438 .pmxops = &pm8xxx_pinmux_ops,
439 .confops = &pm8xxx_pinconf_ops,
440 .owner = THIS_MODULE,
441};
442
443static int pm8xxx_gpio_direction_input(struct gpio_chip *chip,
444 unsigned offset)
445{
446 struct pm8xxx_gpio *pctrl = container_of(chip, struct pm8xxx_gpio, chip);
447 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
448 u8 val;
449
450 pin->mode = PM8XXX_GPIO_MODE_INPUT;
451 val = pin->mode << 2;
452
453 pm8xxx_write_bank(pctrl, pin, 1, val);
454
455 return 0;
456}
457
458static int pm8xxx_gpio_direction_output(struct gpio_chip *chip,
459 unsigned offset,
460 int value)
461{
462 struct pm8xxx_gpio *pctrl = container_of(chip, struct pm8xxx_gpio, chip);
463 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
464 u8 val;
465
466 pin->mode = PM8XXX_GPIO_MODE_OUTPUT;
467 pin->output_value = !!value;
468
469 val = pin->mode << 2;
470 val |= pin->open_drain << 1;
471 val |= pin->output_value;
472
473 pm8xxx_write_bank(pctrl, pin, 1, val);
474
475 return 0;
476}
477
478static int pm8xxx_gpio_get(struct gpio_chip *chip, unsigned offset)
479{
480 struct pm8xxx_gpio *pctrl = container_of(chip, struct pm8xxx_gpio, chip);
481 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
482 bool state;
483 int ret;
484
485 if (pin->mode == PM8XXX_GPIO_MODE_OUTPUT) {
486 ret = pin->output_value;
487 } else {
488 ret = irq_get_irqchip_state(pin->irq, IRQCHIP_STATE_LINE_LEVEL, &state);
489 if (!ret)
490 ret = !!state;
491 }
492
493 return ret;
494}
495
496static void pm8xxx_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
497{
498 struct pm8xxx_gpio *pctrl = container_of(chip, struct pm8xxx_gpio, chip);
499 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
500 u8 val;
501
502 pin->output_value = !!value;
503
504 val = pin->mode << 2;
505 val |= pin->open_drain << 1;
506 val |= pin->output_value;
507
508 pm8xxx_write_bank(pctrl, pin, 1, val);
509}
510
511static int pm8xxx_gpio_of_xlate(struct gpio_chip *chip,
512 const struct of_phandle_args *gpio_desc,
513 u32 *flags)
514{
515 if (chip->of_gpio_n_cells < 2)
516 return -EINVAL;
517
518 if (flags)
519 *flags = gpio_desc->args[1];
520
521 return gpio_desc->args[0] - 1;
522}
523
524
525static int pm8xxx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
526{
527 struct pm8xxx_gpio *pctrl = container_of(chip, struct pm8xxx_gpio, chip);
528 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
529
530 return pin->irq;
531}
532
533#ifdef CONFIG_DEBUG_FS
534#include <linux/seq_file.h>
535
536static void pm8xxx_gpio_dbg_show_one(struct seq_file *s,
537 struct pinctrl_dev *pctldev,
538 struct gpio_chip *chip,
539 unsigned offset,
540 unsigned gpio)
541{
542 struct pm8xxx_gpio *pctrl = container_of(chip, struct pm8xxx_gpio, chip);
543 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
544
545 static const char * const modes[] = {
546 "in", "both", "out", "off"
547 };
548 static const char * const biases[] = {
549 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
550 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
551 };
552 static const char * const buffer_types[] = {
553 "push-pull", "open-drain"
554 };
555 static const char * const strengths[] = {
556 "no", "high", "medium", "low"
557 };
558
559 seq_printf(s, " gpio%-2d:", offset + 1);
560 if (pin->disable) {
561 seq_puts(s, " ---");
562 } else {
563 seq_printf(s, " %-4s", modes[pin->mode]);
564 seq_printf(s, " %-7s", pm8xxx_gpio_functions[pin->function]);
565 seq_printf(s, " VIN%d", pin->power_source);
566 seq_printf(s, " %-27s", biases[pin->bias]);
567 seq_printf(s, " %-10s", buffer_types[pin->open_drain]);
568 seq_printf(s, " %-4s", pin->output_value ? "high" : "low");
569 seq_printf(s, " %-7s", strengths[pin->output_strength]);
570 if (pin->inverted)
571 seq_puts(s, " inverted");
572 }
573}
574
575static void pm8xxx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
576{
577 unsigned gpio = chip->base;
578 unsigned i;
579
580 for (i = 0; i < chip->ngpio; i++, gpio++) {
581 pm8xxx_gpio_dbg_show_one(s, NULL, chip, i, gpio);
582 seq_puts(s, "\n");
583 }
584}
585
586#else
587#define msm_gpio_dbg_show NULL
588#endif
589
590static struct gpio_chip pm8xxx_gpio_template = {
591 .direction_input = pm8xxx_gpio_direction_input,
592 .direction_output = pm8xxx_gpio_direction_output,
593 .get = pm8xxx_gpio_get,
594 .set = pm8xxx_gpio_set,
595 .of_xlate = pm8xxx_gpio_of_xlate,
596 .to_irq = pm8xxx_gpio_to_irq,
597 .dbg_show = pm8xxx_gpio_dbg_show,
598 .owner = THIS_MODULE,
599};
600
601static int pm8xxx_pin_populate(struct pm8xxx_gpio *pctrl,
602 struct pm8xxx_pin_data *pin)
603{
604 int val;
605
606 val = pm8xxx_read_bank(pctrl, pin, 0);
607 if (val < 0)
608 return val;
609
610 pin->power_source = (val >> 1) & 0x7;
611
612 val = pm8xxx_read_bank(pctrl, pin, 1);
613 if (val < 0)
614 return val;
615
616 pin->mode = (val >> 2) & 0x3;
617 pin->open_drain = !!(val & BIT(1));
618 pin->output_value = val & BIT(0);
619
620 val = pm8xxx_read_bank(pctrl, pin, 2);
621 if (val < 0)
622 return val;
623
624 pin->bias = (val >> 1) & 0x7;
625 if (pin->bias <= PM8XXX_GPIO_BIAS_PU_1P5_30)
626 pin->pull_up_strength = pin->bias;
627 else
628 pin->pull_up_strength = PM8XXX_GPIO_BIAS_PU_30;
629
630 val = pm8xxx_read_bank(pctrl, pin, 3);
631 if (val < 0)
632 return val;
633
634 pin->output_strength = (val >> 2) & 0x3;
635 pin->disable = val & BIT(0);
636
637 val = pm8xxx_read_bank(pctrl, pin, 4);
638 if (val < 0)
639 return val;
640
641 pin->function = (val >> 1) & 0x7;
642
643 val = pm8xxx_read_bank(pctrl, pin, 5);
644 if (val < 0)
645 return val;
646
647 pin->inverted = !(val & BIT(3));
648
649 return 0;
650}
651
652static const struct of_device_id pm8xxx_gpio_of_match[] = {
653 { .compatible = "qcom,pm8018-gpio", .data = (void *)6 },
654 { .compatible = "qcom,pm8038-gpio", .data = (void *)12 },
655 { .compatible = "qcom,pm8058-gpio", .data = (void *)40 },
656 { .compatible = "qcom,pm8917-gpio", .data = (void *)38 },
657 { .compatible = "qcom,pm8921-gpio", .data = (void *)44 },
658 { },
659};
660MODULE_DEVICE_TABLE(of, pm8xxx_gpio_of_match);
661
662static int pm8xxx_gpio_probe(struct platform_device *pdev)
663{
664 struct pm8xxx_pin_data *pin_data;
665 struct pinctrl_pin_desc *pins;
666 struct pm8xxx_gpio *pctrl;
667 int ret;
668 int i;
669
670 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
671 if (!pctrl)
672 return -ENOMEM;
673
674 pctrl->dev = &pdev->dev;
675 pctrl->npins = (unsigned)of_device_get_match_data(&pdev->dev);
676
677 pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL);
678 if (!pctrl->regmap) {
679 dev_err(&pdev->dev, "parent regmap unavailable\n");
680 return -ENXIO;
681 }
682
683 pctrl->desc = pm8xxx_pinctrl_desc;
684 pctrl->desc.npins = pctrl->npins;
685
686 pins = devm_kcalloc(&pdev->dev,
687 pctrl->desc.npins,
688 sizeof(struct pinctrl_pin_desc),
689 GFP_KERNEL);
690 if (!pins)
691 return -ENOMEM;
692
693 pin_data = devm_kcalloc(&pdev->dev,
694 pctrl->desc.npins,
695 sizeof(struct pm8xxx_pin_data),
696 GFP_KERNEL);
697 if (!pin_data)
698 return -ENOMEM;
699
700 for (i = 0; i < pctrl->desc.npins; i++) {
701 pin_data[i].reg = SSBI_REG_ADDR_GPIO(i);
702 pin_data[i].irq = platform_get_irq(pdev, i);
703 if (pin_data[i].irq < 0) {
704 dev_err(&pdev->dev,
705 "missing interrupts for pin %d\n", i);
706 return pin_data[i].irq;
707 }
708
709 ret = pm8xxx_pin_populate(pctrl, &pin_data[i]);
710 if (ret)
711 return ret;
712
713 pins[i].number = i;
714 pins[i].name = pm8xxx_groups[i];
715 pins[i].drv_data = &pin_data[i];
716 }
717 pctrl->desc.pins = pins;
718
719 pctrl->desc.num_custom_params = ARRAY_SIZE(pm8xxx_gpio_bindings);
720 pctrl->desc.custom_params = pm8xxx_gpio_bindings;
721#ifdef CONFIG_DEBUG_FS
722 pctrl->desc.custom_conf_items = pm8xxx_conf_items;
723#endif
724
725 pctrl->pctrl = pinctrl_register(&pctrl->desc, &pdev->dev, pctrl);
726 if (!pctrl->pctrl) {
727 dev_err(&pdev->dev, "couldn't register pm8xxx gpio driver\n");
728 return -ENODEV;
729 }
730
731 pctrl->chip = pm8xxx_gpio_template;
732 pctrl->chip.base = -1;
733 pctrl->chip.dev = &pdev->dev;
734 pctrl->chip.of_node = pdev->dev.of_node;
735 pctrl->chip.of_gpio_n_cells = 2;
736 pctrl->chip.label = dev_name(pctrl->dev);
737 pctrl->chip.ngpio = pctrl->npins;
738 ret = gpiochip_add(&pctrl->chip);
739 if (ret) {
740 dev_err(&pdev->dev, "failed register gpiochip\n");
741 goto unregister_pinctrl;
742 }
743
744 ret = gpiochip_add_pin_range(&pctrl->chip,
745 dev_name(pctrl->dev),
746 0, 0, pctrl->chip.ngpio);
747 if (ret) {
748 dev_err(pctrl->dev, "failed to add pin range\n");
749 goto unregister_gpiochip;
750 }
751
752 platform_set_drvdata(pdev, pctrl);
753
754 dev_dbg(&pdev->dev, "Qualcomm pm8xxx gpio driver probed\n");
755
756 return 0;
757
758unregister_gpiochip:
759 gpiochip_remove(&pctrl->chip);
760
761unregister_pinctrl:
762 pinctrl_unregister(pctrl->pctrl);
763
764 return ret;
765}
766
767static int pm8xxx_gpio_remove(struct platform_device *pdev)
768{
769 struct pm8xxx_gpio *pctrl = platform_get_drvdata(pdev);
770
771 gpiochip_remove(&pctrl->chip);
772
773 pinctrl_unregister(pctrl->pctrl);
774
775 return 0;
776}
777
778static struct platform_driver pm8xxx_gpio_driver = {
779 .driver = {
780 .name = "qcom-ssbi-gpio",
781 .of_match_table = pm8xxx_gpio_of_match,
782 },
783 .probe = pm8xxx_gpio_probe,
784 .remove = pm8xxx_gpio_remove,
785};
786
787module_platform_driver(pm8xxx_gpio_driver);
788
789MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");
790MODULE_DESCRIPTION("Qualcomm PM8xxx GPIO driver");
791MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c
new file mode 100644
index 000000000000..2d1b69f171be
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c
@@ -0,0 +1,882 @@
1/*
2 * Copyright (c) 2015, Sony Mobile Communications AB.
3 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 and
7 * only version 2 as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/module.h>
16#include <linux/platform_device.h>
17#include <linux/pinctrl/pinctrl.h>
18#include <linux/pinctrl/pinmux.h>
19#include <linux/pinctrl/pinconf.h>
20#include <linux/pinctrl/pinconf-generic.h>
21#include <linux/slab.h>
22#include <linux/regmap.h>
23#include <linux/gpio.h>
24#include <linux/interrupt.h>
25#include <linux/of_device.h>
26
27#include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
28
29#include "../core.h"
30#include "../pinctrl-utils.h"
31
32/* MPP registers */
33#define SSBI_REG_ADDR_MPP_BASE 0x50
34#define SSBI_REG_ADDR_MPP(n) (SSBI_REG_ADDR_MPP_BASE + n)
35
36/* MPP Type: type */
37#define PM8XXX_MPP_TYPE_D_INPUT 0
38#define PM8XXX_MPP_TYPE_D_OUTPUT 1
39#define PM8XXX_MPP_TYPE_D_BI_DIR 2
40#define PM8XXX_MPP_TYPE_A_INPUT 3
41#define PM8XXX_MPP_TYPE_A_OUTPUT 4
42#define PM8XXX_MPP_TYPE_SINK 5
43#define PM8XXX_MPP_TYPE_DTEST_SINK 6
44#define PM8XXX_MPP_TYPE_DTEST_OUTPUT 7
45
46/* Digital Input: control */
47#define PM8XXX_MPP_DIN_TO_INT 0
48#define PM8XXX_MPP_DIN_TO_DBUS1 1
49#define PM8XXX_MPP_DIN_TO_DBUS2 2
50#define PM8XXX_MPP_DIN_TO_DBUS3 3
51
52/* Digital Output: control */
53#define PM8XXX_MPP_DOUT_CTRL_LOW 0
54#define PM8XXX_MPP_DOUT_CTRL_HIGH 1
55#define PM8XXX_MPP_DOUT_CTRL_MPP 2
56#define PM8XXX_MPP_DOUT_CTRL_INV_MPP 3
57
58/* Bidirectional: control */
59#define PM8XXX_MPP_BI_PULLUP_1KOHM 0
60#define PM8XXX_MPP_BI_PULLUP_OPEN 1
61#define PM8XXX_MPP_BI_PULLUP_10KOHM 2
62#define PM8XXX_MPP_BI_PULLUP_30KOHM 3
63
64/* Analog Output: control */
65#define PM8XXX_MPP_AOUT_CTRL_DISABLE 0
66#define PM8XXX_MPP_AOUT_CTRL_ENABLE 1
67#define PM8XXX_MPP_AOUT_CTRL_MPP_HIGH_EN 2
68#define PM8XXX_MPP_AOUT_CTRL_MPP_LOW_EN 3
69
70/* Current Sink: control */
71#define PM8XXX_MPP_CS_CTRL_DISABLE 0
72#define PM8XXX_MPP_CS_CTRL_ENABLE 1
73#define PM8XXX_MPP_CS_CTRL_MPP_HIGH_EN 2
74#define PM8XXX_MPP_CS_CTRL_MPP_LOW_EN 3
75
76/* DTEST Current Sink: control */
77#define PM8XXX_MPP_DTEST_CS_CTRL_EN1 0
78#define PM8XXX_MPP_DTEST_CS_CTRL_EN2 1
79#define PM8XXX_MPP_DTEST_CS_CTRL_EN3 2
80#define PM8XXX_MPP_DTEST_CS_CTRL_EN4 3
81
82/* DTEST Digital Output: control */
83#define PM8XXX_MPP_DTEST_DBUS1 0
84#define PM8XXX_MPP_DTEST_DBUS2 1
85#define PM8XXX_MPP_DTEST_DBUS3 2
86#define PM8XXX_MPP_DTEST_DBUS4 3
87
88/* custom pinconf parameters */
89#define PM8XXX_CONFIG_AMUX (PIN_CONFIG_END + 1)
90#define PM8XXX_CONFIG_DTEST_SELECTOR (PIN_CONFIG_END + 2)
91#define PM8XXX_CONFIG_ALEVEL (PIN_CONFIG_END + 3)
92#define PM8XXX_CONFIG_PAIRED (PIN_CONFIG_END + 4)
93
94/**
95 * struct pm8xxx_pin_data - dynamic configuration for a pin
96 * @reg: address of the control register
97 * @irq: IRQ from the PMIC interrupt controller
98 * @mode: operating mode for the pin (digital, analog or current sink)
99 * @input: pin is input
100 * @output: pin is output
101 * @high_z: pin is floating
102 * @paired: mpp operates in paired mode
103 * @output_value: logical output value of the mpp
104 * @power_source: selected power source
105 * @dtest: DTEST route selector
106 * @amux: input muxing in analog mode
107 * @aout_level: selector of the output in analog mode
108 * @drive_strength: drive strength of the current sink
109 * @pullup: pull up value, when in digital bidirectional mode
110 */
111struct pm8xxx_pin_data {
112 unsigned reg;
113 int irq;
114
115 u8 mode;
116
117 bool input;
118 bool output;
119 bool high_z;
120 bool paired;
121 bool output_value;
122
123 u8 power_source;
124 u8 dtest;
125 u8 amux;
126 u8 aout_level;
127 u8 drive_strength;
128 unsigned pullup;
129};
130
131struct pm8xxx_mpp {
132 struct device *dev;
133 struct regmap *regmap;
134 struct pinctrl_dev *pctrl;
135 struct gpio_chip chip;
136
137 struct pinctrl_desc desc;
138 unsigned npins;
139};
140
141static const struct pinconf_generic_params pm8xxx_mpp_bindings[] = {
142 {"qcom,amux-route", PM8XXX_CONFIG_AMUX, 0},
143 {"qcom,analog-level", PM8XXX_CONFIG_ALEVEL, 0},
144 {"qcom,dtest", PM8XXX_CONFIG_DTEST_SELECTOR, 0},
145 {"qcom,paired", PM8XXX_CONFIG_PAIRED, 0},
146};
147
148#ifdef CONFIG_DEBUG_FS
149static const struct pin_config_item pm8xxx_conf_items[] = {
150 PCONFDUMP(PM8XXX_CONFIG_AMUX, "analog mux", NULL, true),
151 PCONFDUMP(PM8XXX_CONFIG_ALEVEL, "analog level", NULL, true),
152 PCONFDUMP(PM8XXX_CONFIG_DTEST_SELECTOR, "dtest", NULL, true),
153 PCONFDUMP(PM8XXX_CONFIG_PAIRED, "paired", NULL, false),
154};
155#endif
156
157#define PM8XXX_MAX_MPPS 12
158static const char * const pm8xxx_groups[PM8XXX_MAX_MPPS] = {
159 "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8",
160 "mpp9", "mpp10", "mpp11", "mpp12",
161};
162
163#define PM8XXX_MPP_DIGITAL 0
164#define PM8XXX_MPP_ANALOG 1
165#define PM8XXX_MPP_SINK 2
166
167static const char * const pm8xxx_mpp_functions[] = {
168 "digital", "analog", "sink",
169};
170
171static int pm8xxx_mpp_update(struct pm8xxx_mpp *pctrl,
172 struct pm8xxx_pin_data *pin)
173{
174 unsigned level;
175 unsigned ctrl;
176 unsigned type;
177 int ret;
178 u8 val;
179
180 switch (pin->mode) {
181 case PM8XXX_MPP_DIGITAL:
182 if (pin->dtest) {
183 type = PM8XXX_MPP_TYPE_DTEST_OUTPUT;
184 ctrl = pin->dtest - 1;
185 } else if (pin->input && pin->output) {
186 type = PM8XXX_MPP_TYPE_D_BI_DIR;
187 if (pin->high_z)
188 ctrl = PM8XXX_MPP_BI_PULLUP_OPEN;
189 else if (pin->pullup == 600)
190 ctrl = PM8XXX_MPP_BI_PULLUP_1KOHM;
191 else if (pin->pullup == 10000)
192 ctrl = PM8XXX_MPP_BI_PULLUP_10KOHM;
193 else
194 ctrl = PM8XXX_MPP_BI_PULLUP_30KOHM;
195 } else if (pin->input) {
196 type = PM8XXX_MPP_TYPE_D_INPUT;
197 if (pin->dtest)
198 ctrl = pin->dtest;
199 else
200 ctrl = PM8XXX_MPP_DIN_TO_INT;
201 } else {
202 type = PM8XXX_MPP_TYPE_D_OUTPUT;
203 ctrl = !!pin->output_value;
204 if (pin->paired)
205 ctrl |= BIT(1);
206 }
207
208 level = pin->power_source;
209 break;
210 case PM8XXX_MPP_ANALOG:
211 if (pin->output) {
212 type = PM8XXX_MPP_TYPE_A_OUTPUT;
213 level = pin->aout_level;
214 ctrl = pin->output_value;
215 if (pin->paired)
216 ctrl |= BIT(1);
217 } else {
218 type = PM8XXX_MPP_TYPE_A_INPUT;
219 level = pin->amux;
220 ctrl = 0;
221 }
222 break;
223 case PM8XXX_MPP_SINK:
224 level = (pin->drive_strength / 5) - 1;
225 if (pin->dtest) {
226 type = PM8XXX_MPP_TYPE_DTEST_SINK;
227 ctrl = pin->dtest - 1;
228 } else {
229 type = PM8XXX_MPP_TYPE_SINK;
230 ctrl = pin->output_value;
231 if (pin->paired)
232 ctrl |= BIT(1);
233 }
234 break;
235 default:
236 return -EINVAL;
237 }
238
239 val = type << 5 | level << 2 | ctrl;
240 ret = regmap_write(pctrl->regmap, pin->reg, val);
241 if (ret)
242 dev_err(pctrl->dev, "failed to write register\n");
243
244 return ret;
245}
246
247static int pm8xxx_get_groups_count(struct pinctrl_dev *pctldev)
248{
249 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev);
250
251 return pctrl->npins;
252}
253
254static const char *pm8xxx_get_group_name(struct pinctrl_dev *pctldev,
255 unsigned group)
256{
257 return pm8xxx_groups[group];
258}
259
260
261static int pm8xxx_get_group_pins(struct pinctrl_dev *pctldev,
262 unsigned group,
263 const unsigned **pins,
264 unsigned *num_pins)
265{
266 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev);
267
268 *pins = &pctrl->desc.pins[group].number;
269 *num_pins = 1;
270
271 return 0;
272}
273
274static const struct pinctrl_ops pm8xxx_pinctrl_ops = {
275 .get_groups_count = pm8xxx_get_groups_count,
276 .get_group_name = pm8xxx_get_group_name,
277 .get_group_pins = pm8xxx_get_group_pins,
278 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
279 .dt_free_map = pinctrl_utils_dt_free_map,
280};
281
282static int pm8xxx_get_functions_count(struct pinctrl_dev *pctldev)
283{
284 return ARRAY_SIZE(pm8xxx_mpp_functions);
285}
286
287static const char *pm8xxx_get_function_name(struct pinctrl_dev *pctldev,
288 unsigned function)
289{
290 return pm8xxx_mpp_functions[function];
291}
292
293static int pm8xxx_get_function_groups(struct pinctrl_dev *pctldev,
294 unsigned function,
295 const char * const **groups,
296 unsigned * const num_groups)
297{
298 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev);
299
300 *groups = pm8xxx_groups;
301 *num_groups = pctrl->npins;
302 return 0;
303}
304
305static int pm8xxx_pinmux_set_mux(struct pinctrl_dev *pctldev,
306 unsigned function,
307 unsigned group)
308{
309 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev);
310 struct pm8xxx_pin_data *pin = pctrl->desc.pins[group].drv_data;
311
312 pin->mode = function;
313 pm8xxx_mpp_update(pctrl, pin);
314
315 return 0;
316}
317
318static const struct pinmux_ops pm8xxx_pinmux_ops = {
319 .get_functions_count = pm8xxx_get_functions_count,
320 .get_function_name = pm8xxx_get_function_name,
321 .get_function_groups = pm8xxx_get_function_groups,
322 .set_mux = pm8xxx_pinmux_set_mux,
323};
324
325static int pm8xxx_pin_config_get(struct pinctrl_dev *pctldev,
326 unsigned int offset,
327 unsigned long *config)
328{
329 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev);
330 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
331 unsigned param = pinconf_to_config_param(*config);
332 unsigned arg;
333
334 switch (param) {
335 case PIN_CONFIG_BIAS_PULL_UP:
336 arg = pin->pullup;
337 break;
338 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
339 arg = pin->high_z;
340 break;
341 case PIN_CONFIG_INPUT_ENABLE:
342 arg = pin->input;
343 break;
344 case PIN_CONFIG_OUTPUT:
345 arg = pin->output_value;
346 break;
347 case PIN_CONFIG_POWER_SOURCE:
348 arg = pin->power_source;
349 break;
350 case PIN_CONFIG_DRIVE_STRENGTH:
351 arg = pin->drive_strength;
352 break;
353 case PM8XXX_CONFIG_DTEST_SELECTOR:
354 arg = pin->dtest;
355 break;
356 case PM8XXX_CONFIG_AMUX:
357 arg = pin->amux;
358 break;
359 case PM8XXX_CONFIG_ALEVEL:
360 arg = pin->aout_level;
361 break;
362 case PM8XXX_CONFIG_PAIRED:
363 arg = pin->paired;
364 break;
365 default:
366 return -EINVAL;
367 }
368
369 *config = pinconf_to_config_packed(param, arg);
370
371 return 0;
372}
373
374static int pm8xxx_pin_config_set(struct pinctrl_dev *pctldev,
375 unsigned int offset,
376 unsigned long *configs,
377 unsigned num_configs)
378{
379 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev);
380 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
381 unsigned param;
382 unsigned arg;
383 unsigned i;
384
385 for (i = 0; i < num_configs; i++) {
386 param = pinconf_to_config_param(configs[i]);
387 arg = pinconf_to_config_argument(configs[i]);
388
389 switch (param) {
390 case PIN_CONFIG_BIAS_PULL_UP:
391 pin->pullup = arg;
392 break;
393 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
394 pin->high_z = true;
395 break;
396 case PIN_CONFIG_INPUT_ENABLE:
397 pin->input = true;
398 break;
399 case PIN_CONFIG_OUTPUT:
400 pin->output = true;
401 pin->output_value = !!arg;
402 break;
403 case PIN_CONFIG_POWER_SOURCE:
404 pin->power_source = arg;
405 break;
406 case PIN_CONFIG_DRIVE_STRENGTH:
407 pin->drive_strength = arg;
408 break;
409 case PM8XXX_CONFIG_DTEST_SELECTOR:
410 pin->dtest = arg;
411 break;
412 case PM8XXX_CONFIG_AMUX:
413 pin->amux = arg;
414 break;
415 case PM8XXX_CONFIG_ALEVEL:
416 pin->aout_level = arg;
417 break;
418 case PM8XXX_CONFIG_PAIRED:
419 pin->paired = !!arg;
420 break;
421 default:
422 dev_err(pctrl->dev,
423 "unsupported config parameter: %x\n",
424 param);
425 return -EINVAL;
426 }
427 }
428
429 pm8xxx_mpp_update(pctrl, pin);
430
431 return 0;
432}
433
434static const struct pinconf_ops pm8xxx_pinconf_ops = {
435 .is_generic = true,
436 .pin_config_group_get = pm8xxx_pin_config_get,
437 .pin_config_group_set = pm8xxx_pin_config_set,
438};
439
440static struct pinctrl_desc pm8xxx_pinctrl_desc = {
441 .name = "pm8xxx_mpp",
442 .pctlops = &pm8xxx_pinctrl_ops,
443 .pmxops = &pm8xxx_pinmux_ops,
444 .confops = &pm8xxx_pinconf_ops,
445 .owner = THIS_MODULE,
446};
447
448static int pm8xxx_mpp_direction_input(struct gpio_chip *chip,
449 unsigned offset)
450{
451 struct pm8xxx_mpp *pctrl = container_of(chip, struct pm8xxx_mpp, chip);
452 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
453
454 switch (pin->mode) {
455 case PM8XXX_MPP_DIGITAL:
456 pin->input = true;
457 break;
458 case PM8XXX_MPP_ANALOG:
459 pin->input = true;
460 pin->output = true;
461 break;
462 case PM8XXX_MPP_SINK:
463 return -EINVAL;
464 }
465
466 pm8xxx_mpp_update(pctrl, pin);
467
468 return 0;
469}
470
471static int pm8xxx_mpp_direction_output(struct gpio_chip *chip,
472 unsigned offset,
473 int value)
474{
475 struct pm8xxx_mpp *pctrl = container_of(chip, struct pm8xxx_mpp, chip);
476 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
477
478 switch (pin->mode) {
479 case PM8XXX_MPP_DIGITAL:
480 pin->output = true;
481 break;
482 case PM8XXX_MPP_ANALOG:
483 pin->input = false;
484 pin->output = true;
485 break;
486 case PM8XXX_MPP_SINK:
487 pin->input = false;
488 pin->output = true;
489 break;
490 }
491
492 pm8xxx_mpp_update(pctrl, pin);
493
494 return 0;
495}
496
497static int pm8xxx_mpp_get(struct gpio_chip *chip, unsigned offset)
498{
499 struct pm8xxx_mpp *pctrl = container_of(chip, struct pm8xxx_mpp, chip);
500 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
501 bool state;
502 int ret;
503
504 if (!pin->input)
505 return pin->output_value;
506
507 ret = irq_get_irqchip_state(pin->irq, IRQCHIP_STATE_LINE_LEVEL, &state);
508 if (!ret)
509 ret = !!state;
510
511 return ret;
512}
513
514static void pm8xxx_mpp_set(struct gpio_chip *chip, unsigned offset, int value)
515{
516 struct pm8xxx_mpp *pctrl = container_of(chip, struct pm8xxx_mpp, chip);
517 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
518
519 pin->output_value = !!value;
520
521 pm8xxx_mpp_update(pctrl, pin);
522}
523
524static int pm8xxx_mpp_of_xlate(struct gpio_chip *chip,
525 const struct of_phandle_args *gpio_desc,
526 u32 *flags)
527{
528 if (chip->of_gpio_n_cells < 2)
529 return -EINVAL;
530
531 if (flags)
532 *flags = gpio_desc->args[1];
533
534 return gpio_desc->args[0] - 1;
535}
536
537
538static int pm8xxx_mpp_to_irq(struct gpio_chip *chip, unsigned offset)
539{
540 struct pm8xxx_mpp *pctrl = container_of(chip, struct pm8xxx_mpp, chip);
541 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
542
543 return pin->irq;
544}
545
546#ifdef CONFIG_DEBUG_FS
547#include <linux/seq_file.h>
548
549static void pm8xxx_mpp_dbg_show_one(struct seq_file *s,
550 struct pinctrl_dev *pctldev,
551 struct gpio_chip *chip,
552 unsigned offset,
553 unsigned gpio)
554{
555 struct pm8xxx_mpp *pctrl = container_of(chip, struct pm8xxx_mpp, chip);
556 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
557
558 static const char * const aout_lvls[] = {
559 "1v25", "1v25_2", "0v625", "0v3125", "mpp", "abus1", "abus2",
560 "abus3"
561 };
562
563 static const char * const amuxs[] = {
564 "amux5", "amux6", "amux7", "amux8", "amux9", "abus1", "abus2",
565 "abus3",
566 };
567
568 seq_printf(s, " mpp%-2d:", offset + 1);
569
570 switch (pin->mode) {
571 case PM8XXX_MPP_DIGITAL:
572 seq_puts(s, " digital ");
573 if (pin->dtest) {
574 seq_printf(s, "dtest%d\n", pin->dtest);
575 } else if (pin->input && pin->output) {
576 if (pin->high_z)
577 seq_puts(s, "bi-dir high-z");
578 else
579 seq_printf(s, "bi-dir %dOhm", pin->pullup);
580 } else if (pin->input) {
581 if (pin->dtest)
582 seq_printf(s, "in dtest%d", pin->dtest);
583 else
584 seq_puts(s, "in gpio");
585 } else if (pin->output) {
586 seq_puts(s, "out ");
587
588 if (!pin->paired) {
589 seq_puts(s, pin->output_value ?
590 "high" : "low");
591 } else {
592 seq_puts(s, pin->output_value ?
593 "inverted" : "follow");
594 }
595 }
596 break;
597 case PM8XXX_MPP_ANALOG:
598 seq_puts(s, " analog ");
599 if (pin->output) {
600 seq_printf(s, "out %s ", aout_lvls[pin->aout_level]);
601 if (!pin->paired) {
602 seq_puts(s, pin->output_value ?
603 "high" : "low");
604 } else {
605 seq_puts(s, pin->output_value ?
606 "inverted" : "follow");
607 }
608 } else {
609 seq_printf(s, "input mux %s", amuxs[pin->amux]);
610 }
611 break;
612 case PM8XXX_MPP_SINK:
613 seq_printf(s, " sink %dmA ", pin->drive_strength);
614 if (pin->dtest) {
615 seq_printf(s, "dtest%d", pin->dtest);
616 } else {
617 if (!pin->paired) {
618 seq_puts(s, pin->output_value ?
619 "high" : "low");
620 } else {
621 seq_puts(s, pin->output_value ?
622 "inverted" : "follow");
623 }
624 }
625 break;
626 }
627
628}
629
630static void pm8xxx_mpp_dbg_show(struct seq_file *s, struct gpio_chip *chip)
631{
632 unsigned gpio = chip->base;
633 unsigned i;
634
635 for (i = 0; i < chip->ngpio; i++, gpio++) {
636 pm8xxx_mpp_dbg_show_one(s, NULL, chip, i, gpio);
637 seq_puts(s, "\n");
638 }
639}
640
641#else
642#define msm_mpp_dbg_show NULL
643#endif
644
645static struct gpio_chip pm8xxx_mpp_template = {
646 .direction_input = pm8xxx_mpp_direction_input,
647 .direction_output = pm8xxx_mpp_direction_output,
648 .get = pm8xxx_mpp_get,
649 .set = pm8xxx_mpp_set,
650 .of_xlate = pm8xxx_mpp_of_xlate,
651 .to_irq = pm8xxx_mpp_to_irq,
652 .dbg_show = pm8xxx_mpp_dbg_show,
653 .owner = THIS_MODULE,
654};
655
656static int pm8xxx_pin_populate(struct pm8xxx_mpp *pctrl,
657 struct pm8xxx_pin_data *pin)
658{
659 unsigned int val;
660 unsigned level;
661 unsigned ctrl;
662 unsigned type;
663 int ret;
664
665 ret = regmap_read(pctrl->regmap, pin->reg, &val);
666 if (ret) {
667 dev_err(pctrl->dev, "failed to read register\n");
668 return ret;
669 }
670
671 type = (val >> 5) & 7;
672 level = (val >> 2) & 7;
673 ctrl = (val) & 3;
674
675 switch (type) {
676 case PM8XXX_MPP_TYPE_D_INPUT:
677 pin->mode = PM8XXX_MPP_DIGITAL;
678 pin->input = true;
679 pin->power_source = level;
680 pin->dtest = ctrl;
681 break;
682 case PM8XXX_MPP_TYPE_D_OUTPUT:
683 pin->mode = PM8XXX_MPP_DIGITAL;
684 pin->output = true;
685 pin->power_source = level;
686 pin->output_value = !!(ctrl & BIT(0));
687 pin->paired = !!(ctrl & BIT(1));
688 break;
689 case PM8XXX_MPP_TYPE_D_BI_DIR:
690 pin->mode = PM8XXX_MPP_DIGITAL;
691 pin->input = true;
692 pin->output = true;
693 pin->power_source = level;
694 switch (ctrl) {
695 case PM8XXX_MPP_BI_PULLUP_1KOHM:
696 pin->pullup = 600;
697 break;
698 case PM8XXX_MPP_BI_PULLUP_OPEN:
699 pin->high_z = true;
700 break;
701 case PM8XXX_MPP_BI_PULLUP_10KOHM:
702 pin->pullup = 10000;
703 break;
704 case PM8XXX_MPP_BI_PULLUP_30KOHM:
705 pin->pullup = 30000;
706 break;
707 }
708 break;
709 case PM8XXX_MPP_TYPE_A_INPUT:
710 pin->mode = PM8XXX_MPP_ANALOG;
711 pin->input = true;
712 pin->amux = level;
713 break;
714 case PM8XXX_MPP_TYPE_A_OUTPUT:
715 pin->mode = PM8XXX_MPP_ANALOG;
716 pin->output = true;
717 pin->aout_level = level;
718 pin->output_value = !!(ctrl & BIT(0));
719 pin->paired = !!(ctrl & BIT(1));
720 break;
721 case PM8XXX_MPP_TYPE_SINK:
722 pin->mode = PM8XXX_MPP_SINK;
723 pin->drive_strength = 5 * (level + 1);
724 pin->output_value = !!(ctrl & BIT(0));
725 pin->paired = !!(ctrl & BIT(1));
726 break;
727 case PM8XXX_MPP_TYPE_DTEST_SINK:
728 pin->mode = PM8XXX_MPP_SINK;
729 pin->dtest = ctrl + 1;
730 pin->drive_strength = 5 * (level + 1);
731 break;
732 case PM8XXX_MPP_TYPE_DTEST_OUTPUT:
733 pin->mode = PM8XXX_MPP_DIGITAL;
734 pin->power_source = level;
735 if (ctrl >= 1)
736 pin->dtest = ctrl;
737 break;
738 }
739
740 return 0;
741}
742
743static const struct of_device_id pm8xxx_mpp_of_match[] = {
744 { .compatible = "qcom,pm8018-mpp", .data = (void *)6 },
745 { .compatible = "qcom,pm8038-mpp", .data = (void *)6 },
746 { .compatible = "qcom,pm8917-mpp", .data = (void *)10 },
747 { .compatible = "qcom,pm8821-mpp", .data = (void *)4 },
748 { .compatible = "qcom,pm8921-mpp", .data = (void *)12 },
749 { },
750};
751MODULE_DEVICE_TABLE(of, pm8xxx_mpp_of_match);
752
753static int pm8xxx_mpp_probe(struct platform_device *pdev)
754{
755 struct pm8xxx_pin_data *pin_data;
756 struct pinctrl_pin_desc *pins;
757 struct pm8xxx_mpp *pctrl;
758 int ret;
759 int i;
760
761 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
762 if (!pctrl)
763 return -ENOMEM;
764
765 pctrl->dev = &pdev->dev;
766 pctrl->npins = (unsigned)of_device_get_match_data(&pdev->dev);
767
768 pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL);
769 if (!pctrl->regmap) {
770 dev_err(&pdev->dev, "parent regmap unavailable\n");
771 return -ENXIO;
772 }
773
774 pctrl->desc = pm8xxx_pinctrl_desc;
775 pctrl->desc.npins = pctrl->npins;
776
777 pins = devm_kcalloc(&pdev->dev,
778 pctrl->desc.npins,
779 sizeof(struct pinctrl_pin_desc),
780 GFP_KERNEL);
781 if (!pins)
782 return -ENOMEM;
783
784 pin_data = devm_kcalloc(&pdev->dev,
785 pctrl->desc.npins,
786 sizeof(struct pm8xxx_pin_data),
787 GFP_KERNEL);
788 if (!pin_data)
789 return -ENOMEM;
790
791 for (i = 0; i < pctrl->desc.npins; i++) {
792 pin_data[i].reg = SSBI_REG_ADDR_MPP(i);
793 pin_data[i].irq = platform_get_irq(pdev, i);
794 if (pin_data[i].irq < 0) {
795 dev_err(&pdev->dev,
796 "missing interrupts for pin %d\n", i);
797 return pin_data[i].irq;
798 }
799
800 ret = pm8xxx_pin_populate(pctrl, &pin_data[i]);
801 if (ret)
802 return ret;
803
804 pins[i].number = i;
805 pins[i].name = pm8xxx_groups[i];
806 pins[i].drv_data = &pin_data[i];
807 }
808 pctrl->desc.pins = pins;
809
810 pctrl->desc.num_custom_params = ARRAY_SIZE(pm8xxx_mpp_bindings);
811 pctrl->desc.custom_params = pm8xxx_mpp_bindings;
812#ifdef CONFIG_DEBUG_FS
813 pctrl->desc.custom_conf_items = pm8xxx_conf_items;
814#endif
815
816 pctrl->pctrl = pinctrl_register(&pctrl->desc, &pdev->dev, pctrl);
817 if (!pctrl->pctrl) {
818 dev_err(&pdev->dev, "couldn't register pm8xxx mpp driver\n");
819 return -ENODEV;
820 }
821
822 pctrl->chip = pm8xxx_mpp_template;
823 pctrl->chip.base = -1;
824 pctrl->chip.dev = &pdev->dev;
825 pctrl->chip.of_node = pdev->dev.of_node;
826 pctrl->chip.of_gpio_n_cells = 2;
827 pctrl->chip.label = dev_name(pctrl->dev);
828 pctrl->chip.ngpio = pctrl->npins;
829 ret = gpiochip_add(&pctrl->chip);
830 if (ret) {
831 dev_err(&pdev->dev, "failed register gpiochip\n");
832 goto unregister_pinctrl;
833 }
834
835 ret = gpiochip_add_pin_range(&pctrl->chip,
836 dev_name(pctrl->dev),
837 0, 0, pctrl->chip.ngpio);
838 if (ret) {
839 dev_err(pctrl->dev, "failed to add pin range\n");
840 goto unregister_gpiochip;
841 }
842
843 platform_set_drvdata(pdev, pctrl);
844
845 dev_dbg(&pdev->dev, "Qualcomm pm8xxx mpp driver probed\n");
846
847 return 0;
848
849unregister_gpiochip:
850 gpiochip_remove(&pctrl->chip);
851
852unregister_pinctrl:
853 pinctrl_unregister(pctrl->pctrl);
854
855 return ret;
856}
857
858static int pm8xxx_mpp_remove(struct platform_device *pdev)
859{
860 struct pm8xxx_mpp *pctrl = platform_get_drvdata(pdev);
861
862 gpiochip_remove(&pctrl->chip);
863
864 pinctrl_unregister(pctrl->pctrl);
865
866 return 0;
867}
868
869static struct platform_driver pm8xxx_mpp_driver = {
870 .driver = {
871 .name = "qcom-ssbi-mpp",
872 .of_match_table = pm8xxx_mpp_of_match,
873 },
874 .probe = pm8xxx_mpp_probe,
875 .remove = pm8xxx_mpp_remove,
876};
877
878module_platform_driver(pm8xxx_mpp_driver);
879
880MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");
881MODULE_DESCRIPTION("Qualcomm PM8xxx MPP driver");
882MODULE_LICENSE("GPL v2");
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-31 23:58:56 -0500