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-rw-r--r--CREDITS4
-rw-r--r--Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt37
-rw-r--r--Documentation/devicetree/bindings/pinctrl/cnxt,cx92755-pinctrl.txt86
-rw-r--r--Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt36
-rw-r--r--Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt24
-rw-r--r--Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt7
-rw-r--r--MAINTAINERS1
-rw-r--r--arch/arm/boot/dts/ste-dbx5x0.dtsi23
-rw-r--r--arch/arm/boot/dts/ste-nomadik-stn8815.dtsi8
-rw-r--r--drivers/Makefile2
-rw-r--r--drivers/clk/rockchip/clk-rk3288.c1
-rw-r--r--drivers/pinctrl/Kconfig7
-rw-r--r--drivers/pinctrl/Makefile8
-rw-r--r--drivers/pinctrl/bcm/pinctrl-bcm2835.c5
-rw-r--r--drivers/pinctrl/core.c3
-rw-r--r--drivers/pinctrl/devicetree.c8
-rw-r--r--drivers/pinctrl/freescale/Kconfig7
-rw-r--r--drivers/pinctrl/freescale/Makefile1
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx6ul.c322
-rw-r--r--drivers/pinctrl/intel/pinctrl-baytrail.c68
-rw-r--r--drivers/pinctrl/intel/pinctrl-cherryview.c76
-rw-r--r--drivers/pinctrl/intel/pinctrl-intel.c6
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mt8173.c1
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mtk-common.c120
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mtk-common.h5
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c21
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-nomadik-db8540.c24
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c30
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-nomadik.c241
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-nomadik.h4
-rw-r--r--drivers/pinctrl/pinconf.c88
-rw-r--r--drivers/pinctrl/pinctrl-adi2-bf60x.c8
-rw-r--r--drivers/pinctrl/pinctrl-adi2.c4
-rw-r--r--drivers/pinctrl/pinctrl-amd.c15
-rw-r--r--drivers/pinctrl/pinctrl-at91.c51
-rw-r--r--drivers/pinctrl/pinctrl-coh901.c7
-rw-r--r--drivers/pinctrl/pinctrl-digicolor.c378
-rw-r--r--drivers/pinctrl/pinctrl-lpc18xx.c54
-rw-r--r--drivers/pinctrl/pinctrl-pistachio.c6
-rw-r--r--drivers/pinctrl/pinctrl-rockchip.c71
-rw-r--r--drivers/pinctrl/pinctrl-single.c14
-rw-r--r--drivers/pinctrl/pinctrl-st.c6
-rw-r--r--drivers/pinctrl/pinctrl-zynq.c4
-rw-r--r--drivers/pinctrl/pinmux.c3
-rw-r--r--drivers/pinctrl/qcom/Kconfig20
-rw-r--r--drivers/pinctrl/qcom/Makefile3
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm.c19
-rw-r--r--drivers/pinctrl/qcom/pinctrl-qdf2xxx.c122
-rw-r--r--drivers/pinctrl/qcom/pinctrl-spmi-mpp.c376
-rw-r--r--drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c791
-rw-r--r--drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c882
-rw-r--r--drivers/pinctrl/samsung/pinctrl-exynos.c18
-rw-r--r--drivers/pinctrl/samsung/pinctrl-exynos5440.c90
-rw-r--r--drivers/pinctrl/samsung/pinctrl-s3c24xx.c28
-rw-r--r--drivers/pinctrl/samsung/pinctrl-s3c64xx.c34
-rw-r--r--drivers/pinctrl/sh-pfc/core.c52
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7740.c4
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7790.c21
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7791.c19
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7794.c30
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh73a0.c4
-rw-r--r--drivers/pinctrl/sh-pfc/pinctrl.c86
-rw-r--r--drivers/pinctrl/sh-pfc/sh_pfc.h5
-rw-r--r--drivers/pinctrl/sirf/pinctrl-atlas7.c525
-rw-r--r--drivers/pinctrl/sirf/pinctrl-sirf.c5
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c17
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sunxi.c62
-rw-r--r--drivers/pinctrl/uniphier/Kconfig32
-rw-r--r--drivers/pinctrl/uniphier/Makefile8
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c886
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c1274
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c1554
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c1351
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c794
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-proxstream2.c1269
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier-core.c684
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier.h217
-rw-r--r--include/dt-bindings/pinctrl/qcom,pmic-mpp.h51
78 files changed, 12274 insertions, 954 deletions
diff --git a/CREDITS b/CREDITS
index 4fcf9cd8544c..bcb8efaa9459 100644
--- a/CREDITS
+++ b/CREDITS
@@ -20,6 +20,10 @@ D: One of assisting postmasters for vger.kernel.org's lists
20S: (ask for current address) 20S: (ask for current address)
21S: Finland 21S: Finland
22 22
23N: Thomas Abraham
24E: thomas.ab@samsung.com
25D: Samsung pin controller driver
26
23N: Dragos Acostachioaie 27N: Dragos Acostachioaie
24E: dragos@iname.com 28E: dragos@iname.com
25W: http://www.arbornet.org/~dragos 29W: http://www.arbornet.org/~dragos
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 9462ab7ddd1f..3c821cda1ad0 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -48,7 +48,7 @@ Optional subnode-properties:
48 48
49Examples: 49Examples:
50 50
51pinctrl@01c20800 { 51pio: pinctrl@01c20800 {
52 compatible = "allwinner,sun5i-a13-pinctrl"; 52 compatible = "allwinner,sun5i-a13-pinctrl";
53 reg = <0x01c20800 0x400>; 53 reg = <0x01c20800 0x400>;
54 #address-cells = <1>; 54 #address-cells = <1>;
@@ -68,3 +68,38 @@ pinctrl@01c20800 {
68 allwinner,pull = <0>; 68 allwinner,pull = <0>;
69 }; 69 };
70}; 70};
71
72
73GPIO and interrupt controller
74-----------------------------
75
76This hardware also acts as a GPIO controller and an interrupt
77controller.
78
79Consumers that would want to refer to one or the other (or both)
80should provide through the usual *-gpios and interrupts properties a
81cell with 3 arguments, first the number of the bank, then the pin
82inside that bank, and finally the flags for the GPIO/interrupts.
83
84Example:
85
86xio: gpio@38 {
87 compatible = "nxp,pcf8574a";
88 reg = <0x38>;
89
90 gpio-controller;
91 #gpio-cells = <2>;
92
93 interrupt-parent = <&pio>;
94 interrupts = <6 0 IRQ_TYPE_EDGE_FALLING>;
95 interrupt-controller;
96 #interrupt-cells = <2>;
97};
98
99reg_usb1_vbus: usb1-vbus {
100 compatible = "regulator-fixed";
101 regulator-name = "usb1-vbus";
102 regulator-min-microvolt = <5000000>;
103 regulator-max-microvolt = <5000000>;
104 gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>;
105};
diff --git a/Documentation/devicetree/bindings/pinctrl/cnxt,cx92755-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/cnxt,cx92755-pinctrl.txt
new file mode 100644
index 000000000000..23ce8dc26990
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/cnxt,cx92755-pinctrl.txt
@@ -0,0 +1,86 @@
1Conexant Digicolor CX92755 General Purpose Pin Mapping
2
3This document describes the device tree binding of the pin mapping hardware
4modules in the Conexant Digicolor CX92755 SoCs. The CX92755 in one of the
5Digicolor series of SoCs.
6
7=== Pin Controller Node ===
8
9Required Properties:
10
11- compatible: Must be "cnxt,cx92755-pinctrl"
12- reg: Base address of the General Purpose Pin Mapping register block and the
13 size of the block.
14- gpio-controller: Marks the device node as a GPIO controller.
15- #gpio-cells: Must be <2>. The first cell is the pin number and the
16 second cell is used to specify flags. See include/dt-bindings/gpio/gpio.h
17 for possible values.
18
19For example, the following is the bare minimum node:
20
21 pinctrl: pinctrl@f0000e20 {
22 compatible = "cnxt,cx92755-pinctrl";
23 reg = <0xf0000e20 0x100>;
24 gpio-controller;
25 #gpio-cells = <2>;
26 };
27
28As a pin controller device, in addition to the required properties, this node
29should also contain the pin configuration nodes that client devices reference,
30if any.
31
32For a general description of GPIO bindings, please refer to ../gpio/gpio.txt.
33
34=== Pin Configuration Node ===
35
36Each pin configuration node is a sub-node of the pin controller node and is a
37container of an arbitrary number of subnodes, called pin group nodes in this
38document.
39
40Please refer to the pinctrl-bindings.txt in this directory for details of the
41common pinctrl bindings used by client devices, including the definition of a
42"pin configuration node".
43
44=== Pin Group Node ===
45
46A pin group node specifies the desired pin mux for an arbitrary number of
47pins. The name of the pin group node is optional and not used.
48
49A pin group node only affects the properties specified in the node, and has no
50effect on any properties that are omitted.
51
52The pin group node accepts a subset of the generic pin config properties. For
53details generic pin config properties, please refer to pinctrl-bindings.txt
54and <include/linux/pinctrl/pinconfig-generic.h>.
55
56Required Pin Group Node Properties:
57
58- pins: Multiple strings. Specifies the name(s) of one or more pins to be
59 configured by this node. The format of a pin name string is "GP_xy", where x
60 is an uppercase character from 'A' to 'R', and y is a digit from 0 to 7.
61- function: String. Specifies the pin mux selection. Values must be one of:
62 "gpio", "client_a", "client_b", "client_c"
63
64Example:
65 pinctrl: pinctrl@f0000e20 {
66 compatible = "cnxt,cx92755-pinctrl";
67 reg = <0xf0000e20 0x100>;
68
69 uart0_default: uart0_active {
70 data_signals {
71 pins = "GP_O0", "GP_O1";
72 function = "client_b";
73 };
74 };
75 };
76
77 uart0: uart@f0000740 {
78 compatible = "cnxt,cx92755-usart";
79 ...
80 pinctrl-0 = <&uart0_default>;
81 pinctrl-names = "default";
82 };
83
84In the example above, a single pin group configuration node defines the
85"client select" for the Rx and Tx signals of uart0. The uart0 node references
86that pin configuration node using the &uart0_default phandle.
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt
index ed19991aad35..d7803a2a94e9 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt
@@ -7,8 +7,13 @@ of PMIC's from Qualcomm.
7 Usage: required 7 Usage: required
8 Value type: <string> 8 Value type: <string>
9 Definition: Should contain one of: 9 Definition: Should contain one of:
10 "qcom,pm8018-mpp",
11 "qcom,pm8038-mpp",
12 "qcom,pm8821-mpp",
10 "qcom,pm8841-mpp", 13 "qcom,pm8841-mpp",
11 "qcom,pm8916-mpp", 14 "qcom,pm8916-mpp",
15 "qcom,pm8917-mpp",
16 "qcom,pm8921-mpp",
12 "qcom,pm8941-mpp", 17 "qcom,pm8941-mpp",
13 "qcom,pma8084-mpp", 18 "qcom,pma8084-mpp",
14 19
@@ -77,12 +82,9 @@ to specify in a pin configuration subnode:
77 Value type: <string> 82 Value type: <string>
78 Definition: Specify the alternative function to be configured for the 83 Definition: Specify the alternative function to be configured for the
79 specified pins. Valid values are: 84 specified pins. Valid values are:
80 "normal", 85 "digital",
81 "paired", 86 "analog",
82 "dtest1", 87 "sink"
83 "dtest2",
84 "dtest3",
85 "dtest4"
86 88
87- bias-disable: 89- bias-disable:
88 Usage: optional 90 Usage: optional
@@ -127,12 +129,18 @@ to specify in a pin configuration subnode:
127 Definition: Selects the power source for the specified pins. Valid power 129 Definition: Selects the power source for the specified pins. Valid power
128 sources are defined in <dt-bindings/pinctrl/qcom,pmic-mpp.h> 130 sources are defined in <dt-bindings/pinctrl/qcom,pmic-mpp.h>
129 131
130- qcom,analog-mode: 132- qcom,analog-level:
131 Usage: optional 133 Usage: optional
132 Value type: <none> 134 Value type: <u32>
133 Definition: Selects Analog mode of operation: combined with input-enable 135 Definition: Selects the source for analog output. Valued values are
134 and/or output-high, output-low MPP could operate as 136 defined in <dt-binding/pinctrl/qcom,pmic-mpp.h>
135 Bidirectional Logic, Analog Input, Analog Output. 137 PMIC_MPP_AOUT_LVL_*
138
139- qcom,dtest:
140 Usage: optional
141 Value type: <u32>
142 Definition: Selects which dtest rail to be routed in the various functions.
143 Valid values are 1-4
136 144
137- qcom,amux-route: 145- qcom,amux-route:
138 Usage: optional 146 Usage: optional
@@ -140,6 +148,10 @@ to specify in a pin configuration subnode:
140 Definition: Selects the source for analog input. Valid values are 148 Definition: Selects the source for analog input. Valid values are
141 defined in <dt-bindings/pinctrl/qcom,pmic-mpp.h> 149 defined in <dt-bindings/pinctrl/qcom,pmic-mpp.h>
142 PMIC_MPP_AMUX_ROUTE_CH5, PMIC_MPP_AMUX_ROUTE_CH6... 150 PMIC_MPP_AMUX_ROUTE_CH5, PMIC_MPP_AMUX_ROUTE_CH6...
151- qcom,paired:
152 Usage: optional
153 Value type: <none>
154 Definition: Indicates that the pin should be operating in paired mode.
143 155
144Example: 156Example:
145 157
@@ -156,7 +168,7 @@ Example:
156 pm8841_default: default { 168 pm8841_default: default {
157 gpio { 169 gpio {
158 pins = "mpp1", "mpp2", "mpp3", "mpp4"; 170 pins = "mpp1", "mpp2", "mpp3", "mpp4";
159 function = "normal"; 171 function = "digital";
160 input-enable; 172 input-enable;
161 power-source = <PM8841_MPP_S3>; 173 power-source = <PM8841_MPP_S3>;
162 }; 174 };
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
index 51cee44fc140..9496934528bd 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -58,12 +58,12 @@ are parsed through phandles and processed purely based on their content.
58 58
59Pin Configuration Node Properties: 59Pin Configuration Node Properties:
60 60
61- renesas,pins : An array of strings, each string containing the name of a pin. 61- pins : An array of strings, each string containing the name of a pin.
62- renesas,groups : An array of strings, each string containing the name of a pin 62- groups : An array of strings, each string containing the name of a pin
63 group. 63 group.
64 64
65- renesas,function: A string containing the name of the function to mux to the 65- function: A string containing the name of the function to mux to the pin
66 pin group(s) specified by the renesas,groups property 66 group(s) specified by the groups property.
67 67
68 Valid values for pin, group and function names can be found in the group and 68 Valid values for pin, group and function names can be found in the group and
69 function arrays of the PFC data file corresponding to the SoC 69 function arrays of the PFC data file corresponding to the SoC
@@ -71,7 +71,9 @@ Pin Configuration Node Properties:
71 71
72The pin configuration parameters use the generic pinconf bindings defined in 72The pin configuration parameters use the generic pinconf bindings defined in
73pinctrl-bindings.txt in this directory. The supported parameters are 73pinctrl-bindings.txt in this directory. The supported parameters are
74bias-disable, bias-pull-up and bias-pull-down. 74bias-disable, bias-pull-up, bias-pull-down and power-source. For pins that
75have a configurable I/O voltage, the power-source value should be the
76nominal I/O voltage in millivolts.
75 77
76 78
77GPIO 79GPIO
@@ -141,19 +143,19 @@ Example 3: KZM-A9-GT (SH-Mobile AG5) default pin state hog and pin control maps
141 143
142 mmcif_pins: mmcif { 144 mmcif_pins: mmcif {
143 mux { 145 mux {
144 renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0"; 146 groups = "mmc0_data8_0", "mmc0_ctrl_0";
145 renesas,function = "mmc0"; 147 function = "mmc0";
146 }; 148 };
147 cfg { 149 cfg {
148 renesas,groups = "mmc0_data8_0"; 150 groups = "mmc0_data8_0";
149 renesas,pins = "PORT279"; 151 pins = "PORT279";
150 bias-pull-up; 152 bias-pull-up;
151 }; 153 };
152 }; 154 };
153 155
154 scifa4_pins: scifa4 { 156 scifa4_pins: scifa4 {
155 renesas,groups = "scifa4_data", "scifa4_ctrl"; 157 groups = "scifa4_data", "scifa4_ctrl";
156 renesas,function = "scifa4"; 158 function = "scifa4";
157 }; 159 };
158 }; 160 };
159 161
diff --git a/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt b/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt
index f63fcb3ed352..2213802435e0 100644
--- a/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt
+++ b/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt
@@ -3,7 +3,9 @@ ST Ericsson Nomadik pinmux controller
3Required properties: 3Required properties:
4- compatible: "stericsson,db8500-pinctrl", "stericsson,db8540-pinctrl", 4- compatible: "stericsson,db8500-pinctrl", "stericsson,db8540-pinctrl",
5 "stericsson,stn8815-pinctrl" 5 "stericsson,stn8815-pinctrl"
6- reg: Should contain the register physical address and length of the PRCMU. 6- nomadik-gpio-chips: array of phandles to the corresponding GPIO chips
7 (these have the register ranges used by the pin controller).
8- prcm: phandle to the PRCMU managing the back end of this pin controller
7 9
8Please refer to pinctrl-bindings.txt in this directory for details of the 10Please refer to pinctrl-bindings.txt in this directory for details of the
9common pinctrl bindings used by client devices, including the meaning of the 11common pinctrl bindings used by client devices, including the meaning of the
@@ -74,7 +76,8 @@ Example board file extract:
74 76
75 pinctrl@80157000 { 77 pinctrl@80157000 {
76 compatible = "stericsson,db8500-pinctrl"; 78 compatible = "stericsson,db8500-pinctrl";
77 reg = <0x80157000 0x2000>; 79 nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>;
80 prcm = <&prcmu>;
78 81
79 pinctrl-names = "default"; 82 pinctrl-names = "default";
80 83
diff --git a/MAINTAINERS b/MAINTAINERS
index b4c6754f3144..4660d8fae904 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8045,7 +8045,6 @@ F: drivers/pinctrl/sh-pfc/
8045 8045
8046PIN CONTROLLER - SAMSUNG 8046PIN CONTROLLER - SAMSUNG
8047M: Tomasz Figa <tomasz.figa@gmail.com> 8047M: Tomasz Figa <tomasz.figa@gmail.com>
8048M: Thomas Abraham <thomas.abraham@linaro.org>
8049L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 8048L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
8050L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers) 8049L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
8051S: Maintained 8050S: Maintained
diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi
index c5fbde3afcf6..50f5e9d09203 100644
--- a/arch/arm/boot/dts/ste-dbx5x0.dtsi
+++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi
@@ -294,7 +294,7 @@
294 gpio-controller; 294 gpio-controller;
295 #gpio-cells = <2>; 295 #gpio-cells = <2>;
296 gpio-bank = <0>; 296 gpio-bank = <0>;
297 297 gpio-ranges = <&pinctrl 0 0 32>;
298 clocks = <&prcc_pclk 1 9>; 298 clocks = <&prcc_pclk 1 9>;
299 }; 299 };
300 300
@@ -309,7 +309,7 @@
309 gpio-controller; 309 gpio-controller;
310 #gpio-cells = <2>; 310 #gpio-cells = <2>;
311 gpio-bank = <1>; 311 gpio-bank = <1>;
312 312 gpio-ranges = <&pinctrl 0 32 5>;
313 clocks = <&prcc_pclk 1 9>; 313 clocks = <&prcc_pclk 1 9>;
314 }; 314 };
315 315
@@ -324,7 +324,7 @@
324 gpio-controller; 324 gpio-controller;
325 #gpio-cells = <2>; 325 #gpio-cells = <2>;
326 gpio-bank = <2>; 326 gpio-bank = <2>;
327 327 gpio-ranges = <&pinctrl 0 64 32>;
328 clocks = <&prcc_pclk 3 8>; 328 clocks = <&prcc_pclk 3 8>;
329 }; 329 };
330 330
@@ -339,7 +339,7 @@
339 gpio-controller; 339 gpio-controller;
340 #gpio-cells = <2>; 340 #gpio-cells = <2>;
341 gpio-bank = <3>; 341 gpio-bank = <3>;
342 342 gpio-ranges = <&pinctrl 0 96 2>;
343 clocks = <&prcc_pclk 3 8>; 343 clocks = <&prcc_pclk 3 8>;
344 }; 344 };
345 345
@@ -354,7 +354,7 @@
354 gpio-controller; 354 gpio-controller;
355 #gpio-cells = <2>; 355 #gpio-cells = <2>;
356 gpio-bank = <4>; 356 gpio-bank = <4>;
357 357 gpio-ranges = <&pinctrl 0 128 32>;
358 clocks = <&prcc_pclk 3 8>; 358 clocks = <&prcc_pclk 3 8>;
359 }; 359 };
360 360
@@ -369,7 +369,7 @@
369 gpio-controller; 369 gpio-controller;
370 #gpio-cells = <2>; 370 #gpio-cells = <2>;
371 gpio-bank = <5>; 371 gpio-bank = <5>;
372 372 gpio-ranges = <&pinctrl 0 160 12>;
373 clocks = <&prcc_pclk 3 8>; 373 clocks = <&prcc_pclk 3 8>;
374 }; 374 };
375 375
@@ -384,7 +384,7 @@
384 gpio-controller; 384 gpio-controller;
385 #gpio-cells = <2>; 385 #gpio-cells = <2>;
386 gpio-bank = <6>; 386 gpio-bank = <6>;
387 387 gpio-ranges = <&pinctrl 0 192 32>;
388 clocks = <&prcc_pclk 2 11>; 388 clocks = <&prcc_pclk 2 11>;
389 }; 389 };
390 390
@@ -399,7 +399,7 @@
399 gpio-controller; 399 gpio-controller;
400 #gpio-cells = <2>; 400 #gpio-cells = <2>;
401 gpio-bank = <7>; 401 gpio-bank = <7>;
402 402 gpio-ranges = <&pinctrl 0 224 7>;
403 clocks = <&prcc_pclk 2 11>; 403 clocks = <&prcc_pclk 2 11>;
404 }; 404 };
405 405
@@ -414,12 +414,15 @@
414 gpio-controller; 414 gpio-controller;
415 #gpio-cells = <2>; 415 #gpio-cells = <2>;
416 gpio-bank = <8>; 416 gpio-bank = <8>;
417 417 gpio-ranges = <&pinctrl 0 256 12>;
418 clocks = <&prcc_pclk 5 1>; 418 clocks = <&prcc_pclk 5 1>;
419 }; 419 };
420 420
421 pinctrl { 421 pinctrl: pinctrl {
422 compatible = "stericsson,db8500-pinctrl"; 422 compatible = "stericsson,db8500-pinctrl";
423 nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>,
424 <&gpio4>, <&gpio5>, <&gpio6>, <&gpio7>,
425 <&gpio8>;
423 prcm = <&prcmu>; 426 prcm = <&prcmu>;
424 }; 427 };
425 428
diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
index 176e332fc0bd..314f59c12162 100644
--- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
+++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
@@ -59,6 +59,7 @@
59 gpio-controller; 59 gpio-controller;
60 #gpio-cells = <2>; 60 #gpio-cells = <2>;
61 gpio-bank = <0>; 61 gpio-bank = <0>;
62 gpio-ranges = <&pinctrl 0 0 32>;
62 clocks = <&pclk>; 63 clocks = <&pclk>;
63 }; 64 };
64 65
@@ -72,6 +73,7 @@
72 gpio-controller; 73 gpio-controller;
73 #gpio-cells = <2>; 74 #gpio-cells = <2>;
74 gpio-bank = <1>; 75 gpio-bank = <1>;
76 gpio-ranges = <&pinctrl 0 32 32>;
75 clocks = <&pclk>; 77 clocks = <&pclk>;
76 }; 78 };
77 79
@@ -85,12 +87,14 @@
85 gpio-controller; 87 gpio-controller;
86 #gpio-cells = <2>; 88 #gpio-cells = <2>;
87 gpio-bank = <2>; 89 gpio-bank = <2>;
90 gpio-ranges = <&pinctrl 0 64 32>;
88 clocks = <&pclk>; 91 clocks = <&pclk>;
89 }; 92 };
90 93
91 gpio3: gpio@101e7000 { 94 gpio3: gpio@101e7000 {
92 compatible = "st,nomadik-gpio"; 95 compatible = "st,nomadik-gpio";
93 reg = <0x101e7000 0x80>; 96 reg = <0x101e7000 0x80>;
97 ngpio = <28>;
94 interrupt-parent = <&vica>; 98 interrupt-parent = <&vica>;
95 interrupts = <9>; 99 interrupts = <9>;
96 interrupt-controller; 100 interrupt-controller;
@@ -98,11 +102,13 @@
98 gpio-controller; 102 gpio-controller;
99 #gpio-cells = <2>; 103 #gpio-cells = <2>;
100 gpio-bank = <3>; 104 gpio-bank = <3>;
105 gpio-ranges = <&pinctrl 0 96 28>;
101 clocks = <&pclk>; 106 clocks = <&pclk>;
102 }; 107 };
103 108
104 pinctrl { 109 pinctrl: pinctrl {
105 compatible = "stericsson,stn8815-pinctrl"; 110 compatible = "stericsson,stn8815-pinctrl";
111 nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>;
106 /* Pin configurations */ 112 /* Pin configurations */
107 uart1 { 113 uart1 {
108 uart1_default_mux: uart1_mux { 114 uart1_default_mux: uart1_mux {
diff --git a/drivers/Makefile b/drivers/Makefile
index 47a118aec76f..b250b36b54f2 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -11,7 +11,7 @@ obj-y += bus/
11obj-$(CONFIG_GENERIC_PHY) += phy/ 11obj-$(CONFIG_GENERIC_PHY) += phy/
12 12
13# GPIO must come after pinctrl as gpios may need to mux pins etc 13# GPIO must come after pinctrl as gpios may need to mux pins etc
14obj-y += pinctrl/ 14obj-$(CONFIG_PINCTRL) += pinctrl/
15obj-y += gpio/ 15obj-y += gpio/
16obj-y += pwm/ 16obj-y += pwm/
17obj-$(CONFIG_PCI) += pci/ 17obj-$(CONFIG_PCI) += pci/
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 0df5bae9ddbf..9040878e3e2b 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -780,6 +780,7 @@ static const char *const rk3288_critical_clocks[] __initconst = {
780 "aclk_cpu", 780 "aclk_cpu",
781 "aclk_peri", 781 "aclk_peri",
782 "hclk_peri", 782 "hclk_peri",
783 "pclk_pd_pmu",
783}; 784};
784 785
785#ifdef CONFIG_PM_SLEEP 786#ifdef CONFIG_PM_SLEEP
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 100d9ac2ae1f..84dd2ed47a92 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -82,6 +82,12 @@ config PINCTRL_AMD
82 Requires ACPI/FDT device enumeration code to set up a platform 82 Requires ACPI/FDT device enumeration code to set up a platform
83 device. 83 device.
84 84
85config PINCTRL_DIGICOLOR
86 bool
87 depends on OF && (ARCH_DIGICOLOR || COMPILE_TEST)
88 select PINMUX
89 select GENERIC_PINCONF
90
85config PINCTRL_LANTIQ 91config PINCTRL_LANTIQ
86 bool 92 bool
87 depends on LANTIQ 93 depends on LANTIQ
@@ -240,6 +246,7 @@ source "drivers/pinctrl/samsung/Kconfig"
240source "drivers/pinctrl/sh-pfc/Kconfig" 246source "drivers/pinctrl/sh-pfc/Kconfig"
241source "drivers/pinctrl/spear/Kconfig" 247source "drivers/pinctrl/spear/Kconfig"
242source "drivers/pinctrl/sunxi/Kconfig" 248source "drivers/pinctrl/sunxi/Kconfig"
249source "drivers/pinctrl/uniphier/Kconfig"
243source "drivers/pinctrl/vt8500/Kconfig" 250source "drivers/pinctrl/vt8500/Kconfig"
244source "drivers/pinctrl/mediatek/Kconfig" 251source "drivers/pinctrl/mediatek/Kconfig"
245 252
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index f4216d9347e2..cad077c43fb7 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -2,12 +2,10 @@
2 2
3subdir-ccflags-$(CONFIG_DEBUG_PINCTRL) += -DDEBUG 3subdir-ccflags-$(CONFIG_DEBUG_PINCTRL) += -DDEBUG
4 4
5obj-$(CONFIG_PINCTRL) += core.o pinctrl-utils.o 5obj-y += core.o pinctrl-utils.o
6obj-$(CONFIG_PINMUX) += pinmux.o 6obj-$(CONFIG_PINMUX) += pinmux.o
7obj-$(CONFIG_PINCONF) += pinconf.o 7obj-$(CONFIG_PINCONF) += pinconf.o
8ifeq ($(CONFIG_OF),y) 8obj-$(CONFIG_OF) += devicetree.o
9obj-$(CONFIG_PINCTRL) += devicetree.o
10endif
11obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o 9obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o
12obj-$(CONFIG_PINCTRL_ADI2) += pinctrl-adi2.o 10obj-$(CONFIG_PINCTRL_ADI2) += pinctrl-adi2.o
13obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o 11obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o
@@ -15,6 +13,7 @@ obj-$(CONFIG_PINCTRL_BF54x) += pinctrl-adi2-bf54x.o
15obj-$(CONFIG_PINCTRL_BF60x) += pinctrl-adi2-bf60x.o 13obj-$(CONFIG_PINCTRL_BF60x) += pinctrl-adi2-bf60x.o
16obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o 14obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
17obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o 15obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o
16obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o
18obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o 17obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
19obj-$(CONFIG_PINCTRL_MESON) += meson/ 18obj-$(CONFIG_PINCTRL_MESON) += meson/
20obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o 19obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
@@ -51,5 +50,6 @@ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/
51obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/ 50obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/
52obj-$(CONFIG_PLAT_SPEAR) += spear/ 51obj-$(CONFIG_PLAT_SPEAR) += spear/
53obj-$(CONFIG_ARCH_SUNXI) += sunxi/ 52obj-$(CONFIG_ARCH_SUNXI) += sunxi/
53obj-$(CONFIG_ARCH_UNIPHIER) += uniphier/
54obj-$(CONFIG_ARCH_VT8500) += vt8500/ 54obj-$(CONFIG_ARCH_VT8500) += vt8500/
55obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ 55obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
index 6177315ab74e..8efa235ca1c9 100644
--- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c
+++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
@@ -586,9 +586,9 @@ static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
586 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type); 586 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
587 587
588 if (type & IRQ_TYPE_EDGE_BOTH) 588 if (type & IRQ_TYPE_EDGE_BOTH)
589 __irq_set_handler_locked(data->irq, handle_edge_irq); 589 irq_set_handler_locked(data, handle_edge_irq);
590 else 590 else
591 __irq_set_handler_locked(data->irq, handle_level_irq); 591 irq_set_handler_locked(data, handle_level_irq);
592 592
593 spin_unlock_irqrestore(&pc->irq_lock[bank], flags); 593 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
594 594
@@ -989,7 +989,6 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
989 irq_set_chip_and_handler(irq, &bcm2835_gpio_irq_chip, 989 irq_set_chip_and_handler(irq, &bcm2835_gpio_irq_chip,
990 handle_level_irq); 990 handle_level_irq);
991 irq_set_chip_data(irq, pc); 991 irq_set_chip_data(irq, pc);
992 set_irq_flags(irq, IRQF_VALID);
993 } 992 }
994 993
995 for (i = 0; i < BCM2835_NUM_BANKS; i++) { 994 for (i = 0; i < BCM2835_NUM_BANKS; i++) {
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index 8b8f3a04c353..69723e07036b 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -231,8 +231,7 @@ static int pinctrl_register_one_pin(struct pinctrl_dev *pctldev,
231 231
232 pindesc = pin_desc_get(pctldev, number); 232 pindesc = pin_desc_get(pctldev, number);
233 if (pindesc != NULL) { 233 if (pindesc != NULL) {
234 pr_err("pin %d already registered on %s\n", number, 234 dev_err(pctldev->dev, "pin %d already registered\n", number);
235 pctldev->desc->name);
236 return -EINVAL; 235 return -EINVAL;
237 } 236 }
238 237
diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c
index 0bbf7d71b281..fe04e748dfe4 100644
--- a/drivers/pinctrl/devicetree.c
+++ b/drivers/pinctrl/devicetree.c
@@ -97,13 +97,7 @@ static int dt_remember_or_free_map(struct pinctrl *p, const char *statename,
97 97
98struct pinctrl_dev *of_pinctrl_get(struct device_node *np) 98struct pinctrl_dev *of_pinctrl_get(struct device_node *np)
99{ 99{
100 struct pinctrl_dev *pctldev; 100 return get_pinctrl_dev_from_of_node(np);
101
102 pctldev = get_pinctrl_dev_from_of_node(np);
103 if (!pctldev)
104 return NULL;
105
106 return pctldev;
107} 101}
108 102
109static int dt_to_map_one_config(struct pinctrl *p, const char *statename, 103static int dt_to_map_one_config(struct pinctrl *p, const char *statename,
diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig
index 12ef544b4894..debe1219d76d 100644
--- a/drivers/pinctrl/freescale/Kconfig
+++ b/drivers/pinctrl/freescale/Kconfig
@@ -87,6 +87,13 @@ config PINCTRL_IMX6SX
87 help 87 help
88 Say Y here to enable the imx6sx pinctrl driver 88 Say Y here to enable the imx6sx pinctrl driver
89 89
90config PINCTRL_IMX6UL
91 bool "IMX6UL pinctrl driver"
92 depends on SOC_IMX6UL
93 select PINCTRL_IMX
94 help
95 Say Y here to enable the imx6ul pinctrl driver
96
90config PINCTRL_IMX7D 97config PINCTRL_IMX7D
91 bool "IMX7D pinctrl driver" 98 bool "IMX7D pinctrl driver"
92 depends on SOC_IMX7D 99 depends on SOC_IMX7D
diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile
index 343cb436ab17..d44c9e253f21 100644
--- a/drivers/pinctrl/freescale/Makefile
+++ b/drivers/pinctrl/freescale/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
12obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o 12obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o
13obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o 13obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o
14obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o 14obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o
15obj-$(CONFIG_PINCTRL_IMX6UL) += pinctrl-imx6ul.o
15obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o 16obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o
16obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o 17obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
17obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o 18obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
diff --git a/drivers/pinctrl/freescale/pinctrl-imx6ul.c b/drivers/pinctrl/freescale/pinctrl-imx6ul.c
new file mode 100644
index 000000000000..08e75764e7be
--- /dev/null
+++ b/drivers/pinctrl/freescale/pinctrl-imx6ul.c
@@ -0,0 +1,322 @@
1/*
2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/err.h>
10#include <linux/init.h>
11#include <linux/io.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/of_device.h>
15#include <linux/pinctrl/pinctrl.h>
16
17#include "pinctrl-imx.h"
18
19enum imx6ul_pads {
20 MX6UL_PAD_RESERVE0 = 0,
21 MX6UL_PAD_RESERVE1 = 1,
22 MX6UL_PAD_RESERVE2 = 2,
23 MX6UL_PAD_RESERVE3 = 3,
24 MX6UL_PAD_RESERVE4 = 4,
25 MX6UL_PAD_RESERVE5 = 5,
26 MX6UL_PAD_RESERVE6 = 6,
27 MX6UL_PAD_RESERVE7 = 7,
28 MX6UL_PAD_RESERVE8 = 8,
29 MX6UL_PAD_RESERVE9 = 9,
30 MX6UL_PAD_RESERVE10 = 10,
31 MX6UL_PAD_SNVS_TAMPER4 = 11,
32 MX6UL_PAD_RESERVE12 = 12,
33 MX6UL_PAD_RESERVE13 = 13,
34 MX6UL_PAD_RESERVE14 = 14,
35 MX6UL_PAD_RESERVE15 = 15,
36 MX6UL_PAD_RESERVE16 = 16,
37 MX6UL_PAD_JTAG_MOD = 17,
38 MX6UL_PAD_JTAG_TMS = 18,
39 MX6UL_PAD_JTAG_TDO = 19,
40 MX6UL_PAD_JTAG_TDI = 20,
41 MX6UL_PAD_JTAG_TCK = 21,
42 MX6UL_PAD_JTAG_TRST_B = 22,
43 MX6UL_PAD_GPIO1_IO00 = 23,
44 MX6UL_PAD_GPIO1_IO01 = 24,
45 MX6UL_PAD_GPIO1_IO02 = 25,
46 MX6UL_PAD_GPIO1_IO03 = 26,
47 MX6UL_PAD_GPIO1_IO04 = 27,
48 MX6UL_PAD_GPIO1_IO05 = 28,
49 MX6UL_PAD_GPIO1_IO06 = 29,
50 MX6UL_PAD_GPIO1_IO07 = 30,
51 MX6UL_PAD_GPIO1_IO08 = 31,
52 MX6UL_PAD_GPIO1_IO09 = 32,
53 MX6UL_PAD_UART1_TX_DATA = 33,
54 MX6UL_PAD_UART1_RX_DATA = 34,
55 MX6UL_PAD_UART1_CTS_B = 35,
56 MX6UL_PAD_UART1_RTS_B = 36,
57 MX6UL_PAD_UART2_TX_DATA = 37,
58 MX6UL_PAD_UART2_RX_DATA = 38,
59 MX6UL_PAD_UART2_CTS_B = 39,
60 MX6UL_PAD_UART2_RTS_B = 40,
61 MX6UL_PAD_UART3_TX_DATA = 41,
62 MX6UL_PAD_UART3_RX_DATA = 42,
63 MX6UL_PAD_UART3_CTS_B = 43,
64 MX6UL_PAD_UART3_RTS_B = 44,
65 MX6UL_PAD_UART4_TX_DATA = 45,
66 MX6UL_PAD_UART4_RX_DATA = 46,
67 MX6UL_PAD_UART5_TX_DATA = 47,
68 MX6UL_PAD_UART5_RX_DATA = 48,
69 MX6UL_PAD_ENET1_RX_DATA0 = 49,
70 MX6UL_PAD_ENET1_RX_DATA1 = 50,
71 MX6UL_PAD_ENET1_RX_EN = 51,
72 MX6UL_PAD_ENET1_TX_DATA0 = 52,
73 MX6UL_PAD_ENET1_TX_DATA1 = 53,
74 MX6UL_PAD_ENET1_TX_EN = 54,
75 MX6UL_PAD_ENET1_TX_CLK = 55,
76 MX6UL_PAD_ENET1_RX_ER = 56,
77 MX6UL_PAD_ENET2_RX_DATA0 = 57,
78 MX6UL_PAD_ENET2_RX_DATA1 = 58,
79 MX6UL_PAD_ENET2_RX_EN = 59,
80 MX6UL_PAD_ENET2_TX_DATA0 = 60,
81 MX6UL_PAD_ENET2_TX_DATA1 = 61,
82 MX6UL_PAD_ENET2_TX_EN = 62,
83 MX6UL_PAD_ENET2_TX_CLK = 63,
84 MX6UL_PAD_ENET2_RX_ER = 64,
85 MX6UL_PAD_LCD_CLK = 65,
86 MX6UL_PAD_LCD_ENABLE = 66,
87 MX6UL_PAD_LCD_HSYNC = 67,
88 MX6UL_PAD_LCD_VSYNC = 68,
89 MX6UL_PAD_LCD_RESET = 69,
90 MX6UL_PAD_LCD_DATA00 = 70,
91 MX6UL_PAD_LCD_DATA01 = 71,
92 MX6UL_PAD_LCD_DATA02 = 72,
93 MX6UL_PAD_LCD_DATA03 = 73,
94 MX6UL_PAD_LCD_DATA04 = 74,
95 MX6UL_PAD_LCD_DATA05 = 75,
96 MX6UL_PAD_LCD_DATA06 = 76,
97 MX6UL_PAD_LCD_DATA07 = 77,
98 MX6UL_PAD_LCD_DATA08 = 78,
99 MX6UL_PAD_LCD_DATA09 = 79,
100 MX6UL_PAD_LCD_DATA10 = 80,
101 MX6UL_PAD_LCD_DATA11 = 81,
102 MX6UL_PAD_LCD_DATA12 = 82,
103 MX6UL_PAD_LCD_DATA13 = 83,
104 MX6UL_PAD_LCD_DATA14 = 84,
105 MX6UL_PAD_LCD_DATA15 = 85,
106 MX6UL_PAD_LCD_DATA16 = 86,
107 MX6UL_PAD_LCD_DATA17 = 87,
108 MX6UL_PAD_LCD_DATA18 = 88,
109 MX6UL_PAD_LCD_DATA19 = 89,
110 MX6UL_PAD_LCD_DATA20 = 90,
111 MX6UL_PAD_LCD_DATA21 = 91,
112 MX6UL_PAD_LCD_DATA22 = 92,
113 MX6UL_PAD_LCD_DATA23 = 93,
114 MX6UL_PAD_NAND_RE_B = 94,
115 MX6UL_PAD_NAND_WE_B = 95,
116 MX6UL_PAD_NAND_DATA00 = 96,
117 MX6UL_PAD_NAND_DATA01 = 97,
118 MX6UL_PAD_NAND_DATA02 = 98,
119 MX6UL_PAD_NAND_DATA03 = 99,
120 MX6UL_PAD_NAND_DATA04 = 100,
121 MX6UL_PAD_NAND_DATA05 = 101,
122 MX6UL_PAD_NAND_DATA06 = 102,
123 MX6UL_PAD_NAND_DATA07 = 103,
124 MX6UL_PAD_NAND_ALE = 104,
125 MX6UL_PAD_NAND_WP_B = 105,
126 MX6UL_PAD_NAND_READY_B = 106,
127 MX6UL_PAD_NAND_CE0_B = 107,
128 MX6UL_PAD_NAND_CE1_B = 108,
129 MX6UL_PAD_NAND_CLE = 109,
130 MX6UL_PAD_NAND_DQS = 110,
131 MX6UL_PAD_SD1_CMD = 111,
132 MX6UL_PAD_SD1_CLK = 112,
133 MX6UL_PAD_SD1_DATA0 = 113,
134 MX6UL_PAD_SD1_DATA1 = 114,
135 MX6UL_PAD_SD1_DATA2 = 115,
136 MX6UL_PAD_SD1_DATA3 = 116,
137 MX6UL_PAD_CSI_MCLK = 117,
138 MX6UL_PAD_CSI_PIXCLK = 118,
139 MX6UL_PAD_CSI_VSYNC = 119,
140 MX6UL_PAD_CSI_HSYNC = 120,
141 MX6UL_PAD_CSI_DATA00 = 121,
142 MX6UL_PAD_CSI_DATA01 = 122,
143 MX6UL_PAD_CSI_DATA02 = 123,
144 MX6UL_PAD_CSI_DATA03 = 124,
145 MX6UL_PAD_CSI_DATA04 = 125,
146 MX6UL_PAD_CSI_DATA05 = 126,
147 MX6UL_PAD_CSI_DATA06 = 127,
148 MX6UL_PAD_CSI_DATA07 = 128,
149};
150
151/* Pad names for the pinmux subsystem */
152static const struct pinctrl_pin_desc imx6ul_pinctrl_pads[] = {
153 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE0),
154 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE1),
155 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE2),
156 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE3),
157 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE4),
158 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE5),
159 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE6),
160 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE7),
161 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE8),
162 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE9),
163 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE10),
164 IMX_PINCTRL_PIN(MX6UL_PAD_SNVS_TAMPER4),
165 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE12),
166 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE13),
167 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE14),
168 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE15),
169 IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE16),
170 IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_MOD),
171 IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TMS),
172 IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TDO),
173 IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TDI),
174 IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TCK),
175 IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TRST_B),
176 IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO00),
177 IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO01),
178 IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO02),
179 IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO03),
180 IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO04),
181 IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO05),
182 IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO06),
183 IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO07),
184 IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO08),
185 IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO09),
186 IMX_PINCTRL_PIN(MX6UL_PAD_UART1_TX_DATA),
187 IMX_PINCTRL_PIN(MX6UL_PAD_UART1_RX_DATA),
188 IMX_PINCTRL_PIN(MX6UL_PAD_UART1_CTS_B),
189 IMX_PINCTRL_PIN(MX6UL_PAD_UART1_RTS_B),
190 IMX_PINCTRL_PIN(MX6UL_PAD_UART2_TX_DATA),
191 IMX_PINCTRL_PIN(MX6UL_PAD_UART2_RX_DATA),
192 IMX_PINCTRL_PIN(MX6UL_PAD_UART2_CTS_B),
193 IMX_PINCTRL_PIN(MX6UL_PAD_UART2_RTS_B),
194 IMX_PINCTRL_PIN(MX6UL_PAD_UART3_TX_DATA),
195 IMX_PINCTRL_PIN(MX6UL_PAD_UART3_RX_DATA),
196 IMX_PINCTRL_PIN(MX6UL_PAD_UART3_CTS_B),
197 IMX_PINCTRL_PIN(MX6UL_PAD_UART3_RTS_B),
198 IMX_PINCTRL_PIN(MX6UL_PAD_UART4_TX_DATA),
199 IMX_PINCTRL_PIN(MX6UL_PAD_UART4_RX_DATA),
200 IMX_PINCTRL_PIN(MX6UL_PAD_UART5_TX_DATA),
201 IMX_PINCTRL_PIN(MX6UL_PAD_UART5_RX_DATA),
202 IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_DATA0),
203 IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_DATA1),
204 IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_EN),
205 IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_DATA0),
206 IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_DATA1),
207 IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_EN),
208 IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_CLK),
209 IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_ER),
210 IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_DATA0),
211 IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_DATA1),
212 IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_EN),
213 IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_DATA0),
214 IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_DATA1),
215 IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_EN),
216 IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_CLK),
217 IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_ER),
218 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_CLK),
219 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_ENABLE),
220 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_HSYNC),
221 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_VSYNC),
222 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_RESET),
223 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA00),
224 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA01),
225 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA02),
226 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA03),
227 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA04),
228 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA05),
229 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA06),
230 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA07),
231 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA08),
232 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA09),
233 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA10),
234 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA11),
235 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA12),
236 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA13),
237 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA14),
238 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA15),
239 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA16),
240 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA17),
241 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA18),
242 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA19),
243 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA20),
244 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA21),
245 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA22),
246 IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA23),
247 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_RE_B),
248 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_WE_B),
249 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA00),
250 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA01),
251 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA02),
252 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA03),
253 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA04),
254 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA05),
255 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA06),
256 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA07),
257 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_ALE),
258 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_WP_B),
259 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_READY_B),
260 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_CE0_B),
261 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_CE1_B),
262 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_CLE),
263 IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DQS),
264 IMX_PINCTRL_PIN(MX6UL_PAD_SD1_CMD),
265 IMX_PINCTRL_PIN(MX6UL_PAD_SD1_CLK),
266 IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA0),
267 IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA1),
268 IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA2),
269 IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA3),
270 IMX_PINCTRL_PIN(MX6UL_PAD_CSI_MCLK),
271 IMX_PINCTRL_PIN(MX6UL_PAD_CSI_PIXCLK),
272 IMX_PINCTRL_PIN(MX6UL_PAD_CSI_VSYNC),
273 IMX_PINCTRL_PIN(MX6UL_PAD_CSI_HSYNC),
274 IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA00),
275 IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA01),
276 IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA02),
277 IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA03),
278 IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA04),
279 IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA05),
280 IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA06),
281 IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA07),
282};
283
284static struct imx_pinctrl_soc_info imx6ul_pinctrl_info = {
285 .pins = imx6ul_pinctrl_pads,
286 .npins = ARRAY_SIZE(imx6ul_pinctrl_pads),
287};
288
289static struct of_device_id imx6ul_pinctrl_of_match[] = {
290 { .compatible = "fsl,imx6ul-iomuxc", },
291 { /* sentinel */ }
292};
293
294static int imx6ul_pinctrl_probe(struct platform_device *pdev)
295{
296 return imx_pinctrl_probe(pdev, &imx6ul_pinctrl_info);
297}
298
299static struct platform_driver imx6ul_pinctrl_driver = {
300 .driver = {
301 .name = "imx6ul-pinctrl",
302 .of_match_table = of_match_ptr(imx6ul_pinctrl_of_match),
303 },
304 .probe = imx6ul_pinctrl_probe,
305 .remove = imx_pinctrl_remove,
306};
307
308static int __init imx6ul_pinctrl_init(void)
309{
310 return platform_driver_register(&imx6ul_pinctrl_driver);
311}
312arch_initcall(imx6ul_pinctrl_init);
313
314static void __exit imx6ul_pinctrl_exit(void)
315{
316 platform_driver_unregister(&imx6ul_pinctrl_driver);
317}
318module_exit(imx6ul_pinctrl_exit);
319
320MODULE_AUTHOR("Anson Huang <Anson.Huang@freescale.com>");
321MODULE_DESCRIPTION("Freescale imx6ul pinctrl driver");
322MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c
index 2062c224e32f..dac4865f3203 100644
--- a/drivers/pinctrl/intel/pinctrl-baytrail.c
+++ b/drivers/pinctrl/intel/pinctrl-baytrail.c
@@ -12,11 +12,6 @@
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details. 14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 */ 15 */
21 16
22#include <linux/kernel.h> 17#include <linux/kernel.h>
@@ -146,7 +141,7 @@ struct byt_gpio_pin_context {
146struct byt_gpio { 141struct byt_gpio {
147 struct gpio_chip chip; 142 struct gpio_chip chip;
148 struct platform_device *pdev; 143 struct platform_device *pdev;
149 spinlock_t lock; 144 raw_spinlock_t lock;
150 void __iomem *reg_base; 145 void __iomem *reg_base;
151 struct pinctrl_gpio_range *range; 146 struct pinctrl_gpio_range *range;
152 struct byt_gpio_pin_context *saved_context; 147 struct byt_gpio_pin_context *saved_context;
@@ -174,11 +169,11 @@ static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned offset)
174 unsigned long flags; 169 unsigned long flags;
175 u32 value; 170 u32 value;
176 171
177 spin_lock_irqsave(&vg->lock, flags); 172 raw_spin_lock_irqsave(&vg->lock, flags);
178 value = readl(reg); 173 value = readl(reg);
179 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL); 174 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
180 writel(value, reg); 175 writel(value, reg);
181 spin_unlock_irqrestore(&vg->lock, flags); 176 raw_spin_unlock_irqrestore(&vg->lock, flags);
182} 177}
183 178
184static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned offset) 179static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned offset)
@@ -201,6 +196,9 @@ static int byt_gpio_request(struct gpio_chip *chip, unsigned offset)
201 struct byt_gpio *vg = to_byt_gpio(chip); 196 struct byt_gpio *vg = to_byt_gpio(chip);
202 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_CONF0_REG); 197 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_CONF0_REG);
203 u32 value, gpio_mux; 198 u32 value, gpio_mux;
199 unsigned long flags;
200
201 raw_spin_lock_irqsave(&vg->lock, flags);
204 202
205 /* 203 /*
206 * In most cases, func pin mux 000 means GPIO function. 204 * In most cases, func pin mux 000 means GPIO function.
@@ -214,18 +212,16 @@ static int byt_gpio_request(struct gpio_chip *chip, unsigned offset)
214 value = readl(reg) & BYT_PIN_MUX; 212 value = readl(reg) & BYT_PIN_MUX;
215 gpio_mux = byt_get_gpio_mux(vg, offset); 213 gpio_mux = byt_get_gpio_mux(vg, offset);
216 if (WARN_ON(gpio_mux != value)) { 214 if (WARN_ON(gpio_mux != value)) {
217 unsigned long flags;
218
219 spin_lock_irqsave(&vg->lock, flags);
220 value = readl(reg) & ~BYT_PIN_MUX; 215 value = readl(reg) & ~BYT_PIN_MUX;
221 value |= gpio_mux; 216 value |= gpio_mux;
222 writel(value, reg); 217 writel(value, reg);
223 spin_unlock_irqrestore(&vg->lock, flags);
224 218
225 dev_warn(&vg->pdev->dev, 219 dev_warn(&vg->pdev->dev,
226 "pin %u forcibly re-configured as GPIO\n", offset); 220 "pin %u forcibly re-configured as GPIO\n", offset);
227 } 221 }
228 222
223 raw_spin_unlock_irqrestore(&vg->lock, flags);
224
229 pm_runtime_get(&vg->pdev->dev); 225 pm_runtime_get(&vg->pdev->dev);
230 226
231 return 0; 227 return 0;
@@ -250,7 +246,7 @@ static int byt_irq_type(struct irq_data *d, unsigned type)
250 if (offset >= vg->chip.ngpio) 246 if (offset >= vg->chip.ngpio)
251 return -EINVAL; 247 return -EINVAL;
252 248
253 spin_lock_irqsave(&vg->lock, flags); 249 raw_spin_lock_irqsave(&vg->lock, flags);
254 value = readl(reg); 250 value = readl(reg);
255 251
256 WARN(value & BYT_DIRECT_IRQ_EN, 252 WARN(value & BYT_DIRECT_IRQ_EN,
@@ -265,11 +261,11 @@ static int byt_irq_type(struct irq_data *d, unsigned type)
265 writel(value, reg); 261 writel(value, reg);
266 262
267 if (type & IRQ_TYPE_EDGE_BOTH) 263 if (type & IRQ_TYPE_EDGE_BOTH)
268 __irq_set_handler_locked(d->irq, handle_edge_irq); 264 irq_set_handler_locked(d, handle_edge_irq);
269 else if (type & IRQ_TYPE_LEVEL_MASK) 265 else if (type & IRQ_TYPE_LEVEL_MASK)
270 __irq_set_handler_locked(d->irq, handle_level_irq); 266 irq_set_handler_locked(d, handle_level_irq);
271 267
272 spin_unlock_irqrestore(&vg->lock, flags); 268 raw_spin_unlock_irqrestore(&vg->lock, flags);
273 269
274 return 0; 270 return 0;
275} 271}
@@ -277,7 +273,15 @@ static int byt_irq_type(struct irq_data *d, unsigned type)
277static int byt_gpio_get(struct gpio_chip *chip, unsigned offset) 273static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
278{ 274{
279 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG); 275 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
280 return readl(reg) & BYT_LEVEL; 276 struct byt_gpio *vg = to_byt_gpio(chip);
277 unsigned long flags;
278 u32 val;
279
280 raw_spin_lock_irqsave(&vg->lock, flags);
281 val = readl(reg);
282 raw_spin_unlock_irqrestore(&vg->lock, flags);
283
284 return val & BYT_LEVEL;
281} 285}
282 286
283static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 287static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
@@ -287,7 +291,7 @@ static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
287 unsigned long flags; 291 unsigned long flags;
288 u32 old_val; 292 u32 old_val;
289 293
290 spin_lock_irqsave(&vg->lock, flags); 294 raw_spin_lock_irqsave(&vg->lock, flags);
291 295
292 old_val = readl(reg); 296 old_val = readl(reg);
293 297
@@ -296,7 +300,7 @@ static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
296 else 300 else
297 writel(old_val & ~BYT_LEVEL, reg); 301 writel(old_val & ~BYT_LEVEL, reg);
298 302
299 spin_unlock_irqrestore(&vg->lock, flags); 303 raw_spin_unlock_irqrestore(&vg->lock, flags);
300} 304}
301 305
302static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 306static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
@@ -306,13 +310,13 @@ static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
306 unsigned long flags; 310 unsigned long flags;
307 u32 value; 311 u32 value;
308 312
309 spin_lock_irqsave(&vg->lock, flags); 313 raw_spin_lock_irqsave(&vg->lock, flags);
310 314
311 value = readl(reg) | BYT_DIR_MASK; 315 value = readl(reg) | BYT_DIR_MASK;
312 value &= ~BYT_INPUT_EN; /* active low */ 316 value &= ~BYT_INPUT_EN; /* active low */
313 writel(value, reg); 317 writel(value, reg);
314 318
315 spin_unlock_irqrestore(&vg->lock, flags); 319 raw_spin_unlock_irqrestore(&vg->lock, flags);
316 320
317 return 0; 321 return 0;
318} 322}
@@ -326,7 +330,7 @@ static int byt_gpio_direction_output(struct gpio_chip *chip,
326 unsigned long flags; 330 unsigned long flags;
327 u32 reg_val; 331 u32 reg_val;
328 332
329 spin_lock_irqsave(&vg->lock, flags); 333 raw_spin_lock_irqsave(&vg->lock, flags);
330 334
331 /* 335 /*
332 * Before making any direction modifications, do a check if gpio 336 * Before making any direction modifications, do a check if gpio
@@ -345,7 +349,7 @@ static int byt_gpio_direction_output(struct gpio_chip *chip,
345 else 349 else
346 writel(reg_val & ~BYT_LEVEL, reg); 350 writel(reg_val & ~BYT_LEVEL, reg);
347 351
348 spin_unlock_irqrestore(&vg->lock, flags); 352 raw_spin_unlock_irqrestore(&vg->lock, flags);
349 353
350 return 0; 354 return 0;
351} 355}
@@ -354,18 +358,19 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
354{ 358{
355 struct byt_gpio *vg = to_byt_gpio(chip); 359 struct byt_gpio *vg = to_byt_gpio(chip);
356 int i; 360 int i;
357 unsigned long flags;
358 u32 conf0, val, offs; 361 u32 conf0, val, offs;
359 362
360 spin_lock_irqsave(&vg->lock, flags);
361
362 for (i = 0; i < vg->chip.ngpio; i++) { 363 for (i = 0; i < vg->chip.ngpio; i++) {
363 const char *pull_str = NULL; 364 const char *pull_str = NULL;
364 const char *pull = NULL; 365 const char *pull = NULL;
366 unsigned long flags;
365 const char *label; 367 const char *label;
366 offs = vg->range->pins[i] * 16; 368 offs = vg->range->pins[i] * 16;
369
370 raw_spin_lock_irqsave(&vg->lock, flags);
367 conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG); 371 conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG);
368 val = readl(vg->reg_base + offs + BYT_VAL_REG); 372 val = readl(vg->reg_base + offs + BYT_VAL_REG);
373 raw_spin_unlock_irqrestore(&vg->lock, flags);
369 374
370 label = gpiochip_is_requested(chip, i); 375 label = gpiochip_is_requested(chip, i);
371 if (!label) 376 if (!label)
@@ -418,7 +423,6 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
418 423
419 seq_puts(s, "\n"); 424 seq_puts(s, "\n");
420 } 425 }
421 spin_unlock_irqrestore(&vg->lock, flags);
422} 426}
423 427
424static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc) 428static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
@@ -450,8 +454,10 @@ static void byt_irq_ack(struct irq_data *d)
450 unsigned offset = irqd_to_hwirq(d); 454 unsigned offset = irqd_to_hwirq(d);
451 void __iomem *reg; 455 void __iomem *reg;
452 456
457 raw_spin_lock(&vg->lock);
453 reg = byt_gpio_reg(&vg->chip, offset, BYT_INT_STAT_REG); 458 reg = byt_gpio_reg(&vg->chip, offset, BYT_INT_STAT_REG);
454 writel(BIT(offset % 32), reg); 459 writel(BIT(offset % 32), reg);
460 raw_spin_unlock(&vg->lock);
455} 461}
456 462
457static void byt_irq_unmask(struct irq_data *d) 463static void byt_irq_unmask(struct irq_data *d)
@@ -463,9 +469,9 @@ static void byt_irq_unmask(struct irq_data *d)
463 void __iomem *reg; 469 void __iomem *reg;
464 u32 value; 470 u32 value;
465 471
466 spin_lock_irqsave(&vg->lock, flags);
467
468 reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG); 472 reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
473
474 raw_spin_lock_irqsave(&vg->lock, flags);
469 value = readl(reg); 475 value = readl(reg);
470 476
471 switch (irqd_get_trigger_type(d)) { 477 switch (irqd_get_trigger_type(d)) {
@@ -486,7 +492,7 @@ static void byt_irq_unmask(struct irq_data *d)
486 492
487 writel(value, reg); 493 writel(value, reg);
488 494
489 spin_unlock_irqrestore(&vg->lock, flags); 495 raw_spin_unlock_irqrestore(&vg->lock, flags);
490} 496}
491 497
492static void byt_irq_mask(struct irq_data *d) 498static void byt_irq_mask(struct irq_data *d)
@@ -578,7 +584,7 @@ static int byt_gpio_probe(struct platform_device *pdev)
578 if (IS_ERR(vg->reg_base)) 584 if (IS_ERR(vg->reg_base))
579 return PTR_ERR(vg->reg_base); 585 return PTR_ERR(vg->reg_base);
580 586
581 spin_lock_init(&vg->lock); 587 raw_spin_lock_init(&vg->lock);
582 588
583 gc = &vg->chip; 589 gc = &vg->chip;
584 gc->label = dev_name(&pdev->dev); 590 gc->label = dev_name(&pdev->dev);
diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c
index 3f737daa3fd2..2d5d3ddc36e5 100644
--- a/drivers/pinctrl/intel/pinctrl-cherryview.c
+++ b/drivers/pinctrl/intel/pinctrl-cherryview.c
@@ -174,7 +174,7 @@ struct chv_pinctrl {
174 struct pinctrl_dev *pctldev; 174 struct pinctrl_dev *pctldev;
175 struct gpio_chip chip; 175 struct gpio_chip chip;
176 void __iomem *regs; 176 void __iomem *regs;
177 spinlock_t lock; 177 raw_spinlock_t lock;
178 unsigned intr_lines[16]; 178 unsigned intr_lines[16];
179 const struct chv_community *community; 179 const struct chv_community *community;
180 u32 saved_intmask; 180 u32 saved_intmask;
@@ -720,13 +720,13 @@ static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
720 u32 ctrl0, ctrl1; 720 u32 ctrl0, ctrl1;
721 bool locked; 721 bool locked;
722 722
723 spin_lock_irqsave(&pctrl->lock, flags); 723 raw_spin_lock_irqsave(&pctrl->lock, flags);
724 724
725 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); 725 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
726 ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1)); 726 ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1));
727 locked = chv_pad_locked(pctrl, offset); 727 locked = chv_pad_locked(pctrl, offset);
728 728
729 spin_unlock_irqrestore(&pctrl->lock, flags); 729 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
730 730
731 if (ctrl0 & CHV_PADCTRL0_GPIOEN) { 731 if (ctrl0 & CHV_PADCTRL0_GPIOEN) {
732 seq_puts(s, "GPIO "); 732 seq_puts(s, "GPIO ");
@@ -789,14 +789,14 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
789 789
790 grp = &pctrl->community->groups[group]; 790 grp = &pctrl->community->groups[group];
791 791
792 spin_lock_irqsave(&pctrl->lock, flags); 792 raw_spin_lock_irqsave(&pctrl->lock, flags);
793 793
794 /* Check first that the pad is not locked */ 794 /* Check first that the pad is not locked */
795 for (i = 0; i < grp->npins; i++) { 795 for (i = 0; i < grp->npins; i++) {
796 if (chv_pad_locked(pctrl, grp->pins[i])) { 796 if (chv_pad_locked(pctrl, grp->pins[i])) {
797 dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n", 797 dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n",
798 grp->pins[i]); 798 grp->pins[i]);
799 spin_unlock_irqrestore(&pctrl->lock, flags); 799 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
800 return -EBUSY; 800 return -EBUSY;
801 } 801 }
802 } 802 }
@@ -839,7 +839,7 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
839 pin, altfunc->mode, altfunc->invert_oe ? "" : "not "); 839 pin, altfunc->mode, altfunc->invert_oe ? "" : "not ");
840 } 840 }
841 841
842 spin_unlock_irqrestore(&pctrl->lock, flags); 842 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
843 843
844 return 0; 844 return 0;
845} 845}
@@ -853,13 +853,13 @@ static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
853 void __iomem *reg; 853 void __iomem *reg;
854 u32 value; 854 u32 value;
855 855
856 spin_lock_irqsave(&pctrl->lock, flags); 856 raw_spin_lock_irqsave(&pctrl->lock, flags);
857 857
858 if (chv_pad_locked(pctrl, offset)) { 858 if (chv_pad_locked(pctrl, offset)) {
859 value = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); 859 value = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
860 if (!(value & CHV_PADCTRL0_GPIOEN)) { 860 if (!(value & CHV_PADCTRL0_GPIOEN)) {
861 /* Locked so cannot enable */ 861 /* Locked so cannot enable */
862 spin_unlock_irqrestore(&pctrl->lock, flags); 862 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
863 return -EBUSY; 863 return -EBUSY;
864 } 864 }
865 } else { 865 } else {
@@ -899,7 +899,7 @@ static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
899 chv_writel(value, reg); 899 chv_writel(value, reg);
900 } 900 }
901 901
902 spin_unlock_irqrestore(&pctrl->lock, flags); 902 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
903 903
904 return 0; 904 return 0;
905} 905}
@@ -913,13 +913,13 @@ static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
913 void __iomem *reg; 913 void __iomem *reg;
914 u32 value; 914 u32 value;
915 915
916 spin_lock_irqsave(&pctrl->lock, flags); 916 raw_spin_lock_irqsave(&pctrl->lock, flags);
917 917
918 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); 918 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
919 value = readl(reg) & ~CHV_PADCTRL0_GPIOEN; 919 value = readl(reg) & ~CHV_PADCTRL0_GPIOEN;
920 chv_writel(value, reg); 920 chv_writel(value, reg);
921 921
922 spin_unlock_irqrestore(&pctrl->lock, flags); 922 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
923} 923}
924 924
925static int chv_gpio_set_direction(struct pinctrl_dev *pctldev, 925static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
@@ -931,7 +931,7 @@ static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
931 unsigned long flags; 931 unsigned long flags;
932 u32 ctrl0; 932 u32 ctrl0;
933 933
934 spin_lock_irqsave(&pctrl->lock, flags); 934 raw_spin_lock_irqsave(&pctrl->lock, flags);
935 935
936 ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK; 936 ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK;
937 if (input) 937 if (input)
@@ -940,7 +940,7 @@ static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
940 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT; 940 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT;
941 chv_writel(ctrl0, reg); 941 chv_writel(ctrl0, reg);
942 942
943 spin_unlock_irqrestore(&pctrl->lock, flags); 943 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
944 944
945 return 0; 945 return 0;
946} 946}
@@ -965,10 +965,10 @@ static int chv_config_get(struct pinctrl_dev *pctldev, unsigned pin,
965 u16 arg = 0; 965 u16 arg = 0;
966 u32 term; 966 u32 term;
967 967
968 spin_lock_irqsave(&pctrl->lock, flags); 968 raw_spin_lock_irqsave(&pctrl->lock, flags);
969 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 969 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
970 ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1)); 970 ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
971 spin_unlock_irqrestore(&pctrl->lock, flags); 971 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
972 972
973 term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT; 973 term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT;
974 974
@@ -1042,7 +1042,7 @@ static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin,
1042 unsigned long flags; 1042 unsigned long flags;
1043 u32 ctrl0, pull; 1043 u32 ctrl0, pull;
1044 1044
1045 spin_lock_irqsave(&pctrl->lock, flags); 1045 raw_spin_lock_irqsave(&pctrl->lock, flags);
1046 ctrl0 = readl(reg); 1046 ctrl0 = readl(reg);
1047 1047
1048 switch (param) { 1048 switch (param) {
@@ -1065,7 +1065,7 @@ static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin,
1065 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; 1065 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1066 break; 1066 break;
1067 default: 1067 default:
1068 spin_unlock_irqrestore(&pctrl->lock, flags); 1068 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1069 return -EINVAL; 1069 return -EINVAL;
1070 } 1070 }
1071 1071
@@ -1083,7 +1083,7 @@ static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin,
1083 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; 1083 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1084 break; 1084 break;
1085 default: 1085 default:
1086 spin_unlock_irqrestore(&pctrl->lock, flags); 1086 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1087 return -EINVAL; 1087 return -EINVAL;
1088 } 1088 }
1089 1089
@@ -1091,12 +1091,12 @@ static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin,
1091 break; 1091 break;
1092 1092
1093 default: 1093 default:
1094 spin_unlock_irqrestore(&pctrl->lock, flags); 1094 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1095 return -EINVAL; 1095 return -EINVAL;
1096 } 1096 }
1097 1097
1098 chv_writel(ctrl0, reg); 1098 chv_writel(ctrl0, reg);
1099 spin_unlock_irqrestore(&pctrl->lock, flags); 1099 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1100 1100
1101 return 0; 1101 return 0;
1102} 1102}
@@ -1169,9 +1169,12 @@ static int chv_gpio_get(struct gpio_chip *chip, unsigned offset)
1169{ 1169{
1170 struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(chip); 1170 struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(chip);
1171 int pin = chv_gpio_offset_to_pin(pctrl, offset); 1171 int pin = chv_gpio_offset_to_pin(pctrl, offset);
1172 unsigned long flags;
1172 u32 ctrl0, cfg; 1173 u32 ctrl0, cfg;
1173 1174
1175 raw_spin_lock_irqsave(&pctrl->lock, flags);
1174 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1176 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1177 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1175 1178
1176 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 1179 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1177 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 1180 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
@@ -1189,7 +1192,7 @@ static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1189 void __iomem *reg; 1192 void __iomem *reg;
1190 u32 ctrl0; 1193 u32 ctrl0;
1191 1194
1192 spin_lock_irqsave(&pctrl->lock, flags); 1195 raw_spin_lock_irqsave(&pctrl->lock, flags);
1193 1196
1194 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); 1197 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
1195 ctrl0 = readl(reg); 1198 ctrl0 = readl(reg);
@@ -1201,7 +1204,7 @@ static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1201 1204
1202 chv_writel(ctrl0, reg); 1205 chv_writel(ctrl0, reg);
1203 1206
1204 spin_unlock_irqrestore(&pctrl->lock, flags); 1207 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1205} 1208}
1206 1209
1207static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 1210static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
@@ -1209,8 +1212,11 @@ static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1209 struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(chip); 1212 struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(chip);
1210 unsigned pin = chv_gpio_offset_to_pin(pctrl, offset); 1213 unsigned pin = chv_gpio_offset_to_pin(pctrl, offset);
1211 u32 ctrl0, direction; 1214 u32 ctrl0, direction;
1215 unsigned long flags;
1212 1216
1217 raw_spin_lock_irqsave(&pctrl->lock, flags);
1213 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1218 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1219 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1214 1220
1215 direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 1221 direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1216 direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 1222 direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
@@ -1248,14 +1254,14 @@ static void chv_gpio_irq_ack(struct irq_data *d)
1248 int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d)); 1254 int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d));
1249 u32 intr_line; 1255 u32 intr_line;
1250 1256
1251 spin_lock(&pctrl->lock); 1257 raw_spin_lock(&pctrl->lock);
1252 1258
1253 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1259 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1254 intr_line &= CHV_PADCTRL0_INTSEL_MASK; 1260 intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1255 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; 1261 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1256 chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT); 1262 chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT);
1257 1263
1258 spin_unlock(&pctrl->lock); 1264 raw_spin_unlock(&pctrl->lock);
1259} 1265}
1260 1266
1261static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask) 1267static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
@@ -1266,7 +1272,7 @@ static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
1266 u32 value, intr_line; 1272 u32 value, intr_line;
1267 unsigned long flags; 1273 unsigned long flags;
1268 1274
1269 spin_lock_irqsave(&pctrl->lock, flags); 1275 raw_spin_lock_irqsave(&pctrl->lock, flags);
1270 1276
1271 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1277 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1272 intr_line &= CHV_PADCTRL0_INTSEL_MASK; 1278 intr_line &= CHV_PADCTRL0_INTSEL_MASK;
@@ -1279,7 +1285,7 @@ static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
1279 value |= BIT(intr_line); 1285 value |= BIT(intr_line);
1280 chv_writel(value, pctrl->regs + CHV_INTMASK); 1286 chv_writel(value, pctrl->regs + CHV_INTMASK);
1281 1287
1282 spin_unlock_irqrestore(&pctrl->lock, flags); 1288 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1283} 1289}
1284 1290
1285static void chv_gpio_irq_mask(struct irq_data *d) 1291static void chv_gpio_irq_mask(struct irq_data *d)
@@ -1313,6 +1319,7 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
1313 unsigned long flags; 1319 unsigned long flags;
1314 u32 intsel, value; 1320 u32 intsel, value;
1315 1321
1322 raw_spin_lock_irqsave(&pctrl->lock, flags);
1316 intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); 1323 intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1317 intsel &= CHV_PADCTRL0_INTSEL_MASK; 1324 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1318 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; 1325 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
@@ -1323,12 +1330,11 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
1323 else 1330 else
1324 handler = handle_edge_irq; 1331 handler = handle_edge_irq;
1325 1332
1326 spin_lock_irqsave(&pctrl->lock, flags);
1327 if (!pctrl->intr_lines[intsel]) { 1333 if (!pctrl->intr_lines[intsel]) {
1328 __irq_set_handler_locked(d->irq, handler); 1334 irq_set_handler_locked(d, handler);
1329 pctrl->intr_lines[intsel] = offset; 1335 pctrl->intr_lines[intsel] = offset;
1330 } 1336 }
1331 spin_unlock_irqrestore(&pctrl->lock, flags); 1337 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1332 } 1338 }
1333 1339
1334 chv_gpio_irq_unmask(d); 1340 chv_gpio_irq_unmask(d);
@@ -1344,7 +1350,7 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned type)
1344 unsigned long flags; 1350 unsigned long flags;
1345 u32 value; 1351 u32 value;
1346 1352
1347 spin_lock_irqsave(&pctrl->lock, flags); 1353 raw_spin_lock_irqsave(&pctrl->lock, flags);
1348 1354
1349 /* 1355 /*
1350 * Pins which can be used as shared interrupt are configured in 1356 * Pins which can be used as shared interrupt are configured in
@@ -1389,11 +1395,11 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned type)
1389 pctrl->intr_lines[value] = offset; 1395 pctrl->intr_lines[value] = offset;
1390 1396
1391 if (type & IRQ_TYPE_EDGE_BOTH) 1397 if (type & IRQ_TYPE_EDGE_BOTH)
1392 __irq_set_handler_locked(d->irq, handle_edge_irq); 1398 irq_set_handler_locked(d, handle_edge_irq);
1393 else if (type & IRQ_TYPE_LEVEL_MASK) 1399 else if (type & IRQ_TYPE_LEVEL_MASK)
1394 __irq_set_handler_locked(d->irq, handle_level_irq); 1400 irq_set_handler_locked(d, handle_level_irq);
1395 1401
1396 spin_unlock_irqrestore(&pctrl->lock, flags); 1402 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1397 1403
1398 return 0; 1404 return 0;
1399} 1405}
@@ -1412,7 +1418,7 @@ static void chv_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
1412{ 1418{
1413 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 1419 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1414 struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(gc); 1420 struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(gc);
1415 struct irq_chip *chip = irq_get_chip(irq); 1421 struct irq_chip *chip = irq_desc_get_chip(desc);
1416 unsigned long pending; 1422 unsigned long pending;
1417 u32 intr_line; 1423 u32 intr_line;
1418 1424
@@ -1505,7 +1511,7 @@ static int chv_pinctrl_probe(struct platform_device *pdev)
1505 if (i == ARRAY_SIZE(chv_communities)) 1511 if (i == ARRAY_SIZE(chv_communities))
1506 return -ENODEV; 1512 return -ENODEV;
1507 1513
1508 spin_lock_init(&pctrl->lock); 1514 raw_spin_lock_init(&pctrl->lock);
1509 pctrl->dev = &pdev->dev; 1515 pctrl->dev = &pdev->dev;
1510 1516
1511#ifdef CONFIG_PM_SLEEP 1517#ifdef CONFIG_PM_SLEEP
diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
index f9ee0d68b288..bb377c110541 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.c
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -758,9 +758,9 @@ static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
758 writel(value, reg); 758 writel(value, reg);
759 759
760 if (type & IRQ_TYPE_EDGE_BOTH) 760 if (type & IRQ_TYPE_EDGE_BOTH)
761 __irq_set_handler_locked(d->irq, handle_edge_irq); 761 irq_set_handler_locked(d, handle_edge_irq);
762 else if (type & IRQ_TYPE_LEVEL_MASK) 762 else if (type & IRQ_TYPE_LEVEL_MASK)
763 __irq_set_handler_locked(d->irq, handle_level_irq); 763 irq_set_handler_locked(d, handle_level_irq);
764 764
765 spin_unlock_irqrestore(&pctrl->lock, flags); 765 spin_unlock_irqrestore(&pctrl->lock, flags);
766 766
@@ -840,7 +840,7 @@ static void intel_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
840{ 840{
841 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 841 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
842 struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc); 842 struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc);
843 struct irq_chip *chip = irq_get_chip(irq); 843 struct irq_chip *chip = irq_desc_get_chip(desc);
844 int i; 844 int i;
845 845
846 chained_irq_enter(chip, desc); 846 chained_irq_enter(chip, desc);
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8173.c b/drivers/pinctrl/mediatek/pinctrl-mt8173.c
index d0c811d5f07b..ad271840d865 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c
@@ -385,6 +385,7 @@ static struct platform_driver mtk_pinctrl_driver = {
385 .driver = { 385 .driver = {
386 .name = "mediatek-mt8173-pinctrl", 386 .name = "mediatek-mt8173-pinctrl",
387 .of_match_table = mt8173_pctrl_match, 387 .of_match_table = mt8173_pctrl_match,
388 .pm = &mtk_eint_pm_ops,
388 }, 389 },
389}; 390};
390 391
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index ad1ea1695b4a..7726c6caaf83 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -33,6 +33,7 @@
33#include <linux/mfd/syscon.h> 33#include <linux/mfd/syscon.h>
34#include <linux/delay.h> 34#include <linux/delay.h>
35#include <linux/interrupt.h> 35#include <linux/interrupt.h>
36#include <linux/pm.h>
36#include <dt-bindings/pinctrl/mt65xx.h> 37#include <dt-bindings/pinctrl/mt65xx.h>
37 38
38#include "../core.h" 39#include "../core.h"
@@ -702,7 +703,7 @@ static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
702 703
703 ret = mtk_pctrl_is_function_valid(pctl, g->pin, function); 704 ret = mtk_pctrl_is_function_valid(pctl, g->pin, function);
704 if (!ret) { 705 if (!ret) {
705 dev_err(pctl->dev, "invaild function %d on group %d .\n", 706 dev_err(pctl->dev, "invalid function %d on group %d .\n",
706 function, group); 707 function, group);
707 return -EINVAL; 708 return -EINVAL;
708 } 709 }
@@ -1062,6 +1063,77 @@ static int mtk_eint_set_type(struct irq_data *d,
1062 return 0; 1063 return 0;
1063} 1064}
1064 1065
1066static int mtk_eint_irq_set_wake(struct irq_data *d, unsigned int on)
1067{
1068 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1069 int shift = d->hwirq & 0x1f;
1070 int reg = d->hwirq >> 5;
1071
1072 if (on)
1073 pctl->wake_mask[reg] |= BIT(shift);
1074 else
1075 pctl->wake_mask[reg] &= ~BIT(shift);
1076
1077 return 0;
1078}
1079
1080static void mtk_eint_chip_write_mask(const struct mtk_eint_offsets *chip,
1081 void __iomem *eint_reg_base, u32 *buf)
1082{
1083 int port;
1084 void __iomem *reg;
1085
1086 for (port = 0; port < chip->ports; port++) {
1087 reg = eint_reg_base + (port << 2);
1088 writel_relaxed(~buf[port], reg + chip->mask_set);
1089 writel_relaxed(buf[port], reg + chip->mask_clr);
1090 }
1091}
1092
1093static void mtk_eint_chip_read_mask(const struct mtk_eint_offsets *chip,
1094 void __iomem *eint_reg_base, u32 *buf)
1095{
1096 int port;
1097 void __iomem *reg;
1098
1099 for (port = 0; port < chip->ports; port++) {
1100 reg = eint_reg_base + chip->mask + (port << 2);
1101 buf[port] = ~readl_relaxed(reg);
1102 /* Mask is 0 when irq is enabled, and 1 when disabled. */
1103 }
1104}
1105
1106static int mtk_eint_suspend(struct device *device)
1107{
1108 void __iomem *reg;
1109 struct mtk_pinctrl *pctl = dev_get_drvdata(device);
1110 const struct mtk_eint_offsets *eint_offsets =
1111 &pctl->devdata->eint_offsets;
1112
1113 reg = pctl->eint_reg_base;
1114 mtk_eint_chip_read_mask(eint_offsets, reg, pctl->cur_mask);
1115 mtk_eint_chip_write_mask(eint_offsets, reg, pctl->wake_mask);
1116
1117 return 0;
1118}
1119
1120static int mtk_eint_resume(struct device *device)
1121{
1122 struct mtk_pinctrl *pctl = dev_get_drvdata(device);
1123 const struct mtk_eint_offsets *eint_offsets =
1124 &pctl->devdata->eint_offsets;
1125
1126 mtk_eint_chip_write_mask(eint_offsets,
1127 pctl->eint_reg_base, pctl->cur_mask);
1128
1129 return 0;
1130}
1131
1132const struct dev_pm_ops mtk_eint_pm_ops = {
1133 .suspend = mtk_eint_suspend,
1134 .resume = mtk_eint_resume,
1135};
1136
1065static void mtk_eint_ack(struct irq_data *d) 1137static void mtk_eint_ack(struct irq_data *d)
1066{ 1138{
1067 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d); 1139 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
@@ -1076,10 +1148,12 @@ static void mtk_eint_ack(struct irq_data *d)
1076 1148
1077static struct irq_chip mtk_pinctrl_irq_chip = { 1149static struct irq_chip mtk_pinctrl_irq_chip = {
1078 .name = "mt-eint", 1150 .name = "mt-eint",
1151 .irq_disable = mtk_eint_mask,
1079 .irq_mask = mtk_eint_mask, 1152 .irq_mask = mtk_eint_mask,
1080 .irq_unmask = mtk_eint_unmask, 1153 .irq_unmask = mtk_eint_unmask,
1081 .irq_ack = mtk_eint_ack, 1154 .irq_ack = mtk_eint_ack,
1082 .irq_set_type = mtk_eint_set_type, 1155 .irq_set_type = mtk_eint_set_type,
1156 .irq_set_wake = mtk_eint_irq_set_wake,
1083 .irq_request_resources = mtk_pinctrl_irq_request_resources, 1157 .irq_request_resources = mtk_pinctrl_irq_request_resources,
1084 .irq_release_resources = mtk_pinctrl_irq_release_resources, 1158 .irq_release_resources = mtk_pinctrl_irq_release_resources,
1085}; 1159};
@@ -1118,8 +1192,8 @@ mtk_eint_debounce_process(struct mtk_pinctrl *pctl, int index)
1118 1192
1119static void mtk_eint_irq_handler(unsigned irq, struct irq_desc *desc) 1193static void mtk_eint_irq_handler(unsigned irq, struct irq_desc *desc)
1120{ 1194{
1121 struct irq_chip *chip = irq_get_chip(irq); 1195 struct irq_chip *chip = irq_desc_get_chip(desc);
1122 struct mtk_pinctrl *pctl = irq_get_handler_data(irq); 1196 struct mtk_pinctrl *pctl = irq_desc_get_handler_data(desc);
1123 unsigned int status, eint_num; 1197 unsigned int status, eint_num;
1124 int offset, index, virq; 1198 int offset, index, virq;
1125 const struct mtk_eint_offsets *eint_offsets = 1199 const struct mtk_eint_offsets *eint_offsets =
@@ -1202,12 +1276,6 @@ static int mtk_pctrl_build_state(struct platform_device *pdev)
1202 return 0; 1276 return 0;
1203} 1277}
1204 1278
1205static struct pinctrl_desc mtk_pctrl_desc = {
1206 .confops = &mtk_pconf_ops,
1207 .pctlops = &mtk_pctrl_ops,
1208 .pmxops = &mtk_pmx_ops,
1209};
1210
1211int mtk_pctrl_init(struct platform_device *pdev, 1279int mtk_pctrl_init(struct platform_device *pdev,
1212 const struct mtk_pinctrl_devdata *data, 1280 const struct mtk_pinctrl_devdata *data,
1213 struct regmap *regmap) 1281 struct regmap *regmap)
@@ -1217,7 +1285,7 @@ int mtk_pctrl_init(struct platform_device *pdev,
1217 struct device_node *np = pdev->dev.of_node, *node; 1285 struct device_node *np = pdev->dev.of_node, *node;
1218 struct property *prop; 1286 struct property *prop;
1219 struct resource *res; 1287 struct resource *res;
1220 int i, ret, irq; 1288 int i, ret, irq, ports_buf;
1221 1289
1222 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); 1290 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1223 if (!pctl) 1291 if (!pctl)
@@ -1265,12 +1333,17 @@ int mtk_pctrl_init(struct platform_device *pdev,
1265 1333
1266 for (i = 0; i < pctl->devdata->npins; i++) 1334 for (i = 0; i < pctl->devdata->npins; i++)
1267 pins[i] = pctl->devdata->pins[i].pin; 1335 pins[i] = pctl->devdata->pins[i].pin;
1268 mtk_pctrl_desc.name = dev_name(&pdev->dev); 1336
1269 mtk_pctrl_desc.owner = THIS_MODULE; 1337 pctl->pctl_desc.name = dev_name(&pdev->dev);
1270 mtk_pctrl_desc.pins = pins; 1338 pctl->pctl_desc.owner = THIS_MODULE;
1271 mtk_pctrl_desc.npins = pctl->devdata->npins; 1339 pctl->pctl_desc.pins = pins;
1340 pctl->pctl_desc.npins = pctl->devdata->npins;
1341 pctl->pctl_desc.confops = &mtk_pconf_ops;
1342 pctl->pctl_desc.pctlops = &mtk_pctrl_ops;
1343 pctl->pctl_desc.pmxops = &mtk_pmx_ops;
1272 pctl->dev = &pdev->dev; 1344 pctl->dev = &pdev->dev;
1273 pctl->pctl_dev = pinctrl_register(&mtk_pctrl_desc, &pdev->dev, pctl); 1345
1346 pctl->pctl_dev = pinctrl_register(&pctl->pctl_desc, &pdev->dev, pctl);
1274 if (IS_ERR(pctl->pctl_dev)) { 1347 if (IS_ERR(pctl->pctl_dev)) {
1275 dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); 1348 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
1276 return PTR_ERR(pctl->pctl_dev); 1349 return PTR_ERR(pctl->pctl_dev);
@@ -1319,6 +1392,21 @@ int mtk_pctrl_init(struct platform_device *pdev,
1319 goto chip_error; 1392 goto chip_error;
1320 } 1393 }
1321 1394
1395 ports_buf = pctl->devdata->eint_offsets.ports;
1396 pctl->wake_mask = devm_kcalloc(&pdev->dev, ports_buf,
1397 sizeof(*pctl->wake_mask), GFP_KERNEL);
1398 if (!pctl->wake_mask) {
1399 ret = -ENOMEM;
1400 goto chip_error;
1401 }
1402
1403 pctl->cur_mask = devm_kcalloc(&pdev->dev, ports_buf,
1404 sizeof(*pctl->cur_mask), GFP_KERNEL);
1405 if (!pctl->cur_mask) {
1406 ret = -ENOMEM;
1407 goto chip_error;
1408 }
1409
1322 pctl->eint_dual_edges = devm_kcalloc(&pdev->dev, pctl->devdata->ap_num, 1410 pctl->eint_dual_edges = devm_kcalloc(&pdev->dev, pctl->devdata->ap_num,
1323 sizeof(int), GFP_KERNEL); 1411 sizeof(int), GFP_KERNEL);
1324 if (!pctl->eint_dual_edges) { 1412 if (!pctl->eint_dual_edges) {
@@ -1348,11 +1436,9 @@ int mtk_pctrl_init(struct platform_device *pdev,
1348 irq_set_chip_and_handler(virq, &mtk_pinctrl_irq_chip, 1436 irq_set_chip_and_handler(virq, &mtk_pinctrl_irq_chip,
1349 handle_level_irq); 1437 handle_level_irq);
1350 irq_set_chip_data(virq, pctl); 1438 irq_set_chip_data(virq, pctl);
1351 set_irq_flags(virq, IRQF_VALID);
1352 }; 1439 };
1353 1440
1354 irq_set_chained_handler_and_data(irq, mtk_eint_irq_handler, pctl); 1441 irq_set_chained_handler_and_data(irq, mtk_eint_irq_handler, pctl);
1355 set_irq_flags(irq, IRQF_VALID);
1356 return 0; 1442 return 0;
1357 1443
1358chip_error: 1444chip_error:
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
index 30213e514c2f..55a534338931 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
@@ -256,6 +256,7 @@ struct mtk_pinctrl_devdata {
256struct mtk_pinctrl { 256struct mtk_pinctrl {
257 struct regmap *regmap1; 257 struct regmap *regmap1;
258 struct regmap *regmap2; 258 struct regmap *regmap2;
259 struct pinctrl_desc pctl_desc;
259 struct device *dev; 260 struct device *dev;
260 struct gpio_chip *chip; 261 struct gpio_chip *chip;
261 struct mtk_pinctrl_group *groups; 262 struct mtk_pinctrl_group *groups;
@@ -266,6 +267,8 @@ struct mtk_pinctrl {
266 void __iomem *eint_reg_base; 267 void __iomem *eint_reg_base;
267 struct irq_domain *domain; 268 struct irq_domain *domain;
268 int *eint_dual_edges; 269 int *eint_dual_edges;
270 u32 *wake_mask;
271 u32 *cur_mask;
269}; 272};
270 273
271int mtk_pctrl_init(struct platform_device *pdev, 274int mtk_pctrl_init(struct platform_device *pdev,
@@ -281,4 +284,6 @@ int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
281 const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num, 284 const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num,
282 unsigned int pin, unsigned char align, int value); 285 unsigned int pin, unsigned char align, int value);
283 286
287extern const struct dev_pm_ops mtk_eint_pm_ops;
288
284#endif /* __PINCTRL_MTK_COMMON_H */ 289#endif /* __PINCTRL_MTK_COMMON_H */
diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c b/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c
index c74840729648..8392083514fb 100644
--- a/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c
+++ b/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c
@@ -355,25 +355,6 @@ static const struct pinctrl_pin_desc nmk_db8500_pins[] = {
355 PINCTRL_PIN(DB8500_PIN_AC27, "GPIO267_AC27"), 355 PINCTRL_PIN(DB8500_PIN_AC27, "GPIO267_AC27"),
356}; 356};
357 357
358#define DB8500_GPIO_RANGE(a, b, c) { .name = "DB8500", .id = a, .base = b, \
359 .pin_base = b, .npins = c }
360
361/*
362 * This matches the 32-pin gpio chips registered by the GPIO portion. This
363 * cannot be const since we assign the struct gpio_chip * pointer at runtime.
364 */
365static struct pinctrl_gpio_range nmk_db8500_ranges[] = {
366 DB8500_GPIO_RANGE(0, 0, 32),
367 DB8500_GPIO_RANGE(1, 32, 5),
368 DB8500_GPIO_RANGE(2, 64, 32),
369 DB8500_GPIO_RANGE(3, 96, 2),
370 DB8500_GPIO_RANGE(4, 128, 32),
371 DB8500_GPIO_RANGE(5, 160, 12),
372 DB8500_GPIO_RANGE(6, 192, 32),
373 DB8500_GPIO_RANGE(7, 224, 7),
374 DB8500_GPIO_RANGE(8, 256, 12),
375};
376
377/* 358/*
378 * Read the pin group names like this: 359 * Read the pin group names like this:
379 * u0_a_1 = first groups of pins for uart0 on alt function a 360 * u0_a_1 = first groups of pins for uart0 on alt function a
@@ -1238,8 +1219,6 @@ static const u16 db8500_prcm_gpiocr_regs[] = {
1238}; 1219};
1239 1220
1240static const struct nmk_pinctrl_soc_data nmk_db8500_soc = { 1221static const struct nmk_pinctrl_soc_data nmk_db8500_soc = {
1241 .gpio_ranges = nmk_db8500_ranges,
1242 .gpio_num_ranges = ARRAY_SIZE(nmk_db8500_ranges),
1243 .pins = nmk_db8500_pins, 1222 .pins = nmk_db8500_pins,
1244 .npins = ARRAY_SIZE(nmk_db8500_pins), 1223 .npins = ARRAY_SIZE(nmk_db8500_pins),
1245 .functions = nmk_db8500_functions, 1224 .functions = nmk_db8500_functions,
diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik-db8540.c b/drivers/pinctrl/nomadik/pinctrl-nomadik-db8540.c
index d7ba5443bae0..2860eafd1b42 100644
--- a/drivers/pinctrl/nomadik/pinctrl-nomadik-db8540.c
+++ b/drivers/pinctrl/nomadik/pinctrl-nomadik-db8540.c
@@ -341,28 +341,6 @@ static const struct pinctrl_pin_desc nmk_db8540_pins[] = {
341 PINCTRL_PIN(DB8540_PIN_D17, "GPIO267_D17"), 341 PINCTRL_PIN(DB8540_PIN_D17, "GPIO267_D17"),
342}; 342};
343 343
344#define DB8540_GPIO_RANGE(a, b, c) { .name = "db8540", .id = a, .base = b, \
345 .pin_base = b, .npins = c }
346
347/*
348 * This matches the 32-pin gpio chips registered by the GPIO portion. This
349 * cannot be const since we assign the struct gpio_chip * pointer at runtime.
350 */
351static struct pinctrl_gpio_range nmk_db8540_ranges[] = {
352 DB8540_GPIO_RANGE(0, 0, 18),
353 DB8540_GPIO_RANGE(0, 22, 7),
354 DB8540_GPIO_RANGE(1, 33, 6),
355 DB8540_GPIO_RANGE(2, 64, 4),
356 DB8540_GPIO_RANGE(2, 70, 18),
357 DB8540_GPIO_RANGE(3, 116, 12),
358 DB8540_GPIO_RANGE(4, 128, 32),
359 DB8540_GPIO_RANGE(5, 160, 9),
360 DB8540_GPIO_RANGE(6, 192, 23),
361 DB8540_GPIO_RANGE(6, 219, 5),
362 DB8540_GPIO_RANGE(7, 224, 9),
363 DB8540_GPIO_RANGE(8, 256, 12),
364};
365
366/* 344/*
367 * Read the pin group names like this: 345 * Read the pin group names like this:
368 * u0_a_1 = first groups of pins for uart0 on alt function a 346 * u0_a_1 = first groups of pins for uart0 on alt function a
@@ -1247,8 +1225,6 @@ static const u16 db8540_prcm_gpiocr_regs[] = {
1247}; 1225};
1248 1226
1249static const struct nmk_pinctrl_soc_data nmk_db8540_soc = { 1227static const struct nmk_pinctrl_soc_data nmk_db8540_soc = {
1250 .gpio_ranges = nmk_db8540_ranges,
1251 .gpio_num_ranges = ARRAY_SIZE(nmk_db8540_ranges),
1252 .pins = nmk_db8540_pins, 1228 .pins = nmk_db8540_pins,
1253 .npins = ARRAY_SIZE(nmk_db8540_pins), 1229 .npins = ARRAY_SIZE(nmk_db8540_pins),
1254 .functions = nmk_db8540_functions, 1230 .functions = nmk_db8540_functions,
diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c b/drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c
index 2cd71470f270..587b222f12f3 100644
--- a/drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c
+++ b/drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c
@@ -264,20 +264,6 @@ static const struct pinctrl_pin_desc nmk_stn8815_pins[] = {
264 PINCTRL_PIN(STN8815_PIN_J22, "GPIO123_J22"), 264 PINCTRL_PIN(STN8815_PIN_J22, "GPIO123_J22"),
265}; 265};
266 266
267#define STN8815_GPIO_RANGE(a, b, c) { .name = "STN8815", .id = a, .base = b, \
268 .pin_base = b, .npins = c }
269
270/*
271 * This matches the 32-pin gpio chips registered by the GPIO portion. This
272 * cannot be const since we assign the struct gpio_chip * pointer at runtime.
273 */
274static struct pinctrl_gpio_range nmk_stn8815_ranges[] = {
275 STN8815_GPIO_RANGE(0, 0, 32),
276 STN8815_GPIO_RANGE(1, 32, 32),
277 STN8815_GPIO_RANGE(2, 64, 32),
278 STN8815_GPIO_RANGE(3, 96, 28),
279};
280
281/* 267/*
282 * Read the pin group names like this: 268 * Read the pin group names like this:
283 * u0_a_1 = first groups of pins for uart0 on alt function a 269 * u0_a_1 = first groups of pins for uart0 on alt function a
@@ -285,9 +271,11 @@ static struct pinctrl_gpio_range nmk_stn8815_ranges[] = {
285 */ 271 */
286 272
287/* Altfunction A */ 273/* Altfunction A */
288static const unsigned u0_a_1_pins[] = { STN8815_PIN_B4, STN8815_PIN_D5, 274static const unsigned u0txrx_a_1_pins[] = { STN8815_PIN_B4, STN8815_PIN_D5 };
289 STN8815_PIN_C5, STN8815_PIN_A4, STN8815_PIN_B5, STN8815_PIN_D6, 275static const unsigned u0ctsrts_a_1_pins[] = { STN8815_PIN_C5, STN8815_PIN_B6 };
290 STN8815_PIN_C6, STN8815_PIN_B6 }; 276/* Modem pins: DCD, DSR, RI, DTR */
277static const unsigned u0modem_a_1_pins[] = { STN8815_PIN_A4, STN8815_PIN_B5,
278 STN8815_PIN_D6, STN8815_PIN_C6 };
291static const unsigned mmcsd_a_1_pins[] = { STN8815_PIN_B10, STN8815_PIN_A10, 279static const unsigned mmcsd_a_1_pins[] = { STN8815_PIN_B10, STN8815_PIN_A10,
292 STN8815_PIN_C11, STN8815_PIN_B11, STN8815_PIN_A11, STN8815_PIN_C12, 280 STN8815_PIN_C11, STN8815_PIN_B11, STN8815_PIN_A11, STN8815_PIN_C12,
293 STN8815_PIN_B12, STN8815_PIN_A12, STN8815_PIN_C13, STN8815_PIN_C15 }; 281 STN8815_PIN_B12, STN8815_PIN_A12, STN8815_PIN_C13, STN8815_PIN_C15 };
@@ -304,7 +292,9 @@ static const unsigned i2cusb_b_1_pins[] = { STN8815_PIN_C21, STN8815_PIN_C20 };
304 .npins = ARRAY_SIZE(a##_pins), .altsetting = b } 292 .npins = ARRAY_SIZE(a##_pins), .altsetting = b }
305 293
306static const struct nmk_pingroup nmk_stn8815_groups[] = { 294static const struct nmk_pingroup nmk_stn8815_groups[] = {
307 STN8815_PIN_GROUP(u0_a_1, NMK_GPIO_ALT_A), 295 STN8815_PIN_GROUP(u0txrx_a_1, NMK_GPIO_ALT_A),
296 STN8815_PIN_GROUP(u0ctsrts_a_1, NMK_GPIO_ALT_A),
297 STN8815_PIN_GROUP(u0modem_a_1, NMK_GPIO_ALT_A),
308 STN8815_PIN_GROUP(mmcsd_a_1, NMK_GPIO_ALT_A), 298 STN8815_PIN_GROUP(mmcsd_a_1, NMK_GPIO_ALT_A),
309 STN8815_PIN_GROUP(mmcsd_b_1, NMK_GPIO_ALT_B), 299 STN8815_PIN_GROUP(mmcsd_b_1, NMK_GPIO_ALT_B),
310 STN8815_PIN_GROUP(u1_a_1, NMK_GPIO_ALT_A), 300 STN8815_PIN_GROUP(u1_a_1, NMK_GPIO_ALT_A),
@@ -318,7 +308,7 @@ static const struct nmk_pingroup nmk_stn8815_groups[] = {
318#define STN8815_FUNC_GROUPS(a, b...) \ 308#define STN8815_FUNC_GROUPS(a, b...) \
319static const char * const a##_groups[] = { b }; 309static const char * const a##_groups[] = { b };
320 310
321STN8815_FUNC_GROUPS(u0, "u0_a_1"); 311STN8815_FUNC_GROUPS(u0, "u0txrx_a_1", "u0ctsrts_a_1", "u0modem_a_1");
322STN8815_FUNC_GROUPS(mmcsd, "mmcsd_a_1", "mmcsd_b_1"); 312STN8815_FUNC_GROUPS(mmcsd, "mmcsd_a_1", "mmcsd_b_1");
323STN8815_FUNC_GROUPS(u1, "u1_a_1", "u1_b_1"); 313STN8815_FUNC_GROUPS(u1, "u1_a_1", "u1_b_1");
324STN8815_FUNC_GROUPS(i2c1, "i2c1_a_1"); 314STN8815_FUNC_GROUPS(i2c1, "i2c1_a_1");
@@ -342,8 +332,6 @@ static const struct nmk_function nmk_stn8815_functions[] = {
342}; 332};
343 333
344static const struct nmk_pinctrl_soc_data nmk_stn8815_soc = { 334static const struct nmk_pinctrl_soc_data nmk_stn8815_soc = {
345 .gpio_ranges = nmk_stn8815_ranges,
346 .gpio_num_ranges = ARRAY_SIZE(nmk_stn8815_ranges),
347 .pins = nmk_stn8815_pins, 335 .pins = nmk_stn8815_pins,
348 .npins = ARRAY_SIZE(nmk_stn8815_pins), 336 .npins = ARRAY_SIZE(nmk_stn8815_pins),
349 .functions = nmk_stn8815_functions, 337 .functions = nmk_stn8815_functions,
diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c
index 809d88445db5..352ede13a9e9 100644
--- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c
+++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c
@@ -203,6 +203,7 @@ typedef unsigned long pin_cfg_t;
203 203
204#define GPIO_BLOCK_SHIFT 5 204#define GPIO_BLOCK_SHIFT 5
205#define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT) 205#define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT)
206#define NMK_MAX_BANKS DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)
206 207
207/* Register in the logic block */ 208/* Register in the logic block */
208#define NMK_GPIO_DAT 0x00 209#define NMK_GPIO_DAT 0x00
@@ -282,8 +283,7 @@ struct nmk_pinctrl {
282 void __iomem *prcm_base; 283 void __iomem *prcm_base;
283}; 284};
284 285
285static struct nmk_gpio_chip * 286static struct nmk_gpio_chip *nmk_gpio_chips[NMK_MAX_BANKS];
286nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
287 287
288static DEFINE_SPINLOCK(nmk_gpio_slpm_lock); 288static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
289 289
@@ -843,10 +843,9 @@ static void nmk_gpio_irq_shutdown(struct irq_data *d)
843 clk_disable(nmk_chip->clk); 843 clk_disable(nmk_chip->clk);
844} 844}
845 845
846static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, 846static void __nmk_gpio_irq_handler(struct irq_desc *desc, u32 status)
847 u32 status)
848{ 847{
849 struct irq_chip *host_chip = irq_get_chip(irq); 848 struct irq_chip *host_chip = irq_desc_get_chip(desc);
850 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 849 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
851 850
852 chained_irq_enter(host_chip, desc); 851 chained_irq_enter(host_chip, desc);
@@ -871,17 +870,16 @@ static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
871 status = readl(nmk_chip->addr + NMK_GPIO_IS); 870 status = readl(nmk_chip->addr + NMK_GPIO_IS);
872 clk_disable(nmk_chip->clk); 871 clk_disable(nmk_chip->clk);
873 872
874 __nmk_gpio_irq_handler(irq, desc, status); 873 __nmk_gpio_irq_handler(desc, status);
875} 874}
876 875
877static void nmk_gpio_latent_irq_handler(unsigned int irq, 876static void nmk_gpio_latent_irq_handler(unsigned int irq, struct irq_desc *desc)
878 struct irq_desc *desc)
879{ 877{
880 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 878 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
881 struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); 879 struct nmk_gpio_chip *nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
882 u32 status = nmk_chip->get_latent_status(nmk_chip->bank); 880 u32 status = nmk_chip->get_latent_status(nmk_chip->bank);
883 881
884 __nmk_gpio_irq_handler(irq, desc, status); 882 __nmk_gpio_irq_handler(desc, status);
885} 883}
886 884
887/* I/O Functions */ 885/* I/O Functions */
@@ -1012,6 +1010,7 @@ static void nmk_gpio_dbg_show_one(struct seq_file *s,
1012 int irq = gpio_to_irq(gpio); 1010 int irq = gpio_to_irq(gpio);
1013 struct irq_desc *desc = irq_to_desc(irq); 1011 struct irq_desc *desc = irq_to_desc(irq);
1014 int pullidx = 0; 1012 int pullidx = 0;
1013 int val;
1015 1014
1016 if (pull) 1015 if (pull)
1017 pullidx = data_out ? 1 : 2; 1016 pullidx = data_out ? 1 : 2;
@@ -1021,6 +1020,10 @@ static void nmk_gpio_dbg_show_one(struct seq_file *s,
1021 label ?: "(none)", 1020 label ?: "(none)",
1022 pulls[pullidx], 1021 pulls[pullidx],
1023 (mode < 0) ? "unknown" : modes[mode]); 1022 (mode < 0) ? "unknown" : modes[mode]);
1023
1024 val = nmk_gpio_get_input(chip, offset);
1025 seq_printf(s, " VAL %d", val);
1026
1024 /* 1027 /*
1025 * This races with request_irq(), set_irq_type(), 1028 * This races with request_irq(), set_irq_type(),
1026 * and set_irq_wake() ... but those are "rare". 1029 * and set_irq_wake() ... but those are "rare".
@@ -1162,29 +1165,90 @@ void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up)
1162 } 1165 }
1163} 1166}
1164 1167
1168/*
1169 * We will allocate memory for the state container using devm* allocators
1170 * binding to the first device reaching this point, it doesn't matter if
1171 * it is the pin controller or GPIO driver. However we need to use the right
1172 * platform device when looking up resources so pay attention to pdev.
1173 */
1174static struct nmk_gpio_chip *nmk_gpio_populate_chip(struct device_node *np,
1175 struct platform_device *pdev)
1176{
1177 struct nmk_gpio_chip *nmk_chip;
1178 struct platform_device *gpio_pdev;
1179 struct gpio_chip *chip;
1180 struct resource *res;
1181 struct clk *clk;
1182 void __iomem *base;
1183 u32 id;
1184
1185 gpio_pdev = of_find_device_by_node(np);
1186 if (!gpio_pdev) {
1187 pr_err("populate \"%s\": device not found\n", np->name);
1188 return ERR_PTR(-ENODEV);
1189 }
1190 if (of_property_read_u32(np, "gpio-bank", &id)) {
1191 dev_err(&pdev->dev, "populate: gpio-bank property not found\n");
1192 return ERR_PTR(-EINVAL);
1193 }
1194
1195 /* Already populated? */
1196 nmk_chip = nmk_gpio_chips[id];
1197 if (nmk_chip)
1198 return nmk_chip;
1199
1200 nmk_chip = devm_kzalloc(&pdev->dev, sizeof(*nmk_chip), GFP_KERNEL);
1201 if (!nmk_chip)
1202 return ERR_PTR(-ENOMEM);
1203
1204 nmk_chip->bank = id;
1205 chip = &nmk_chip->chip;
1206 chip->base = id * NMK_GPIO_PER_CHIP;
1207 chip->ngpio = NMK_GPIO_PER_CHIP;
1208 chip->label = dev_name(&gpio_pdev->dev);
1209 chip->dev = &gpio_pdev->dev;
1210
1211 res = platform_get_resource(gpio_pdev, IORESOURCE_MEM, 0);
1212 base = devm_ioremap_resource(&pdev->dev, res);
1213 if (IS_ERR(base))
1214 return base;
1215 nmk_chip->addr = base;
1216
1217 clk = clk_get(&gpio_pdev->dev, NULL);
1218 if (IS_ERR(clk))
1219 return (void *) clk;
1220 clk_prepare(clk);
1221 nmk_chip->clk = clk;
1222
1223 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1224 nmk_gpio_chips[id] = nmk_chip;
1225 return nmk_chip;
1226}
1227
1165static int nmk_gpio_probe(struct platform_device *dev) 1228static int nmk_gpio_probe(struct platform_device *dev)
1166{ 1229{
1167 struct device_node *np = dev->dev.of_node; 1230 struct device_node *np = dev->dev.of_node;
1168 struct nmk_gpio_chip *nmk_chip; 1231 struct nmk_gpio_chip *nmk_chip;
1169 struct gpio_chip *chip; 1232 struct gpio_chip *chip;
1170 struct irq_chip *irqchip; 1233 struct irq_chip *irqchip;
1171 struct resource *res;
1172 struct clk *clk;
1173 int latent_irq; 1234 int latent_irq;
1174 bool supports_sleepmode; 1235 bool supports_sleepmode;
1175 void __iomem *base;
1176 int irq; 1236 int irq;
1177 int ret; 1237 int ret;
1178 1238
1239 nmk_chip = nmk_gpio_populate_chip(np, dev);
1240 if (IS_ERR(nmk_chip)) {
1241 dev_err(&dev->dev, "could not populate nmk chip struct\n");
1242 return PTR_ERR(nmk_chip);
1243 }
1244
1179 if (of_get_property(np, "st,supports-sleepmode", NULL)) 1245 if (of_get_property(np, "st,supports-sleepmode", NULL))
1180 supports_sleepmode = true; 1246 supports_sleepmode = true;
1181 else 1247 else
1182 supports_sleepmode = false; 1248 supports_sleepmode = false;
1183 1249
1184 if (of_property_read_u32(np, "gpio-bank", &dev->id)) { 1250 /* Correct platform device ID */
1185 dev_err(&dev->dev, "gpio-bank property not found\n"); 1251 dev->id = nmk_chip->bank;
1186 return -EINVAL;
1187 }
1188 1252
1189 irq = platform_get_irq(dev, 0); 1253 irq = platform_get_irq(dev, 0);
1190 if (irq < 0) 1254 if (irq < 0)
@@ -1193,27 +1257,10 @@ static int nmk_gpio_probe(struct platform_device *dev)
1193 /* It's OK for this IRQ not to be present */ 1257 /* It's OK for this IRQ not to be present */
1194 latent_irq = platform_get_irq(dev, 1); 1258 latent_irq = platform_get_irq(dev, 1);
1195 1259
1196 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1197 base = devm_ioremap_resource(&dev->dev, res);
1198 if (IS_ERR(base))
1199 return PTR_ERR(base);
1200
1201 clk = devm_clk_get(&dev->dev, NULL);
1202 if (IS_ERR(clk))
1203 return PTR_ERR(clk);
1204 clk_prepare(clk);
1205
1206 nmk_chip = devm_kzalloc(&dev->dev, sizeof(*nmk_chip), GFP_KERNEL);
1207 if (!nmk_chip)
1208 return -ENOMEM;
1209
1210 /* 1260 /*
1211 * The virt address in nmk_chip->addr is in the nomadik register space, 1261 * The virt address in nmk_chip->addr is in the nomadik register space,
1212 * so we can simply convert the resource address, without remapping 1262 * so we can simply convert the resource address, without remapping
1213 */ 1263 */
1214 nmk_chip->bank = dev->id;
1215 nmk_chip->clk = clk;
1216 nmk_chip->addr = base;
1217 nmk_chip->parent_irq = irq; 1264 nmk_chip->parent_irq = irq;
1218 nmk_chip->latent_parent_irq = latent_irq; 1265 nmk_chip->latent_parent_irq = latent_irq;
1219 nmk_chip->sleepmode = supports_sleepmode; 1266 nmk_chip->sleepmode = supports_sleepmode;
@@ -1228,10 +1275,6 @@ static int nmk_gpio_probe(struct platform_device *dev)
1228 chip->set = nmk_gpio_set_output; 1275 chip->set = nmk_gpio_set_output;
1229 chip->dbg_show = nmk_gpio_dbg_show; 1276 chip->dbg_show = nmk_gpio_dbg_show;
1230 chip->can_sleep = false; 1277 chip->can_sleep = false;
1231 chip->base = dev->id * NMK_GPIO_PER_CHIP;
1232 chip->ngpio = NMK_GPIO_PER_CHIP;
1233 chip->label = dev_name(&dev->dev);
1234 chip->dev = &dev->dev;
1235 chip->owner = THIS_MODULE; 1278 chip->owner = THIS_MODULE;
1236 1279
1237 irqchip = &nmk_chip->irqchip; 1280 irqchip = &nmk_chip->irqchip;
@@ -1253,14 +1296,10 @@ static int nmk_gpio_probe(struct platform_device *dev)
1253 clk_disable(nmk_chip->clk); 1296 clk_disable(nmk_chip->clk);
1254 chip->of_node = np; 1297 chip->of_node = np;
1255 1298
1256 ret = gpiochip_add(&nmk_chip->chip); 1299 ret = gpiochip_add(chip);
1257 if (ret) 1300 if (ret)
1258 return ret; 1301 return ret;
1259 1302
1260 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1261
1262 nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
1263
1264 platform_set_drvdata(dev, nmk_chip); 1303 platform_set_drvdata(dev, nmk_chip);
1265 1304
1266 /* 1305 /*
@@ -1320,35 +1359,40 @@ static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
1320 return 0; 1359 return 0;
1321} 1360}
1322 1361
1323static struct pinctrl_gpio_range * 1362static struct nmk_gpio_chip *find_nmk_gpio_from_pin(unsigned pin)
1324nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset)
1325{ 1363{
1326 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1327 int i; 1364 int i;
1365 struct nmk_gpio_chip *nmk_gpio;
1328 1366
1329 for (i = 0; i < npct->soc->gpio_num_ranges; i++) { 1367 for(i = 0; i < NMK_MAX_BANKS; i++) {
1330 struct pinctrl_gpio_range *range; 1368 nmk_gpio = nmk_gpio_chips[i];
1331 1369 if (!nmk_gpio)
1332 range = &npct->soc->gpio_ranges[i]; 1370 continue;
1333 if (offset >= range->pin_base && 1371 if (pin >= nmk_gpio->chip.base &&
1334 offset <= (range->pin_base + range->npins - 1)) 1372 pin < nmk_gpio->chip.base + nmk_gpio->chip.ngpio)
1335 return range; 1373 return nmk_gpio;
1336 } 1374 }
1337 return NULL; 1375 return NULL;
1338} 1376}
1339 1377
1378static struct gpio_chip *find_gc_from_pin(unsigned pin)
1379{
1380 struct nmk_gpio_chip *nmk_gpio = find_nmk_gpio_from_pin(pin);
1381
1382 if (nmk_gpio)
1383 return &nmk_gpio->chip;
1384 return NULL;
1385}
1386
1340static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 1387static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1341 unsigned offset) 1388 unsigned offset)
1342{ 1389{
1343 struct pinctrl_gpio_range *range; 1390 struct gpio_chip *chip = find_gc_from_pin(offset);
1344 struct gpio_chip *chip;
1345 1391
1346 range = nmk_match_gpio_range(pctldev, offset); 1392 if (!chip) {
1347 if (!range || !range->gc) {
1348 seq_printf(s, "invalid pin offset"); 1393 seq_printf(s, "invalid pin offset");
1349 return; 1394 return;
1350 } 1395 }
1351 chip = range->gc;
1352 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset); 1396 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset);
1353} 1397}
1354 1398
@@ -1693,25 +1737,16 @@ static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
1693 } 1737 }
1694 1738
1695 for (i = 0; i < g->npins; i++) { 1739 for (i = 0; i < g->npins; i++) {
1696 struct pinctrl_gpio_range *range;
1697 struct nmk_gpio_chip *nmk_chip; 1740 struct nmk_gpio_chip *nmk_chip;
1698 struct gpio_chip *chip;
1699 unsigned bit; 1741 unsigned bit;
1700 1742
1701 range = nmk_match_gpio_range(pctldev, g->pins[i]); 1743 nmk_chip = find_nmk_gpio_from_pin(g->pins[i]);
1702 if (!range) { 1744 if (!nmk_chip) {
1703 dev_err(npct->dev, 1745 dev_err(npct->dev,
1704 "invalid pin offset %d in group %s at index %d\n", 1746 "invalid pin offset %d in group %s at index %d\n",
1705 g->pins[i], g->name, i); 1747 g->pins[i], g->name, i);
1706 goto out_glitch; 1748 goto out_glitch;
1707 } 1749 }
1708 if (!range->gc) {
1709 dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n",
1710 g->pins[i], g->name, i);
1711 goto out_glitch;
1712 }
1713 chip = range->gc;
1714 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1715 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting); 1750 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);
1716 1751
1717 clk_enable(nmk_chip->clk); 1752 clk_enable(nmk_chip->clk);
@@ -1827,25 +1862,17 @@ static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
1827 }; 1862 };
1828 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); 1863 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1829 struct nmk_gpio_chip *nmk_chip; 1864 struct nmk_gpio_chip *nmk_chip;
1830 struct pinctrl_gpio_range *range;
1831 struct gpio_chip *chip;
1832 unsigned bit; 1865 unsigned bit;
1833 pin_cfg_t cfg; 1866 pin_cfg_t cfg;
1834 int pull, slpm, output, val, i; 1867 int pull, slpm, output, val, i;
1835 bool lowemi, gpiomode, sleep; 1868 bool lowemi, gpiomode, sleep;
1836 1869
1837 range = nmk_match_gpio_range(pctldev, pin); 1870 nmk_chip = find_nmk_gpio_from_pin(pin);
1838 if (!range) { 1871 if (!nmk_chip) {
1839 dev_err(npct->dev, "invalid pin offset %d\n", pin); 1872 dev_err(npct->dev,
1840 return -EINVAL; 1873 "invalid pin offset %d\n", pin);
1841 }
1842 if (!range->gc) {
1843 dev_err(npct->dev, "GPIO chip missing in range for pin %d\n",
1844 pin);
1845 return -EINVAL; 1874 return -EINVAL;
1846 } 1875 }
1847 chip = range->gc;
1848 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1849 1876
1850 for (i = 0; i < num_configs; i++) { 1877 for (i = 0; i < num_configs; i++) {
1851 /* 1878 /*
@@ -1997,6 +2024,31 @@ static int nmk_pinctrl_probe(struct platform_device *pdev)
1997 if (version == PINCTRL_NMK_DB8540) 2024 if (version == PINCTRL_NMK_DB8540)
1998 nmk_pinctrl_db8540_init(&npct->soc); 2025 nmk_pinctrl_db8540_init(&npct->soc);
1999 2026
2027 /*
2028 * Since we depend on the GPIO chips to provide clock and register base
2029 * for the pin control operations, make sure that we have these
2030 * populated before we continue. Follow the phandles to instantiate
2031 * them. The GPIO portion of the actual hardware may be probed before
2032 * or after this point: it shouldn't matter as the APIs are orthogonal.
2033 */
2034 for (i = 0; i < NMK_MAX_BANKS; i++) {
2035 struct device_node *gpio_np;
2036 struct nmk_gpio_chip *nmk_chip;
2037
2038 gpio_np = of_parse_phandle(np, "nomadik-gpio-chips", i);
2039 if (gpio_np) {
2040 dev_info(&pdev->dev,
2041 "populate NMK GPIO %d \"%s\"\n",
2042 i, gpio_np->name);
2043 nmk_chip = nmk_gpio_populate_chip(gpio_np, pdev);
2044 if (IS_ERR(nmk_chip))
2045 dev_err(&pdev->dev,
2046 "could not populate nmk chip struct "
2047 "- continue anyway\n");
2048 of_node_put(gpio_np);
2049 }
2050 }
2051
2000 prcm_np = of_parse_phandle(np, "prcm", 0); 2052 prcm_np = of_parse_phandle(np, "prcm", 0);
2001 if (prcm_np) 2053 if (prcm_np)
2002 npct->prcm_base = of_iomap(prcm_np, 0); 2054 npct->prcm_base = of_iomap(prcm_np, 0);
@@ -2011,19 +2063,6 @@ static int nmk_pinctrl_probe(struct platform_device *pdev)
2011 } 2063 }
2012 } 2064 }
2013 2065
2014 /*
2015 * We need all the GPIO drivers to probe FIRST, or we will not be able
2016 * to obtain references to the struct gpio_chip * for them, and we
2017 * need this to proceed.
2018 */
2019 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
2020 if (!nmk_gpio_chips[npct->soc->gpio_ranges[i].id]) {
2021 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
2022 return -EPROBE_DEFER;
2023 }
2024 npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[npct->soc->gpio_ranges[i].id]->chip;
2025 }
2026
2027 nmk_pinctrl_desc.pins = npct->soc->pins; 2066 nmk_pinctrl_desc.pins = npct->soc->pins;
2028 nmk_pinctrl_desc.npins = npct->soc->npins; 2067 nmk_pinctrl_desc.npins = npct->soc->npins;
2029 npct->dev = &pdev->dev; 2068 npct->dev = &pdev->dev;
@@ -2034,10 +2073,6 @@ static int nmk_pinctrl_probe(struct platform_device *pdev)
2034 return PTR_ERR(npct->pctl); 2073 return PTR_ERR(npct->pctl);
2035 } 2074 }
2036 2075
2037 /* We will handle a range of GPIO pins */
2038 for (i = 0; i < npct->soc->gpio_num_ranges; i++)
2039 pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]);
2040
2041 platform_set_drvdata(pdev, npct); 2076 platform_set_drvdata(pdev, npct);
2042 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n"); 2077 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
2043 2078
@@ -2072,15 +2107,15 @@ static struct platform_driver nmk_pinctrl_driver = {
2072 2107
2073static int __init nmk_gpio_init(void) 2108static int __init nmk_gpio_init(void)
2074{ 2109{
2075 int ret; 2110 return platform_driver_register(&nmk_gpio_driver);
2111}
2112subsys_initcall(nmk_gpio_init);
2076 2113
2077 ret = platform_driver_register(&nmk_gpio_driver); 2114static int __init nmk_pinctrl_init(void)
2078 if (ret) 2115{
2079 return ret;
2080 return platform_driver_register(&nmk_pinctrl_driver); 2116 return platform_driver_register(&nmk_pinctrl_driver);
2081} 2117}
2082 2118core_initcall(nmk_pinctrl_init);
2083core_initcall(nmk_gpio_init);
2084 2119
2085MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini"); 2120MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
2086MODULE_DESCRIPTION("Nomadik GPIO Driver"); 2121MODULE_DESCRIPTION("Nomadik GPIO Driver");
diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.h b/drivers/pinctrl/nomadik/pinctrl-nomadik.h
index d8215f1e70c7..30bba2a75a58 100644
--- a/drivers/pinctrl/nomadik/pinctrl-nomadik.h
+++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.h
@@ -121,8 +121,6 @@ struct nmk_pingroup {
121 121
122/** 122/**
123 * struct nmk_pinctrl_soc_data - Nomadik pin controller per-SoC configuration 123 * struct nmk_pinctrl_soc_data - Nomadik pin controller per-SoC configuration
124 * @gpio_ranges: An array of GPIO ranges for this SoC
125 * @gpio_num_ranges: The number of GPIO ranges for this SoC
126 * @pins: An array describing all pins the pin controller affects. 124 * @pins: An array describing all pins the pin controller affects.
127 * All pins which are also GPIOs must be listed first within the 125 * All pins which are also GPIOs must be listed first within the
128 * array, and be numbered identically to the GPIO controller's 126 * array, and be numbered identically to the GPIO controller's
@@ -137,8 +135,6 @@ struct nmk_pingroup {
137 * @prcm_gpiocr_registers: The array of PRCM GPIOCR registers on this SoC 135 * @prcm_gpiocr_registers: The array of PRCM GPIOCR registers on this SoC
138 */ 136 */
139struct nmk_pinctrl_soc_data { 137struct nmk_pinctrl_soc_data {
140 struct pinctrl_gpio_range *gpio_ranges;
141 unsigned gpio_num_ranges;
142 const struct pinctrl_pin_desc *pins; 138 const struct pinctrl_pin_desc *pins;
143 unsigned npins; 139 unsigned npins;
144 const struct nmk_function *functions; 140 const struct nmk_function *functions;
diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c
index 1fc09dc20199..29a7bb17a42f 100644
--- a/drivers/pinctrl/pinconf.c
+++ b/drivers/pinctrl/pinconf.c
@@ -61,8 +61,8 @@ int pin_config_get_for_pin(struct pinctrl_dev *pctldev, unsigned pin,
61 const struct pinconf_ops *ops = pctldev->desc->confops; 61 const struct pinconf_ops *ops = pctldev->desc->confops;
62 62
63 if (!ops || !ops->pin_config_get) { 63 if (!ops || !ops->pin_config_get) {
64 dev_dbg(pctldev->dev, "cannot get pin configuration, missing " 64 dev_dbg(pctldev->dev,
65 "pin_config_get() function in driver\n"); 65 "cannot get pin configuration, .pin_config_get missing in driver\n");
66 return -ENOTSUPP; 66 return -ENOTSUPP;
67 } 67 }
68 68
@@ -202,18 +202,34 @@ int pinconf_apply_setting(struct pinctrl_setting const *setting)
202 202
203#ifdef CONFIG_DEBUG_FS 203#ifdef CONFIG_DEBUG_FS
204 204
205void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map) 205static void pinconf_show_config(struct seq_file *s, struct pinctrl_dev *pctldev,
206 unsigned long *configs, unsigned num_configs)
206{ 207{
207 struct pinctrl_dev *pctldev;
208 const struct pinconf_ops *confops; 208 const struct pinconf_ops *confops;
209 int i; 209 int i;
210 210
211 pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name);
212 if (pctldev) 211 if (pctldev)
213 confops = pctldev->desc->confops; 212 confops = pctldev->desc->confops;
214 else 213 else
215 confops = NULL; 214 confops = NULL;
216 215
216 for (i = 0; i < num_configs; i++) {
217 seq_puts(s, "config ");
218 if (confops && confops->pin_config_config_dbg_show)
219 confops->pin_config_config_dbg_show(pctldev, s,
220 configs[i]);
221 else
222 seq_printf(s, "%08lx", configs[i]);
223 seq_puts(s, "\n");
224 }
225}
226
227void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map)
228{
229 struct pinctrl_dev *pctldev;
230
231 pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name);
232
217 switch (map->type) { 233 switch (map->type) {
218 case PIN_MAP_TYPE_CONFIGS_PIN: 234 case PIN_MAP_TYPE_CONFIGS_PIN:
219 seq_printf(s, "pin "); 235 seq_printf(s, "pin ");
@@ -227,15 +243,8 @@ void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map)
227 243
228 seq_printf(s, "%s\n", map->data.configs.group_or_pin); 244 seq_printf(s, "%s\n", map->data.configs.group_or_pin);
229 245
230 for (i = 0; i < map->data.configs.num_configs; i++) { 246 pinconf_show_config(s, pctldev, map->data.configs.configs,
231 seq_printf(s, "config "); 247 map->data.configs.num_configs);
232 if (confops && confops->pin_config_config_dbg_show)
233 confops->pin_config_config_dbg_show(pctldev, s,
234 map->data.configs.configs[i]);
235 else
236 seq_printf(s, "%08lx", map->data.configs.configs[i]);
237 seq_printf(s, "\n");
238 }
239} 248}
240 249
241void pinconf_show_setting(struct seq_file *s, 250void pinconf_show_setting(struct seq_file *s,
@@ -243,9 +252,7 @@ void pinconf_show_setting(struct seq_file *s,
243{ 252{
244 struct pinctrl_dev *pctldev = setting->pctldev; 253 struct pinctrl_dev *pctldev = setting->pctldev;
245 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; 254 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
246 const struct pinconf_ops *confops = pctldev->desc->confops;
247 struct pin_desc *desc; 255 struct pin_desc *desc;
248 int i;
249 256
250 switch (setting->type) { 257 switch (setting->type) {
251 case PIN_MAP_TYPE_CONFIGS_PIN: 258 case PIN_MAP_TYPE_CONFIGS_PIN:
@@ -269,17 +276,8 @@ void pinconf_show_setting(struct seq_file *s,
269 * FIXME: We should really get the pin controler to dump the config 276 * FIXME: We should really get the pin controler to dump the config
270 * values, so they can be decoded to something meaningful. 277 * values, so they can be decoded to something meaningful.
271 */ 278 */
272 for (i = 0; i < setting->data.configs.num_configs; i++) { 279 pinconf_show_config(s, pctldev, setting->data.configs.configs,
273 seq_printf(s, " "); 280 setting->data.configs.num_configs);
274 if (confops && confops->pin_config_config_dbg_show)
275 confops->pin_config_config_dbg_show(pctldev, s,
276 setting->data.configs.configs[i]);
277 else
278 seq_printf(s, "%08lx",
279 setting->data.configs.configs[i]);
280 }
281
282 seq_printf(s, "\n");
283} 281}
284 282
285static void pinconf_dump_pin(struct pinctrl_dev *pctldev, 283static void pinconf_dump_pin(struct pinctrl_dev *pctldev,
@@ -412,10 +410,8 @@ static int pinconf_dbg_config_print(struct seq_file *s, void *d)
412 const struct pinctrl_map *map; 410 const struct pinctrl_map *map;
413 const struct pinctrl_map *found = NULL; 411 const struct pinctrl_map *found = NULL;
414 struct pinctrl_dev *pctldev; 412 struct pinctrl_dev *pctldev;
415 const struct pinconf_ops *confops = NULL;
416 struct dbg_cfg *dbg = &pinconf_dbg_conf; 413 struct dbg_cfg *dbg = &pinconf_dbg_conf;
417 int i, j; 414 int i, j;
418 unsigned long config;
419 415
420 mutex_lock(&pinctrl_maps_mutex); 416 mutex_lock(&pinctrl_maps_mutex);
421 417
@@ -449,16 +445,10 @@ static int pinconf_dbg_config_print(struct seq_file *s, void *d)
449 } 445 }
450 446
451 pctldev = get_pinctrl_dev_from_devname(found->ctrl_dev_name); 447 pctldev = get_pinctrl_dev_from_devname(found->ctrl_dev_name);
452 config = *found->data.configs.configs; 448 seq_printf(s, "Dev %s has config of %s in state %s:\n",
453 seq_printf(s, "Dev %s has config of %s in state %s: 0x%08lX\n", 449 dbg->dev_name, dbg->pin_name, dbg->state_name);
454 dbg->dev_name, dbg->pin_name, 450 pinconf_show_config(s, pctldev, found->data.configs.configs,
455 dbg->state_name, config); 451 found->data.configs.num_configs);
456
457 if (pctldev)
458 confops = pctldev->desc->confops;
459
460 if (confops && confops->pin_config_config_dbg_show)
461 confops->pin_config_config_dbg_show(pctldev, s, config);
462 452
463exit: 453exit:
464 mutex_unlock(&pinctrl_maps_mutex); 454 mutex_unlock(&pinctrl_maps_mutex);
@@ -470,10 +460,12 @@ exit:
470 * pinconf_dbg_config_write() - modify the pinctrl config in the pinctrl 460 * pinconf_dbg_config_write() - modify the pinctrl config in the pinctrl
471 * map, of a dev/pin/state entry based on user entries to pinconf-config 461 * map, of a dev/pin/state entry based on user entries to pinconf-config
472 * @user_buf: contains the modification request with expected format: 462 * @user_buf: contains the modification request with expected format:
473 * modify config_pin <devicename> <state> <pinname> <newvalue> 463 * modify <config> <devicename> <state> <name> <newvalue>
474 * modify is literal string, alternatives like add/delete not supported yet 464 * modify is literal string, alternatives like add/delete not supported yet
475 * config_pin is literal, alternatives like config_mux not supported yet 465 * <config> is the configuration to be changed. Supported configs are
476 * <devicename> <state> <pinname> are values that should match the pinctrl-maps 466 * "config_pin" or "config_group", alternatives like config_mux are not
467 * supported yet.
468 * <devicename> <state> <name> are values that should match the pinctrl-maps
477 * <newvalue> reflects the new config and is driver dependant 469 * <newvalue> reflects the new config and is driver dependant
478 */ 470 */
479static ssize_t pinconf_dbg_config_write(struct file *file, 471static ssize_t pinconf_dbg_config_write(struct file *file,
@@ -511,13 +503,19 @@ static ssize_t pinconf_dbg_config_write(struct file *file,
511 if (strcmp(token, "modify")) 503 if (strcmp(token, "modify"))
512 return -EINVAL; 504 return -EINVAL;
513 505
514 /* Get arg type: "config_pin" type supported so far */ 506 /*
507 * Get arg type: "config_pin" and "config_group"
508 * types are supported so far
509 */
515 token = strsep(&b, " "); 510 token = strsep(&b, " ");
516 if (!token) 511 if (!token)
517 return -EINVAL; 512 return -EINVAL;
518 if (strcmp(token, "config_pin")) 513 if (!strcmp(token, "config_pin"))
514 dbg->map_type = PIN_MAP_TYPE_CONFIGS_PIN;
515 else if (!strcmp(token, "config_group"))
516 dbg->map_type = PIN_MAP_TYPE_CONFIGS_GROUP;
517 else
519 return -EINVAL; 518 return -EINVAL;
520 dbg->map_type = PIN_MAP_TYPE_CONFIGS_PIN;
521 519
522 /* get arg 'device_name' */ 520 /* get arg 'device_name' */
523 token = strsep(&b, " "); 521 token = strsep(&b, " ");
diff --git a/drivers/pinctrl/pinctrl-adi2-bf60x.c b/drivers/pinctrl/pinctrl-adi2-bf60x.c
index 4cb59fe9be70..fcfa00821f12 100644
--- a/drivers/pinctrl/pinctrl-adi2-bf60x.c
+++ b/drivers/pinctrl/pinctrl-adi2-bf60x.c
@@ -394,25 +394,25 @@ static const unsigned short ppi2_16b_mux[] = {
394static const unsigned short lp0_mux[] = { 394static const unsigned short lp0_mux[] = {
395 P_LP0_CLK, P_LP0_ACK, P_LP0_D0, P_LP0_D1, P_LP0_D2, 395 P_LP0_CLK, P_LP0_ACK, P_LP0_D0, P_LP0_D1, P_LP0_D2,
396 P_LP0_D3, P_LP0_D4, P_LP0_D5, P_LP0_D6, P_LP0_D7, 396 P_LP0_D3, P_LP0_D4, P_LP0_D5, P_LP0_D6, P_LP0_D7,
397 0 397 0
398}; 398};
399 399
400static const unsigned short lp1_mux[] = { 400static const unsigned short lp1_mux[] = {
401 P_LP1_CLK, P_LP1_ACK, P_LP1_D0, P_LP1_D1, P_LP1_D2, 401 P_LP1_CLK, P_LP1_ACK, P_LP1_D0, P_LP1_D1, P_LP1_D2,
402 P_LP1_D3, P_LP1_D4, P_LP1_D5, P_LP1_D6, P_LP1_D7, 402 P_LP1_D3, P_LP1_D4, P_LP1_D5, P_LP1_D6, P_LP1_D7,
403 0 403 0
404}; 404};
405 405
406static const unsigned short lp2_mux[] = { 406static const unsigned short lp2_mux[] = {
407 P_LP2_CLK, P_LP2_ACK, P_LP2_D0, P_LP2_D1, P_LP2_D2, 407 P_LP2_CLK, P_LP2_ACK, P_LP2_D0, P_LP2_D1, P_LP2_D2,
408 P_LP2_D3, P_LP2_D4, P_LP2_D5, P_LP2_D6, P_LP2_D7, 408 P_LP2_D3, P_LP2_D4, P_LP2_D5, P_LP2_D6, P_LP2_D7,
409 0 409 0
410}; 410};
411 411
412static const unsigned short lp3_mux[] = { 412static const unsigned short lp3_mux[] = {
413 P_LP3_CLK, P_LP3_ACK, P_LP3_D0, P_LP3_D1, P_LP3_D2, 413 P_LP3_CLK, P_LP3_ACK, P_LP3_D0, P_LP3_D1, P_LP3_D2,
414 P_LP3_D3, P_LP3_D4, P_LP3_D5, P_LP3_D6, P_LP3_D7, 414 P_LP3_D3, P_LP3_D4, P_LP3_D5, P_LP3_D6, P_LP3_D7,
415 0 415 0
416}; 416};
417 417
418static const struct adi_pin_group adi_pin_groups[] = { 418static const struct adi_pin_group adi_pin_groups[] = {
diff --git a/drivers/pinctrl/pinctrl-adi2.c b/drivers/pinctrl/pinctrl-adi2.c
index c3c3d2345fc6..a5976ebc4482 100644
--- a/drivers/pinctrl/pinctrl-adi2.c
+++ b/drivers/pinctrl/pinctrl-adi2.c
@@ -427,10 +427,10 @@ static int adi_gpio_irq_type(struct irq_data *d, unsigned int type)
427 427
428 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { 428 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
429 writel(pintmask, &pint_regs->edge_set); 429 writel(pintmask, &pint_regs->edge_set);
430 __irq_set_handler_locked(irq, handle_edge_irq); 430 irq_set_handler_locked(d, handle_edge_irq);
431 } else { 431 } else {
432 writel(pintmask, &pint_regs->edge_clear); 432 writel(pintmask, &pint_regs->edge_clear);
433 __irq_set_handler_locked(irq, handle_level_irq); 433 irq_set_handler_locked(d, handle_level_irq);
434 } 434 }
435 435
436out: 436out:
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index d8e3f7c7fea3..5e86bb8ca80e 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -420,7 +420,7 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
420 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 420 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
421 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 421 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
422 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 422 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
423 __irq_set_handler_locked(d->irq, handle_edge_irq); 423 irq_set_handler_locked(d, handle_edge_irq);
424 break; 424 break;
425 425
426 case IRQ_TYPE_EDGE_FALLING: 426 case IRQ_TYPE_EDGE_FALLING:
@@ -428,7 +428,7 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
428 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 428 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
429 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 429 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
430 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 430 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
431 __irq_set_handler_locked(d->irq, handle_edge_irq); 431 irq_set_handler_locked(d, handle_edge_irq);
432 break; 432 break;
433 433
434 case IRQ_TYPE_EDGE_BOTH: 434 case IRQ_TYPE_EDGE_BOTH:
@@ -436,7 +436,7 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
436 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 436 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
437 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; 437 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
438 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 438 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
439 __irq_set_handler_locked(d->irq, handle_edge_irq); 439 irq_set_handler_locked(d, handle_edge_irq);
440 break; 440 break;
441 441
442 case IRQ_TYPE_LEVEL_HIGH: 442 case IRQ_TYPE_LEVEL_HIGH:
@@ -445,7 +445,7 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
445 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 445 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
446 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 446 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
447 pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF; 447 pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF;
448 __irq_set_handler_locked(d->irq, handle_level_irq); 448 irq_set_handler_locked(d, handle_level_irq);
449 break; 449 break;
450 450
451 case IRQ_TYPE_LEVEL_LOW: 451 case IRQ_TYPE_LEVEL_LOW:
@@ -454,7 +454,7 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
454 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 454 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
455 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 455 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
456 pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF; 456 pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF;
457 __irq_set_handler_locked(d->irq, handle_level_irq); 457 irq_set_handler_locked(d, handle_level_irq);
458 break; 458 break;
459 459
460 case IRQ_TYPE_NONE: 460 case IRQ_TYPE_NONE:
@@ -492,8 +492,9 @@ static struct irq_chip amd_gpio_irqchip = {
492 .irq_set_type = amd_gpio_irq_set_type, 492 .irq_set_type = amd_gpio_irq_set_type,
493}; 493};
494 494
495static void amd_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) 495static void amd_gpio_irq_handler(unsigned int __irq, struct irq_desc *desc)
496{ 496{
497 unsigned int irq = irq_desc_get_irq(desc);
497 u32 i; 498 u32 i;
498 u32 off; 499 u32 off;
499 u32 reg; 500 u32 reg;
@@ -501,7 +502,7 @@ static void amd_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
501 u64 reg64; 502 u64 reg64;
502 int handled = 0; 503 int handled = 0;
503 unsigned long flags; 504 unsigned long flags;
504 struct irq_chip *chip = irq_get_chip(irq); 505 struct irq_chip *chip = irq_desc_get_chip(desc);
505 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 506 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
506 struct amd_gpio *gpio_dev = to_amd_gpio(gc); 507 struct amd_gpio *gpio_dev = to_amd_gpio(gc);
507 508
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index a0824477072b..bae0012ee356 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -320,6 +320,9 @@ static const struct pinctrl_ops at91_pctrl_ops = {
320static void __iomem *pin_to_controller(struct at91_pinctrl *info, 320static void __iomem *pin_to_controller(struct at91_pinctrl *info,
321 unsigned int bank) 321 unsigned int bank)
322{ 322{
323 if (!gpio_chips[bank])
324 return NULL;
325
323 return gpio_chips[bank]->regbase; 326 return gpio_chips[bank]->regbase;
324} 327}
325 328
@@ -729,6 +732,10 @@ static int at91_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
729 pin = &pins_conf[i]; 732 pin = &pins_conf[i];
730 at91_pin_dbg(info->dev, pin); 733 at91_pin_dbg(info->dev, pin);
731 pio = pin_to_controller(info, pin->bank); 734 pio = pin_to_controller(info, pin->bank);
735
736 if (!pio)
737 continue;
738
732 mask = pin_to_mask(pin->pin); 739 mask = pin_to_mask(pin->pin);
733 at91_mux_disable_interrupt(pio, mask); 740 at91_mux_disable_interrupt(pio, mask);
734 switch (pin->mux) { 741 switch (pin->mux) {
@@ -848,6 +855,10 @@ static int at91_pinconf_get(struct pinctrl_dev *pctldev,
848 *config = 0; 855 *config = 0;
849 dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id); 856 dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id);
850 pio = pin_to_controller(info, pin_to_bank(pin_id)); 857 pio = pin_to_controller(info, pin_to_bank(pin_id));
858
859 if (!pio)
860 return -EINVAL;
861
851 pin = pin_id % MAX_NB_GPIO_PER_BANK; 862 pin = pin_id % MAX_NB_GPIO_PER_BANK;
852 863
853 if (at91_mux_get_multidrive(pio, pin)) 864 if (at91_mux_get_multidrive(pio, pin))
@@ -889,6 +900,10 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
889 "%s:%d, pin_id=%d, config=0x%lx", 900 "%s:%d, pin_id=%d, config=0x%lx",
890 __func__, __LINE__, pin_id, config); 901 __func__, __LINE__, pin_id, config);
891 pio = pin_to_controller(info, pin_to_bank(pin_id)); 902 pio = pin_to_controller(info, pin_to_bank(pin_id));
903
904 if (!pio)
905 return -EINVAL;
906
892 pin = pin_id % MAX_NB_GPIO_PER_BANK; 907 pin = pin_id % MAX_NB_GPIO_PER_BANK;
893 mask = pin_to_mask(pin); 908 mask = pin_to_mask(pin);
894 909
@@ -1444,22 +1459,22 @@ static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
1444 1459
1445 switch (type) { 1460 switch (type) {
1446 case IRQ_TYPE_EDGE_RISING: 1461 case IRQ_TYPE_EDGE_RISING:
1447 __irq_set_handler_locked(d->irq, handle_simple_irq); 1462 irq_set_handler_locked(d, handle_simple_irq);
1448 writel_relaxed(mask, pio + PIO_ESR); 1463 writel_relaxed(mask, pio + PIO_ESR);
1449 writel_relaxed(mask, pio + PIO_REHLSR); 1464 writel_relaxed(mask, pio + PIO_REHLSR);
1450 break; 1465 break;
1451 case IRQ_TYPE_EDGE_FALLING: 1466 case IRQ_TYPE_EDGE_FALLING:
1452 __irq_set_handler_locked(d->irq, handle_simple_irq); 1467 irq_set_handler_locked(d, handle_simple_irq);
1453 writel_relaxed(mask, pio + PIO_ESR); 1468 writel_relaxed(mask, pio + PIO_ESR);
1454 writel_relaxed(mask, pio + PIO_FELLSR); 1469 writel_relaxed(mask, pio + PIO_FELLSR);
1455 break; 1470 break;
1456 case IRQ_TYPE_LEVEL_LOW: 1471 case IRQ_TYPE_LEVEL_LOW:
1457 __irq_set_handler_locked(d->irq, handle_level_irq); 1472 irq_set_handler_locked(d, handle_level_irq);
1458 writel_relaxed(mask, pio + PIO_LSR); 1473 writel_relaxed(mask, pio + PIO_LSR);
1459 writel_relaxed(mask, pio + PIO_FELLSR); 1474 writel_relaxed(mask, pio + PIO_FELLSR);
1460 break; 1475 break;
1461 case IRQ_TYPE_LEVEL_HIGH: 1476 case IRQ_TYPE_LEVEL_HIGH:
1462 __irq_set_handler_locked(d->irq, handle_level_irq); 1477 irq_set_handler_locked(d, handle_level_irq);
1463 writel_relaxed(mask, pio + PIO_LSR); 1478 writel_relaxed(mask, pio + PIO_LSR);
1464 writel_relaxed(mask, pio + PIO_REHLSR); 1479 writel_relaxed(mask, pio + PIO_REHLSR);
1465 break; 1480 break;
@@ -1468,7 +1483,7 @@ static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
1468 * disable additional interrupt modes: 1483 * disable additional interrupt modes:
1469 * fall back to default behavior 1484 * fall back to default behavior
1470 */ 1485 */
1471 __irq_set_handler_locked(d->irq, handle_simple_irq); 1486 irq_set_handler_locked(d, handle_simple_irq);
1472 writel_relaxed(mask, pio + PIO_AIMDR); 1487 writel_relaxed(mask, pio + PIO_AIMDR);
1473 return 0; 1488 return 0;
1474 case IRQ_TYPE_NONE: 1489 case IRQ_TYPE_NONE:
@@ -1488,28 +1503,6 @@ static void gpio_irq_ack(struct irq_data *d)
1488 /* the interrupt is already cleared before by reading ISR */ 1503 /* the interrupt is already cleared before by reading ISR */
1489} 1504}
1490 1505
1491static int gpio_irq_request_res(struct irq_data *d)
1492{
1493 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1494 unsigned pin = d->hwirq;
1495 int ret;
1496
1497 ret = gpiochip_lock_as_irq(&at91_gpio->chip, pin);
1498 if (ret)
1499 dev_err(at91_gpio->chip.dev, "unable to lock pind %lu IRQ\n",
1500 d->hwirq);
1501
1502 return ret;
1503}
1504
1505static void gpio_irq_release_res(struct irq_data *d)
1506{
1507 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
1508 unsigned pin = d->hwirq;
1509
1510 gpiochip_unlock_as_irq(&at91_gpio->chip, pin);
1511}
1512
1513#ifdef CONFIG_PM 1506#ifdef CONFIG_PM
1514 1507
1515static u32 wakeups[MAX_GPIO_BANKS]; 1508static u32 wakeups[MAX_GPIO_BANKS];
@@ -1585,8 +1578,6 @@ void at91_pinctrl_gpio_resume(void)
1585static struct irq_chip gpio_irqchip = { 1578static struct irq_chip gpio_irqchip = {
1586 .name = "GPIO", 1579 .name = "GPIO",
1587 .irq_ack = gpio_irq_ack, 1580 .irq_ack = gpio_irq_ack,
1588 .irq_request_resources = gpio_irq_request_res,
1589 .irq_release_resources = gpio_irq_release_res,
1590 .irq_disable = gpio_irq_mask, 1581 .irq_disable = gpio_irq_mask,
1591 .irq_mask = gpio_irq_mask, 1582 .irq_mask = gpio_irq_mask,
1592 .irq_unmask = gpio_irq_unmask, 1583 .irq_unmask = gpio_irq_unmask,
@@ -1596,7 +1587,7 @@ static struct irq_chip gpio_irqchip = {
1596 1587
1597static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) 1588static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
1598{ 1589{
1599 struct irq_chip *chip = irq_get_chip(irq); 1590 struct irq_chip *chip = irq_desc_get_chip(desc);
1600 struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc); 1591 struct gpio_chip *gpio_chip = irq_desc_get_handler_data(desc);
1601 struct at91_gpio_chip *at91_gpio = container_of(gpio_chip, 1592 struct at91_gpio_chip *at91_gpio = container_of(gpio_chip,
1602 struct at91_gpio_chip, chip); 1593 struct at91_gpio_chip, chip);
diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c
index 29cbbab8c3a6..3731cc67a88b 100644
--- a/drivers/pinctrl/pinctrl-coh901.c
+++ b/drivers/pinctrl/pinctrl-coh901.c
@@ -519,10 +519,11 @@ static struct irq_chip u300_gpio_irqchip = {
519 .irq_set_type = u300_gpio_irq_type, 519 .irq_set_type = u300_gpio_irq_type,
520}; 520};
521 521
522static void u300_gpio_irq_handler(unsigned irq, struct irq_desc *desc) 522static void u300_gpio_irq_handler(unsigned __irq, struct irq_desc *desc)
523{ 523{
524 struct irq_chip *parent_chip = irq_get_chip(irq); 524 unsigned int irq = irq_desc_get_irq(desc);
525 struct gpio_chip *chip = irq_get_handler_data(irq); 525 struct irq_chip *parent_chip = irq_desc_get_chip(desc);
526 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
526 struct u300_gpio *gpio = to_u300_gpio(chip); 527 struct u300_gpio *gpio = to_u300_gpio(chip);
527 struct u300_gpio_port *port = &gpio->ports[irq - chip->base]; 528 struct u300_gpio_port *port = &gpio->ports[irq - chip->base];
528 int pinoffset = port->number << 3; /* get the right stride */ 529 int pinoffset = port->number << 3; /* get the right stride */
diff --git a/drivers/pinctrl/pinctrl-digicolor.c b/drivers/pinctrl/pinctrl-digicolor.c
new file mode 100644
index 000000000000..461fffc4c62a
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-digicolor.c
@@ -0,0 +1,378 @@
1/*
2 * Driver for Conexant Digicolor General Purpose Pin Mapping
3 *
4 * Author: Baruch Siach <baruch@tkos.co.il>
5 *
6 * Copyright (C) 2015 Paradox Innovation Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * TODO:
14 * - GPIO interrupt support
15 * - Pin pad configuration (pull up/down, strength)
16 */
17
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/of.h>
21#include <linux/of_device.h>
22#include <linux/io.h>
23#include <linux/gpio.h>
24#include <linux/gpio/driver.h>
25#include <linux/spinlock.h>
26#include <linux/pinctrl/machine.h>
27#include <linux/pinctrl/pinconf.h>
28#include <linux/pinctrl/pinconf-generic.h>
29#include <linux/pinctrl/pinctrl.h>
30#include <linux/pinctrl/pinmux.h>
31#include "pinctrl-utils.h"
32
33#define DRIVER_NAME "pinctrl-digicolor"
34
35#define GP_CLIENTSEL(clct) ((clct)*8 + 0x20)
36#define GP_DRIVE0(clct) (GP_CLIENTSEL(clct) + 2)
37#define GP_OUTPUT0(clct) (GP_CLIENTSEL(clct) + 3)
38#define GP_INPUT(clct) (GP_CLIENTSEL(clct) + 6)
39
40#define PIN_COLLECTIONS ('R' - 'A' + 1)
41#define PINS_PER_COLLECTION 8
42#define PINS_COUNT (PIN_COLLECTIONS * PINS_PER_COLLECTION)
43
44struct dc_pinmap {
45 void __iomem *regs;
46 struct device *dev;
47 struct pinctrl_dev *pctl;
48
49 struct pinctrl_desc *desc;
50 const char *pin_names[PINS_COUNT];
51
52 struct gpio_chip chip;
53 spinlock_t lock;
54};
55
56static int dc_get_groups_count(struct pinctrl_dev *pctldev)
57{
58 return PINS_COUNT;
59}
60
61static const char *dc_get_group_name(struct pinctrl_dev *pctldev,
62 unsigned selector)
63{
64 struct dc_pinmap *pmap = pinctrl_dev_get_drvdata(pctldev);
65
66 /* Exactly one group per pin */
67 return pmap->desc->pins[selector].name;
68}
69
70static int dc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
71 const unsigned **pins,
72 unsigned *num_pins)
73{
74 struct dc_pinmap *pmap = pinctrl_dev_get_drvdata(pctldev);
75
76 *pins = &pmap->desc->pins[selector].number;
77 *num_pins = 1;
78
79 return 0;
80}
81
82static struct pinctrl_ops dc_pinctrl_ops = {
83 .get_groups_count = dc_get_groups_count,
84 .get_group_name = dc_get_group_name,
85 .get_group_pins = dc_get_group_pins,
86 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
87 .dt_free_map = pinctrl_utils_dt_free_map,
88};
89
90static const char *const dc_functions[] = {
91 "gpio",
92 "client_a",
93 "client_b",
94 "client_c",
95};
96
97static int dc_get_functions_count(struct pinctrl_dev *pctldev)
98{
99 return ARRAY_SIZE(dc_functions);
100}
101
102static const char *dc_get_fname(struct pinctrl_dev *pctldev, unsigned selector)
103{
104 return dc_functions[selector];
105}
106
107static int dc_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
108 const char * const **groups,
109 unsigned * const num_groups)
110{
111 struct dc_pinmap *pmap = pinctrl_dev_get_drvdata(pctldev);
112
113 *groups = pmap->pin_names;
114 *num_groups = PINS_COUNT;
115
116 return 0;
117}
118
119static void dc_client_sel(int pin_num, int *reg, int *bit)
120{
121 *bit = (pin_num % PINS_PER_COLLECTION) * 2;
122 *reg = GP_CLIENTSEL(pin_num/PINS_PER_COLLECTION);
123
124 if (*bit >= PINS_PER_COLLECTION) {
125 *bit -= PINS_PER_COLLECTION;
126 *reg += 1;
127 }
128}
129
130static int dc_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
131 unsigned group)
132{
133 struct dc_pinmap *pmap = pinctrl_dev_get_drvdata(pctldev);
134 int bit_off, reg_off;
135 u8 reg;
136
137 dc_client_sel(group, &reg_off, &bit_off);
138
139 reg = readb_relaxed(pmap->regs + reg_off);
140 reg &= ~(3 << bit_off);
141 reg |= (selector << bit_off);
142 writeb_relaxed(reg, pmap->regs + reg_off);
143
144 return 0;
145}
146
147static int dc_pmx_request_gpio(struct pinctrl_dev *pcdev,
148 struct pinctrl_gpio_range *range,
149 unsigned offset)
150{
151 struct dc_pinmap *pmap = pinctrl_dev_get_drvdata(pcdev);
152 int bit_off, reg_off;
153 u8 reg;
154
155 dc_client_sel(offset, &reg_off, &bit_off);
156
157 reg = readb_relaxed(pmap->regs + reg_off);
158 if ((reg & (3 << bit_off)) != 0)
159 return -EBUSY;
160
161 return 0;
162}
163
164static struct pinmux_ops dc_pmxops = {
165 .get_functions_count = dc_get_functions_count,
166 .get_function_name = dc_get_fname,
167 .get_function_groups = dc_get_groups,
168 .set_mux = dc_set_mux,
169 .gpio_request_enable = dc_pmx_request_gpio,
170};
171
172static int dc_gpio_request(struct gpio_chip *chip, unsigned gpio)
173{
174 return pinctrl_request_gpio(chip->base + gpio);
175}
176
177static void dc_gpio_free(struct gpio_chip *chip, unsigned gpio)
178{
179 pinctrl_free_gpio(chip->base + gpio);
180}
181
182static int dc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
183{
184 struct dc_pinmap *pmap = container_of(chip, struct dc_pinmap, chip);
185 int reg_off = GP_DRIVE0(gpio/PINS_PER_COLLECTION);
186 int bit_off = gpio % PINS_PER_COLLECTION;
187 u8 drive;
188 unsigned long flags;
189
190 spin_lock_irqsave(&pmap->lock, flags);
191 drive = readb_relaxed(pmap->regs + reg_off);
192 drive &= ~BIT(bit_off);
193 writeb_relaxed(drive, pmap->regs + reg_off);
194 spin_unlock_irqrestore(&pmap->lock, flags);
195
196 return 0;
197}
198
199static void dc_gpio_set(struct gpio_chip *chip, unsigned gpio, int value);
200
201static int dc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
202 int value)
203{
204 struct dc_pinmap *pmap = container_of(chip, struct dc_pinmap, chip);
205 int reg_off = GP_DRIVE0(gpio/PINS_PER_COLLECTION);
206 int bit_off = gpio % PINS_PER_COLLECTION;
207 u8 drive;
208 unsigned long flags;
209
210 dc_gpio_set(chip, gpio, value);
211
212 spin_lock_irqsave(&pmap->lock, flags);
213 drive = readb_relaxed(pmap->regs + reg_off);
214 drive |= BIT(bit_off);
215 writeb_relaxed(drive, pmap->regs + reg_off);
216 spin_unlock_irqrestore(&pmap->lock, flags);
217
218 return 0;
219}
220
221static int dc_gpio_get(struct gpio_chip *chip, unsigned gpio)
222{
223 struct dc_pinmap *pmap = container_of(chip, struct dc_pinmap, chip);
224 int reg_off = GP_INPUT(gpio/PINS_PER_COLLECTION);
225 int bit_off = gpio % PINS_PER_COLLECTION;
226 u8 input;
227
228 input = readb_relaxed(pmap->regs + reg_off);
229
230 return !!(input & BIT(bit_off));
231}
232
233static void dc_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
234{
235 struct dc_pinmap *pmap = container_of(chip, struct dc_pinmap, chip);
236 int reg_off = GP_OUTPUT0(gpio/PINS_PER_COLLECTION);
237 int bit_off = gpio % PINS_PER_COLLECTION;
238 u8 output;
239 unsigned long flags;
240
241 spin_lock_irqsave(&pmap->lock, flags);
242 output = readb_relaxed(pmap->regs + reg_off);
243 if (value)
244 output |= BIT(bit_off);
245 else
246 output &= ~BIT(bit_off);
247 writeb_relaxed(output, pmap->regs + reg_off);
248 spin_unlock_irqrestore(&pmap->lock, flags);
249}
250
251static int dc_gpiochip_add(struct dc_pinmap *pmap, struct device_node *np)
252{
253 struct gpio_chip *chip = &pmap->chip;
254 int ret;
255
256 chip->label = DRIVER_NAME;
257 chip->dev = pmap->dev;
258 chip->request = dc_gpio_request;
259 chip->free = dc_gpio_free;
260 chip->direction_input = dc_gpio_direction_input;
261 chip->direction_output = dc_gpio_direction_output;
262 chip->get = dc_gpio_get;
263 chip->set = dc_gpio_set;
264 chip->base = -1;
265 chip->ngpio = PINS_COUNT;
266 chip->of_node = np;
267 chip->of_gpio_n_cells = 2;
268
269 spin_lock_init(&pmap->lock);
270
271 ret = gpiochip_add(chip);
272 if (ret < 0)
273 return ret;
274
275 ret = gpiochip_add_pin_range(chip, dev_name(pmap->dev), 0, 0,
276 PINS_COUNT);
277 if (ret < 0) {
278 gpiochip_remove(chip);
279 return ret;
280 }
281
282 return 0;
283}
284
285static int dc_pinctrl_probe(struct platform_device *pdev)
286{
287 struct dc_pinmap *pmap;
288 struct resource *r;
289 struct pinctrl_pin_desc *pins;
290 struct pinctrl_desc *pctl_desc;
291 char *pin_names;
292 int name_len = strlen("GP_xx") + 1;
293 int i, j, ret;
294
295 pmap = devm_kzalloc(&pdev->dev, sizeof(*pmap), GFP_KERNEL);
296 if (!pmap)
297 return -ENOMEM;
298
299 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
300 pmap->regs = devm_ioremap_resource(&pdev->dev, r);
301 if (IS_ERR(pmap->regs))
302 return PTR_ERR(pmap->regs);
303
304 pins = devm_kzalloc(&pdev->dev, sizeof(*pins)*PINS_COUNT, GFP_KERNEL);
305 if (!pins)
306 return -ENOMEM;
307 pin_names = devm_kzalloc(&pdev->dev, name_len * PINS_COUNT,
308 GFP_KERNEL);
309 if (!pin_names)
310 return -ENOMEM;
311
312 for (i = 0; i < PIN_COLLECTIONS; i++) {
313 for (j = 0; j < PINS_PER_COLLECTION; j++) {
314 int pin_id = i*PINS_PER_COLLECTION + j;
315 char *name = &pin_names[pin_id * name_len];
316
317 snprintf(name, name_len, "GP_%c%c", 'A'+i, '0'+j);
318
319 pins[pin_id].number = pin_id;
320 pins[pin_id].name = name;
321 pmap->pin_names[pin_id] = name;
322 }
323 }
324
325 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL);
326 if (!pctl_desc)
327 return -ENOMEM;
328
329 pctl_desc->name = DRIVER_NAME,
330 pctl_desc->owner = THIS_MODULE,
331 pctl_desc->pctlops = &dc_pinctrl_ops,
332 pctl_desc->pmxops = &dc_pmxops,
333 pctl_desc->npins = PINS_COUNT;
334 pctl_desc->pins = pins;
335 pmap->desc = pctl_desc;
336
337 pmap->dev = &pdev->dev;
338
339 pmap->pctl = pinctrl_register(pctl_desc, &pdev->dev, pmap);
340 if (!pmap->pctl) {
341 dev_err(&pdev->dev, "pinctrl driver registration failed\n");
342 return -EINVAL;
343 }
344
345 ret = dc_gpiochip_add(pmap, pdev->dev.of_node);
346 if (ret < 0) {
347 pinctrl_unregister(pmap->pctl);
348 return ret;
349 }
350
351 return 0;
352}
353
354static int dc_pinctrl_remove(struct platform_device *pdev)
355{
356 struct dc_pinmap *pmap = platform_get_drvdata(pdev);
357
358 pinctrl_unregister(pmap->pctl);
359 gpiochip_remove(&pmap->chip);
360
361 return 0;
362}
363
364static const struct of_device_id dc_pinctrl_ids[] = {
365 { .compatible = "cnxt,cx92755-pinctrl" },
366 { /* sentinel */ }
367};
368MODULE_DEVICE_TABLE(of, dc_pinctrl_ids);
369
370static struct platform_driver dc_pinctrl_driver = {
371 .driver = {
372 .name = DRIVER_NAME,
373 .of_match_table = dc_pinctrl_ids,
374 },
375 .probe = dc_pinctrl_probe,
376 .remove = dc_pinctrl_remove,
377};
378module_platform_driver(dc_pinctrl_driver);
diff --git a/drivers/pinctrl/pinctrl-lpc18xx.c b/drivers/pinctrl/pinctrl-lpc18xx.c
index 347c763a6a78..f0bebbe0682b 100644
--- a/drivers/pinctrl/pinctrl-lpc18xx.c
+++ b/drivers/pinctrl/pinctrl-lpc18xx.c
@@ -37,6 +37,9 @@
37#define LPC18XX_SCU_PIN_EHD_MASK 0x300 37#define LPC18XX_SCU_PIN_EHD_MASK 0x300
38#define LPC18XX_SCU_PIN_EHD_POS 8 38#define LPC18XX_SCU_PIN_EHD_POS 8
39 39
40#define LPC18XX_SCU_USB1_EPD BIT(2)
41#define LPC18XX_SCU_USB1_EPWR BIT(4)
42
40#define LPC18XX_SCU_I2C0_EFP BIT(0) 43#define LPC18XX_SCU_I2C0_EFP BIT(0)
41#define LPC18XX_SCU_I2C0_EHD BIT(2) 44#define LPC18XX_SCU_I2C0_EHD BIT(2)
42#define LPC18XX_SCU_I2C0_EZI BIT(3) 45#define LPC18XX_SCU_I2C0_EZI BIT(3)
@@ -617,8 +620,31 @@ static const struct pinctrl_pin_desc lpc18xx_pins[] = {
617 620
618static int lpc18xx_pconf_get_usb1(enum pin_config_param param, int *arg, u32 reg) 621static int lpc18xx_pconf_get_usb1(enum pin_config_param param, int *arg, u32 reg)
619{ 622{
620 /* TODO */ 623 switch (param) {
621 return -ENOTSUPP; 624 case PIN_CONFIG_LOW_POWER_MODE:
625 if (reg & LPC18XX_SCU_USB1_EPWR)
626 *arg = 0;
627 else
628 *arg = 1;
629 break;
630
631 case PIN_CONFIG_BIAS_DISABLE:
632 if (reg & LPC18XX_SCU_USB1_EPD)
633 return -EINVAL;
634 break;
635
636 case PIN_CONFIG_BIAS_PULL_DOWN:
637 if (reg & LPC18XX_SCU_USB1_EPD)
638 *arg = 1;
639 else
640 return -EINVAL;
641 break;
642
643 default:
644 return -ENOTSUPP;
645 }
646
647 return 0;
622} 648}
623 649
624static int lpc18xx_pconf_get_i2c0(enum pin_config_param param, int *arg, u32 reg, 650static int lpc18xx_pconf_get_i2c0(enum pin_config_param param, int *arg, u32 reg,
@@ -782,8 +808,28 @@ static int lpc18xx_pconf_set_usb1(struct pinctrl_dev *pctldev,
782 enum pin_config_param param, 808 enum pin_config_param param,
783 u16 param_val, u32 *reg) 809 u16 param_val, u32 *reg)
784{ 810{
785 /* TODO */ 811 switch (param) {
786 return -ENOTSUPP; 812 case PIN_CONFIG_LOW_POWER_MODE:
813 if (param_val)
814 *reg &= ~LPC18XX_SCU_USB1_EPWR;
815 else
816 *reg |= LPC18XX_SCU_USB1_EPWR;
817 break;
818
819 case PIN_CONFIG_BIAS_DISABLE:
820 *reg &= ~LPC18XX_SCU_USB1_EPD;
821 break;
822
823 case PIN_CONFIG_BIAS_PULL_DOWN:
824 *reg |= LPC18XX_SCU_USB1_EPD;
825 break;
826
827 default:
828 dev_err(pctldev->dev, "Property not supported\n");
829 return -ENOTSUPP;
830 }
831
832 return 0;
787} 833}
788 834
789static int lpc18xx_pconf_set_i2c0(struct pinctrl_dev *pctldev, 835static int lpc18xx_pconf_set_i2c0(struct pinctrl_dev *pctldev,
diff --git a/drivers/pinctrl/pinctrl-pistachio.c b/drivers/pinctrl/pinctrl-pistachio.c
index 63100be81015..3dc2ae15f3a1 100644
--- a/drivers/pinctrl/pinctrl-pistachio.c
+++ b/drivers/pinctrl/pinctrl-pistachio.c
@@ -1310,9 +1310,11 @@ static int pistachio_gpio_irq_set_type(struct irq_data *data, unsigned int type)
1310 return 0; 1310 return 0;
1311} 1311}
1312 1312
1313static void pistachio_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) 1313static void pistachio_gpio_irq_handler(unsigned int __irq,
1314 struct irq_desc *desc)
1314{ 1315{
1315 struct gpio_chip *gc = irq_get_handler_data(irq); 1316 unsigned int irq = irq_desc_get_irq(desc);
1317 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1316 struct pistachio_gpio_bank *bank = gc_to_bank(gc); 1318 struct pistachio_gpio_bank *bank = gc_to_bank(gc);
1317 struct irq_chip *chip = irq_get_chip(irq); 1319 struct irq_chip *chip = irq_get_chip(irq);
1318 unsigned long pending; 1320 unsigned long pending;
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 9affcd725776..c5246c05f70c 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -945,6 +945,7 @@ static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
945 if (ret < 0) 945 if (ret < 0)
946 return ret; 946 return ret;
947 947
948 clk_enable(bank->clk);
948 spin_lock_irqsave(&bank->slock, flags); 949 spin_lock_irqsave(&bank->slock, flags);
949 950
950 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 951 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
@@ -956,6 +957,7 @@ static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
956 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); 957 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
957 958
958 spin_unlock_irqrestore(&bank->slock, flags); 959 spin_unlock_irqrestore(&bank->slock, flags);
960 clk_disable(bank->clk);
959 961
960 return 0; 962 return 0;
961} 963}
@@ -1389,6 +1391,7 @@ static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
1389 unsigned long flags; 1391 unsigned long flags;
1390 u32 data; 1392 u32 data;
1391 1393
1394 clk_enable(bank->clk);
1392 spin_lock_irqsave(&bank->slock, flags); 1395 spin_lock_irqsave(&bank->slock, flags);
1393 1396
1394 data = readl(reg); 1397 data = readl(reg);
@@ -1398,6 +1401,7 @@ static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
1398 writel(data, reg); 1401 writel(data, reg);
1399 1402
1400 spin_unlock_irqrestore(&bank->slock, flags); 1403 spin_unlock_irqrestore(&bank->slock, flags);
1404 clk_disable(bank->clk);
1401} 1405}
1402 1406
1403/* 1407/*
@@ -1409,7 +1413,9 @@ static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
1409 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); 1413 struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
1410 u32 data; 1414 u32 data;
1411 1415
1416 clk_enable(bank->clk);
1412 data = readl(bank->reg_base + GPIO_EXT_PORT); 1417 data = readl(bank->reg_base + GPIO_EXT_PORT);
1418 clk_disable(bank->clk);
1413 data >>= offset; 1419 data >>= offset;
1414 data &= 1; 1420 data &= 1;
1415 return data; 1421 return data;
@@ -1469,10 +1475,10 @@ static const struct gpio_chip rockchip_gpiolib_chip = {
1469 * Interrupt handling 1475 * Interrupt handling
1470 */ 1476 */
1471 1477
1472static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc) 1478static void rockchip_irq_demux(unsigned int __irq, struct irq_desc *desc)
1473{ 1479{
1474 struct irq_chip *chip = irq_get_chip(irq); 1480 struct irq_chip *chip = irq_desc_get_chip(desc);
1475 struct rockchip_pin_bank *bank = irq_get_handler_data(irq); 1481 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
1476 u32 pend; 1482 u32 pend;
1477 1483
1478 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); 1484 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
@@ -1482,7 +1488,7 @@ static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
1482 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); 1488 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1483 1489
1484 while (pend) { 1490 while (pend) {
1485 unsigned int virq; 1491 unsigned int irq, virq;
1486 1492
1487 irq = __ffs(pend); 1493 irq = __ffs(pend);
1488 pend &= ~BIT(irq); 1494 pend &= ~BIT(irq);
@@ -1546,6 +1552,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1546 if (ret < 0) 1552 if (ret < 0)
1547 return ret; 1553 return ret;
1548 1554
1555 clk_enable(bank->clk);
1549 spin_lock_irqsave(&bank->slock, flags); 1556 spin_lock_irqsave(&bank->slock, flags);
1550 1557
1551 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); 1558 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
@@ -1555,9 +1562,9 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1555 spin_unlock_irqrestore(&bank->slock, flags); 1562 spin_unlock_irqrestore(&bank->slock, flags);
1556 1563
1557 if (type & IRQ_TYPE_EDGE_BOTH) 1564 if (type & IRQ_TYPE_EDGE_BOTH)
1558 __irq_set_handler_locked(d->irq, handle_edge_irq); 1565 irq_set_handler_locked(d, handle_edge_irq);
1559 else 1566 else
1560 __irq_set_handler_locked(d->irq, handle_level_irq); 1567 irq_set_handler_locked(d, handle_level_irq);
1561 1568
1562 spin_lock_irqsave(&bank->slock, flags); 1569 spin_lock_irqsave(&bank->slock, flags);
1563 irq_gc_lock(gc); 1570 irq_gc_lock(gc);
@@ -1603,6 +1610,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1603 default: 1610 default:
1604 irq_gc_unlock(gc); 1611 irq_gc_unlock(gc);
1605 spin_unlock_irqrestore(&bank->slock, flags); 1612 spin_unlock_irqrestore(&bank->slock, flags);
1613 clk_disable(bank->clk);
1606 return -EINVAL; 1614 return -EINVAL;
1607 } 1615 }
1608 1616
@@ -1611,6 +1619,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1611 1619
1612 irq_gc_unlock(gc); 1620 irq_gc_unlock(gc);
1613 spin_unlock_irqrestore(&bank->slock, flags); 1621 spin_unlock_irqrestore(&bank->slock, flags);
1622 clk_disable(bank->clk);
1614 1623
1615 return 0; 1624 return 0;
1616} 1625}
@@ -1620,8 +1629,10 @@ static void rockchip_irq_suspend(struct irq_data *d)
1620 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 1629 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1621 struct rockchip_pin_bank *bank = gc->private; 1630 struct rockchip_pin_bank *bank = gc->private;
1622 1631
1632 clk_enable(bank->clk);
1623 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK); 1633 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
1624 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK); 1634 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
1635 clk_disable(bank->clk);
1625} 1636}
1626 1637
1627static void rockchip_irq_resume(struct irq_data *d) 1638static void rockchip_irq_resume(struct irq_data *d)
@@ -1629,7 +1640,27 @@ static void rockchip_irq_resume(struct irq_data *d)
1629 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 1640 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1630 struct rockchip_pin_bank *bank = gc->private; 1641 struct rockchip_pin_bank *bank = gc->private;
1631 1642
1643 clk_enable(bank->clk);
1632 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK); 1644 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
1645 clk_disable(bank->clk);
1646}
1647
1648static void rockchip_irq_gc_mask_clr_bit(struct irq_data *d)
1649{
1650 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1651 struct rockchip_pin_bank *bank = gc->private;
1652
1653 clk_enable(bank->clk);
1654 irq_gc_mask_clr_bit(d);
1655}
1656
1657void rockchip_irq_gc_mask_set_bit(struct irq_data *d)
1658{
1659 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1660 struct rockchip_pin_bank *bank = gc->private;
1661
1662 irq_gc_mask_set_bit(d);
1663 clk_disable(bank->clk);
1633} 1664}
1634 1665
1635static int rockchip_interrupts_register(struct platform_device *pdev, 1666static int rockchip_interrupts_register(struct platform_device *pdev,
@@ -1640,7 +1671,7 @@ static int rockchip_interrupts_register(struct platform_device *pdev,
1640 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 1671 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1641 struct irq_chip_generic *gc; 1672 struct irq_chip_generic *gc;
1642 int ret; 1673 int ret;
1643 int i; 1674 int i, j;
1644 1675
1645 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 1676 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1646 if (!bank->valid) { 1677 if (!bank->valid) {
@@ -1649,11 +1680,19 @@ static int rockchip_interrupts_register(struct platform_device *pdev,
1649 continue; 1680 continue;
1650 } 1681 }
1651 1682
1683 ret = clk_enable(bank->clk);
1684 if (ret) {
1685 dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
1686 bank->name);
1687 continue;
1688 }
1689
1652 bank->domain = irq_domain_add_linear(bank->of_node, 32, 1690 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1653 &irq_generic_chip_ops, NULL); 1691 &irq_generic_chip_ops, NULL);
1654 if (!bank->domain) { 1692 if (!bank->domain) {
1655 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n", 1693 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1656 bank->name); 1694 bank->name);
1695 clk_disable(bank->clk);
1657 continue; 1696 continue;
1658 } 1697 }
1659 1698
@@ -1664,6 +1703,7 @@ static int rockchip_interrupts_register(struct platform_device *pdev,
1664 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", 1703 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
1665 bank->name); 1704 bank->name);
1666 irq_domain_remove(bank->domain); 1705 irq_domain_remove(bank->domain);
1706 clk_disable(bank->clk);
1667 continue; 1707 continue;
1668 } 1708 }
1669 1709
@@ -1681,16 +1721,23 @@ static int rockchip_interrupts_register(struct platform_device *pdev,
1681 gc->chip_types[0].regs.mask = GPIO_INTMASK; 1721 gc->chip_types[0].regs.mask = GPIO_INTMASK;
1682 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI; 1722 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
1683 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; 1723 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
1684 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; 1724 gc->chip_types[0].chip.irq_mask = rockchip_irq_gc_mask_set_bit;
1685 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; 1725 gc->chip_types[0].chip.irq_unmask =
1726 rockchip_irq_gc_mask_clr_bit;
1686 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; 1727 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
1687 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend; 1728 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
1688 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume; 1729 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
1689 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; 1730 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
1690 gc->wake_enabled = IRQ_MSK(bank->nr_pins); 1731 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
1691 1732
1692 irq_set_handler_data(bank->irq, bank); 1733 irq_set_chained_handler_and_data(bank->irq,
1693 irq_set_chained_handler(bank->irq, rockchip_irq_demux); 1734 rockchip_irq_demux, bank);
1735
1736 /* map the gpio irqs here, when the clock is still running */
1737 for (j = 0 ; j < 32 ; j++)
1738 irq_create_mapping(bank->domain, j);
1739
1740 clk_disable(bank->clk);
1694 } 1741 }
1695 1742
1696 return 0; 1743 return 0;
@@ -1808,7 +1855,7 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1808 if (IS_ERR(bank->clk)) 1855 if (IS_ERR(bank->clk))
1809 return PTR_ERR(bank->clk); 1856 return PTR_ERR(bank->clk);
1810 1857
1811 return clk_prepare_enable(bank->clk); 1858 return clk_prepare(bank->clk);
1812} 1859}
1813 1860
1814static const struct of_device_id rockchip_pinctrl_dt_match[]; 1861static const struct of_device_id rockchip_pinctrl_dt_match[];
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 0b8d480171a3..bf548c2a7a9d 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -1684,7 +1684,7 @@ static void pcs_irq_chain_handler(unsigned int irq, struct irq_desc *desc)
1684 struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc); 1684 struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1685 struct irq_chip *chip; 1685 struct irq_chip *chip;
1686 1686
1687 chip = irq_get_chip(irq); 1687 chip = irq_desc_get_chip(desc);
1688 chained_irq_enter(chip, desc); 1688 chained_irq_enter(chip, desc);
1689 pcs_irq_handle(pcs_soc); 1689 pcs_irq_handle(pcs_soc);
1690 /* REVISIT: export and add handle_bad_irq(irq, desc)? */ 1690 /* REVISIT: export and add handle_bad_irq(irq, desc)? */
@@ -1716,12 +1716,7 @@ static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
1716 irq_set_chip_data(irq, pcs_soc); 1716 irq_set_chip_data(irq, pcs_soc);
1717 irq_set_chip_and_handler(irq, &pcs->chip, 1717 irq_set_chip_and_handler(irq, &pcs->chip,
1718 handle_level_irq); 1718 handle_level_irq);
1719
1720#ifdef CONFIG_ARM
1721 set_irq_flags(irq, IRQF_VALID);
1722#else
1723 irq_set_noprobe(irq); 1719 irq_set_noprobe(irq);
1724#endif
1725 1720
1726 return 0; 1721 return 0;
1727} 1722}
@@ -1768,9 +1763,9 @@ static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1768 return res; 1763 return res;
1769 } 1764 }
1770 } else { 1765 } else {
1771 irq_set_handler_data(pcs_soc->irq, pcs_soc); 1766 irq_set_chained_handler_and_data(pcs_soc->irq,
1772 irq_set_chained_handler(pcs_soc->irq, 1767 pcs_irq_chain_handler,
1773 pcs_irq_chain_handler); 1768 pcs_soc);
1774 } 1769 }
1775 1770
1776 /* 1771 /*
@@ -1983,7 +1978,6 @@ static const struct pcs_soc_data pinctrl_single_omap_wkup = {
1983}; 1978};
1984 1979
1985static const struct pcs_soc_data pinctrl_single_dra7 = { 1980static const struct pcs_soc_data pinctrl_single_dra7 = {
1986 .flags = PCS_QUIRK_SHARED_IRQ,
1987 .irq_enable_mask = (1 << 24), /* WAKEUPENABLE */ 1981 .irq_enable_mask = (1 << 24), /* WAKEUPENABLE */
1988 .irq_status_mask = (1 << 25), /* WAKEUPEVENT */ 1982 .irq_status_mask = (1 << 25), /* WAKEUPEVENT */
1989}; 1983};
diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
index c262e5f35c28..f8338d2e6b6b 100644
--- a/drivers/pinctrl/pinctrl-st.c
+++ b/drivers/pinctrl/pinctrl-st.c
@@ -1463,7 +1463,7 @@ static void __gpio_irq_handler(struct st_gpio_bank *bank)
1463static void st_gpio_irq_handler(unsigned irq, struct irq_desc *desc) 1463static void st_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
1464{ 1464{
1465 /* interrupt dedicated per bank */ 1465 /* interrupt dedicated per bank */
1466 struct irq_chip *chip = irq_get_chip(irq); 1466 struct irq_chip *chip = irq_desc_get_chip(desc);
1467 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 1467 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1468 struct st_gpio_bank *bank = gpio_chip_to_bank(gc); 1468 struct st_gpio_bank *bank = gpio_chip_to_bank(gc);
1469 1469
@@ -1474,8 +1474,8 @@ static void st_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
1474 1474
1475static void st_gpio_irqmux_handler(unsigned irq, struct irq_desc *desc) 1475static void st_gpio_irqmux_handler(unsigned irq, struct irq_desc *desc)
1476{ 1476{
1477 struct irq_chip *chip = irq_get_chip(irq); 1477 struct irq_chip *chip = irq_desc_get_chip(desc);
1478 struct st_pinctrl *info = irq_get_handler_data(irq); 1478 struct st_pinctrl *info = irq_desc_get_handler_data(desc);
1479 unsigned long status; 1479 unsigned long status;
1480 int n; 1480 int n;
1481 1481
diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c
index 7ce23b6282ad..5aafea8c6590 100644
--- a/drivers/pinctrl/pinctrl-zynq.c
+++ b/drivers/pinctrl/pinctrl-zynq.c
@@ -706,10 +706,10 @@ static const char * const sdio1_wp_groups[] = {"gpio0_0_grp",
706 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp", 706 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
707 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp", 707 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
708 "gpio0_51_grp", "gpio0_53_grp", "sdio1_emio_wp_grp"}; 708 "gpio0_51_grp", "gpio0_53_grp", "sdio1_emio_wp_grp"};
709static const char * const smc0_nor_groups[] = {"smc0_nor"}; 709static const char * const smc0_nor_groups[] = {"smc0_nor_grp"};
710static const char * const smc0_nor_cs1_groups[] = {"smc0_nor_cs1_grp"}; 710static const char * const smc0_nor_cs1_groups[] = {"smc0_nor_cs1_grp"};
711static const char * const smc0_nor_addr25_groups[] = {"smc0_nor_addr25_grp"}; 711static const char * const smc0_nor_addr25_groups[] = {"smc0_nor_addr25_grp"};
712static const char * const smc0_nand_groups[] = {"smc0_nand"}; 712static const char * const smc0_nand_groups[] = {"smc0_nand_grp"};
713static const char * const can0_groups[] = {"can0_0_grp", "can0_1_grp", 713static const char * const can0_groups[] = {"can0_0_grp", "can0_1_grp",
714 "can0_2_grp", "can0_3_grp", "can0_4_grp", "can0_5_grp", 714 "can0_2_grp", "can0_3_grp", "can0_4_grp", "can0_5_grp",
715 "can0_6_grp", "can0_7_grp", "can0_8_grp", "can0_9_grp", 715 "can0_6_grp", "can0_7_grp", "can0_8_grp", "can0_9_grp",
diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c
index e7ae890dcf1a..67e08cb315c4 100644
--- a/drivers/pinctrl/pinmux.c
+++ b/drivers/pinctrl/pinmux.c
@@ -322,8 +322,7 @@ static int pinmux_func_name_to_selector(struct pinctrl_dev *pctldev,
322 selector++; 322 selector++;
323 } 323 }
324 324
325 pr_err("%s does not support function %s\n", 325 dev_err(pctldev->dev, "function '%s' not supported\n", function);
326 pinctrl_dev_get_name(pctldev), function);
327 return -EINVAL; 326 return -EINVAL;
328} 327}
329 328
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 58f5632b27f4..383263a92e59 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -63,6 +63,14 @@ config PINCTRL_MSM8916
63 This is the pinctrl, pinmux, pinconf and gpiolib driver for the 63 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
64 Qualcomm TLMM block found on the Qualcomm 8916 platform. 64 Qualcomm TLMM block found on the Qualcomm 8916 platform.
65 65
66config PINCTRL_QDF2XXX
67 tristate "Qualcomm Technologies QDF2xxx pin controller driver"
68 depends on GPIOLIB && ACPI
69 select PINCTRL_MSM
70 help
71 This is the GPIO driver for the TLMM block found on the
72 Qualcomm Technologies QDF2xxx SOCs.
73
66config PINCTRL_QCOM_SPMI_PMIC 74config PINCTRL_QCOM_SPMI_PMIC
67 tristate "Qualcomm SPMI PMIC pin controller driver" 75 tristate "Qualcomm SPMI PMIC pin controller driver"
68 depends on GPIOLIB && OF && SPMI 76 depends on GPIOLIB && OF && SPMI
@@ -76,4 +84,16 @@ config PINCTRL_QCOM_SPMI_PMIC
76 which are using SPMI for communication with SoC. Example PMIC's 84 which are using SPMI for communication with SoC. Example PMIC's
77 devices are pm8841, pm8941 and pma8084. 85 devices are pm8841, pm8941 and pma8084.
78 86
87config PINCTRL_QCOM_SSBI_PMIC
88 tristate "Qualcomm SSBI PMIC pin controller driver"
89 depends on GPIOLIB && OF
90 select PINMUX
91 select PINCONF
92 select GENERIC_PINCONF
93 help
94 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
95 Qualcomm GPIO and MPP blocks found in the Qualcomm PMIC's chips,
96 which are using SSBI for communication with SoC. Example PMIC's
97 devices are pm8058 and pm8921.
98
79endif 99endif
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 3666c703ce88..13b190e72c21 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -7,5 +7,8 @@ obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o
7obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o 7obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o
8obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o 8obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
9obj-$(CONFIG_PINCTRL_MSM8916) += pinctrl-msm8916.o 9obj-$(CONFIG_PINCTRL_MSM8916) += pinctrl-msm8916.o
10obj-$(CONFIG_PINCTRL_QDF2XXX) += pinctrl-qdf2xxx.o
10obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o 11obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o
11obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o 12obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o
13obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o
14obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index e457d52302a2..492cdd51dc5c 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -28,6 +28,7 @@
28#include <linux/interrupt.h> 28#include <linux/interrupt.h>
29#include <linux/spinlock.h> 29#include <linux/spinlock.h>
30#include <linux/reboot.h> 30#include <linux/reboot.h>
31#include <linux/pm.h>
31 32
32#include "../core.h" 33#include "../core.h"
33#include "../pinconf.h" 34#include "../pinconf.h"
@@ -733,9 +734,9 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
733 spin_unlock_irqrestore(&pctrl->lock, flags); 734 spin_unlock_irqrestore(&pctrl->lock, flags);
734 735
735 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 736 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
736 __irq_set_handler_locked(d->irq, handle_level_irq); 737 irq_set_handler_locked(d, handle_level_irq);
737 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 738 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
738 __irq_set_handler_locked(d->irq, handle_edge_irq); 739 irq_set_handler_locked(d, handle_edge_irq);
739 740
740 return 0; 741 return 0;
741} 742}
@@ -764,12 +765,13 @@ static struct irq_chip msm_gpio_irq_chip = {
764 .irq_set_wake = msm_gpio_irq_set_wake, 765 .irq_set_wake = msm_gpio_irq_set_wake,
765}; 766};
766 767
767static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) 768static void msm_gpio_irq_handler(unsigned int __irq, struct irq_desc *desc)
768{ 769{
770 unsigned int irq = irq_desc_get_irq(desc);
769 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 771 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
770 const struct msm_pingroup *g; 772 const struct msm_pingroup *g;
771 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); 773 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
772 struct irq_chip *chip = irq_get_chip(irq); 774 struct irq_chip *chip = irq_desc_get_chip(desc);
773 int irq_pin; 775 int irq_pin;
774 int handled = 0; 776 int handled = 0;
775 u32 val; 777 u32 val;
@@ -855,6 +857,13 @@ static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action,
855 return NOTIFY_DONE; 857 return NOTIFY_DONE;
856} 858}
857 859
860static struct msm_pinctrl *poweroff_pctrl;
861
862static void msm_ps_hold_poweroff(void)
863{
864 msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL);
865}
866
858static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) 867static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
859{ 868{
860 int i; 869 int i;
@@ -867,6 +876,8 @@ static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
867 if (register_restart_handler(&pctrl->restart_nb)) 876 if (register_restart_handler(&pctrl->restart_nb))
868 dev_err(pctrl->dev, 877 dev_err(pctrl->dev,
869 "failed to setup restart handler.\n"); 878 "failed to setup restart handler.\n");
879 poweroff_pctrl = pctrl;
880 pm_power_off = msm_ps_hold_poweroff;
870 break; 881 break;
871 } 882 }
872} 883}
diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
new file mode 100644
index 000000000000..e9ff3bc150bb
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
@@ -0,0 +1,122 @@
1/*
2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * GPIO and pin control functions on this SOC are handled by the "TLMM"
14 * device. The driver which controls this device is pinctrl-msm.c. Each
15 * SOC with a TLMM is expected to create a client driver that registers
16 * with pinctrl-msm.c. This means that all TLMM drivers are pin control
17 * drivers.
18 *
19 * This pin control driver is intended to be used only an ACPI-enabled
20 * system. As such, UEFI will handle all pin control configuration, so
21 * this driver does not provide pin control functions. It is effectively
22 * a GPIO-only driver. The alternative is to duplicate the GPIO code of
23 * pinctrl-msm.c into another driver.
24 */
25
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/pinctrl/pinctrl.h>
29#include <linux/acpi.h>
30
31#include "pinctrl-msm.h"
32
33static struct msm_pinctrl_soc_data qdf2xxx_pinctrl;
34
35static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
36{
37 struct pinctrl_pin_desc *pins;
38 struct msm_pingroup *groups;
39 unsigned int i;
40 u32 num_gpios;
41 int ret;
42
43 /* Query the number of GPIOs from ACPI */
44 ret = device_property_read_u32(&pdev->dev, "num-gpios", &num_gpios);
45 if (ret < 0)
46 return ret;
47
48 if (!num_gpios) {
49 dev_warn(&pdev->dev, "missing num-gpios property\n");
50 return -ENODEV;
51 }
52
53 pins = devm_kcalloc(&pdev->dev, num_gpios,
54 sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
55 groups = devm_kcalloc(&pdev->dev, num_gpios,
56 sizeof(struct msm_pingroup), GFP_KERNEL);
57
58 for (i = 0; i < num_gpios; i++) {
59 pins[i].number = i;
60
61 groups[i].npins = 1,
62 groups[i].pins = &pins[i].number;
63 groups[i].ctl_reg = 0x10000 * i;
64 groups[i].io_reg = 0x04 + 0x10000 * i;
65 groups[i].intr_cfg_reg = 0x08 + 0x10000 * i;
66 groups[i].intr_status_reg = 0x0c + 0x10000 * i;
67 groups[i].intr_target_reg = 0x08 + 0x10000 * i;
68
69 groups[i].mux_bit = 2;
70 groups[i].pull_bit = 0;
71 groups[i].drv_bit = 6;
72 groups[i].oe_bit = 9;
73 groups[i].in_bit = 0;
74 groups[i].out_bit = 1;
75 groups[i].intr_enable_bit = 0;
76 groups[i].intr_status_bit = 0;
77 groups[i].intr_target_bit = 5;
78 groups[i].intr_target_kpss_val = 1;
79 groups[i].intr_raw_status_bit = 4;
80 groups[i].intr_polarity_bit = 1;
81 groups[i].intr_detection_bit = 2;
82 groups[i].intr_detection_width = 2;
83 }
84
85 qdf2xxx_pinctrl.pins = pins;
86 qdf2xxx_pinctrl.groups = groups;
87 qdf2xxx_pinctrl.npins = num_gpios;
88 qdf2xxx_pinctrl.ngroups = num_gpios;
89 qdf2xxx_pinctrl.ngpios = num_gpios;
90
91 return msm_pinctrl_probe(pdev, &qdf2xxx_pinctrl);
92}
93
94static const struct acpi_device_id qdf2xxx_acpi_ids[] = {
95 {"QCOM8001"},
96 {},
97};
98MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids);
99
100static struct platform_driver qdf2xxx_pinctrl_driver = {
101 .driver = {
102 .name = "qdf2xxx-pinctrl",
103 .acpi_match_table = ACPI_PTR(qdf2xxx_acpi_ids),
104 },
105 .probe = qdf2xxx_pinctrl_probe,
106 .remove = msm_pinctrl_remove,
107};
108
109static int __init qdf2xxx_pinctrl_init(void)
110{
111 return platform_driver_register(&qdf2xxx_pinctrl_driver);
112}
113arch_initcall(qdf2xxx_pinctrl_init);
114
115static void __exit qdf2xxx_pinctrl_exit(void)
116{
117 platform_driver_unregister(&qdf2xxx_pinctrl_driver);
118}
119module_exit(qdf2xxx_pinctrl_exit);
120
121MODULE_DESCRIPTION("Qualcomm Technologies QDF2xxx pin control driver");
122MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
index 3121de9b6331..e3be3ce2cada 100644
--- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
+++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
@@ -61,7 +61,9 @@
61#define PMIC_MPP_REG_DIG_PULL_CTL 0x42 61#define PMIC_MPP_REG_DIG_PULL_CTL 0x42
62#define PMIC_MPP_REG_DIG_IN_CTL 0x43 62#define PMIC_MPP_REG_DIG_IN_CTL 0x43
63#define PMIC_MPP_REG_EN_CTL 0x46 63#define PMIC_MPP_REG_EN_CTL 0x46
64#define PMIC_MPP_REG_AOUT_CTL 0x48
64#define PMIC_MPP_REG_AIN_CTL 0x4a 65#define PMIC_MPP_REG_AIN_CTL 0x4a
66#define PMIC_MPP_REG_SINK_CTL 0x4c
65 67
66/* PMIC_MPP_REG_MODE_CTL */ 68/* PMIC_MPP_REG_MODE_CTL */
67#define PMIC_MPP_REG_MODE_VALUE_MASK 0x1 69#define PMIC_MPP_REG_MODE_VALUE_MASK 0x1
@@ -85,11 +87,25 @@
85#define PMIC_MPP_REG_AIN_ROUTE_SHIFT 0 87#define PMIC_MPP_REG_AIN_ROUTE_SHIFT 0
86#define PMIC_MPP_REG_AIN_ROUTE_MASK 0x7 88#define PMIC_MPP_REG_AIN_ROUTE_MASK 0x7
87 89
90#define PMIC_MPP_MODE_DIGITAL_INPUT 0
91#define PMIC_MPP_MODE_DIGITAL_OUTPUT 1
92#define PMIC_MPP_MODE_DIGITAL_BIDIR 2
93#define PMIC_MPP_MODE_ANALOG_BIDIR 3
94#define PMIC_MPP_MODE_ANALOG_INPUT 4
95#define PMIC_MPP_MODE_ANALOG_OUTPUT 5
96#define PMIC_MPP_MODE_CURRENT_SINK 6
97
98#define PMIC_MPP_SELECTOR_NORMAL 0
99#define PMIC_MPP_SELECTOR_PAIRED 1
100#define PMIC_MPP_SELECTOR_DTEST_FIRST 4
101
88#define PMIC_MPP_PHYSICAL_OFFSET 1 102#define PMIC_MPP_PHYSICAL_OFFSET 1
89 103
90/* Qualcomm specific pin configurations */ 104/* Qualcomm specific pin configurations */
91#define PMIC_MPP_CONF_AMUX_ROUTE (PIN_CONFIG_END + 1) 105#define PMIC_MPP_CONF_AMUX_ROUTE (PIN_CONFIG_END + 1)
92#define PMIC_MPP_CONF_ANALOG_MODE (PIN_CONFIG_END + 2) 106#define PMIC_MPP_CONF_ANALOG_LEVEL (PIN_CONFIG_END + 2)
107#define PMIC_MPP_CONF_DTEST_SELECTOR (PIN_CONFIG_END + 3)
108#define PMIC_MPP_CONF_PAIRED (PIN_CONFIG_END + 4)
93 109
94/** 110/**
95 * struct pmic_mpp_pad - keep current MPP settings 111 * struct pmic_mpp_pad - keep current MPP settings
@@ -99,13 +115,15 @@
99 * @out_value: Cached pin output value. 115 * @out_value: Cached pin output value.
100 * @output_enabled: Set to true if MPP output logic is enabled. 116 * @output_enabled: Set to true if MPP output logic is enabled.
101 * @input_enabled: Set to true if MPP input buffer logic is enabled. 117 * @input_enabled: Set to true if MPP input buffer logic is enabled.
102 * @analog_mode: Set to true when MPP should operate in Analog Input, Analog 118 * @paired: Pin operates in paired mode
103 * Output or Bidirectional Analog mode.
104 * @num_sources: Number of power-sources supported by this MPP. 119 * @num_sources: Number of power-sources supported by this MPP.
105 * @power_source: Current power-source used. 120 * @power_source: Current power-source used.
106 * @amux_input: Set the source for analog input. 121 * @amux_input: Set the source for analog input.
122 * @aout_level: Analog output level
107 * @pullup: Pullup resistor value. Valid in Bidirectional mode only. 123 * @pullup: Pullup resistor value. Valid in Bidirectional mode only.
108 * @function: See pmic_mpp_functions[]. 124 * @function: See pmic_mpp_functions[].
125 * @drive_strength: Amount of current in sink mode
126 * @dtest: DTEST route selector
109 */ 127 */
110struct pmic_mpp_pad { 128struct pmic_mpp_pad {
111 u16 base; 129 u16 base;
@@ -114,12 +132,15 @@ struct pmic_mpp_pad {
114 bool out_value; 132 bool out_value;
115 bool output_enabled; 133 bool output_enabled;
116 bool input_enabled; 134 bool input_enabled;
117 bool analog_mode; 135 bool paired;
118 unsigned int num_sources; 136 unsigned int num_sources;
119 unsigned int power_source; 137 unsigned int power_source;
120 unsigned int amux_input; 138 unsigned int amux_input;
139 unsigned int aout_level;
121 unsigned int pullup; 140 unsigned int pullup;
122 unsigned int function; 141 unsigned int function;
142 unsigned int drive_strength;
143 unsigned int dtest;
123}; 144};
124 145
125struct pmic_mpp_state { 146struct pmic_mpp_state {
@@ -129,25 +150,32 @@ struct pmic_mpp_state {
129 struct gpio_chip chip; 150 struct gpio_chip chip;
130}; 151};
131 152
132struct pmic_mpp_bindings { 153static const struct pinconf_generic_params pmic_mpp_bindings[] = {
133 const char *property; 154 {"qcom,amux-route", PMIC_MPP_CONF_AMUX_ROUTE, 0},
134 unsigned param; 155 {"qcom,analog-level", PMIC_MPP_CONF_ANALOG_LEVEL, 0},
156 {"qcom,dtest", PMIC_MPP_CONF_DTEST_SELECTOR, 0},
157 {"qcom,paired", PMIC_MPP_CONF_PAIRED, 0},
135}; 158};
136 159
137static struct pmic_mpp_bindings pmic_mpp_bindings[] = { 160#ifdef CONFIG_DEBUG_FS
138 {"qcom,amux-route", PMIC_MPP_CONF_AMUX_ROUTE}, 161static const struct pin_config_item pmic_conf_items[] = {
139 {"qcom,analog-mode", PMIC_MPP_CONF_ANALOG_MODE}, 162 PCONFDUMP(PMIC_MPP_CONF_AMUX_ROUTE, "analog mux", NULL, true),
163 PCONFDUMP(PMIC_MPP_CONF_ANALOG_LEVEL, "analog level", NULL, true),
164 PCONFDUMP(PMIC_MPP_CONF_DTEST_SELECTOR, "dtest", NULL, true),
165 PCONFDUMP(PMIC_MPP_CONF_PAIRED, "paired", NULL, false),
140}; 166};
167#endif
141 168
142static const char *const pmic_mpp_groups[] = { 169static const char *const pmic_mpp_groups[] = {
143 "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", 170 "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8",
144}; 171};
145 172
173#define PMIC_MPP_DIGITAL 0
174#define PMIC_MPP_ANALOG 1
175#define PMIC_MPP_SINK 2
176
146static const char *const pmic_mpp_functions[] = { 177static const char *const pmic_mpp_functions[] = {
147 PMIC_MPP_FUNC_NORMAL, PMIC_MPP_FUNC_PAIRED, 178 "digital", "analog", "sink"
148 "reserved1", "reserved2",
149 PMIC_MPP_FUNC_DTEST1, PMIC_MPP_FUNC_DTEST2,
150 PMIC_MPP_FUNC_DTEST3, PMIC_MPP_FUNC_DTEST4,
151}; 179};
152 180
153static inline struct pmic_mpp_state *to_mpp_state(struct gpio_chip *chip) 181static inline struct pmic_mpp_state *to_mpp_state(struct gpio_chip *chip)
@@ -204,118 +232,11 @@ static int pmic_mpp_get_group_pins(struct pinctrl_dev *pctldev,
204 return 0; 232 return 0;
205} 233}
206 234
207static int pmic_mpp_parse_dt_config(struct device_node *np,
208 struct pinctrl_dev *pctldev,
209 unsigned long **configs,
210 unsigned int *nconfs)
211{
212 struct pmic_mpp_bindings *par;
213 unsigned long cfg;
214 int ret, i;
215 u32 val;
216
217 for (i = 0; i < ARRAY_SIZE(pmic_mpp_bindings); i++) {
218 par = &pmic_mpp_bindings[i];
219 ret = of_property_read_u32(np, par->property, &val);
220
221 /* property not found */
222 if (ret == -EINVAL)
223 continue;
224
225 /* use zero as default value, when no value is specified */
226 if (ret)
227 val = 0;
228
229 dev_dbg(pctldev->dev, "found %s with value %u\n",
230 par->property, val);
231
232 cfg = pinconf_to_config_packed(par->param, val);
233
234 ret = pinctrl_utils_add_config(pctldev, configs, nconfs, cfg);
235 if (ret)
236 return ret;
237 }
238
239 return 0;
240}
241
242static int pmic_mpp_dt_subnode_to_map(struct pinctrl_dev *pctldev,
243 struct device_node *np,
244 struct pinctrl_map **map,
245 unsigned *reserv, unsigned *nmaps,
246 enum pinctrl_map_type type)
247{
248 unsigned long *configs = NULL;
249 unsigned nconfs = 0;
250 struct property *prop;
251 const char *group;
252 int ret;
253
254 ret = pmic_mpp_parse_dt_config(np, pctldev, &configs, &nconfs);
255 if (ret < 0)
256 return ret;
257
258 if (!nconfs)
259 return 0;
260
261 ret = of_property_count_strings(np, "pins");
262 if (ret < 0)
263 goto exit;
264
265 ret = pinctrl_utils_reserve_map(pctldev, map, reserv, nmaps, ret);
266 if (ret < 0)
267 goto exit;
268
269 of_property_for_each_string(np, "pins", prop, group) {
270 ret = pinctrl_utils_add_map_configs(pctldev, map,
271 reserv, nmaps, group,
272 configs, nconfs, type);
273 if (ret < 0)
274 break;
275 }
276exit:
277 kfree(configs);
278 return ret;
279}
280
281static int pmic_mpp_dt_node_to_map(struct pinctrl_dev *pctldev,
282 struct device_node *np_config,
283 struct pinctrl_map **map, unsigned *nmaps)
284{
285 struct device_node *np;
286 enum pinctrl_map_type type;
287 unsigned reserv;
288 int ret;
289
290 ret = 0;
291 *map = NULL;
292 *nmaps = 0;
293 reserv = 0;
294 type = PIN_MAP_TYPE_CONFIGS_GROUP;
295
296 for_each_child_of_node(np_config, np) {
297 ret = pinconf_generic_dt_subnode_to_map(pctldev, np, map,
298 &reserv, nmaps, type);
299 if (ret)
300 break;
301
302 ret = pmic_mpp_dt_subnode_to_map(pctldev, np, map, &reserv,
303 nmaps, type);
304 if (ret)
305 break;
306 }
307
308 if (ret < 0)
309 pinctrl_utils_dt_free_map(pctldev, *map, *nmaps);
310
311 return ret;
312}
313
314static const struct pinctrl_ops pmic_mpp_pinctrl_ops = { 235static const struct pinctrl_ops pmic_mpp_pinctrl_ops = {
315 .get_groups_count = pmic_mpp_get_groups_count, 236 .get_groups_count = pmic_mpp_get_groups_count,
316 .get_group_name = pmic_mpp_get_group_name, 237 .get_group_name = pmic_mpp_get_group_name,
317 .get_group_pins = pmic_mpp_get_group_pins, 238 .get_group_pins = pmic_mpp_get_group_pins,
318 .dt_node_to_map = pmic_mpp_dt_node_to_map, 239 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
319 .dt_free_map = pinctrl_utils_dt_free_map, 240 .dt_free_map = pinctrl_utils_dt_free_map,
320}; 241};
321 242
@@ -340,6 +261,53 @@ static int pmic_mpp_get_function_groups(struct pinctrl_dev *pctldev,
340 return 0; 261 return 0;
341} 262}
342 263
264static int pmic_mpp_write_mode_ctl(struct pmic_mpp_state *state,
265 struct pmic_mpp_pad *pad)
266{
267 unsigned int mode;
268 unsigned int sel;
269 unsigned int val;
270 unsigned int en;
271
272 switch (pad->function) {
273 case PMIC_MPP_ANALOG:
274 if (pad->input_enabled && pad->output_enabled)
275 mode = PMIC_MPP_MODE_ANALOG_BIDIR;
276 else if (pad->input_enabled)
277 mode = PMIC_MPP_MODE_ANALOG_INPUT;
278 else
279 mode = PMIC_MPP_MODE_ANALOG_OUTPUT;
280 break;
281 case PMIC_MPP_DIGITAL:
282 if (pad->input_enabled && pad->output_enabled)
283 mode = PMIC_MPP_MODE_DIGITAL_BIDIR;
284 else if (pad->input_enabled)
285 mode = PMIC_MPP_MODE_DIGITAL_INPUT;
286 else
287 mode = PMIC_MPP_MODE_DIGITAL_OUTPUT;
288 break;
289 case PMIC_MPP_SINK:
290 default:
291 mode = PMIC_MPP_MODE_CURRENT_SINK;
292 break;
293 }
294
295 if (pad->dtest)
296 sel = PMIC_MPP_SELECTOR_DTEST_FIRST + pad->dtest - 1;
297 else if (pad->paired)
298 sel = PMIC_MPP_SELECTOR_PAIRED;
299 else
300 sel = PMIC_MPP_SELECTOR_NORMAL;
301
302 en = !!pad->out_value;
303
304 val = mode << PMIC_MPP_REG_MODE_DIR_SHIFT |
305 sel << PMIC_MPP_REG_MODE_FUNCTION_SHIFT |
306 en;
307
308 return pmic_mpp_write(state, pad, PMIC_MPP_REG_MODE_CTL, val);
309}
310
343static int pmic_mpp_set_mux(struct pinctrl_dev *pctldev, unsigned function, 311static int pmic_mpp_set_mux(struct pinctrl_dev *pctldev, unsigned function,
344 unsigned pin) 312 unsigned pin)
345{ 313{
@@ -352,31 +320,7 @@ static int pmic_mpp_set_mux(struct pinctrl_dev *pctldev, unsigned function,
352 320
353 pad->function = function; 321 pad->function = function;
354 322
355 if (!pad->analog_mode) { 323 ret = pmic_mpp_write_mode_ctl(state, pad);
356 val = 0; /* just digital input */
357 if (pad->output_enabled) {
358 if (pad->input_enabled)
359 val = 2; /* digital input and output */
360 else
361 val = 1; /* just digital output */
362 }
363 } else {
364 val = 4; /* just analog input */
365 if (pad->output_enabled) {
366 if (pad->input_enabled)
367 val = 3; /* analog input and output */
368 else
369 val = 5; /* just analog output */
370 }
371 }
372
373 val = val << PMIC_MPP_REG_MODE_DIR_SHIFT;
374 val |= pad->function << PMIC_MPP_REG_MODE_FUNCTION_SHIFT;
375 val |= pad->out_value & PMIC_MPP_REG_MODE_VALUE_MASK;
376
377 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_MODE_CTL, val);
378 if (ret < 0)
379 return ret;
380 324
381 val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT; 325 val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT;
382 326
@@ -433,11 +377,20 @@ static int pmic_mpp_config_get(struct pinctrl_dev *pctldev,
433 case PIN_CONFIG_OUTPUT: 377 case PIN_CONFIG_OUTPUT:
434 arg = pad->out_value; 378 arg = pad->out_value;
435 break; 379 break;
380 case PMIC_MPP_CONF_DTEST_SELECTOR:
381 arg = pad->dtest;
382 break;
436 case PMIC_MPP_CONF_AMUX_ROUTE: 383 case PMIC_MPP_CONF_AMUX_ROUTE:
437 arg = pad->amux_input; 384 arg = pad->amux_input;
438 break; 385 break;
439 case PMIC_MPP_CONF_ANALOG_MODE: 386 case PMIC_MPP_CONF_PAIRED:
440 arg = pad->analog_mode; 387 arg = pad->paired;
388 break;
389 case PIN_CONFIG_DRIVE_STRENGTH:
390 arg = pad->drive_strength;
391 break;
392 case PMIC_MPP_CONF_ANALOG_LEVEL:
393 arg = pad->aout_level;
441 break; 394 break;
442 default: 395 default:
443 return -EINVAL; 396 return -EINVAL;
@@ -459,6 +412,9 @@ static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
459 412
460 pad = pctldev->desc->pins[pin].drv_data; 413 pad = pctldev->desc->pins[pin].drv_data;
461 414
415 /* Make it possible to enable the pin, by not setting high impedance */
416 pad->is_enabled = true;
417
462 for (i = 0; i < nconfs; i++) { 418 for (i = 0; i < nconfs; i++) {
463 param = pinconf_to_config_param(configs[i]); 419 param = pinconf_to_config_param(configs[i]);
464 arg = pinconf_to_config_argument(configs[i]); 420 arg = pinconf_to_config_argument(configs[i]);
@@ -497,13 +453,22 @@ static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
497 pad->output_enabled = true; 453 pad->output_enabled = true;
498 pad->out_value = arg; 454 pad->out_value = arg;
499 break; 455 break;
456 case PMIC_MPP_CONF_DTEST_SELECTOR:
457 pad->dtest = arg;
458 break;
459 case PIN_CONFIG_DRIVE_STRENGTH:
460 arg = pad->drive_strength;
461 break;
500 case PMIC_MPP_CONF_AMUX_ROUTE: 462 case PMIC_MPP_CONF_AMUX_ROUTE:
501 if (arg >= PMIC_MPP_AMUX_ROUTE_ABUS4) 463 if (arg >= PMIC_MPP_AMUX_ROUTE_ABUS4)
502 return -EINVAL; 464 return -EINVAL;
503 pad->amux_input = arg; 465 pad->amux_input = arg;
504 break; 466 break;
505 case PMIC_MPP_CONF_ANALOG_MODE: 467 case PMIC_MPP_CONF_ANALOG_LEVEL:
506 pad->analog_mode = true; 468 pad->aout_level = arg;
469 break;
470 case PMIC_MPP_CONF_PAIRED:
471 pad->paired = !!arg;
507 break; 472 break;
508 default: 473 default:
509 return -EINVAL; 474 return -EINVAL;
@@ -528,29 +493,17 @@ static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
528 if (ret < 0) 493 if (ret < 0)
529 return ret; 494 return ret;
530 495
531 if (!pad->analog_mode) { 496 ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_AOUT_CTL, pad->aout_level);
532 val = 0; /* just digital input */ 497 if (ret < 0)
533 if (pad->output_enabled) { 498 return ret;
534 if (pad->input_enabled) 499
535 val = 2; /* digital input and output */ 500 ret = pmic_mpp_write_mode_ctl(state, pad);
536 else 501 if (ret < 0)
537 val = 1; /* just digital output */ 502 return ret;
538 }
539 } else {
540 val = 4; /* just analog input */
541 if (pad->output_enabled) {
542 if (pad->input_enabled)
543 val = 3; /* analog input and output */
544 else
545 val = 5; /* just analog output */
546 }
547 }
548 503
549 val = val << PMIC_MPP_REG_MODE_DIR_SHIFT; 504 val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT;
550 val |= pad->function << PMIC_MPP_REG_MODE_FUNCTION_SHIFT;
551 val |= pad->out_value & PMIC_MPP_REG_MODE_VALUE_MASK;
552 505
553 return pmic_mpp_write(state, pad, PMIC_MPP_REG_MODE_CTL, val); 506 return pmic_mpp_write(state, pad, PMIC_MPP_REG_EN_CTL, val);
554} 507}
555 508
556static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev, 509static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev,
@@ -558,20 +511,17 @@ static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev,
558{ 511{
559 struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev); 512 struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev);
560 struct pmic_mpp_pad *pad; 513 struct pmic_mpp_pad *pad;
561 int ret, val; 514 int ret;
562 515
563 static const char *const biases[] = { 516 static const char *const biases[] = {
564 "0.6kOhm", "10kOhm", "30kOhm", "Disabled" 517 "0.6kOhm", "10kOhm", "30kOhm", "Disabled"
565 }; 518 };
566 519
567
568 pad = pctldev->desc->pins[pin].drv_data; 520 pad = pctldev->desc->pins[pin].drv_data;
569 521
570 seq_printf(s, " mpp%-2d:", pin + PMIC_MPP_PHYSICAL_OFFSET); 522 seq_printf(s, " mpp%-2d:", pin + PMIC_MPP_PHYSICAL_OFFSET);
571 523
572 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_EN_CTL); 524 if (!pad->is_enabled) {
573
574 if (val < 0 || !(val >> PMIC_MPP_REG_MASTER_EN_SHIFT)) {
575 seq_puts(s, " ---"); 525 seq_puts(s, " ---");
576 } else { 526 } else {
577 527
@@ -585,15 +535,20 @@ static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev,
585 } 535 }
586 536
587 seq_printf(s, " %-4s", pad->output_enabled ? "out" : "in"); 537 seq_printf(s, " %-4s", pad->output_enabled ? "out" : "in");
588 seq_printf(s, " %-4s", pad->analog_mode ? "ana" : "dig");
589 seq_printf(s, " %-7s", pmic_mpp_functions[pad->function]); 538 seq_printf(s, " %-7s", pmic_mpp_functions[pad->function]);
590 seq_printf(s, " vin-%d", pad->power_source); 539 seq_printf(s, " vin-%d", pad->power_source);
540 seq_printf(s, " %d", pad->aout_level);
591 seq_printf(s, " %-8s", biases[pad->pullup]); 541 seq_printf(s, " %-8s", biases[pad->pullup]);
592 seq_printf(s, " %-4s", pad->out_value ? "high" : "low"); 542 seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
543 if (pad->dtest)
544 seq_printf(s, " dtest%d", pad->dtest);
545 if (pad->paired)
546 seq_puts(s, " paired");
593 } 547 }
594} 548}
595 549
596static const struct pinconf_ops pmic_mpp_pinconf_ops = { 550static const struct pinconf_ops pmic_mpp_pinconf_ops = {
551 .is_generic = true,
597 .pin_config_group_get = pmic_mpp_config_get, 552 .pin_config_group_get = pmic_mpp_config_get,
598 .pin_config_group_set = pmic_mpp_config_set, 553 .pin_config_group_set = pmic_mpp_config_set,
599 .pin_config_group_dbg_show = pmic_mpp_config_dbg_show, 554 .pin_config_group_dbg_show = pmic_mpp_config_dbg_show,
@@ -709,6 +664,7 @@ static int pmic_mpp_populate(struct pmic_mpp_state *state,
709 struct pmic_mpp_pad *pad) 664 struct pmic_mpp_pad *pad)
710{ 665{
711 int type, subtype, val, dir; 666 int type, subtype, val, dir;
667 unsigned int sel;
712 668
713 type = pmic_mpp_read(state, pad, PMIC_MPP_REG_TYPE); 669 type = pmic_mpp_read(state, pad, PMIC_MPP_REG_TYPE);
714 if (type < 0) 670 if (type < 0)
@@ -751,43 +707,53 @@ static int pmic_mpp_populate(struct pmic_mpp_state *state,
751 dir &= PMIC_MPP_REG_MODE_DIR_MASK; 707 dir &= PMIC_MPP_REG_MODE_DIR_MASK;
752 708
753 switch (dir) { 709 switch (dir) {
754 case 0: 710 case PMIC_MPP_MODE_DIGITAL_INPUT:
755 pad->input_enabled = true; 711 pad->input_enabled = true;
756 pad->output_enabled = false; 712 pad->output_enabled = false;
757 pad->analog_mode = false; 713 pad->function = PMIC_MPP_DIGITAL;
758 break; 714 break;
759 case 1: 715 case PMIC_MPP_MODE_DIGITAL_OUTPUT:
760 pad->input_enabled = false; 716 pad->input_enabled = false;
761 pad->output_enabled = true; 717 pad->output_enabled = true;
762 pad->analog_mode = false; 718 pad->function = PMIC_MPP_DIGITAL;
763 break; 719 break;
764 case 2: 720 case PMIC_MPP_MODE_DIGITAL_BIDIR:
765 pad->input_enabled = true; 721 pad->input_enabled = true;
766 pad->output_enabled = true; 722 pad->output_enabled = true;
767 pad->analog_mode = false; 723 pad->function = PMIC_MPP_DIGITAL;
768 break; 724 break;
769 case 3: 725 case PMIC_MPP_MODE_ANALOG_BIDIR:
770 pad->input_enabled = true; 726 pad->input_enabled = true;
771 pad->output_enabled = true; 727 pad->output_enabled = true;
772 pad->analog_mode = true; 728 pad->function = PMIC_MPP_ANALOG;
773 break; 729 break;
774 case 4: 730 case PMIC_MPP_MODE_ANALOG_INPUT:
775 pad->input_enabled = true; 731 pad->input_enabled = true;
776 pad->output_enabled = false; 732 pad->output_enabled = false;
777 pad->analog_mode = true; 733 pad->function = PMIC_MPP_ANALOG;
778 break; 734 break;
779 case 5: 735 case PMIC_MPP_MODE_ANALOG_OUTPUT:
780 pad->input_enabled = false; 736 pad->input_enabled = false;
781 pad->output_enabled = true; 737 pad->output_enabled = true;
782 pad->analog_mode = true; 738 pad->function = PMIC_MPP_ANALOG;
739 break;
740 case PMIC_MPP_MODE_CURRENT_SINK:
741 pad->input_enabled = false;
742 pad->output_enabled = true;
743 pad->function = PMIC_MPP_SINK;
783 break; 744 break;
784 default: 745 default:
785 dev_err(state->dev, "unknown MPP direction\n"); 746 dev_err(state->dev, "unknown MPP direction\n");
786 return -ENODEV; 747 return -ENODEV;
787 } 748 }
788 749
789 pad->function = val >> PMIC_MPP_REG_MODE_FUNCTION_SHIFT; 750 sel = val >> PMIC_MPP_REG_MODE_FUNCTION_SHIFT;
790 pad->function &= PMIC_MPP_REG_MODE_FUNCTION_MASK; 751 sel &= PMIC_MPP_REG_MODE_FUNCTION_MASK;
752
753 if (sel >= PMIC_MPP_SELECTOR_DTEST_FIRST)
754 pad->dtest = sel + 1;
755 else if (sel == PMIC_MPP_SELECTOR_PAIRED)
756 pad->paired = true;
791 757
792 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_VIN_CTL); 758 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_VIN_CTL);
793 if (val < 0) 759 if (val < 0)
@@ -810,8 +776,24 @@ static int pmic_mpp_populate(struct pmic_mpp_state *state,
810 pad->amux_input = val >> PMIC_MPP_REG_AIN_ROUTE_SHIFT; 776 pad->amux_input = val >> PMIC_MPP_REG_AIN_ROUTE_SHIFT;
811 pad->amux_input &= PMIC_MPP_REG_AIN_ROUTE_MASK; 777 pad->amux_input &= PMIC_MPP_REG_AIN_ROUTE_MASK;
812 778
813 /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */ 779 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_SINK_CTL);
814 pad->is_enabled = true; 780 if (val < 0)
781 return val;
782
783 pad->drive_strength = val;
784
785 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AOUT_CTL);
786 if (val < 0)
787 return val;
788
789 pad->aout_level = val;
790
791 val = pmic_mpp_read(state, pad, PMIC_MPP_REG_EN_CTL);
792 if (val < 0)
793 return val;
794
795 pad->is_enabled = !!val;
796
815 return 0; 797 return 0;
816} 798}
817 799
@@ -866,6 +848,12 @@ static int pmic_mpp_probe(struct platform_device *pdev)
866 pctrldesc->pins = pindesc; 848 pctrldesc->pins = pindesc;
867 pctrldesc->npins = npins; 849 pctrldesc->npins = npins;
868 850
851 pctrldesc->num_custom_params = ARRAY_SIZE(pmic_mpp_bindings);
852 pctrldesc->custom_params = pmic_mpp_bindings;
853#ifdef CONFIG_DEBUG_FS
854 pctrldesc->custom_conf_items = pmic_conf_items;
855#endif
856
869 for (i = 0; i < npins; i++, pindesc++) { 857 for (i = 0; i < npins; i++, pindesc++) {
870 pad = &pads[i]; 858 pad = &pads[i];
871 pindesc->drv_data = pad; 859 pindesc->drv_data = pad;
diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c
new file mode 100644
index 000000000000..c978b311031b
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c
@@ -0,0 +1,791 @@
1/*
2 * Copyright (c) 2015, Sony Mobile Communications AB.
3 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 and
7 * only version 2 as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/module.h>
16#include <linux/platform_device.h>
17#include <linux/pinctrl/pinctrl.h>
18#include <linux/pinctrl/pinmux.h>
19#include <linux/pinctrl/pinconf.h>
20#include <linux/pinctrl/pinconf-generic.h>
21#include <linux/slab.h>
22#include <linux/regmap.h>
23#include <linux/gpio.h>
24#include <linux/interrupt.h>
25#include <linux/of_device.h>
26
27#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
28
29#include "../core.h"
30#include "../pinctrl-utils.h"
31
32/* mode */
33#define PM8XXX_GPIO_MODE_ENABLED BIT(0)
34#define PM8XXX_GPIO_MODE_INPUT 0
35#define PM8XXX_GPIO_MODE_OUTPUT 2
36
37/* output buffer */
38#define PM8XXX_GPIO_PUSH_PULL 0
39#define PM8XXX_GPIO_OPEN_DRAIN 1
40
41/* bias */
42#define PM8XXX_GPIO_BIAS_PU_30 0
43#define PM8XXX_GPIO_BIAS_PU_1P5 1
44#define PM8XXX_GPIO_BIAS_PU_31P5 2
45#define PM8XXX_GPIO_BIAS_PU_1P5_30 3
46#define PM8XXX_GPIO_BIAS_PD 4
47#define PM8XXX_GPIO_BIAS_NP 5
48
49/* GPIO registers */
50#define SSBI_REG_ADDR_GPIO_BASE 0x150
51#define SSBI_REG_ADDR_GPIO(n) (SSBI_REG_ADDR_GPIO_BASE + n)
52
53#define PM8XXX_BANK_WRITE BIT(7)
54
55#define PM8XXX_MAX_GPIOS 44
56
57/* custom pinconf parameters */
58#define PM8XXX_QCOM_DRIVE_STRENGH (PIN_CONFIG_END + 1)
59#define PM8XXX_QCOM_PULL_UP_STRENGTH (PIN_CONFIG_END + 2)
60
61/**
62 * struct pm8xxx_pin_data - dynamic configuration for a pin
63 * @reg: address of the control register
64 * @irq: IRQ from the PMIC interrupt controller
65 * @power_source: logical selected voltage source, mapping in static data
66 * is used translate to register values
67 * @mode: operating mode for the pin (input/output)
68 * @open_drain: output buffer configured as open-drain (vs push-pull)
69 * @output_value: configured output value
70 * @bias: register view of configured bias
71 * @pull_up_strength: placeholder for selected pull up strength
72 * only used to configure bias when pull up is selected
73 * @output_strength: selector of output-strength
74 * @disable: pin disabled / configured as tristate
75 * @function: pinmux selector
76 * @inverted: pin logic is inverted
77 */
78struct pm8xxx_pin_data {
79 unsigned reg;
80 int irq;
81 u8 power_source;
82 u8 mode;
83 bool open_drain;
84 bool output_value;
85 u8 bias;
86 u8 pull_up_strength;
87 u8 output_strength;
88 bool disable;
89 u8 function;
90 bool inverted;
91};
92
93struct pm8xxx_gpio {
94 struct device *dev;
95 struct regmap *regmap;
96 struct pinctrl_dev *pctrl;
97 struct gpio_chip chip;
98
99 struct pinctrl_desc desc;
100 unsigned npins;
101};
102
103static const struct pinconf_generic_params pm8xxx_gpio_bindings[] = {
104 {"qcom,drive-strength", PM8XXX_QCOM_DRIVE_STRENGH, 0},
105 {"qcom,pull-up-strength", PM8XXX_QCOM_PULL_UP_STRENGTH, 0},
106};
107
108#ifdef CONFIG_DEBUG_FS
109static const struct pin_config_item pm8xxx_conf_items[ARRAY_SIZE(pm8xxx_gpio_bindings)] = {
110 PCONFDUMP(PM8XXX_QCOM_DRIVE_STRENGH, "drive-strength", NULL, true),
111 PCONFDUMP(PM8XXX_QCOM_PULL_UP_STRENGTH, "pull up strength", NULL, true),
112};
113#endif
114
115static const char * const pm8xxx_groups[PM8XXX_MAX_GPIOS] = {
116 "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
117 "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
118 "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
119 "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
120 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
121 "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
122 "gpio44",
123};
124
125static const char * const pm8xxx_gpio_functions[] = {
126 PMIC_GPIO_FUNC_NORMAL, PMIC_GPIO_FUNC_PAIRED,
127 PMIC_GPIO_FUNC_FUNC1, PMIC_GPIO_FUNC_FUNC2,
128 PMIC_GPIO_FUNC_DTEST1, PMIC_GPIO_FUNC_DTEST2,
129 PMIC_GPIO_FUNC_DTEST3, PMIC_GPIO_FUNC_DTEST4,
130};
131
132static int pm8xxx_read_bank(struct pm8xxx_gpio *pctrl,
133 struct pm8xxx_pin_data *pin, int bank)
134{
135 unsigned int val = bank << 4;
136 int ret;
137
138 ret = regmap_write(pctrl->regmap, pin->reg, val);
139 if (ret) {
140 dev_err(pctrl->dev, "failed to select bank %d\n", bank);
141 return ret;
142 }
143
144 ret = regmap_read(pctrl->regmap, pin->reg, &val);
145 if (ret) {
146 dev_err(pctrl->dev, "failed to read register %d\n", bank);
147 return ret;
148 }
149
150 return val;
151}
152
153static int pm8xxx_write_bank(struct pm8xxx_gpio *pctrl,
154 struct pm8xxx_pin_data *pin,
155 int bank,
156 u8 val)
157{
158 int ret;
159
160 val |= PM8XXX_BANK_WRITE;
161 val |= bank << 4;
162
163 ret = regmap_write(pctrl->regmap, pin->reg, val);
164 if (ret)
165 dev_err(pctrl->dev, "failed to write register\n");
166
167 return ret;
168}
169
170static int pm8xxx_get_groups_count(struct pinctrl_dev *pctldev)
171{
172 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
173
174 return pctrl->npins;
175}
176
177static const char *pm8xxx_get_group_name(struct pinctrl_dev *pctldev,
178 unsigned group)
179{
180 return pm8xxx_groups[group];
181}
182
183
184static int pm8xxx_get_group_pins(struct pinctrl_dev *pctldev,
185 unsigned group,
186 const unsigned **pins,
187 unsigned *num_pins)
188{
189 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
190
191 *pins = &pctrl->desc.pins[group].number;
192 *num_pins = 1;
193
194 return 0;
195}
196
197static const struct pinctrl_ops pm8xxx_pinctrl_ops = {
198 .get_groups_count = pm8xxx_get_groups_count,
199 .get_group_name = pm8xxx_get_group_name,
200 .get_group_pins = pm8xxx_get_group_pins,
201 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
202 .dt_free_map = pinctrl_utils_dt_free_map,
203};
204
205static int pm8xxx_get_functions_count(struct pinctrl_dev *pctldev)
206{
207 return ARRAY_SIZE(pm8xxx_gpio_functions);
208}
209
210static const char *pm8xxx_get_function_name(struct pinctrl_dev *pctldev,
211 unsigned function)
212{
213 return pm8xxx_gpio_functions[function];
214}
215
216static int pm8xxx_get_function_groups(struct pinctrl_dev *pctldev,
217 unsigned function,
218 const char * const **groups,
219 unsigned * const num_groups)
220{
221 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
222
223 *groups = pm8xxx_groups;
224 *num_groups = pctrl->npins;
225 return 0;
226}
227
228static int pm8xxx_pinmux_set_mux(struct pinctrl_dev *pctldev,
229 unsigned function,
230 unsigned group)
231{
232 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
233 struct pm8xxx_pin_data *pin = pctrl->desc.pins[group].drv_data;
234 u8 val;
235
236 pin->function = function;
237 val = pin->function << 1;
238
239 pm8xxx_write_bank(pctrl, pin, 4, val);
240
241 return 0;
242}
243
244static const struct pinmux_ops pm8xxx_pinmux_ops = {
245 .get_functions_count = pm8xxx_get_functions_count,
246 .get_function_name = pm8xxx_get_function_name,
247 .get_function_groups = pm8xxx_get_function_groups,
248 .set_mux = pm8xxx_pinmux_set_mux,
249};
250
251static int pm8xxx_pin_config_get(struct pinctrl_dev *pctldev,
252 unsigned int offset,
253 unsigned long *config)
254{
255 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
256 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
257 unsigned param = pinconf_to_config_param(*config);
258 unsigned arg;
259
260 switch (param) {
261 case PIN_CONFIG_BIAS_DISABLE:
262 arg = pin->bias == PM8XXX_GPIO_BIAS_NP;
263 break;
264 case PIN_CONFIG_BIAS_PULL_DOWN:
265 arg = pin->bias == PM8XXX_GPIO_BIAS_PD;
266 break;
267 case PIN_CONFIG_BIAS_PULL_UP:
268 arg = pin->bias <= PM8XXX_GPIO_BIAS_PU_1P5_30;
269 break;
270 case PM8XXX_QCOM_PULL_UP_STRENGTH:
271 arg = pin->pull_up_strength;
272 break;
273 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
274 arg = pin->disable;
275 break;
276 case PIN_CONFIG_INPUT_ENABLE:
277 arg = pin->mode == PM8XXX_GPIO_MODE_INPUT;
278 break;
279 case PIN_CONFIG_OUTPUT:
280 if (pin->mode & PM8XXX_GPIO_MODE_OUTPUT)
281 arg = pin->output_value;
282 else
283 arg = 0;
284 break;
285 case PIN_CONFIG_POWER_SOURCE:
286 arg = pin->power_source;
287 break;
288 case PM8XXX_QCOM_DRIVE_STRENGH:
289 arg = pin->output_strength;
290 break;
291 case PIN_CONFIG_DRIVE_PUSH_PULL:
292 arg = !pin->open_drain;
293 break;
294 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
295 arg = pin->open_drain;
296 break;
297 default:
298 return -EINVAL;
299 }
300
301 *config = pinconf_to_config_packed(param, arg);
302
303 return 0;
304}
305
306static int pm8xxx_pin_config_set(struct pinctrl_dev *pctldev,
307 unsigned int offset,
308 unsigned long *configs,
309 unsigned num_configs)
310{
311 struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
312 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
313 unsigned param;
314 unsigned arg;
315 unsigned i;
316 u8 banks = 0;
317 u8 val;
318
319 for (i = 0; i < num_configs; i++) {
320 param = pinconf_to_config_param(configs[i]);
321 arg = pinconf_to_config_argument(configs[i]);
322
323 switch (param) {
324 case PIN_CONFIG_BIAS_DISABLE:
325 pin->bias = PM8XXX_GPIO_BIAS_NP;
326 banks |= BIT(2);
327 pin->disable = 0;
328 banks |= BIT(3);
329 break;
330 case PIN_CONFIG_BIAS_PULL_DOWN:
331 pin->bias = PM8XXX_GPIO_BIAS_PD;
332 banks |= BIT(2);
333 pin->disable = 0;
334 banks |= BIT(3);
335 break;
336 case PM8XXX_QCOM_PULL_UP_STRENGTH:
337 if (arg > PM8XXX_GPIO_BIAS_PU_1P5_30) {
338 dev_err(pctrl->dev, "invalid pull-up strength\n");
339 return -EINVAL;
340 }
341 pin->pull_up_strength = arg;
342 /* FALLTHROUGH */
343 case PIN_CONFIG_BIAS_PULL_UP:
344 pin->bias = pin->pull_up_strength;
345 banks |= BIT(2);
346 pin->disable = 0;
347 banks |= BIT(3);
348 break;
349 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
350 pin->disable = 1;
351 banks |= BIT(3);
352 break;
353 case PIN_CONFIG_INPUT_ENABLE:
354 pin->mode = PM8XXX_GPIO_MODE_INPUT;
355 banks |= BIT(0) | BIT(1);
356 break;
357 case PIN_CONFIG_OUTPUT:
358 pin->mode = PM8XXX_GPIO_MODE_OUTPUT;
359 pin->output_value = !!arg;
360 banks |= BIT(0) | BIT(1);
361 break;
362 case PIN_CONFIG_POWER_SOURCE:
363 pin->power_source = arg;
364 banks |= BIT(0);
365 break;
366 case PM8XXX_QCOM_DRIVE_STRENGH:
367 if (arg > PMIC_GPIO_STRENGTH_LOW) {
368 dev_err(pctrl->dev, "invalid drive strength\n");
369 return -EINVAL;
370 }
371 pin->output_strength = arg;
372 banks |= BIT(3);
373 break;
374 case PIN_CONFIG_DRIVE_PUSH_PULL:
375 pin->open_drain = 0;
376 banks |= BIT(1);
377 break;
378 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
379 pin->open_drain = 1;
380 banks |= BIT(1);
381 break;
382 default:
383 dev_err(pctrl->dev,
384 "unsupported config parameter: %x\n",
385 param);
386 return -EINVAL;
387 }
388 }
389
390 if (banks & BIT(0)) {
391 val = pin->power_source << 1;
392 val |= PM8XXX_GPIO_MODE_ENABLED;
393 pm8xxx_write_bank(pctrl, pin, 0, val);
394 }
395
396 if (banks & BIT(1)) {
397 val = pin->mode << 2;
398 val |= pin->open_drain << 1;
399 val |= pin->output_value;
400 pm8xxx_write_bank(pctrl, pin, 1, val);
401 }
402
403 if (banks & BIT(2)) {
404 val = pin->bias << 1;
405 pm8xxx_write_bank(pctrl, pin, 2, val);
406 }
407
408 if (banks & BIT(3)) {
409 val = pin->output_strength << 2;
410 val |= pin->disable;
411 pm8xxx_write_bank(pctrl, pin, 3, val);
412 }
413
414 if (banks & BIT(4)) {
415 val = pin->function << 1;
416 pm8xxx_write_bank(pctrl, pin, 4, val);
417 }
418
419 if (banks & BIT(5)) {
420 val = 0;
421 if (!pin->inverted)
422 val |= BIT(3);
423 pm8xxx_write_bank(pctrl, pin, 5, val);
424 }
425
426 return 0;
427}
428
429static const struct pinconf_ops pm8xxx_pinconf_ops = {
430 .is_generic = true,
431 .pin_config_group_get = pm8xxx_pin_config_get,
432 .pin_config_group_set = pm8xxx_pin_config_set,
433};
434
435static struct pinctrl_desc pm8xxx_pinctrl_desc = {
436 .name = "pm8xxx_gpio",
437 .pctlops = &pm8xxx_pinctrl_ops,
438 .pmxops = &pm8xxx_pinmux_ops,
439 .confops = &pm8xxx_pinconf_ops,
440 .owner = THIS_MODULE,
441};
442
443static int pm8xxx_gpio_direction_input(struct gpio_chip *chip,
444 unsigned offset)
445{
446 struct pm8xxx_gpio *pctrl = container_of(chip, struct pm8xxx_gpio, chip);
447 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
448 u8 val;
449
450 pin->mode = PM8XXX_GPIO_MODE_INPUT;
451 val = pin->mode << 2;
452
453 pm8xxx_write_bank(pctrl, pin, 1, val);
454
455 return 0;
456}
457
458static int pm8xxx_gpio_direction_output(struct gpio_chip *chip,
459 unsigned offset,
460 int value)
461{
462 struct pm8xxx_gpio *pctrl = container_of(chip, struct pm8xxx_gpio, chip);
463 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
464 u8 val;
465
466 pin->mode = PM8XXX_GPIO_MODE_OUTPUT;
467 pin->output_value = !!value;
468
469 val = pin->mode << 2;
470 val |= pin->open_drain << 1;
471 val |= pin->output_value;
472
473 pm8xxx_write_bank(pctrl, pin, 1, val);
474
475 return 0;
476}
477
478static int pm8xxx_gpio_get(struct gpio_chip *chip, unsigned offset)
479{
480 struct pm8xxx_gpio *pctrl = container_of(chip, struct pm8xxx_gpio, chip);
481 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
482 bool state;
483 int ret;
484
485 if (pin->mode == PM8XXX_GPIO_MODE_OUTPUT) {
486 ret = pin->output_value;
487 } else {
488 ret = irq_get_irqchip_state(pin->irq, IRQCHIP_STATE_LINE_LEVEL, &state);
489 if (!ret)
490 ret = !!state;
491 }
492
493 return ret;
494}
495
496static void pm8xxx_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
497{
498 struct pm8xxx_gpio *pctrl = container_of(chip, struct pm8xxx_gpio, chip);
499 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
500 u8 val;
501
502 pin->output_value = !!value;
503
504 val = pin->mode << 2;
505 val |= pin->open_drain << 1;
506 val |= pin->output_value;
507
508 pm8xxx_write_bank(pctrl, pin, 1, val);
509}
510
511static int pm8xxx_gpio_of_xlate(struct gpio_chip *chip,
512 const struct of_phandle_args *gpio_desc,
513 u32 *flags)
514{
515 if (chip->of_gpio_n_cells < 2)
516 return -EINVAL;
517
518 if (flags)
519 *flags = gpio_desc->args[1];
520
521 return gpio_desc->args[0] - 1;
522}
523
524
525static int pm8xxx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
526{
527 struct pm8xxx_gpio *pctrl = container_of(chip, struct pm8xxx_gpio, chip);
528 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
529
530 return pin->irq;
531}
532
533#ifdef CONFIG_DEBUG_FS
534#include <linux/seq_file.h>
535
536static void pm8xxx_gpio_dbg_show_one(struct seq_file *s,
537 struct pinctrl_dev *pctldev,
538 struct gpio_chip *chip,
539 unsigned offset,
540 unsigned gpio)
541{
542 struct pm8xxx_gpio *pctrl = container_of(chip, struct pm8xxx_gpio, chip);
543 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
544
545 static const char * const modes[] = {
546 "in", "both", "out", "off"
547 };
548 static const char * const biases[] = {
549 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
550 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
551 };
552 static const char * const buffer_types[] = {
553 "push-pull", "open-drain"
554 };
555 static const char * const strengths[] = {
556 "no", "high", "medium", "low"
557 };
558
559 seq_printf(s, " gpio%-2d:", offset + 1);
560 if (pin->disable) {
561 seq_puts(s, " ---");
562 } else {
563 seq_printf(s, " %-4s", modes[pin->mode]);
564 seq_printf(s, " %-7s", pm8xxx_gpio_functions[pin->function]);
565 seq_printf(s, " VIN%d", pin->power_source);
566 seq_printf(s, " %-27s", biases[pin->bias]);
567 seq_printf(s, " %-10s", buffer_types[pin->open_drain]);
568 seq_printf(s, " %-4s", pin->output_value ? "high" : "low");
569 seq_printf(s, " %-7s", strengths[pin->output_strength]);
570 if (pin->inverted)
571 seq_puts(s, " inverted");
572 }
573}
574
575static void pm8xxx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
576{
577 unsigned gpio = chip->base;
578 unsigned i;
579
580 for (i = 0; i < chip->ngpio; i++, gpio++) {
581 pm8xxx_gpio_dbg_show_one(s, NULL, chip, i, gpio);
582 seq_puts(s, "\n");
583 }
584}
585
586#else
587#define msm_gpio_dbg_show NULL
588#endif
589
590static struct gpio_chip pm8xxx_gpio_template = {
591 .direction_input = pm8xxx_gpio_direction_input,
592 .direction_output = pm8xxx_gpio_direction_output,
593 .get = pm8xxx_gpio_get,
594 .set = pm8xxx_gpio_set,
595 .of_xlate = pm8xxx_gpio_of_xlate,
596 .to_irq = pm8xxx_gpio_to_irq,
597 .dbg_show = pm8xxx_gpio_dbg_show,
598 .owner = THIS_MODULE,
599};
600
601static int pm8xxx_pin_populate(struct pm8xxx_gpio *pctrl,
602 struct pm8xxx_pin_data *pin)
603{
604 int val;
605
606 val = pm8xxx_read_bank(pctrl, pin, 0);
607 if (val < 0)
608 return val;
609
610 pin->power_source = (val >> 1) & 0x7;
611
612 val = pm8xxx_read_bank(pctrl, pin, 1);
613 if (val < 0)
614 return val;
615
616 pin->mode = (val >> 2) & 0x3;
617 pin->open_drain = !!(val & BIT(1));
618 pin->output_value = val & BIT(0);
619
620 val = pm8xxx_read_bank(pctrl, pin, 2);
621 if (val < 0)
622 return val;
623
624 pin->bias = (val >> 1) & 0x7;
625 if (pin->bias <= PM8XXX_GPIO_BIAS_PU_1P5_30)
626 pin->pull_up_strength = pin->bias;
627 else
628 pin->pull_up_strength = PM8XXX_GPIO_BIAS_PU_30;
629
630 val = pm8xxx_read_bank(pctrl, pin, 3);
631 if (val < 0)
632 return val;
633
634 pin->output_strength = (val >> 2) & 0x3;
635 pin->disable = val & BIT(0);
636
637 val = pm8xxx_read_bank(pctrl, pin, 4);
638 if (val < 0)
639 return val;
640
641 pin->function = (val >> 1) & 0x7;
642
643 val = pm8xxx_read_bank(pctrl, pin, 5);
644 if (val < 0)
645 return val;
646
647 pin->inverted = !(val & BIT(3));
648
649 return 0;
650}
651
652static const struct of_device_id pm8xxx_gpio_of_match[] = {
653 { .compatible = "qcom,pm8018-gpio", .data = (void *)6 },
654 { .compatible = "qcom,pm8038-gpio", .data = (void *)12 },
655 { .compatible = "qcom,pm8058-gpio", .data = (void *)40 },
656 { .compatible = "qcom,pm8917-gpio", .data = (void *)38 },
657 { .compatible = "qcom,pm8921-gpio", .data = (void *)44 },
658 { },
659};
660MODULE_DEVICE_TABLE(of, pm8xxx_gpio_of_match);
661
662static int pm8xxx_gpio_probe(struct platform_device *pdev)
663{
664 struct pm8xxx_pin_data *pin_data;
665 struct pinctrl_pin_desc *pins;
666 struct pm8xxx_gpio *pctrl;
667 int ret;
668 int i;
669
670 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
671 if (!pctrl)
672 return -ENOMEM;
673
674 pctrl->dev = &pdev->dev;
675 pctrl->npins = (unsigned)of_device_get_match_data(&pdev->dev);
676
677 pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL);
678 if (!pctrl->regmap) {
679 dev_err(&pdev->dev, "parent regmap unavailable\n");
680 return -ENXIO;
681 }
682
683 pctrl->desc = pm8xxx_pinctrl_desc;
684 pctrl->desc.npins = pctrl->npins;
685
686 pins = devm_kcalloc(&pdev->dev,
687 pctrl->desc.npins,
688 sizeof(struct pinctrl_pin_desc),
689 GFP_KERNEL);
690 if (!pins)
691 return -ENOMEM;
692
693 pin_data = devm_kcalloc(&pdev->dev,
694 pctrl->desc.npins,
695 sizeof(struct pm8xxx_pin_data),
696 GFP_KERNEL);
697 if (!pin_data)
698 return -ENOMEM;
699
700 for (i = 0; i < pctrl->desc.npins; i++) {
701 pin_data[i].reg = SSBI_REG_ADDR_GPIO(i);
702 pin_data[i].irq = platform_get_irq(pdev, i);
703 if (pin_data[i].irq < 0) {
704 dev_err(&pdev->dev,
705 "missing interrupts for pin %d\n", i);
706 return pin_data[i].irq;
707 }
708
709 ret = pm8xxx_pin_populate(pctrl, &pin_data[i]);
710 if (ret)
711 return ret;
712
713 pins[i].number = i;
714 pins[i].name = pm8xxx_groups[i];
715 pins[i].drv_data = &pin_data[i];
716 }
717 pctrl->desc.pins = pins;
718
719 pctrl->desc.num_custom_params = ARRAY_SIZE(pm8xxx_gpio_bindings);
720 pctrl->desc.custom_params = pm8xxx_gpio_bindings;
721#ifdef CONFIG_DEBUG_FS
722 pctrl->desc.custom_conf_items = pm8xxx_conf_items;
723#endif
724
725 pctrl->pctrl = pinctrl_register(&pctrl->desc, &pdev->dev, pctrl);
726 if (!pctrl->pctrl) {
727 dev_err(&pdev->dev, "couldn't register pm8xxx gpio driver\n");
728 return -ENODEV;
729 }
730
731 pctrl->chip = pm8xxx_gpio_template;
732 pctrl->chip.base = -1;
733 pctrl->chip.dev = &pdev->dev;
734 pctrl->chip.of_node = pdev->dev.of_node;
735 pctrl->chip.of_gpio_n_cells = 2;
736 pctrl->chip.label = dev_name(pctrl->dev);
737 pctrl->chip.ngpio = pctrl->npins;
738 ret = gpiochip_add(&pctrl->chip);
739 if (ret) {
740 dev_err(&pdev->dev, "failed register gpiochip\n");
741 goto unregister_pinctrl;
742 }
743
744 ret = gpiochip_add_pin_range(&pctrl->chip,
745 dev_name(pctrl->dev),
746 0, 0, pctrl->chip.ngpio);
747 if (ret) {
748 dev_err(pctrl->dev, "failed to add pin range\n");
749 goto unregister_gpiochip;
750 }
751
752 platform_set_drvdata(pdev, pctrl);
753
754 dev_dbg(&pdev->dev, "Qualcomm pm8xxx gpio driver probed\n");
755
756 return 0;
757
758unregister_gpiochip:
759 gpiochip_remove(&pctrl->chip);
760
761unregister_pinctrl:
762 pinctrl_unregister(pctrl->pctrl);
763
764 return ret;
765}
766
767static int pm8xxx_gpio_remove(struct platform_device *pdev)
768{
769 struct pm8xxx_gpio *pctrl = platform_get_drvdata(pdev);
770
771 gpiochip_remove(&pctrl->chip);
772
773 pinctrl_unregister(pctrl->pctrl);
774
775 return 0;
776}
777
778static struct platform_driver pm8xxx_gpio_driver = {
779 .driver = {
780 .name = "qcom-ssbi-gpio",
781 .of_match_table = pm8xxx_gpio_of_match,
782 },
783 .probe = pm8xxx_gpio_probe,
784 .remove = pm8xxx_gpio_remove,
785};
786
787module_platform_driver(pm8xxx_gpio_driver);
788
789MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");
790MODULE_DESCRIPTION("Qualcomm PM8xxx GPIO driver");
791MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c
new file mode 100644
index 000000000000..2d1b69f171be
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c
@@ -0,0 +1,882 @@
1/*
2 * Copyright (c) 2015, Sony Mobile Communications AB.
3 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 and
7 * only version 2 as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/module.h>
16#include <linux/platform_device.h>
17#include <linux/pinctrl/pinctrl.h>
18#include <linux/pinctrl/pinmux.h>
19#include <linux/pinctrl/pinconf.h>
20#include <linux/pinctrl/pinconf-generic.h>
21#include <linux/slab.h>
22#include <linux/regmap.h>
23#include <linux/gpio.h>
24#include <linux/interrupt.h>
25#include <linux/of_device.h>
26
27#include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
28
29#include "../core.h"
30#include "../pinctrl-utils.h"
31
32/* MPP registers */
33#define SSBI_REG_ADDR_MPP_BASE 0x50
34#define SSBI_REG_ADDR_MPP(n) (SSBI_REG_ADDR_MPP_BASE + n)
35
36/* MPP Type: type */
37#define PM8XXX_MPP_TYPE_D_INPUT 0
38#define PM8XXX_MPP_TYPE_D_OUTPUT 1
39#define PM8XXX_MPP_TYPE_D_BI_DIR 2
40#define PM8XXX_MPP_TYPE_A_INPUT 3
41#define PM8XXX_MPP_TYPE_A_OUTPUT 4
42#define PM8XXX_MPP_TYPE_SINK 5
43#define PM8XXX_MPP_TYPE_DTEST_SINK 6
44#define PM8XXX_MPP_TYPE_DTEST_OUTPUT 7
45
46/* Digital Input: control */
47#define PM8XXX_MPP_DIN_TO_INT 0
48#define PM8XXX_MPP_DIN_TO_DBUS1 1
49#define PM8XXX_MPP_DIN_TO_DBUS2 2
50#define PM8XXX_MPP_DIN_TO_DBUS3 3
51
52/* Digital Output: control */
53#define PM8XXX_MPP_DOUT_CTRL_LOW 0
54#define PM8XXX_MPP_DOUT_CTRL_HIGH 1
55#define PM8XXX_MPP_DOUT_CTRL_MPP 2
56#define PM8XXX_MPP_DOUT_CTRL_INV_MPP 3
57
58/* Bidirectional: control */
59#define PM8XXX_MPP_BI_PULLUP_1KOHM 0
60#define PM8XXX_MPP_BI_PULLUP_OPEN 1
61#define PM8XXX_MPP_BI_PULLUP_10KOHM 2
62#define PM8XXX_MPP_BI_PULLUP_30KOHM 3
63
64/* Analog Output: control */
65#define PM8XXX_MPP_AOUT_CTRL_DISABLE 0
66#define PM8XXX_MPP_AOUT_CTRL_ENABLE 1
67#define PM8XXX_MPP_AOUT_CTRL_MPP_HIGH_EN 2
68#define PM8XXX_MPP_AOUT_CTRL_MPP_LOW_EN 3
69
70/* Current Sink: control */
71#define PM8XXX_MPP_CS_CTRL_DISABLE 0
72#define PM8XXX_MPP_CS_CTRL_ENABLE 1
73#define PM8XXX_MPP_CS_CTRL_MPP_HIGH_EN 2
74#define PM8XXX_MPP_CS_CTRL_MPP_LOW_EN 3
75
76/* DTEST Current Sink: control */
77#define PM8XXX_MPP_DTEST_CS_CTRL_EN1 0
78#define PM8XXX_MPP_DTEST_CS_CTRL_EN2 1
79#define PM8XXX_MPP_DTEST_CS_CTRL_EN3 2
80#define PM8XXX_MPP_DTEST_CS_CTRL_EN4 3
81
82/* DTEST Digital Output: control */
83#define PM8XXX_MPP_DTEST_DBUS1 0
84#define PM8XXX_MPP_DTEST_DBUS2 1
85#define PM8XXX_MPP_DTEST_DBUS3 2
86#define PM8XXX_MPP_DTEST_DBUS4 3
87
88/* custom pinconf parameters */
89#define PM8XXX_CONFIG_AMUX (PIN_CONFIG_END + 1)
90#define PM8XXX_CONFIG_DTEST_SELECTOR (PIN_CONFIG_END + 2)
91#define PM8XXX_CONFIG_ALEVEL (PIN_CONFIG_END + 3)
92#define PM8XXX_CONFIG_PAIRED (PIN_CONFIG_END + 4)
93
94/**
95 * struct pm8xxx_pin_data - dynamic configuration for a pin
96 * @reg: address of the control register
97 * @irq: IRQ from the PMIC interrupt controller
98 * @mode: operating mode for the pin (digital, analog or current sink)
99 * @input: pin is input
100 * @output: pin is output
101 * @high_z: pin is floating
102 * @paired: mpp operates in paired mode
103 * @output_value: logical output value of the mpp
104 * @power_source: selected power source
105 * @dtest: DTEST route selector
106 * @amux: input muxing in analog mode
107 * @aout_level: selector of the output in analog mode
108 * @drive_strength: drive strength of the current sink
109 * @pullup: pull up value, when in digital bidirectional mode
110 */
111struct pm8xxx_pin_data {
112 unsigned reg;
113 int irq;
114
115 u8 mode;
116
117 bool input;
118 bool output;
119 bool high_z;
120 bool paired;
121 bool output_value;
122
123 u8 power_source;
124 u8 dtest;
125 u8 amux;
126 u8 aout_level;
127 u8 drive_strength;
128 unsigned pullup;
129};
130
131struct pm8xxx_mpp {
132 struct device *dev;
133 struct regmap *regmap;
134 struct pinctrl_dev *pctrl;
135 struct gpio_chip chip;
136
137 struct pinctrl_desc desc;
138 unsigned npins;
139};
140
141static const struct pinconf_generic_params pm8xxx_mpp_bindings[] = {
142 {"qcom,amux-route", PM8XXX_CONFIG_AMUX, 0},
143 {"qcom,analog-level", PM8XXX_CONFIG_ALEVEL, 0},
144 {"qcom,dtest", PM8XXX_CONFIG_DTEST_SELECTOR, 0},
145 {"qcom,paired", PM8XXX_CONFIG_PAIRED, 0},
146};
147
148#ifdef CONFIG_DEBUG_FS
149static const struct pin_config_item pm8xxx_conf_items[] = {
150 PCONFDUMP(PM8XXX_CONFIG_AMUX, "analog mux", NULL, true),
151 PCONFDUMP(PM8XXX_CONFIG_ALEVEL, "analog level", NULL, true),
152 PCONFDUMP(PM8XXX_CONFIG_DTEST_SELECTOR, "dtest", NULL, true),
153 PCONFDUMP(PM8XXX_CONFIG_PAIRED, "paired", NULL, false),
154};
155#endif
156
157#define PM8XXX_MAX_MPPS 12
158static const char * const pm8xxx_groups[PM8XXX_MAX_MPPS] = {
159 "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8",
160 "mpp9", "mpp10", "mpp11", "mpp12",
161};
162
163#define PM8XXX_MPP_DIGITAL 0
164#define PM8XXX_MPP_ANALOG 1
165#define PM8XXX_MPP_SINK 2
166
167static const char * const pm8xxx_mpp_functions[] = {
168 "digital", "analog", "sink",
169};
170
171static int pm8xxx_mpp_update(struct pm8xxx_mpp *pctrl,
172 struct pm8xxx_pin_data *pin)
173{
174 unsigned level;
175 unsigned ctrl;
176 unsigned type;
177 int ret;
178 u8 val;
179
180 switch (pin->mode) {
181 case PM8XXX_MPP_DIGITAL:
182 if (pin->dtest) {
183 type = PM8XXX_MPP_TYPE_DTEST_OUTPUT;
184 ctrl = pin->dtest - 1;
185 } else if (pin->input && pin->output) {
186 type = PM8XXX_MPP_TYPE_D_BI_DIR;
187 if (pin->high_z)
188 ctrl = PM8XXX_MPP_BI_PULLUP_OPEN;
189 else if (pin->pullup == 600)
190 ctrl = PM8XXX_MPP_BI_PULLUP_1KOHM;
191 else if (pin->pullup == 10000)
192 ctrl = PM8XXX_MPP_BI_PULLUP_10KOHM;
193 else
194 ctrl = PM8XXX_MPP_BI_PULLUP_30KOHM;
195 } else if (pin->input) {
196 type = PM8XXX_MPP_TYPE_D_INPUT;
197 if (pin->dtest)
198 ctrl = pin->dtest;
199 else
200 ctrl = PM8XXX_MPP_DIN_TO_INT;
201 } else {
202 type = PM8XXX_MPP_TYPE_D_OUTPUT;
203 ctrl = !!pin->output_value;
204 if (pin->paired)
205 ctrl |= BIT(1);
206 }
207
208 level = pin->power_source;
209 break;
210 case PM8XXX_MPP_ANALOG:
211 if (pin->output) {
212 type = PM8XXX_MPP_TYPE_A_OUTPUT;
213 level = pin->aout_level;
214 ctrl = pin->output_value;
215 if (pin->paired)
216 ctrl |= BIT(1);
217 } else {
218 type = PM8XXX_MPP_TYPE_A_INPUT;
219 level = pin->amux;
220 ctrl = 0;
221 }
222 break;
223 case PM8XXX_MPP_SINK:
224 level = (pin->drive_strength / 5) - 1;
225 if (pin->dtest) {
226 type = PM8XXX_MPP_TYPE_DTEST_SINK;
227 ctrl = pin->dtest - 1;
228 } else {
229 type = PM8XXX_MPP_TYPE_SINK;
230 ctrl = pin->output_value;
231 if (pin->paired)
232 ctrl |= BIT(1);
233 }
234 break;
235 default:
236 return -EINVAL;
237 }
238
239 val = type << 5 | level << 2 | ctrl;
240 ret = regmap_write(pctrl->regmap, pin->reg, val);
241 if (ret)
242 dev_err(pctrl->dev, "failed to write register\n");
243
244 return ret;
245}
246
247static int pm8xxx_get_groups_count(struct pinctrl_dev *pctldev)
248{
249 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev);
250
251 return pctrl->npins;
252}
253
254static const char *pm8xxx_get_group_name(struct pinctrl_dev *pctldev,
255 unsigned group)
256{
257 return pm8xxx_groups[group];
258}
259
260
261static int pm8xxx_get_group_pins(struct pinctrl_dev *pctldev,
262 unsigned group,
263 const unsigned **pins,
264 unsigned *num_pins)
265{
266 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev);
267
268 *pins = &pctrl->desc.pins[group].number;
269 *num_pins = 1;
270
271 return 0;
272}
273
274static const struct pinctrl_ops pm8xxx_pinctrl_ops = {
275 .get_groups_count = pm8xxx_get_groups_count,
276 .get_group_name = pm8xxx_get_group_name,
277 .get_group_pins = pm8xxx_get_group_pins,
278 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
279 .dt_free_map = pinctrl_utils_dt_free_map,
280};
281
282static int pm8xxx_get_functions_count(struct pinctrl_dev *pctldev)
283{
284 return ARRAY_SIZE(pm8xxx_mpp_functions);
285}
286
287static const char *pm8xxx_get_function_name(struct pinctrl_dev *pctldev,
288 unsigned function)
289{
290 return pm8xxx_mpp_functions[function];
291}
292
293static int pm8xxx_get_function_groups(struct pinctrl_dev *pctldev,
294 unsigned function,
295 const char * const **groups,
296 unsigned * const num_groups)
297{
298 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev);
299
300 *groups = pm8xxx_groups;
301 *num_groups = pctrl->npins;
302 return 0;
303}
304
305static int pm8xxx_pinmux_set_mux(struct pinctrl_dev *pctldev,
306 unsigned function,
307 unsigned group)
308{
309 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev);
310 struct pm8xxx_pin_data *pin = pctrl->desc.pins[group].drv_data;
311
312 pin->mode = function;
313 pm8xxx_mpp_update(pctrl, pin);
314
315 return 0;
316}
317
318static const struct pinmux_ops pm8xxx_pinmux_ops = {
319 .get_functions_count = pm8xxx_get_functions_count,
320 .get_function_name = pm8xxx_get_function_name,
321 .get_function_groups = pm8xxx_get_function_groups,
322 .set_mux = pm8xxx_pinmux_set_mux,
323};
324
325static int pm8xxx_pin_config_get(struct pinctrl_dev *pctldev,
326 unsigned int offset,
327 unsigned long *config)
328{
329 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev);
330 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
331 unsigned param = pinconf_to_config_param(*config);
332 unsigned arg;
333
334 switch (param) {
335 case PIN_CONFIG_BIAS_PULL_UP:
336 arg = pin->pullup;
337 break;
338 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
339 arg = pin->high_z;
340 break;
341 case PIN_CONFIG_INPUT_ENABLE:
342 arg = pin->input;
343 break;
344 case PIN_CONFIG_OUTPUT:
345 arg = pin->output_value;
346 break;
347 case PIN_CONFIG_POWER_SOURCE:
348 arg = pin->power_source;
349 break;
350 case PIN_CONFIG_DRIVE_STRENGTH:
351 arg = pin->drive_strength;
352 break;
353 case PM8XXX_CONFIG_DTEST_SELECTOR:
354 arg = pin->dtest;
355 break;
356 case PM8XXX_CONFIG_AMUX:
357 arg = pin->amux;
358 break;
359 case PM8XXX_CONFIG_ALEVEL:
360 arg = pin->aout_level;
361 break;
362 case PM8XXX_CONFIG_PAIRED:
363 arg = pin->paired;
364 break;
365 default:
366 return -EINVAL;
367 }
368
369 *config = pinconf_to_config_packed(param, arg);
370
371 return 0;
372}
373
374static int pm8xxx_pin_config_set(struct pinctrl_dev *pctldev,
375 unsigned int offset,
376 unsigned long *configs,
377 unsigned num_configs)
378{
379 struct pm8xxx_mpp *pctrl = pinctrl_dev_get_drvdata(pctldev);
380 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
381 unsigned param;
382 unsigned arg;
383 unsigned i;
384
385 for (i = 0; i < num_configs; i++) {
386 param = pinconf_to_config_param(configs[i]);
387 arg = pinconf_to_config_argument(configs[i]);
388
389 switch (param) {
390 case PIN_CONFIG_BIAS_PULL_UP:
391 pin->pullup = arg;
392 break;
393 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
394 pin->high_z = true;
395 break;
396 case PIN_CONFIG_INPUT_ENABLE:
397 pin->input = true;
398 break;
399 case PIN_CONFIG_OUTPUT:
400 pin->output = true;
401 pin->output_value = !!arg;
402 break;
403 case PIN_CONFIG_POWER_SOURCE:
404 pin->power_source = arg;
405 break;
406 case PIN_CONFIG_DRIVE_STRENGTH:
407 pin->drive_strength = arg;
408 break;
409 case PM8XXX_CONFIG_DTEST_SELECTOR:
410 pin->dtest = arg;
411 break;
412 case PM8XXX_CONFIG_AMUX:
413 pin->amux = arg;
414 break;
415 case PM8XXX_CONFIG_ALEVEL:
416 pin->aout_level = arg;
417 break;
418 case PM8XXX_CONFIG_PAIRED:
419 pin->paired = !!arg;
420 break;
421 default:
422 dev_err(pctrl->dev,
423 "unsupported config parameter: %x\n",
424 param);
425 return -EINVAL;
426 }
427 }
428
429 pm8xxx_mpp_update(pctrl, pin);
430
431 return 0;
432}
433
434static const struct pinconf_ops pm8xxx_pinconf_ops = {
435 .is_generic = true,
436 .pin_config_group_get = pm8xxx_pin_config_get,
437 .pin_config_group_set = pm8xxx_pin_config_set,
438};
439
440static struct pinctrl_desc pm8xxx_pinctrl_desc = {
441 .name = "pm8xxx_mpp",
442 .pctlops = &pm8xxx_pinctrl_ops,
443 .pmxops = &pm8xxx_pinmux_ops,
444 .confops = &pm8xxx_pinconf_ops,
445 .owner = THIS_MODULE,
446};
447
448static int pm8xxx_mpp_direction_input(struct gpio_chip *chip,
449 unsigned offset)
450{
451 struct pm8xxx_mpp *pctrl = container_of(chip, struct pm8xxx_mpp, chip);
452 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
453
454 switch (pin->mode) {
455 case PM8XXX_MPP_DIGITAL:
456 pin->input = true;
457 break;
458 case PM8XXX_MPP_ANALOG:
459 pin->input = true;
460 pin->output = true;
461 break;
462 case PM8XXX_MPP_SINK:
463 return -EINVAL;
464 }
465
466 pm8xxx_mpp_update(pctrl, pin);
467
468 return 0;
469}
470
471static int pm8xxx_mpp_direction_output(struct gpio_chip *chip,
472 unsigned offset,
473 int value)
474{
475 struct pm8xxx_mpp *pctrl = container_of(chip, struct pm8xxx_mpp, chip);
476 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
477
478 switch (pin->mode) {
479 case PM8XXX_MPP_DIGITAL:
480 pin->output = true;
481 break;
482 case PM8XXX_MPP_ANALOG:
483 pin->input = false;
484 pin->output = true;
485 break;
486 case PM8XXX_MPP_SINK:
487 pin->input = false;
488 pin->output = true;
489 break;
490 }
491
492 pm8xxx_mpp_update(pctrl, pin);
493
494 return 0;
495}
496
497static int pm8xxx_mpp_get(struct gpio_chip *chip, unsigned offset)
498{
499 struct pm8xxx_mpp *pctrl = container_of(chip, struct pm8xxx_mpp, chip);
500 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
501 bool state;
502 int ret;
503
504 if (!pin->input)
505 return pin->output_value;
506
507 ret = irq_get_irqchip_state(pin->irq, IRQCHIP_STATE_LINE_LEVEL, &state);
508 if (!ret)
509 ret = !!state;
510
511 return ret;
512}
513
514static void pm8xxx_mpp_set(struct gpio_chip *chip, unsigned offset, int value)
515{
516 struct pm8xxx_mpp *pctrl = container_of(chip, struct pm8xxx_mpp, chip);
517 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
518
519 pin->output_value = !!value;
520
521 pm8xxx_mpp_update(pctrl, pin);
522}
523
524static int pm8xxx_mpp_of_xlate(struct gpio_chip *chip,
525 const struct of_phandle_args *gpio_desc,
526 u32 *flags)
527{
528 if (chip->of_gpio_n_cells < 2)
529 return -EINVAL;
530
531 if (flags)
532 *flags = gpio_desc->args[1];
533
534 return gpio_desc->args[0] - 1;
535}
536
537
538static int pm8xxx_mpp_to_irq(struct gpio_chip *chip, unsigned offset)
539{
540 struct pm8xxx_mpp *pctrl = container_of(chip, struct pm8xxx_mpp, chip);
541 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
542
543 return pin->irq;
544}
545
546#ifdef CONFIG_DEBUG_FS
547#include <linux/seq_file.h>
548
549static void pm8xxx_mpp_dbg_show_one(struct seq_file *s,
550 struct pinctrl_dev *pctldev,
551 struct gpio_chip *chip,
552 unsigned offset,
553 unsigned gpio)
554{
555 struct pm8xxx_mpp *pctrl = container_of(chip, struct pm8xxx_mpp, chip);
556 struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
557
558 static const char * const aout_lvls[] = {
559 "1v25", "1v25_2", "0v625", "0v3125", "mpp", "abus1", "abus2",
560 "abus3"
561 };
562
563 static const char * const amuxs[] = {
564 "amux5", "amux6", "amux7", "amux8", "amux9", "abus1", "abus2",
565 "abus3",
566 };
567
568 seq_printf(s, " mpp%-2d:", offset + 1);
569
570 switch (pin->mode) {
571 case PM8XXX_MPP_DIGITAL:
572 seq_puts(s, " digital ");
573 if (pin->dtest) {
574 seq_printf(s, "dtest%d\n", pin->dtest);
575 } else if (pin->input && pin->output) {
576 if (pin->high_z)
577 seq_puts(s, "bi-dir high-z");
578 else
579 seq_printf(s, "bi-dir %dOhm", pin->pullup);
580 } else if (pin->input) {
581 if (pin->dtest)
582 seq_printf(s, "in dtest%d", pin->dtest);
583 else
584 seq_puts(s, "in gpio");
585 } else if (pin->output) {
586 seq_puts(s, "out ");
587
588 if (!pin->paired) {
589 seq_puts(s, pin->output_value ?
590 "high" : "low");
591 } else {
592 seq_puts(s, pin->output_value ?
593 "inverted" : "follow");
594 }
595 }
596 break;
597 case PM8XXX_MPP_ANALOG:
598 seq_puts(s, " analog ");
599 if (pin->output) {
600 seq_printf(s, "out %s ", aout_lvls[pin->aout_level]);
601 if (!pin->paired) {
602 seq_puts(s, pin->output_value ?
603 "high" : "low");
604 } else {
605 seq_puts(s, pin->output_value ?
606 "inverted" : "follow");
607 }
608 } else {
609 seq_printf(s, "input mux %s", amuxs[pin->amux]);
610 }
611 break;
612 case PM8XXX_MPP_SINK:
613 seq_printf(s, " sink %dmA ", pin->drive_strength);
614 if (pin->dtest) {
615 seq_printf(s, "dtest%d", pin->dtest);
616 } else {
617 if (!pin->paired) {
618 seq_puts(s, pin->output_value ?
619 "high" : "low");
620 } else {
621 seq_puts(s, pin->output_value ?
622 "inverted" : "follow");
623 }
624 }
625 break;
626 }
627
628}
629
630static void pm8xxx_mpp_dbg_show(struct seq_file *s, struct gpio_chip *chip)
631{
632 unsigned gpio = chip->base;
633 unsigned i;
634
635 for (i = 0; i < chip->ngpio; i++, gpio++) {
636 pm8xxx_mpp_dbg_show_one(s, NULL, chip, i, gpio);
637 seq_puts(s, "\n");
638 }
639}
640
641#else
642#define msm_mpp_dbg_show NULL
643#endif
644
645static struct gpio_chip pm8xxx_mpp_template = {
646 .direction_input = pm8xxx_mpp_direction_input,
647 .direction_output = pm8xxx_mpp_direction_output,
648 .get = pm8xxx_mpp_get,
649 .set = pm8xxx_mpp_set,
650 .of_xlate = pm8xxx_mpp_of_xlate,
651 .to_irq = pm8xxx_mpp_to_irq,
652 .dbg_show = pm8xxx_mpp_dbg_show,
653 .owner = THIS_MODULE,
654};
655
656static int pm8xxx_pin_populate(struct pm8xxx_mpp *pctrl,
657 struct pm8xxx_pin_data *pin)
658{
659 unsigned int val;
660 unsigned level;
661 unsigned ctrl;
662 unsigned type;
663 int ret;
664
665 ret = regmap_read(pctrl->regmap, pin->reg, &val);
666 if (ret) {
667 dev_err(pctrl->dev, "failed to read register\n");
668 return ret;
669 }
670
671 type = (val >> 5) & 7;
672 level = (val >> 2) & 7;
673 ctrl = (val) & 3;
674
675 switch (type) {
676 case PM8XXX_MPP_TYPE_D_INPUT:
677 pin->mode = PM8XXX_MPP_DIGITAL;
678 pin->input = true;
679 pin->power_source = level;
680 pin->dtest = ctrl;
681 break;
682 case PM8XXX_MPP_TYPE_D_OUTPUT:
683 pin->mode = PM8XXX_MPP_DIGITAL;
684 pin->output = true;
685 pin->power_source = level;
686 pin->output_value = !!(ctrl & BIT(0));
687 pin->paired = !!(ctrl & BIT(1));
688 break;
689 case PM8XXX_MPP_TYPE_D_BI_DIR:
690 pin->mode = PM8XXX_MPP_DIGITAL;
691 pin->input = true;
692 pin->output = true;
693 pin->power_source = level;
694 switch (ctrl) {
695 case PM8XXX_MPP_BI_PULLUP_1KOHM:
696 pin->pullup = 600;
697 break;
698 case PM8XXX_MPP_BI_PULLUP_OPEN:
699 pin->high_z = true;
700 break;
701 case PM8XXX_MPP_BI_PULLUP_10KOHM:
702 pin->pullup = 10000;
703 break;
704 case PM8XXX_MPP_BI_PULLUP_30KOHM:
705 pin->pullup = 30000;
706 break;
707 }
708 break;
709 case PM8XXX_MPP_TYPE_A_INPUT:
710 pin->mode = PM8XXX_MPP_ANALOG;
711 pin->input = true;
712 pin->amux = level;
713 break;
714 case PM8XXX_MPP_TYPE_A_OUTPUT:
715 pin->mode = PM8XXX_MPP_ANALOG;
716 pin->output = true;
717 pin->aout_level = level;
718 pin->output_value = !!(ctrl & BIT(0));
719 pin->paired = !!(ctrl & BIT(1));
720 break;
721 case PM8XXX_MPP_TYPE_SINK:
722 pin->mode = PM8XXX_MPP_SINK;
723 pin->drive_strength = 5 * (level + 1);
724 pin->output_value = !!(ctrl & BIT(0));
725 pin->paired = !!(ctrl & BIT(1));
726 break;
727 case PM8XXX_MPP_TYPE_DTEST_SINK:
728 pin->mode = PM8XXX_MPP_SINK;
729 pin->dtest = ctrl + 1;
730 pin->drive_strength = 5 * (level + 1);
731 break;
732 case PM8XXX_MPP_TYPE_DTEST_OUTPUT:
733 pin->mode = PM8XXX_MPP_DIGITAL;
734 pin->power_source = level;
735 if (ctrl >= 1)
736 pin->dtest = ctrl;
737 break;
738 }
739
740 return 0;
741}
742
743static const struct of_device_id pm8xxx_mpp_of_match[] = {
744 { .compatible = "qcom,pm8018-mpp", .data = (void *)6 },
745 { .compatible = "qcom,pm8038-mpp", .data = (void *)6 },
746 { .compatible = "qcom,pm8917-mpp", .data = (void *)10 },
747 { .compatible = "qcom,pm8821-mpp", .data = (void *)4 },
748 { .compatible = "qcom,pm8921-mpp", .data = (void *)12 },
749 { },
750};
751MODULE_DEVICE_TABLE(of, pm8xxx_mpp_of_match);
752
753static int pm8xxx_mpp_probe(struct platform_device *pdev)
754{
755 struct pm8xxx_pin_data *pin_data;
756 struct pinctrl_pin_desc *pins;
757 struct pm8xxx_mpp *pctrl;
758 int ret;
759 int i;
760
761 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
762 if (!pctrl)
763 return -ENOMEM;
764
765 pctrl->dev = &pdev->dev;
766 pctrl->npins = (unsigned)of_device_get_match_data(&pdev->dev);
767
768 pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL);
769 if (!pctrl->regmap) {
770 dev_err(&pdev->dev, "parent regmap unavailable\n");
771 return -ENXIO;
772 }
773
774 pctrl->desc = pm8xxx_pinctrl_desc;
775 pctrl->desc.npins = pctrl->npins;
776
777 pins = devm_kcalloc(&pdev->dev,
778 pctrl->desc.npins,
779 sizeof(struct pinctrl_pin_desc),
780 GFP_KERNEL);
781 if (!pins)
782 return -ENOMEM;
783
784 pin_data = devm_kcalloc(&pdev->dev,
785 pctrl->desc.npins,
786 sizeof(struct pm8xxx_pin_data),
787 GFP_KERNEL);
788 if (!pin_data)
789 return -ENOMEM;
790
791 for (i = 0; i < pctrl->desc.npins; i++) {
792 pin_data[i].reg = SSBI_REG_ADDR_MPP(i);
793 pin_data[i].irq = platform_get_irq(pdev, i);
794 if (pin_data[i].irq < 0) {
795 dev_err(&pdev->dev,
796 "missing interrupts for pin %d\n", i);
797 return pin_data[i].irq;
798 }
799
800 ret = pm8xxx_pin_populate(pctrl, &pin_data[i]);
801 if (ret)
802 return ret;
803
804 pins[i].number = i;
805 pins[i].name = pm8xxx_groups[i];
806 pins[i].drv_data = &pin_data[i];
807 }
808 pctrl->desc.pins = pins;
809
810 pctrl->desc.num_custom_params = ARRAY_SIZE(pm8xxx_mpp_bindings);
811 pctrl->desc.custom_params = pm8xxx_mpp_bindings;
812#ifdef CONFIG_DEBUG_FS
813 pctrl->desc.custom_conf_items = pm8xxx_conf_items;
814#endif
815
816 pctrl->pctrl = pinctrl_register(&pctrl->desc, &pdev->dev, pctrl);
817 if (!pctrl->pctrl) {
818 dev_err(&pdev->dev, "couldn't register pm8xxx mpp driver\n");
819 return -ENODEV;
820 }
821
822 pctrl->chip = pm8xxx_mpp_template;
823 pctrl->chip.base = -1;
824 pctrl->chip.dev = &pdev->dev;
825 pctrl->chip.of_node = pdev->dev.of_node;
826 pctrl->chip.of_gpio_n_cells = 2;
827 pctrl->chip.label = dev_name(pctrl->dev);
828 pctrl->chip.ngpio = pctrl->npins;
829 ret = gpiochip_add(&pctrl->chip);
830 if (ret) {
831 dev_err(&pdev->dev, "failed register gpiochip\n");
832 goto unregister_pinctrl;
833 }
834
835 ret = gpiochip_add_pin_range(&pctrl->chip,
836 dev_name(pctrl->dev),
837 0, 0, pctrl->chip.ngpio);
838 if (ret) {
839 dev_err(pctrl->dev, "failed to add pin range\n");
840 goto unregister_gpiochip;
841 }
842
843 platform_set_drvdata(pdev, pctrl);
844
845 dev_dbg(&pdev->dev, "Qualcomm pm8xxx mpp driver probed\n");
846
847 return 0;
848
849unregister_gpiochip:
850 gpiochip_remove(&pctrl->chip);
851
852unregister_pinctrl:
853 pinctrl_unregister(pctrl->pctrl);
854
855 return ret;
856}
857
858static int pm8xxx_mpp_remove(struct platform_device *pdev)
859{
860 struct pm8xxx_mpp *pctrl = platform_get_drvdata(pdev);
861
862 gpiochip_remove(&pctrl->chip);
863
864 pinctrl_unregister(pctrl->pctrl);
865
866 return 0;
867}
868
869static struct platform_driver pm8xxx_mpp_driver = {
870 .driver = {
871 .name = "qcom-ssbi-mpp",
872 .of_match_table = pm8xxx_mpp_of_match,
873 },
874 .probe = pm8xxx_mpp_probe,
875 .remove = pm8xxx_mpp_remove,
876};
877
878module_platform_driver(pm8xxx_mpp_driver);
879
880MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");
881MODULE_DESCRIPTION("Qualcomm PM8xxx MPP driver");
882MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index b18dabba03a4..5f45caaef46d 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -148,9 +148,9 @@ static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
148 } 148 }
149 149
150 if (type & IRQ_TYPE_EDGE_BOTH) 150 if (type & IRQ_TYPE_EDGE_BOTH)
151 __irq_set_handler_locked(irqd->irq, handle_edge_irq); 151 irq_set_handler_locked(irqd, handle_edge_irq);
152 else 152 else
153 __irq_set_handler_locked(irqd->irq, handle_level_irq); 153 irq_set_handler_locked(irqd, handle_level_irq);
154 154
155 con = readl(d->virt_base + reg_con); 155 con = readl(d->virt_base + reg_con);
156 con &= ~(EXYNOS_EINT_CON_MASK << shift); 156 con &= ~(EXYNOS_EINT_CON_MASK << shift);
@@ -256,7 +256,6 @@ static int exynos_eint_irq_map(struct irq_domain *h, unsigned int virq,
256 irq_set_chip_data(virq, b); 256 irq_set_chip_data(virq, b);
257 irq_set_chip_and_handler(virq, &b->irq_chip->chip, 257 irq_set_chip_and_handler(virq, &b->irq_chip->chip,
258 handle_level_irq); 258 handle_level_irq);
259 set_irq_flags(virq, IRQF_VALID);
260 return 0; 259 return 0;
261} 260}
262 261
@@ -422,9 +421,9 @@ static const struct of_device_id exynos_wkup_irq_ids[] = {
422/* interrupt handler for wakeup interrupts 0..15 */ 421/* interrupt handler for wakeup interrupts 0..15 */
423static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc) 422static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
424{ 423{
425 struct exynos_weint_data *eintd = irq_get_handler_data(irq); 424 struct exynos_weint_data *eintd = irq_desc_get_handler_data(desc);
426 struct samsung_pin_bank *bank = eintd->bank; 425 struct samsung_pin_bank *bank = eintd->bank;
427 struct irq_chip *chip = irq_get_chip(irq); 426 struct irq_chip *chip = irq_desc_get_chip(desc);
428 int eint_irq; 427 int eint_irq;
429 428
430 chained_irq_enter(chip, desc); 429 chained_irq_enter(chip, desc);
@@ -454,8 +453,8 @@ static inline void exynos_irq_demux_eint(unsigned long pend,
454/* interrupt handler for wakeup interrupt 16 */ 453/* interrupt handler for wakeup interrupt 16 */
455static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) 454static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
456{ 455{
457 struct irq_chip *chip = irq_get_chip(irq); 456 struct irq_chip *chip = irq_desc_get_chip(desc);
458 struct exynos_muxed_weint_data *eintd = irq_get_handler_data(irq); 457 struct exynos_muxed_weint_data *eintd = irq_desc_get_handler_data(desc);
459 struct samsung_pinctrl_drv_data *d = eintd->banks[0]->drvdata; 458 struct samsung_pinctrl_drv_data *d = eintd->banks[0]->drvdata;
460 unsigned long pend; 459 unsigned long pend;
461 unsigned long mask; 460 unsigned long mask;
@@ -542,8 +541,9 @@ static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
542 } 541 }
543 weint_data[idx].irq = idx; 542 weint_data[idx].irq = idx;
544 weint_data[idx].bank = bank; 543 weint_data[idx].bank = bank;
545 irq_set_handler_data(irq, &weint_data[idx]); 544 irq_set_chained_handler_and_data(irq,
546 irq_set_chained_handler(irq, exynos_irq_eint0_15); 545 exynos_irq_eint0_15,
546 &weint_data[idx]);
547 } 547 }
548 } 548 }
549 549
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos5440.c b/drivers/pinctrl/samsung/pinctrl-exynos5440.c
index f5619fb50447..9ce0b8619d4c 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos5440.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos5440.c
@@ -44,9 +44,7 @@
44#define PIN_NAME_LENGTH 10 44#define PIN_NAME_LENGTH 10
45 45
46#define GROUP_SUFFIX "-grp" 46#define GROUP_SUFFIX "-grp"
47#define GSUFFIX_LEN sizeof(GROUP_SUFFIX)
48#define FUNCTION_SUFFIX "-mux" 47#define FUNCTION_SUFFIX "-mux"
49#define FSUFFIX_LEN sizeof(FUNCTION_SUFFIX)
50 48
51/* 49/*
52 * pin configuration type and its value are packed together into a 16-bits. 50 * pin configuration type and its value are packed together into a 16-bits.
@@ -205,22 +203,17 @@ static int exynos5440_dt_node_to_map(struct pinctrl_dev *pctldev,
205 203
206 /* Allocate memory for pin-map entries */ 204 /* Allocate memory for pin-map entries */
207 map = kzalloc(sizeof(*map) * map_cnt, GFP_KERNEL); 205 map = kzalloc(sizeof(*map) * map_cnt, GFP_KERNEL);
208 if (!map) { 206 if (!map)
209 dev_err(dev, "could not alloc memory for pin-maps\n");
210 return -ENOMEM; 207 return -ENOMEM;
211 }
212 *nmaps = 0; 208 *nmaps = 0;
213 209
214 /* 210 /*
215 * Allocate memory for pin group name. The pin group name is derived 211 * Allocate memory for pin group name. The pin group name is derived
216 * from the node name from which these map entries are be created. 212 * from the node name from which these map entries are be created.
217 */ 213 */
218 gname = kzalloc(strlen(np->name) + GSUFFIX_LEN, GFP_KERNEL); 214 gname = kasprintf(GFP_KERNEL, "%s%s", np->name, GROUP_SUFFIX);
219 if (!gname) { 215 if (!gname)
220 dev_err(dev, "failed to alloc memory for group name\n");
221 goto free_map; 216 goto free_map;
222 }
223 snprintf(gname, strlen(np->name) + 4, "%s%s", np->name, GROUP_SUFFIX);
224 217
225 /* 218 /*
226 * don't have config options? then skip over to creating function 219 * don't have config options? then skip over to creating function
@@ -231,10 +224,8 @@ static int exynos5440_dt_node_to_map(struct pinctrl_dev *pctldev,
231 224
232 /* Allocate memory for config entries */ 225 /* Allocate memory for config entries */
233 cfg = kzalloc(sizeof(*cfg) * cfg_cnt, GFP_KERNEL); 226 cfg = kzalloc(sizeof(*cfg) * cfg_cnt, GFP_KERNEL);
234 if (!cfg) { 227 if (!cfg)
235 dev_err(dev, "failed to alloc memory for configs\n");
236 goto free_gname; 228 goto free_gname;
237 }
238 229
239 /* Prepare a list of config settings */ 230 /* Prepare a list of config settings */
240 for (idx = 0, cfg_cnt = 0; idx < ARRAY_SIZE(pcfgs); idx++) { 231 for (idx = 0, cfg_cnt = 0; idx < ARRAY_SIZE(pcfgs); idx++) {
@@ -254,13 +245,10 @@ static int exynos5440_dt_node_to_map(struct pinctrl_dev *pctldev,
254skip_cfgs: 245skip_cfgs:
255 /* create the function map entry */ 246 /* create the function map entry */
256 if (of_find_property(np, "samsung,exynos5440-pin-function", NULL)) { 247 if (of_find_property(np, "samsung,exynos5440-pin-function", NULL)) {
257 fname = kzalloc(strlen(np->name) + FSUFFIX_LEN, GFP_KERNEL); 248 fname = kasprintf(GFP_KERNEL,
258 if (!fname) { 249 "%s%s", np->name, FUNCTION_SUFFIX);
259 dev_err(dev, "failed to alloc memory for func name\n"); 250 if (!fname)
260 goto free_cfg; 251 goto free_cfg;
261 }
262 snprintf(fname, strlen(np->name) + 4, "%s%s", np->name,
263 FUNCTION_SUFFIX);
264 252
265 map[*nmaps].data.mux.group = gname; 253 map[*nmaps].data.mux.group = gname;
266 map[*nmaps].data.mux.function = fname; 254 map[*nmaps].data.mux.function = fname;
@@ -651,10 +639,8 @@ static int exynos5440_pinctrl_parse_dt_pins(struct platform_device *pdev,
651 } 639 }
652 640
653 *pin_list = devm_kzalloc(dev, *npins * sizeof(**pin_list), GFP_KERNEL); 641 *pin_list = devm_kzalloc(dev, *npins * sizeof(**pin_list), GFP_KERNEL);
654 if (!*pin_list) { 642 if (!*pin_list)
655 dev_err(dev, "failed to allocate memory for pin list\n");
656 return -ENOMEM; 643 return -ENOMEM;
657 }
658 644
659 return of_property_read_u32_array(cfg_np, "samsung,exynos5440-pins", 645 return of_property_read_u32_array(cfg_np, "samsung,exynos5440-pins",
660 *pin_list, *npins); 646 *pin_list, *npins);
@@ -682,17 +668,15 @@ static int exynos5440_pinctrl_parse_dt(struct platform_device *pdev,
682 return -EINVAL; 668 return -EINVAL;
683 669
684 groups = devm_kzalloc(dev, grp_cnt * sizeof(*groups), GFP_KERNEL); 670 groups = devm_kzalloc(dev, grp_cnt * sizeof(*groups), GFP_KERNEL);
685 if (!groups) { 671 if (!groups)
686 dev_err(dev, "failed allocate memory for ping group list\n");
687 return -EINVAL; 672 return -EINVAL;
688 } 673
689 grp = groups; 674 grp = groups;
690 675
691 functions = devm_kzalloc(dev, grp_cnt * sizeof(*functions), GFP_KERNEL); 676 functions = devm_kzalloc(dev, grp_cnt * sizeof(*functions), GFP_KERNEL);
692 if (!functions) { 677 if (!functions)
693 dev_err(dev, "failed to allocate memory for function list\n");
694 return -EINVAL; 678 return -EINVAL;
695 } 679
696 func = functions; 680 func = functions;
697 681
698 /* 682 /*
@@ -710,14 +694,10 @@ static int exynos5440_pinctrl_parse_dt(struct platform_device *pdev,
710 } 694 }
711 695
712 /* derive pin group name from the node name */ 696 /* derive pin group name from the node name */
713 gname = devm_kzalloc(dev, strlen(cfg_np->name) + GSUFFIX_LEN, 697 gname = devm_kasprintf(dev, GFP_KERNEL,
714 GFP_KERNEL); 698 "%s%s", cfg_np->name, GROUP_SUFFIX);
715 if (!gname) { 699 if (!gname)
716 dev_err(dev, "failed to alloc memory for group name\n");
717 return -ENOMEM; 700 return -ENOMEM;
718 }
719 snprintf(gname, strlen(cfg_np->name) + 4, "%s%s", cfg_np->name,
720 GROUP_SUFFIX);
721 701
722 grp->name = gname; 702 grp->name = gname;
723 grp->pins = pin_list; 703 grp->pins = pin_list;
@@ -731,22 +711,15 @@ skip_to_pin_function:
731 continue; 711 continue;
732 712
733 /* derive function name from the node name */ 713 /* derive function name from the node name */
734 fname = devm_kzalloc(dev, strlen(cfg_np->name) + FSUFFIX_LEN, 714 fname = devm_kasprintf(dev, GFP_KERNEL,
735 GFP_KERNEL); 715 "%s%s", cfg_np->name, FUNCTION_SUFFIX);
736 if (!fname) { 716 if (!fname)
737 dev_err(dev, "failed to alloc memory for func name\n");
738 return -ENOMEM; 717 return -ENOMEM;
739 }
740 snprintf(fname, strlen(cfg_np->name) + 4, "%s%s", cfg_np->name,
741 FUNCTION_SUFFIX);
742 718
743 func->name = fname; 719 func->name = fname;
744 func->groups = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL); 720 func->groups = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL);
745 if (!func->groups) { 721 if (!func->groups)
746 dev_err(dev, "failed to alloc memory for group list "
747 "in pin function");
748 return -ENOMEM; 722 return -ENOMEM;
749 }
750 func->groups[0] = gname; 723 func->groups[0] = gname;
751 func->num_groups = gname ? 1 : 0; 724 func->num_groups = gname ? 1 : 0;
752 func->function = function; 725 func->function = function;
@@ -774,10 +747,8 @@ static int exynos5440_pinctrl_register(struct platform_device *pdev,
774 int pin, ret; 747 int pin, ret;
775 748
776 ctrldesc = devm_kzalloc(dev, sizeof(*ctrldesc), GFP_KERNEL); 749 ctrldesc = devm_kzalloc(dev, sizeof(*ctrldesc), GFP_KERNEL);
777 if (!ctrldesc) { 750 if (!ctrldesc)
778 dev_err(dev, "could not allocate memory for pinctrl desc\n");
779 return -ENOMEM; 751 return -ENOMEM;
780 }
781 752
782 ctrldesc->name = "exynos5440-pinctrl"; 753 ctrldesc->name = "exynos5440-pinctrl";
783 ctrldesc->owner = THIS_MODULE; 754 ctrldesc->owner = THIS_MODULE;
@@ -787,10 +758,8 @@ static int exynos5440_pinctrl_register(struct platform_device *pdev,
787 758
788 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) * 759 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
789 EXYNOS5440_MAX_PINS, GFP_KERNEL); 760 EXYNOS5440_MAX_PINS, GFP_KERNEL);
790 if (!pindesc) { 761 if (!pindesc)
791 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
792 return -ENOMEM; 762 return -ENOMEM;
793 }
794 ctrldesc->pins = pindesc; 763 ctrldesc->pins = pindesc;
795 ctrldesc->npins = EXYNOS5440_MAX_PINS; 764 ctrldesc->npins = EXYNOS5440_MAX_PINS;
796 765
@@ -804,10 +773,8 @@ static int exynos5440_pinctrl_register(struct platform_device *pdev,
804 */ 773 */
805 pin_names = devm_kzalloc(&pdev->dev, sizeof(char) * PIN_NAME_LENGTH * 774 pin_names = devm_kzalloc(&pdev->dev, sizeof(char) * PIN_NAME_LENGTH *
806 ctrldesc->npins, GFP_KERNEL); 775 ctrldesc->npins, GFP_KERNEL);
807 if (!pin_names) { 776 if (!pin_names)
808 dev_err(&pdev->dev, "mem alloc for pin names failed\n");
809 return -ENOMEM; 777 return -ENOMEM;
810 }
811 778
812 /* for each pin, set the name of the pin */ 779 /* for each pin, set the name of the pin */
813 for (pin = 0; pin < ctrldesc->npins; pin++) { 780 for (pin = 0; pin < ctrldesc->npins; pin++) {
@@ -844,10 +811,8 @@ static int exynos5440_gpiolib_register(struct platform_device *pdev,
844 int ret; 811 int ret;
845 812
846 gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL); 813 gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
847 if (!gc) { 814 if (!gc)
848 dev_err(&pdev->dev, "mem alloc for gpio_chip failed\n");
849 return -ENOMEM; 815 return -ENOMEM;
850 }
851 816
852 priv->gc = gc; 817 priv->gc = gc;
853 gc->base = 0; 818 gc->base = 0;
@@ -929,7 +894,6 @@ static int exynos5440_gpio_irq_map(struct irq_domain *h, unsigned int virq,
929 irq_set_chip_data(virq, d); 894 irq_set_chip_data(virq, d);
930 irq_set_chip_and_handler(virq, &exynos5440_gpio_irq_chip, 895 irq_set_chip_and_handler(virq, &exynos5440_gpio_irq_chip,
931 handle_level_irq); 896 handle_level_irq);
932 set_irq_flags(virq, IRQF_VALID);
933 return 0; 897 return 0;
934} 898}
935 899
@@ -949,10 +913,8 @@ static int exynos5440_gpio_irq_init(struct platform_device *pdev,
949 913
950 intd = devm_kzalloc(dev, sizeof(*intd) * EXYNOS5440_MAX_GPIO_INT, 914 intd = devm_kzalloc(dev, sizeof(*intd) * EXYNOS5440_MAX_GPIO_INT,
951 GFP_KERNEL); 915 GFP_KERNEL);
952 if (!intd) { 916 if (!intd)
953 dev_err(dev, "failed to allocate memory for gpio intr data\n");
954 return -ENOMEM; 917 return -ENOMEM;
955 }
956 918
957 for (i = 0; i < EXYNOS5440_MAX_GPIO_INT; i++) { 919 for (i = 0; i < EXYNOS5440_MAX_GPIO_INT; i++) {
958 irq = irq_of_parse_and_map(dev->of_node, i); 920 irq = irq_of_parse_and_map(dev->of_node, i);
@@ -995,10 +957,8 @@ static int exynos5440_pinctrl_probe(struct platform_device *pdev)
995 } 957 }
996 958
997 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 959 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
998 if (!priv) { 960 if (!priv)
999 dev_err(dev, "could not allocate memory for private data\n");
1000 return -ENOMEM; 961 return -ENOMEM;
1001 }
1002 962
1003 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 963 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1004 priv->reg_base = devm_ioremap_resource(&pdev->dev, res); 964 priv->reg_base = devm_ioremap_resource(&pdev->dev, res);
diff --git a/drivers/pinctrl/samsung/pinctrl-s3c24xx.c b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c
index 01b43dbfb795..019844d479bb 100644
--- a/drivers/pinctrl/samsung/pinctrl-s3c24xx.c
+++ b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c
@@ -131,13 +131,13 @@ static int s3c24xx_eint_get_trigger(unsigned int type)
131 } 131 }
132} 132}
133 133
134static void s3c24xx_eint_set_handler(unsigned int irq, unsigned int type) 134static void s3c24xx_eint_set_handler(struct irq_data *d, unsigned int type)
135{ 135{
136 /* Edge- and level-triggered interrupts need different handlers */ 136 /* Edge- and level-triggered interrupts need different handlers */
137 if (type & IRQ_TYPE_EDGE_BOTH) 137 if (type & IRQ_TYPE_EDGE_BOTH)
138 __irq_set_handler_locked(irq, handle_edge_irq); 138 irq_set_handler_locked(d, handle_edge_irq);
139 else 139 else
140 __irq_set_handler_locked(irq, handle_level_irq); 140 irq_set_handler_locked(d, handle_level_irq);
141} 141}
142 142
143static void s3c24xx_eint_set_function(struct samsung_pinctrl_drv_data *d, 143static void s3c24xx_eint_set_function(struct samsung_pinctrl_drv_data *d,
@@ -181,7 +181,7 @@ static int s3c24xx_eint_type(struct irq_data *data, unsigned int type)
181 return -EINVAL; 181 return -EINVAL;
182 } 182 }
183 183
184 s3c24xx_eint_set_handler(data->irq, type); 184 s3c24xx_eint_set_handler(data, type);
185 185
186 /* Set up interrupt trigger */ 186 /* Set up interrupt trigger */
187 reg = d->virt_base + EINT_REG(index); 187 reg = d->virt_base + EINT_REG(index);
@@ -243,7 +243,7 @@ static struct irq_chip s3c2410_eint0_3_chip = {
243static void s3c2410_demux_eint0_3(unsigned int irq, struct irq_desc *desc) 243static void s3c2410_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
244{ 244{
245 struct irq_data *data = irq_desc_get_irq_data(desc); 245 struct irq_data *data = irq_desc_get_irq_data(desc);
246 struct s3c24xx_eint_data *eint_data = irq_get_handler_data(irq); 246 struct s3c24xx_eint_data *eint_data = irq_desc_get_handler_data(desc);
247 unsigned int virq; 247 unsigned int virq;
248 248
249 /* the first 4 eints have a simple 1 to 1 mapping */ 249 /* the first 4 eints have a simple 1 to 1 mapping */
@@ -297,9 +297,9 @@ static struct irq_chip s3c2412_eint0_3_chip = {
297 297
298static void s3c2412_demux_eint0_3(unsigned int irq, struct irq_desc *desc) 298static void s3c2412_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
299{ 299{
300 struct irq_chip *chip = irq_get_chip(irq); 300 struct s3c24xx_eint_data *eint_data = irq_desc_get_handler_data(desc);
301 struct irq_data *data = irq_desc_get_irq_data(desc); 301 struct irq_data *data = irq_desc_get_irq_data(desc);
302 struct s3c24xx_eint_data *eint_data = irq_get_handler_data(irq); 302 struct irq_chip *chip = irq_data_get_irq_chip(data);
303 unsigned int virq; 303 unsigned int virq;
304 304
305 chained_irq_enter(chip, desc); 305 chained_irq_enter(chip, desc);
@@ -357,11 +357,11 @@ static struct irq_chip s3c24xx_eint_chip = {
357 .irq_set_type = s3c24xx_eint_type, 357 .irq_set_type = s3c24xx_eint_type,
358}; 358};
359 359
360static inline void s3c24xx_demux_eint(unsigned int irq, struct irq_desc *desc, 360static inline void s3c24xx_demux_eint(struct irq_desc *desc,
361 u32 offset, u32 range) 361 u32 offset, u32 range)
362{ 362{
363 struct irq_chip *chip = irq_get_chip(irq); 363 struct s3c24xx_eint_data *data = irq_desc_get_handler_data(desc);
364 struct s3c24xx_eint_data *data = irq_get_handler_data(irq); 364 struct irq_chip *chip = irq_desc_get_irq_chip(desc);
365 struct samsung_pinctrl_drv_data *d = data->drvdata; 365 struct samsung_pinctrl_drv_data *d = data->drvdata;
366 unsigned int pend, mask; 366 unsigned int pend, mask;
367 367
@@ -374,7 +374,7 @@ static inline void s3c24xx_demux_eint(unsigned int irq, struct irq_desc *desc,
374 pend &= range; 374 pend &= range;
375 375
376 while (pend) { 376 while (pend) {
377 unsigned int virq; 377 unsigned int virq, irq;
378 378
379 irq = __ffs(pend); 379 irq = __ffs(pend);
380 pend &= ~(1 << irq); 380 pend &= ~(1 << irq);
@@ -390,12 +390,12 @@ static inline void s3c24xx_demux_eint(unsigned int irq, struct irq_desc *desc,
390 390
391static void s3c24xx_demux_eint4_7(unsigned int irq, struct irq_desc *desc) 391static void s3c24xx_demux_eint4_7(unsigned int irq, struct irq_desc *desc)
392{ 392{
393 s3c24xx_demux_eint(irq, desc, 0, 0xf0); 393 s3c24xx_demux_eint(desc, 0, 0xf0);
394} 394}
395 395
396static void s3c24xx_demux_eint8_23(unsigned int irq, struct irq_desc *desc) 396static void s3c24xx_demux_eint8_23(unsigned int irq, struct irq_desc *desc)
397{ 397{
398 s3c24xx_demux_eint(irq, desc, 8, 0xffff00); 398 s3c24xx_demux_eint(desc, 8, 0xffff00);
399} 399}
400 400
401static irq_flow_handler_t s3c2410_eint_handlers[NUM_EINT_IRQ] = { 401static irq_flow_handler_t s3c2410_eint_handlers[NUM_EINT_IRQ] = {
@@ -437,7 +437,6 @@ static int s3c24xx_gpf_irq_map(struct irq_domain *h, unsigned int virq,
437 handle_edge_irq); 437 handle_edge_irq);
438 } 438 }
439 irq_set_chip_data(virq, bank); 439 irq_set_chip_data(virq, bank);
440 set_irq_flags(virq, IRQF_VALID);
441 return 0; 440 return 0;
442} 441}
443 442
@@ -457,7 +456,6 @@ static int s3c24xx_gpg_irq_map(struct irq_domain *h, unsigned int virq,
457 456
458 irq_set_chip_and_handler(virq, &s3c24xx_eint_chip, handle_edge_irq); 457 irq_set_chip_and_handler(virq, &s3c24xx_eint_chip, handle_edge_irq);
459 irq_set_chip_data(virq, bank); 458 irq_set_chip_data(virq, bank);
460 set_irq_flags(virq, IRQF_VALID);
461 return 0; 459 return 0;
462} 460}
463 461
diff --git a/drivers/pinctrl/samsung/pinctrl-s3c64xx.c b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c
index ec8cc3b47621..f5ea40a69711 100644
--- a/drivers/pinctrl/samsung/pinctrl-s3c64xx.c
+++ b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c
@@ -260,13 +260,13 @@ static int s3c64xx_irq_get_trigger(unsigned int type)
260 return trigger; 260 return trigger;
261} 261}
262 262
263static void s3c64xx_irq_set_handler(unsigned int irq, unsigned int type) 263static void s3c64xx_irq_set_handler(struct irq_data *d, unsigned int type)
264{ 264{
265 /* Edge- and level-triggered interrupts need different handlers */ 265 /* Edge- and level-triggered interrupts need different handlers */
266 if (type & IRQ_TYPE_EDGE_BOTH) 266 if (type & IRQ_TYPE_EDGE_BOTH)
267 __irq_set_handler_locked(irq, handle_edge_irq); 267 irq_set_handler_locked(d, handle_edge_irq);
268 else 268 else
269 __irq_set_handler_locked(irq, handle_level_irq); 269 irq_set_handler_locked(d, handle_level_irq);
270} 270}
271 271
272static void s3c64xx_irq_set_function(struct samsung_pinctrl_drv_data *d, 272static void s3c64xx_irq_set_function(struct samsung_pinctrl_drv_data *d,
@@ -356,7 +356,7 @@ static int s3c64xx_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
356 return -EINVAL; 356 return -EINVAL;
357 } 357 }
358 358
359 s3c64xx_irq_set_handler(irqd->irq, type); 359 s3c64xx_irq_set_handler(irqd, type);
360 360
361 /* Set up interrupt trigger */ 361 /* Set up interrupt trigger */
362 reg = d->virt_base + EINTCON_REG(bank->eint_offset); 362 reg = d->virt_base + EINTCON_REG(bank->eint_offset);
@@ -395,7 +395,6 @@ static int s3c64xx_gpio_irq_map(struct irq_domain *h, unsigned int virq,
395 irq_set_chip_and_handler(virq, 395 irq_set_chip_and_handler(virq,
396 &s3c64xx_gpio_irq_chip, handle_level_irq); 396 &s3c64xx_gpio_irq_chip, handle_level_irq);
397 irq_set_chip_data(virq, bank); 397 irq_set_chip_data(virq, bank);
398 set_irq_flags(virq, IRQF_VALID);
399 398
400 return 0; 399 return 0;
401} 400}
@@ -410,8 +409,8 @@ static const struct irq_domain_ops s3c64xx_gpio_irqd_ops = {
410 409
411static void s3c64xx_eint_gpio_irq(unsigned int irq, struct irq_desc *desc) 410static void s3c64xx_eint_gpio_irq(unsigned int irq, struct irq_desc *desc)
412{ 411{
413 struct irq_chip *chip = irq_get_chip(irq); 412 struct irq_chip *chip = irq_desc_get_chip(desc);
414 struct s3c64xx_eint_gpio_data *data = irq_get_handler_data(irq); 413 struct s3c64xx_eint_gpio_data *data = irq_desc_get_handler_data(desc);
415 struct samsung_pinctrl_drv_data *drvdata = data->drvdata; 414 struct samsung_pinctrl_drv_data *drvdata = data->drvdata;
416 415
417 chained_irq_enter(chip, desc); 416 chained_irq_enter(chip, desc);
@@ -567,7 +566,7 @@ static int s3c64xx_eint0_irq_set_type(struct irq_data *irqd, unsigned int type)
567 return -EINVAL; 566 return -EINVAL;
568 } 567 }
569 568
570 s3c64xx_irq_set_handler(irqd->irq, type); 569 s3c64xx_irq_set_handler(irqd, type);
571 570
572 /* Set up interrupt trigger */ 571 /* Set up interrupt trigger */
573 reg = d->virt_base + EINT0CON0_REG; 572 reg = d->virt_base + EINT0CON0_REG;
@@ -599,11 +598,10 @@ static struct irq_chip s3c64xx_eint0_irq_chip = {
599 .irq_set_type = s3c64xx_eint0_irq_set_type, 598 .irq_set_type = s3c64xx_eint0_irq_set_type,
600}; 599};
601 600
602static inline void s3c64xx_irq_demux_eint(unsigned int irq, 601static inline void s3c64xx_irq_demux_eint(struct irq_desc *desc, u32 range)
603 struct irq_desc *desc, u32 range)
604{ 602{
605 struct irq_chip *chip = irq_get_chip(irq); 603 struct irq_chip *chip = irq_desc_get_chip(desc);
606 struct s3c64xx_eint0_data *data = irq_get_handler_data(irq); 604 struct s3c64xx_eint0_data *data = irq_desc_get_handler_data(desc);
607 struct samsung_pinctrl_drv_data *drvdata = data->drvdata; 605 struct samsung_pinctrl_drv_data *drvdata = data->drvdata;
608 unsigned int pend, mask; 606 unsigned int pend, mask;
609 607
@@ -616,11 +614,10 @@ static inline void s3c64xx_irq_demux_eint(unsigned int irq,
616 pend &= range; 614 pend &= range;
617 615
618 while (pend) { 616 while (pend) {
619 unsigned int virq; 617 unsigned int virq, irq;
620 618
621 irq = fls(pend) - 1; 619 irq = fls(pend) - 1;
622 pend &= ~(1 << irq); 620 pend &= ~(1 << irq);
623
624 virq = irq_linear_revmap(data->domains[irq], data->pins[irq]); 621 virq = irq_linear_revmap(data->domains[irq], data->pins[irq]);
625 /* 622 /*
626 * Something must be really wrong if an unmapped EINT 623 * Something must be really wrong if an unmapped EINT
@@ -636,22 +633,22 @@ static inline void s3c64xx_irq_demux_eint(unsigned int irq,
636 633
637static void s3c64xx_demux_eint0_3(unsigned int irq, struct irq_desc *desc) 634static void s3c64xx_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
638{ 635{
639 s3c64xx_irq_demux_eint(irq, desc, 0xf); 636 s3c64xx_irq_demux_eint(desc, 0xf);
640} 637}
641 638
642static void s3c64xx_demux_eint4_11(unsigned int irq, struct irq_desc *desc) 639static void s3c64xx_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
643{ 640{
644 s3c64xx_irq_demux_eint(irq, desc, 0xff0); 641 s3c64xx_irq_demux_eint(desc, 0xff0);
645} 642}
646 643
647static void s3c64xx_demux_eint12_19(unsigned int irq, struct irq_desc *desc) 644static void s3c64xx_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
648{ 645{
649 s3c64xx_irq_demux_eint(irq, desc, 0xff000); 646 s3c64xx_irq_demux_eint(desc, 0xff000);
650} 647}
651 648
652static void s3c64xx_demux_eint20_27(unsigned int irq, struct irq_desc *desc) 649static void s3c64xx_demux_eint20_27(unsigned int irq, struct irq_desc *desc)
653{ 650{
654 s3c64xx_irq_demux_eint(irq, desc, 0xff00000); 651 s3c64xx_irq_demux_eint(desc, 0xff00000);
655} 652}
656 653
657static irq_flow_handler_t s3c64xx_eint0_handlers[NUM_EINT0_IRQ] = { 654static irq_flow_handler_t s3c64xx_eint0_handlers[NUM_EINT0_IRQ] = {
@@ -673,7 +670,6 @@ static int s3c64xx_eint0_irq_map(struct irq_domain *h, unsigned int virq,
673 irq_set_chip_and_handler(virq, 670 irq_set_chip_and_handler(virq,
674 &s3c64xx_eint0_irq_chip, handle_level_irq); 671 &s3c64xx_eint0_irq_chip, handle_level_irq);
675 irq_set_chip_data(virq, ddata); 672 irq_set_chip_data(virq, ddata);
676 set_irq_flags(virq, IRQF_VALID);
677 673
678 return 0; 674 return 0;
679} 675}
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 865d235612c5..fb9c44805234 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -29,24 +29,25 @@
29static int sh_pfc_map_resources(struct sh_pfc *pfc, 29static int sh_pfc_map_resources(struct sh_pfc *pfc,
30 struct platform_device *pdev) 30 struct platform_device *pdev)
31{ 31{
32 unsigned int num_windows = 0; 32 unsigned int num_windows, num_irqs;
33 unsigned int num_irqs = 0;
34 struct sh_pfc_window *windows; 33 struct sh_pfc_window *windows;
35 unsigned int *irqs = NULL; 34 unsigned int *irqs = NULL;
36 struct resource *res; 35 struct resource *res;
37 unsigned int i; 36 unsigned int i;
37 int irq;
38 38
39 /* Count the MEM and IRQ resources. */ 39 /* Count the MEM and IRQ resources. */
40 for (i = 0; i < pdev->num_resources; ++i) { 40 for (num_windows = 0;; num_windows++) {
41 switch (resource_type(&pdev->resource[i])) { 41 res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows);
42 case IORESOURCE_MEM: 42 if (!res)
43 num_windows++;
44 break; 43 break;
45 44 }
46 case IORESOURCE_IRQ: 45 for (num_irqs = 0;; num_irqs++) {
47 num_irqs++; 46 irq = platform_get_irq(pdev, num_irqs);
47 if (irq == -EPROBE_DEFER)
48 return irq;
49 if (irq < 0)
48 break; 50 break;
49 }
50 } 51 }
51 52
52 if (num_windows == 0) 53 if (num_windows == 0)
@@ -72,22 +73,17 @@ static int sh_pfc_map_resources(struct sh_pfc *pfc,
72 } 73 }
73 74
74 /* Fill them. */ 75 /* Fill them. */
75 for (i = 0, res = pdev->resource; i < pdev->num_resources; i++, res++) { 76 for (i = 0; i < num_windows; i++) {
76 switch (resource_type(res)) { 77 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
77 case IORESOURCE_MEM: 78 windows->phys = res->start;
78 windows->phys = res->start; 79 windows->size = resource_size(res);
79 windows->size = resource_size(res); 80 windows->virt = devm_ioremap_resource(pfc->dev, res);
80 windows->virt = devm_ioremap_resource(pfc->dev, res); 81 if (IS_ERR(windows->virt))
81 if (IS_ERR(windows->virt)) 82 return -ENOMEM;
82 return -ENOMEM; 83 windows++;
83 windows++;
84 break;
85
86 case IORESOURCE_IRQ:
87 *irqs++ = res->start;
88 break;
89 }
90 } 84 }
85 for (i = 0; i < num_irqs; i++)
86 *irqs++ = platform_get_irq(pdev, i);
91 87
92 return 0; 88 return 0;
93} 89}
@@ -591,9 +587,6 @@ static int sh_pfc_remove(struct platform_device *pdev)
591} 587}
592 588
593static const struct platform_device_id sh_pfc_id_table[] = { 589static const struct platform_device_id sh_pfc_id_table[] = {
594#ifdef CONFIG_PINCTRL_PFC_R8A7740
595 { "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
596#endif
597#ifdef CONFIG_PINCTRL_PFC_R8A7778 590#ifdef CONFIG_PINCTRL_PFC_R8A7778
598 { "pfc-r8a7778", (kernel_ulong_t)&r8a7778_pinmux_info }, 591 { "pfc-r8a7778", (kernel_ulong_t)&r8a7778_pinmux_info },
599#endif 592#endif
@@ -609,9 +602,6 @@ static const struct platform_device_id sh_pfc_id_table[] = {
609#ifdef CONFIG_PINCTRL_PFC_SH7269 602#ifdef CONFIG_PINCTRL_PFC_SH7269
610 { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info }, 603 { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
611#endif 604#endif
612#ifdef CONFIG_PINCTRL_PFC_SH73A0
613 { "pfc-sh73a0", (kernel_ulong_t)&sh73a0_pinmux_info },
614#endif
615#ifdef CONFIG_PINCTRL_PFC_SH7720 605#ifdef CONFIG_PINCTRL_PFC_SH7720
616 { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info }, 606 { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
617#endif 607#endif
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index d0bb1459783a..82ef1862dd1b 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -22,10 +22,6 @@
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/pinctrl/pinconf-generic.h> 23#include <linux/pinctrl/pinconf-generic.h>
24 24
25#ifndef CONFIG_ARCH_MULTIPLATFORM
26#include <mach/irqs.h>
27#endif
28
29#include "core.h" 25#include "core.h"
30#include "sh_pfc.h" 26#include "sh_pfc.h"
31 27
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index baab81ead9ff..fc344a7c2b53 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -27,10 +27,27 @@
27#include "core.h" 27#include "core.h"
28#include "sh_pfc.h" 28#include "sh_pfc.h"
29 29
30#define PORT_GP_30(bank, fn, sfx) \
31 PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
32 PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
33 PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
34 PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
35 PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
36 PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
37 PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
38 PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
39 PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
40 PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
41 PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
42 PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
43 PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \
44 PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \
45 PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx)
46
30#define CPU_ALL_PORT(fn, sfx) \ 47#define CPU_ALL_PORT(fn, sfx) \
31 PORT_GP_32(0, fn, sfx), \ 48 PORT_GP_32(0, fn, sfx), \
32 PORT_GP_32(1, fn, sfx), \ 49 PORT_GP_30(1, fn, sfx), \
33 PORT_GP_32(2, fn, sfx), \ 50 PORT_GP_30(2, fn, sfx), \
34 PORT_GP_32(3, fn, sfx), \ 51 PORT_GP_32(3, fn, sfx), \
35 PORT_GP_32(4, fn, sfx), \ 52 PORT_GP_32(4, fn, sfx), \
36 PORT_GP_32(5, fn, sfx) 53 PORT_GP_32(5, fn, sfx)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
index 3ddf23ec9f0b..25e8117f5a1a 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
@@ -14,15 +14,30 @@
14#include "core.h" 14#include "core.h"
15#include "sh_pfc.h" 15#include "sh_pfc.h"
16 16
17#define PORT_GP_26(bank, fn, sfx) \
18 PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
19 PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
20 PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
21 PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
22 PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
23 PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
24 PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
25 PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
26 PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
27 PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
28 PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
29 PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
30 PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx)
31
17#define CPU_ALL_PORT(fn, sfx) \ 32#define CPU_ALL_PORT(fn, sfx) \
18 PORT_GP_32(0, fn, sfx), \ 33 PORT_GP_32(0, fn, sfx), \
19 PORT_GP_32(1, fn, sfx), \ 34 PORT_GP_26(1, fn, sfx), \
20 PORT_GP_32(2, fn, sfx), \ 35 PORT_GP_32(2, fn, sfx), \
21 PORT_GP_32(3, fn, sfx), \ 36 PORT_GP_32(3, fn, sfx), \
22 PORT_GP_32(4, fn, sfx), \ 37 PORT_GP_32(4, fn, sfx), \
23 PORT_GP_32(5, fn, sfx), \ 38 PORT_GP_32(5, fn, sfx), \
24 PORT_GP_32(6, fn, sfx), \ 39 PORT_GP_32(6, fn, sfx), \
25 PORT_GP_32(7, fn, sfx) 40 PORT_GP_26(7, fn, sfx)
26 41
27enum { 42enum {
28 PINMUX_RESERVED = 0, 43 PINMUX_RESERVED = 0,
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
index bfdcac4b3bc4..5248685dbb4e 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
@@ -2770,6 +2770,24 @@ static const unsigned int sdhi2_wp_pins[] = {
2770static const unsigned int sdhi2_wp_mux[] = { 2770static const unsigned int sdhi2_wp_mux[] = {
2771 SD2_WP_MARK, 2771 SD2_WP_MARK,
2772}; 2772};
2773/* - USB0 ------------------------------------------------------------------- */
2774static const unsigned int usb0_pins[] = {
2775 RCAR_GP_PIN(5, 24), /* PWEN */
2776 RCAR_GP_PIN(5, 25), /* OVC */
2777};
2778static const unsigned int usb0_mux[] = {
2779 USB0_PWEN_MARK,
2780 USB0_OVC_MARK,
2781};
2782/* - USB1 ------------------------------------------------------------------- */
2783static const unsigned int usb1_pins[] = {
2784 RCAR_GP_PIN(5, 26), /* PWEN */
2785 RCAR_GP_PIN(5, 27), /* OVC */
2786};
2787static const unsigned int usb1_mux[] = {
2788 USB1_PWEN_MARK,
2789 USB1_OVC_MARK,
2790};
2773 2791
2774static const struct sh_pfc_pin_group pinmux_groups[] = { 2792static const struct sh_pfc_pin_group pinmux_groups[] = {
2775 SH_PFC_PIN_GROUP(eth_link), 2793 SH_PFC_PIN_GROUP(eth_link),
@@ -2945,6 +2963,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
2945 SH_PFC_PIN_GROUP(sdhi2_ctrl), 2963 SH_PFC_PIN_GROUP(sdhi2_ctrl),
2946 SH_PFC_PIN_GROUP(sdhi2_cd), 2964 SH_PFC_PIN_GROUP(sdhi2_cd),
2947 SH_PFC_PIN_GROUP(sdhi2_wp), 2965 SH_PFC_PIN_GROUP(sdhi2_wp),
2966 SH_PFC_PIN_GROUP(usb0),
2967 SH_PFC_PIN_GROUP(usb1),
2948}; 2968};
2949 2969
2950static const char * const eth_groups[] = { 2970static const char * const eth_groups[] = {
@@ -3219,6 +3239,14 @@ static const char * const sdhi2_groups[] = {
3219 "sdhi2_wp", 3239 "sdhi2_wp",
3220}; 3240};
3221 3241
3242static const char * const usb0_groups[] = {
3243 "usb0",
3244};
3245
3246static const char * const usb1_groups[] = {
3247 "usb1",
3248};
3249
3222static const struct sh_pfc_function pinmux_functions[] = { 3250static const struct sh_pfc_function pinmux_functions[] = {
3223 SH_PFC_FUNCTION(eth), 3251 SH_PFC_FUNCTION(eth),
3224 SH_PFC_FUNCTION(hscif0), 3252 SH_PFC_FUNCTION(hscif0),
@@ -3253,6 +3281,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
3253 SH_PFC_FUNCTION(sdhi0), 3281 SH_PFC_FUNCTION(sdhi0),
3254 SH_PFC_FUNCTION(sdhi1), 3282 SH_PFC_FUNCTION(sdhi1),
3255 SH_PFC_FUNCTION(sdhi2), 3283 SH_PFC_FUNCTION(sdhi2),
3284 SH_PFC_FUNCTION(usb0),
3285 SH_PFC_FUNCTION(usb1),
3256}; 3286};
3257 3287
3258static const struct pinmux_cfg_reg pinmux_config_regs[] = { 3288static const struct pinmux_cfg_reg pinmux_config_regs[] = {
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index d2efbfb776ac..097526576f88 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -26,10 +26,6 @@
26#include <linux/regulator/machine.h> 26#include <linux/regulator/machine.h>
27#include <linux/slab.h> 27#include <linux/slab.h>
28 28
29#ifndef CONFIG_ARCH_MULTIPLATFORM
30#include <mach/irqs.h>
31#endif
32
33#include "core.h" 29#include "core.h"
34#include "sh_pfc.h" 30#include "sh_pfc.h"
35 31
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index ff678966008b..863c3e30ce05 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -40,6 +40,10 @@ struct sh_pfc_pinctrl {
40 40
41 struct pinctrl_pin_desc *pins; 41 struct pinctrl_pin_desc *pins;
42 struct sh_pfc_pin_config *configs; 42 struct sh_pfc_pin_config *configs;
43
44 const char *func_prop_name;
45 const char *groups_prop_name;
46 const char *pins_prop_name;
43}; 47};
44 48
45static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev) 49static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
@@ -96,10 +100,13 @@ static int sh_pfc_map_add_config(struct pinctrl_map *map,
96 return 0; 100 return 0;
97} 101}
98 102
99static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np, 103static int sh_pfc_dt_subnode_to_map(struct pinctrl_dev *pctldev,
104 struct device_node *np,
100 struct pinctrl_map **map, 105 struct pinctrl_map **map,
101 unsigned int *num_maps, unsigned int *index) 106 unsigned int *num_maps, unsigned int *index)
102{ 107{
108 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
109 struct device *dev = pmx->pfc->dev;
103 struct pinctrl_map *maps = *map; 110 struct pinctrl_map *maps = *map;
104 unsigned int nmaps = *num_maps; 111 unsigned int nmaps = *num_maps;
105 unsigned int idx = *index; 112 unsigned int idx = *index;
@@ -113,10 +120,27 @@ static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np,
113 const char *pin; 120 const char *pin;
114 int ret; 121 int ret;
115 122
123 /* Support both the old Renesas-specific properties and the new standard
124 * properties. Mixing old and new properties isn't allowed, neither
125 * inside a subnode nor across subnodes.
126 */
127 if (!pmx->func_prop_name) {
128 if (of_find_property(np, "groups", NULL) ||
129 of_find_property(np, "pins", NULL)) {
130 pmx->func_prop_name = "function";
131 pmx->groups_prop_name = "groups";
132 pmx->pins_prop_name = "pins";
133 } else {
134 pmx->func_prop_name = "renesas,function";
135 pmx->groups_prop_name = "renesas,groups";
136 pmx->pins_prop_name = "renesas,pins";
137 }
138 }
139
116 /* Parse the function and configuration properties. At least a function 140 /* Parse the function and configuration properties. At least a function
117 * or one configuration must be specified. 141 * or one configuration must be specified.
118 */ 142 */
119 ret = of_property_read_string(np, "renesas,function", &function); 143 ret = of_property_read_string(np, pmx->func_prop_name, &function);
120 if (ret < 0 && ret != -EINVAL) { 144 if (ret < 0 && ret != -EINVAL) {
121 dev_err(dev, "Invalid function in DT\n"); 145 dev_err(dev, "Invalid function in DT\n");
122 return ret; 146 return ret;
@@ -129,11 +153,12 @@ static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np,
129 if (!function && num_configs == 0) { 153 if (!function && num_configs == 0) {
130 dev_err(dev, 154 dev_err(dev,
131 "DT node must contain at least a function or config\n"); 155 "DT node must contain at least a function or config\n");
156 ret = -ENODEV;
132 goto done; 157 goto done;
133 } 158 }
134 159
135 /* Count the number of pins and groups and reallocate mappings. */ 160 /* Count the number of pins and groups and reallocate mappings. */
136 ret = of_property_count_strings(np, "renesas,pins"); 161 ret = of_property_count_strings(np, pmx->pins_prop_name);
137 if (ret == -EINVAL) { 162 if (ret == -EINVAL) {
138 num_pins = 0; 163 num_pins = 0;
139 } else if (ret < 0) { 164 } else if (ret < 0) {
@@ -143,7 +168,7 @@ static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np,
143 num_pins = ret; 168 num_pins = ret;
144 } 169 }
145 170
146 ret = of_property_count_strings(np, "renesas,groups"); 171 ret = of_property_count_strings(np, pmx->groups_prop_name);
147 if (ret == -EINVAL) { 172 if (ret == -EINVAL) {
148 num_groups = 0; 173 num_groups = 0;
149 } else if (ret < 0) { 174 } else if (ret < 0) {
@@ -174,7 +199,7 @@ static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np,
174 *num_maps = nmaps; 199 *num_maps = nmaps;
175 200
176 /* Iterate over pins and groups and create the mappings. */ 201 /* Iterate over pins and groups and create the mappings. */
177 of_property_for_each_string(np, "renesas,groups", prop, group) { 202 of_property_for_each_string(np, pmx->groups_prop_name, prop, group) {
178 if (function) { 203 if (function) {
179 maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; 204 maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
180 maps[idx].data.mux.group = group; 205 maps[idx].data.mux.group = group;
@@ -198,7 +223,7 @@ static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np,
198 goto done; 223 goto done;
199 } 224 }
200 225
201 of_property_for_each_string(np, "renesas,pins", prop, pin) { 226 of_property_for_each_string(np, pmx->pins_prop_name, prop, pin) {
202 ret = sh_pfc_map_add_config(&maps[idx], pin, 227 ret = sh_pfc_map_add_config(&maps[idx], pin,
203 PIN_MAP_TYPE_CONFIGS_PIN, 228 PIN_MAP_TYPE_CONFIGS_PIN,
204 configs, num_configs); 229 configs, num_configs);
@@ -246,7 +271,7 @@ static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev,
246 index = 0; 271 index = 0;
247 272
248 for_each_child_of_node(np, child) { 273 for_each_child_of_node(np, child) {
249 ret = sh_pfc_dt_subnode_to_map(dev, child, map, num_maps, 274 ret = sh_pfc_dt_subnode_to_map(pctldev, child, map, num_maps,
250 &index); 275 &index);
251 if (ret < 0) 276 if (ret < 0)
252 goto done; 277 goto done;
@@ -254,7 +279,8 @@ static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev,
254 279
255 /* If no mapping has been found in child nodes try the config node. */ 280 /* If no mapping has been found in child nodes try the config node. */
256 if (*num_maps == 0) { 281 if (*num_maps == 0) {
257 ret = sh_pfc_dt_subnode_to_map(dev, np, map, num_maps, &index); 282 ret = sh_pfc_dt_subnode_to_map(pctldev, np, map, num_maps,
283 &index);
258 if (ret < 0) 284 if (ret < 0)
259 goto done; 285 goto done;
260 } 286 }
@@ -465,6 +491,9 @@ static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
465 case PIN_CONFIG_BIAS_PULL_DOWN: 491 case PIN_CONFIG_BIAS_PULL_DOWN:
466 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN; 492 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
467 493
494 case PIN_CONFIG_POWER_SOURCE:
495 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
496
468 default: 497 default:
469 return false; 498 return false;
470 } 499 }
@@ -477,7 +506,6 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
477 struct sh_pfc *pfc = pmx->pfc; 506 struct sh_pfc *pfc = pmx->pfc;
478 enum pin_config_param param = pinconf_to_config_param(*config); 507 enum pin_config_param param = pinconf_to_config_param(*config);
479 unsigned long flags; 508 unsigned long flags;
480 unsigned int bias;
481 509
482 if (!sh_pfc_pinconf_validate(pfc, _pin, param)) 510 if (!sh_pfc_pinconf_validate(pfc, _pin, param))
483 return -ENOTSUPP; 511 return -ENOTSUPP;
@@ -485,7 +513,9 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
485 switch (param) { 513 switch (param) {
486 case PIN_CONFIG_BIAS_DISABLE: 514 case PIN_CONFIG_BIAS_DISABLE:
487 case PIN_CONFIG_BIAS_PULL_UP: 515 case PIN_CONFIG_BIAS_PULL_UP:
488 case PIN_CONFIG_BIAS_PULL_DOWN: 516 case PIN_CONFIG_BIAS_PULL_DOWN: {
517 unsigned int bias;
518
489 if (!pfc->info->ops || !pfc->info->ops->get_bias) 519 if (!pfc->info->ops || !pfc->info->ops->get_bias)
490 return -ENOTSUPP; 520 return -ENOTSUPP;
491 521
@@ -498,6 +528,24 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
498 528
499 *config = 0; 529 *config = 0;
500 break; 530 break;
531 }
532
533 case PIN_CONFIG_POWER_SOURCE: {
534 int ret;
535
536 if (!pfc->info->ops || !pfc->info->ops->get_io_voltage)
537 return -ENOTSUPP;
538
539 spin_lock_irqsave(&pfc->lock, flags);
540 ret = pfc->info->ops->get_io_voltage(pfc, _pin);
541 spin_unlock_irqrestore(&pfc->lock, flags);
542
543 if (ret < 0)
544 return ret;
545
546 *config = ret;
547 break;
548 }
501 549
502 default: 550 default:
503 return -ENOTSUPP; 551 return -ENOTSUPP;
@@ -534,6 +582,24 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
534 582
535 break; 583 break;
536 584
585 case PIN_CONFIG_POWER_SOURCE: {
586 unsigned int arg =
587 pinconf_to_config_argument(configs[i]);
588 int ret;
589
590 if (!pfc->info->ops || !pfc->info->ops->set_io_voltage)
591 return -ENOTSUPP;
592
593 spin_lock_irqsave(&pfc->lock, flags);
594 ret = pfc->info->ops->set_io_voltage(pfc, _pin, arg);
595 spin_unlock_irqrestore(&pfc->lock, flags);
596
597 if (ret)
598 return ret;
599
600 break;
601 }
602
537 default: 603 default:
538 return -ENOTSUPP; 604 return -ENOTSUPP;
539 } 605 }
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 0874cfee6889..15afd49fd4e3 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -12,6 +12,7 @@
12#define __SH_PFC_H 12#define __SH_PFC_H
13 13
14#include <linux/bug.h> 14#include <linux/bug.h>
15#include <linux/pinctrl/pinconf-generic.h>
15#include <linux/stringify.h> 16#include <linux/stringify.h>
16 17
17enum { 18enum {
@@ -26,6 +27,7 @@ enum {
26#define SH_PFC_PIN_CFG_OUTPUT (1 << 1) 27#define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
27#define SH_PFC_PIN_CFG_PULL_UP (1 << 2) 28#define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
28#define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3) 29#define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
30#define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
29#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31) 31#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
30 32
31struct sh_pfc_pin { 33struct sh_pfc_pin {
@@ -121,6 +123,9 @@ struct sh_pfc_soc_operations {
121 unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin); 123 unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
122 void (*set_bias)(struct sh_pfc *pfc, unsigned int pin, 124 void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
123 unsigned int bias); 125 unsigned int bias);
126 int (*get_io_voltage)(struct sh_pfc *pfc, unsigned int pin);
127 int (*set_io_voltage)(struct sh_pfc *pfc, unsigned int pin,
128 u16 voltage_mV);
124}; 129};
125 130
126struct sh_pfc_soc_info { 131struct sh_pfc_soc_info {
diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c b/drivers/pinctrl/sirf/pinctrl-atlas7.c
index 9384e0aa3996..9df0c5f25824 100644
--- a/drivers/pinctrl/sirf/pinctrl-atlas7.c
+++ b/drivers/pinctrl/sirf/pinctrl-atlas7.c
@@ -148,6 +148,19 @@ enum altas7_pad_type {
148#define DIV_DISABLE 0x1 148#define DIV_DISABLE 0x1
149#define DIV_ENABLE 0x0 149#define DIV_ENABLE 0x0
150 150
151/* Number of Function input disable registers */
152#define NUM_OF_IN_DISABLE_REG 0x2
153
154/* Offset of Function input disable registers */
155#define IN_DISABLE_0_REG_SET 0x0A00
156#define IN_DISABLE_0_REG_CLR 0x0A04
157#define IN_DISABLE_1_REG_SET 0x0A08
158#define IN_DISABLE_1_REG_CLR 0x0A0C
159#define IN_DISABLE_VAL_0_REG_SET 0x0A80
160#define IN_DISABLE_VAL_0_REG_CLR 0x0A84
161#define IN_DISABLE_VAL_1_REG_SET 0x0A88
162#define IN_DISABLE_VAL_1_REG_CLR 0x0A8C
163
151struct dt_params { 164struct dt_params {
152 const char *property; 165 const char *property;
153 int value; 166 int value;
@@ -197,6 +210,16 @@ struct atlas7_pad_config {
197 } 210 }
198 211
199/** 212/**
213 * struct atlas7_pad_status - Atlas7 Pad status
214 */
215struct atlas7_pad_status {
216 u8 func;
217 u8 pull;
218 u8 dstr;
219 u8 reserved;
220};
221
222/**
200 * struct atlas7_pad_mux - Atlas7 mux 223 * struct atlas7_pad_mux - Atlas7 mux
201 * @bank: The bank of this pad's registers on. 224 * @bank: The bank of this pad's registers on.
202 * @pin : The ID of this Pad. 225 * @pin : The ID of this Pad.
@@ -285,6 +308,9 @@ struct atlas7_pinctrl_data {
285/* Platform info of atlas7 pinctrl */ 308/* Platform info of atlas7 pinctrl */
286#define ATLAS7_PINCTRL_REG_BANKS 2 309#define ATLAS7_PINCTRL_REG_BANKS 2
287#define ATLAS7_PINCTRL_BANK_0_PINS 18 310#define ATLAS7_PINCTRL_BANK_0_PINS 18
311#define ATLAS7_PINCTRL_BANK_1_PINS 141
312#define ATLAS7_PINCTRL_TOTAL_PINS \
313 (ATLAS7_PINCTRL_BANK_0_PINS + ATLAS7_PINCTRL_BANK_1_PINS)
288 314
289/** 315/**
290 * Atlas7 GPIO Chip 316 * Atlas7 GPIO Chip
@@ -316,6 +342,7 @@ struct atlas7_gpio_bank {
316 unsigned int gpio_offset; 342 unsigned int gpio_offset;
317 unsigned int ngpio; 343 unsigned int ngpio;
318 const unsigned int *gpio_pins; 344 const unsigned int *gpio_pins;
345 u32 sleep_data[NGPIO_OF_BANK];
319}; 346};
320 347
321struct atlas7_gpio_chip { 348struct atlas7_gpio_chip {
@@ -343,6 +370,9 @@ struct atlas7_pmx {
343 struct pinctrl_desc pctl_desc; 370 struct pinctrl_desc pctl_desc;
344 struct atlas7_pinctrl_data *pctl_data; 371 struct atlas7_pinctrl_data *pctl_data;
345 void __iomem *regs[ATLAS7_PINCTRL_REG_BANKS]; 372 void __iomem *regs[ATLAS7_PINCTRL_REG_BANKS];
373 u32 status_ds[NUM_OF_IN_DISABLE_REG];
374 u32 status_dsv[NUM_OF_IN_DISABLE_REG];
375 struct atlas7_pad_status sleep_data[ATLAS7_PINCTRL_TOTAL_PINS];
346}; 376};
347 377
348/* 378/*
@@ -3480,6 +3510,160 @@ struct atlas7_pinctrl_data atlas7_ioc_data = {
3480 .confs_cnt = ARRAY_SIZE(atlas7_ioc_pad_confs), 3510 .confs_cnt = ARRAY_SIZE(atlas7_ioc_pad_confs),
3481}; 3511};
3482 3512
3513/* Simple map data structure */
3514struct map_data {
3515 u8 idx;
3516 u8 data;
3517};
3518
3519/**
3520 * struct atlas7_pull_info - Atlas7 Pad pull info
3521 * @type:The type of this Pad.
3522 * @mask:The mas value of this pin's pull bits.
3523 * @v2s: The map of pull register value to pull status.
3524 * @s2v: The map of pull status to pull register value.
3525 */
3526struct atlas7_pull_info {
3527 u8 pad_type;
3528 u8 mask;
3529 const struct map_data *v2s;
3530 const struct map_data *s2v;
3531};
3532
3533/* Pull Register value map to status */
3534static const struct map_data p4we_pull_v2s[] = {
3535 { P4WE_PULL_UP, PULL_UP },
3536 { P4WE_HIGH_HYSTERESIS, HIGH_HYSTERESIS },
3537 { P4WE_HIGH_Z, HIGH_Z },
3538 { P4WE_PULL_DOWN, PULL_DOWN },
3539};
3540
3541static const struct map_data p16st_pull_v2s[] = {
3542 { P16ST_PULL_UP, PULL_UP },
3543 { PD, PULL_UNKNOWN },
3544 { P16ST_HIGH_Z, HIGH_Z },
3545 { P16ST_PULL_DOWN, PULL_DOWN },
3546};
3547
3548static const struct map_data pm31_pull_v2s[] = {
3549 { PM31_PULL_DISABLED, PULL_DOWN },
3550 { PM31_PULL_ENABLED, PULL_UP },
3551};
3552
3553static const struct map_data pangd_pull_v2s[] = {
3554 { PANGD_PULL_UP, PULL_UP },
3555 { PD, PULL_UNKNOWN },
3556 { PANGD_HIGH_Z, HIGH_Z },
3557 { PANGD_PULL_DOWN, PULL_DOWN },
3558};
3559
3560/* Pull status map to register value */
3561static const struct map_data p4we_pull_s2v[] = {
3562 { PULL_UP, P4WE_PULL_UP },
3563 { HIGH_HYSTERESIS, P4WE_HIGH_HYSTERESIS },
3564 { HIGH_Z, P4WE_HIGH_Z },
3565 { PULL_DOWN, P4WE_PULL_DOWN },
3566 { PULL_DISABLE, -1 },
3567 { PULL_ENABLE, -1 },
3568};
3569
3570static const struct map_data p16st_pull_s2v[] = {
3571 { PULL_UP, P16ST_PULL_UP },
3572 { HIGH_HYSTERESIS, -1 },
3573 { HIGH_Z, P16ST_HIGH_Z },
3574 { PULL_DOWN, P16ST_PULL_DOWN },
3575 { PULL_DISABLE, -1 },
3576 { PULL_ENABLE, -1 },
3577};
3578
3579static const struct map_data pm31_pull_s2v[] = {
3580 { PULL_UP, PM31_PULL_ENABLED },
3581 { HIGH_HYSTERESIS, -1 },
3582 { HIGH_Z, -1 },
3583 { PULL_DOWN, PM31_PULL_DISABLED },
3584 { PULL_DISABLE, -1 },
3585 { PULL_ENABLE, -1 },
3586};
3587
3588static const struct map_data pangd_pull_s2v[] = {
3589 { PULL_UP, PANGD_PULL_UP },
3590 { HIGH_HYSTERESIS, -1 },
3591 { HIGH_Z, PANGD_HIGH_Z },
3592 { PULL_DOWN, PANGD_PULL_DOWN },
3593 { PULL_DISABLE, -1 },
3594 { PULL_ENABLE, -1 },
3595};
3596
3597static const struct atlas7_pull_info atlas7_pull_map[] = {
3598 { PAD_T_4WE_PD, P4WE_PULL_MASK, p4we_pull_v2s, p4we_pull_s2v },
3599 { PAD_T_4WE_PU, P4WE_PULL_MASK, p4we_pull_v2s, p4we_pull_s2v },
3600 { PAD_T_16ST, P16ST_PULL_MASK, p16st_pull_v2s, p16st_pull_s2v },
3601 { PAD_T_M31_0204_PD, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
3602 { PAD_T_M31_0204_PU, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
3603 { PAD_T_M31_0610_PD, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
3604 { PAD_T_M31_0610_PU, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
3605 { PAD_T_AD, PANGD_PULL_MASK, pangd_pull_v2s, pangd_pull_s2v },
3606};
3607
3608/**
3609 * struct atlas7_ds_ma_info - Atlas7 Pad DriveStrength & currents info
3610 * @ma: The Drive Strength in current value .
3611 * @ds_16st: The correspond raw value of 16st pad.
3612 * @ds_4we: The correspond raw value of 4we pad.
3613 * @ds_0204m31: The correspond raw value of 0204m31 pad.
3614 * @ds_0610m31: The correspond raw value of 0610m31 pad.
3615 */
3616struct atlas7_ds_ma_info {
3617 u32 ma;
3618 u32 ds_16st;
3619 u32 ds_4we;
3620 u32 ds_0204m31;
3621 u32 ds_0610m31;
3622};
3623
3624static const struct atlas7_ds_ma_info atlas7_ma2ds_map[] = {
3625 { 2, DS_16ST_0, DS_4WE_0, DS_M31_0, DS_NULL },
3626 { 4, DS_16ST_1, DS_NULL, DS_M31_1, DS_NULL },
3627 { 6, DS_16ST_2, DS_NULL, DS_NULL, DS_M31_0 },
3628 { 8, DS_16ST_3, DS_4WE_1, DS_NULL, DS_NULL },
3629 { 10, DS_16ST_4, DS_NULL, DS_NULL, DS_M31_1 },
3630 { 12, DS_16ST_5, DS_NULL, DS_NULL, DS_NULL },
3631 { 14, DS_16ST_6, DS_NULL, DS_NULL, DS_NULL },
3632 { 16, DS_16ST_7, DS_4WE_2, DS_NULL, DS_NULL },
3633 { 18, DS_16ST_8, DS_NULL, DS_NULL, DS_NULL },
3634 { 20, DS_16ST_9, DS_NULL, DS_NULL, DS_NULL },
3635 { 22, DS_16ST_10, DS_NULL, DS_NULL, DS_NULL },
3636 { 24, DS_16ST_11, DS_NULL, DS_NULL, DS_NULL },
3637 { 26, DS_16ST_12, DS_NULL, DS_NULL, DS_NULL },
3638 { 28, DS_16ST_13, DS_4WE_3, DS_NULL, DS_NULL },
3639 { 30, DS_16ST_14, DS_NULL, DS_NULL, DS_NULL },
3640 { 32, DS_16ST_15, DS_NULL, DS_NULL, DS_NULL },
3641};
3642
3643/**
3644 * struct atlas7_ds_info - Atlas7 Pad DriveStrength info
3645 * @type: The type of this Pad.
3646 * @mask: The mask value of this pin's pull bits.
3647 * @imval: The immediate value of drives trength register.
3648 */
3649struct atlas7_ds_info {
3650 u8 type;
3651 u8 mask;
3652 u8 imval;
3653 u8 reserved;
3654};
3655
3656static const struct atlas7_ds_info atlas7_ds_map[] = {
3657 { PAD_T_4WE_PD, DS_2BIT_MASK, DS_2BIT_IM_VAL },
3658 { PAD_T_4WE_PU, DS_2BIT_MASK, DS_2BIT_IM_VAL },
3659 { PAD_T_16ST, DS_4BIT_MASK, DS_4BIT_IM_VAL },
3660 { PAD_T_M31_0204_PD, DS_1BIT_MASK, DS_1BIT_IM_VAL },
3661 { PAD_T_M31_0204_PU, DS_1BIT_MASK, DS_1BIT_IM_VAL },
3662 { PAD_T_M31_0610_PD, DS_1BIT_MASK, DS_1BIT_IM_VAL },
3663 { PAD_T_M31_0610_PU, DS_1BIT_MASK, DS_1BIT_IM_VAL },
3664 { PAD_T_AD, DS_NULL, DS_NULL },
3665};
3666
3483static inline u32 atlas7_pin_to_bank(u32 pin) 3667static inline u32 atlas7_pin_to_bank(u32 pin)
3484{ 3668{
3485 return (pin >= ATLAS7_PINCTRL_BANK_0_PINS) ? 1 : 0; 3669 return (pin >= ATLAS7_PINCTRL_BANK_0_PINS) ? 1 : 0;
@@ -3682,49 +3866,22 @@ static int atlas7_pmx_set_mux(struct pinctrl_dev *pctldev,
3682 return 0; 3866 return 0;
3683} 3867}
3684 3868
3685struct atlas7_ds_info {
3686 u32 ma;
3687 u32 ds_16st;
3688 u32 ds_4we;
3689 u32 ds_0204m31;
3690 u32 ds_0610m31;
3691};
3692
3693const struct atlas7_ds_info atlas7_ds_map[] = {
3694 { 2, DS_16ST_0, DS_4WE_0, DS_M31_0, DS_NULL},
3695 { 4, DS_16ST_1, DS_NULL, DS_M31_1, DS_NULL},
3696 { 6, DS_16ST_2, DS_NULL, DS_NULL, DS_M31_0},
3697 { 8, DS_16ST_3, DS_4WE_1, DS_NULL, DS_NULL},
3698 { 10, DS_16ST_4, DS_NULL, DS_NULL, DS_M31_1},
3699 { 12, DS_16ST_5, DS_NULL, DS_NULL, DS_NULL},
3700 { 14, DS_16ST_6, DS_NULL, DS_NULL, DS_NULL},
3701 { 16, DS_16ST_7, DS_4WE_2, DS_NULL, DS_NULL},
3702 { 18, DS_16ST_8, DS_NULL, DS_NULL, DS_NULL},
3703 { 20, DS_16ST_9, DS_NULL, DS_NULL, DS_NULL},
3704 { 22, DS_16ST_10, DS_NULL, DS_NULL, DS_NULL},
3705 { 24, DS_16ST_11, DS_NULL, DS_NULL, DS_NULL},
3706 { 26, DS_16ST_12, DS_NULL, DS_NULL, DS_NULL},
3707 { 28, DS_16ST_13, DS_4WE_3, DS_NULL, DS_NULL},
3708 { 30, DS_16ST_14, DS_NULL, DS_NULL, DS_NULL},
3709 { 32, DS_16ST_15, DS_NULL, DS_NULL, DS_NULL},
3710};
3711
3712static u32 convert_current_to_drive_strength(u32 type, u32 ma) 3869static u32 convert_current_to_drive_strength(u32 type, u32 ma)
3713{ 3870{
3714 int idx; 3871 int idx;
3715 3872
3716 for (idx = 0; idx < ARRAY_SIZE(atlas7_ds_map); idx++) { 3873 for (idx = 0; idx < ARRAY_SIZE(atlas7_ma2ds_map); idx++) {
3717 if (atlas7_ds_map[idx].ma != ma) 3874 if (atlas7_ma2ds_map[idx].ma != ma)
3718 continue; 3875 continue;
3719 3876
3720 if (type == PAD_T_4WE_PD || type == PAD_T_4WE_PU) 3877 if (type == PAD_T_4WE_PD || type == PAD_T_4WE_PU)
3721 return atlas7_ds_map[idx].ds_4we; 3878 return atlas7_ma2ds_map[idx].ds_4we;
3722 else if (type == PAD_T_16ST) 3879 else if (type == PAD_T_16ST)
3723 return atlas7_ds_map[idx].ds_16st; 3880 return atlas7_ma2ds_map[idx].ds_16st;
3724 else if (type == PAD_T_M31_0204_PD || type == PAD_T_M31_0204_PU) 3881 else if (type == PAD_T_M31_0204_PD || type == PAD_T_M31_0204_PU)
3725 return atlas7_ds_map[idx].ds_0204m31; 3882 return atlas7_ma2ds_map[idx].ds_0204m31;
3726 else if (type == PAD_T_M31_0610_PD || type == PAD_T_M31_0610_PU) 3883 else if (type == PAD_T_M31_0610_PD || type == PAD_T_M31_0610_PU)
3727 return atlas7_ds_map[idx].ds_0610m31; 3884 return atlas7_ma2ds_map[idx].ds_0610m31;
3728 } 3885 }
3729 3886
3730 return DS_NULL; 3887 return DS_NULL;
@@ -3735,78 +3892,21 @@ static int altas7_pinctrl_set_pull_sel(struct pinctrl_dev *pctldev,
3735{ 3892{
3736 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 3893 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
3737 struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin]; 3894 struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
3738 u32 type = conf->type; 3895 const struct atlas7_pull_info *pull_info;
3739 u32 shift = conf->pupd_bit; 3896 u32 bank;
3740 u32 bank = atlas7_pin_to_bank(pin); 3897 unsigned long regv;
3741 void __iomem *pull_sel_reg, *pull_clr_reg; 3898 void __iomem *pull_sel_reg;
3742 3899
3900 bank = atlas7_pin_to_bank(pin);
3901 pull_info = &atlas7_pull_map[conf->type];
3743 pull_sel_reg = pmx->regs[bank] + conf->pupd_reg; 3902 pull_sel_reg = pmx->regs[bank] + conf->pupd_reg;
3744 pull_clr_reg = CLR_REG(pull_sel_reg); 3903
3745 3904 /* Retrieve correspond register value from table by sel */
3746 if (type == PAD_T_4WE_PD || type == PAD_T_4WE_PU) { 3905 regv = pull_info->s2v[sel].data & pull_info->mask;
3747 writel(P4WE_PULL_MASK << shift, pull_clr_reg); 3906
3748 3907 /* Clear & Set new value to pull register */
3749 if (sel == PULL_UP) 3908 writel(pull_info->mask << conf->pupd_bit, CLR_REG(pull_sel_reg));
3750 writel(P4WE_PULL_UP << shift, pull_sel_reg); 3909 writel(regv << conf->pupd_bit, pull_sel_reg);
3751 else if (sel == HIGH_HYSTERESIS)
3752 writel(P4WE_HIGH_HYSTERESIS << shift, pull_sel_reg);
3753 else if (sel == HIGH_Z)
3754 writel(P4WE_HIGH_Z << shift, pull_sel_reg);
3755 else if (sel == PULL_DOWN)
3756 writel(P4WE_PULL_DOWN << shift, pull_sel_reg);
3757 else {
3758 pr_err("Unknown Pull select type for 4WEPAD#%d\n",
3759 pin);
3760 return -ENOTSUPP;
3761 }
3762 } else if (type == PAD_T_16ST) {
3763 writel(P16ST_PULL_MASK << shift, pull_clr_reg);
3764
3765 if (sel == PULL_UP)
3766 writel(P16ST_PULL_UP << shift, pull_sel_reg);
3767 else if (sel == HIGH_Z)
3768 writel(P16ST_HIGH_Z << shift, pull_sel_reg);
3769 else if (sel == PULL_DOWN)
3770 writel(P16ST_PULL_DOWN << shift, pull_sel_reg);
3771 else {
3772 pr_err("Unknown Pull select type for 16STPAD#%d\n",
3773 pin);
3774 return -ENOTSUPP;
3775 }
3776 } else if (type == PAD_T_M31_0204_PD ||
3777 type == PAD_T_M31_0204_PU ||
3778 type == PAD_T_M31_0610_PD ||
3779 type == PAD_T_M31_0610_PU) {
3780 writel(PM31_PULL_MASK << shift, pull_clr_reg);
3781
3782 if (sel == PULL_UP)
3783 writel(PM31_PULL_ENABLED << shift, pull_sel_reg);
3784 else if (sel == PULL_DOWN)
3785 writel(PM31_PULL_DISABLED << shift, pull_sel_reg);
3786 else {
3787 pr_err("Unknown Pull select type for M31PAD#%d\n",
3788 pin);
3789 return -ENOTSUPP;
3790 }
3791 } else if (type == PAD_T_AD) {
3792 writel(PANGD_PULL_MASK << shift, pull_clr_reg);
3793
3794 if (sel == PULL_UP)
3795 writel(PANGD_PULL_UP << shift, pull_sel_reg);
3796 else if (sel == HIGH_Z)
3797 writel(PANGD_HIGH_Z << shift, pull_sel_reg);
3798 else if (sel == PULL_DOWN)
3799 writel(PANGD_PULL_DOWN << shift, pull_sel_reg);
3800 else {
3801 pr_err("Unknown Pull select type for A/D PAD#%d\n",
3802 pin);
3803 return -ENOTSUPP;
3804 }
3805 } else {
3806 pr_err("Unknown Pad type[%d] for pull select PAD#%d\n",
3807 type, pin);
3808 return -ENOTSUPP;
3809 }
3810 3910
3811 pr_debug("PIN_CFG ### SET PIN#%d PULL SELECTOR:%d == OK ####\n", 3911 pr_debug("PIN_CFG ### SET PIN#%d PULL SELECTOR:%d == OK ####\n",
3812 pin, sel); 3912 pin, sel);
@@ -3818,43 +3918,25 @@ static int __altas7_pinctrl_set_drive_strength_sel(struct pinctrl_dev *pctldev,
3818{ 3918{
3819 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); 3919 struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
3820 struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin]; 3920 struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
3821 u32 type = conf->type; 3921 const struct atlas7_ds_info *ds_info;
3822 u32 shift = conf->drvstr_bit; 3922 u32 bank;
3823 u32 bank = atlas7_pin_to_bank(pin); 3923 void __iomem *ds_sel_reg;
3824 void __iomem *ds_sel_reg, *ds_clr_reg;
3825
3826 ds_sel_reg = pmx->regs[bank] + conf->drvstr_reg;
3827 ds_clr_reg = CLR_REG(ds_sel_reg);
3828 if (type == PAD_T_4WE_PD || type == PAD_T_4WE_PU) {
3829 if (sel & (~DS_2BIT_MASK))
3830 goto unsupport;
3831
3832 writel(DS_2BIT_IM_VAL << shift, ds_clr_reg);
3833 writel(sel << shift, ds_sel_reg);
3834
3835 return 0;
3836 } else if (type == PAD_T_16ST) {
3837 if (sel & (~DS_4BIT_MASK))
3838 goto unsupport;
3839 3924
3840 writel(DS_4BIT_IM_VAL << shift, ds_clr_reg); 3925 ds_info = &atlas7_ds_map[conf->type];
3841 writel(sel << shift, ds_sel_reg); 3926 if (sel & (~(ds_info->mask)))
3927 goto unsupport;
3842 3928
3843 return 0; 3929 bank = atlas7_pin_to_bank(pin);
3844 } else if (type == PAD_T_M31_0204_PD || type == PAD_T_M31_0204_PU || 3930 ds_sel_reg = pmx->regs[bank] + conf->drvstr_reg;
3845 type == PAD_T_M31_0610_PD || type == PAD_T_M31_0610_PU) {
3846 if (sel & (~DS_1BIT_MASK))
3847 goto unsupport;
3848 3931
3849 writel(DS_1BIT_IM_VAL << shift, ds_clr_reg); 3932 writel(ds_info->imval << conf->drvstr_bit, CLR_REG(ds_sel_reg));
3850 writel(sel << shift, ds_sel_reg); 3933 writel(sel << conf->drvstr_bit, ds_sel_reg);
3851 3934
3852 return 0; 3935 return 0;
3853 }
3854 3936
3855unsupport: 3937unsupport:
3856 pr_err("Pad#%d type[%d] doesn't support ds code[%d]!\n", 3938 pr_err("Pad#%d type[%d] doesn't support ds code[%d]!\n",
3857 pin, type, sel); 3939 pin, conf->type, sel);
3858 return -ENOTSUPP; 3940 return -ENOTSUPP;
3859} 3941}
3860 3942
@@ -4101,14 +4183,135 @@ unmap_io:
4101 return ret; 4183 return ret;
4102} 4184}
4103 4185
4186#ifdef CONFIG_PM_SLEEP
4187static int atlas7_pinmux_suspend_noirq(struct device *dev)
4188{
4189 struct atlas7_pmx *pmx = dev_get_drvdata(dev);
4190 struct atlas7_pad_status *status;
4191 struct atlas7_pad_config *conf;
4192 const struct atlas7_ds_info *ds_info;
4193 const struct atlas7_pull_info *pull_info;
4194 int idx;
4195 u32 bank;
4196 unsigned long regv;
4197
4198 for (idx = 0; idx < pmx->pctl_desc.npins; idx++) {
4199 /* Get this Pad's descriptor from PINCTRL */
4200 conf = &pmx->pctl_data->confs[idx];
4201 bank = atlas7_pin_to_bank(idx);
4202 status = &pmx->sleep_data[idx];
4203
4204 /* Save Function selector */
4205 regv = readl(pmx->regs[bank] + conf->mux_reg);
4206 status->func = (regv >> conf->mux_bit) & FUNC_CLEAR_MASK;
4207
4208 /* Check if Pad is in Analogue selector */
4209 if (conf->ad_ctrl_reg == -1)
4210 goto save_ds_sel;
4211
4212 regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg);
4213 if (!(regv & (conf->ad_ctrl_bit << ANA_CLEAR_MASK)))
4214 status->func = FUNC_ANALOGUE;
4215
4216save_ds_sel:
4217 if (conf->drvstr_reg == -1)
4218 goto save_pull_sel;
4219
4220 /* Save Drive Strength selector */
4221 ds_info = &atlas7_ds_map[conf->type];
4222 regv = readl(pmx->regs[bank] + conf->drvstr_reg);
4223 status->dstr = (regv >> conf->drvstr_bit) & ds_info->mask;
4224
4225save_pull_sel:
4226 /* Save Pull selector */
4227 pull_info = &atlas7_pull_map[conf->type];
4228 regv = readl(pmx->regs[bank] + conf->pupd_reg);
4229 regv = (regv >> conf->pupd_bit) & pull_info->mask;
4230 status->pull = pull_info->v2s[regv].data;
4231 }
4232
4233 /*
4234 * Save disable input selector, this selector is not for Pin,
4235 * but for Mux function.
4236 */
4237 for (idx = 0; idx < NUM_OF_IN_DISABLE_REG; idx++) {
4238 pmx->status_ds[idx] = readl(pmx->regs[BANK_DS] +
4239 IN_DISABLE_0_REG_SET + 0x8 * idx);
4240 pmx->status_dsv[idx] = readl(pmx->regs[BANK_DS] +
4241 IN_DISABLE_VAL_0_REG_SET + 0x8 * idx);
4242 }
4243
4244 return 0;
4245}
4246
4247static int atlas7_pinmux_resume_noirq(struct device *dev)
4248{
4249 struct atlas7_pmx *pmx = dev_get_drvdata(dev);
4250 struct atlas7_pad_status *status;
4251 struct atlas7_pad_config *conf;
4252 int idx;
4253 u32 bank;
4254
4255 for (idx = 0; idx < pmx->pctl_desc.npins; idx++) {
4256 /* Get this Pad's descriptor from PINCTRL */
4257 conf = &pmx->pctl_data->confs[idx];
4258 bank = atlas7_pin_to_bank(idx);
4259 status = &pmx->sleep_data[idx];
4260
4261 /* Restore Function selector */
4262 __atlas7_pmx_pin_enable(pmx, idx, (u32)status->func & 0xff);
4263
4264 if (FUNC_ANALOGUE == status->func)
4265 goto restore_pull_sel;
4266
4267 /* Restore Drive Strength selector */
4268 __altas7_pinctrl_set_drive_strength_sel(pmx->pctl, idx,
4269 (u32)status->dstr & 0xff);
4270
4271restore_pull_sel:
4272 /* Restore Pull selector */
4273 altas7_pinctrl_set_pull_sel(pmx->pctl, idx,
4274 (u32)status->pull & 0xff);
4275 }
4276
4277 /*
4278 * Restore disable input selector, this selector is not for Pin,
4279 * but for Mux function
4280 */
4281 for (idx = 0; idx < NUM_OF_IN_DISABLE_REG; idx++) {
4282 writel(~0, pmx->regs[BANK_DS] +
4283 IN_DISABLE_0_REG_CLR + 0x8 * idx);
4284 writel(pmx->status_ds[idx], pmx->regs[BANK_DS] +
4285 IN_DISABLE_0_REG_SET + 0x8 * idx);
4286 writel(~0, pmx->regs[BANK_DS] +
4287 IN_DISABLE_VAL_0_REG_CLR + 0x8 * idx);
4288 writel(pmx->status_dsv[idx], pmx->regs[BANK_DS] +
4289 IN_DISABLE_VAL_0_REG_SET + 0x8 * idx);
4290 }
4291
4292 return 0;
4293}
4294
4295static const struct dev_pm_ops atlas7_pinmux_pm_ops = {
4296 .suspend_noirq = atlas7_pinmux_suspend_noirq,
4297 .resume_noirq = atlas7_pinmux_resume_noirq,
4298 .freeze_noirq = atlas7_pinmux_suspend_noirq,
4299 .restore_noirq = atlas7_pinmux_resume_noirq,
4300};
4301#endif
4302
4104static const struct of_device_id atlas7_pinmux_ids[] = { 4303static const struct of_device_id atlas7_pinmux_ids[] = {
4105 { .compatible = "sirf,atlas7-ioc",}, 4304 { .compatible = "sirf,atlas7-ioc",},
4305 {},
4106}; 4306};
4107 4307
4108static struct platform_driver atlas7_pinmux_driver = { 4308static struct platform_driver atlas7_pinmux_driver = {
4109 .driver = { 4309 .driver = {
4110 .name = "atlas7-ioc", 4310 .name = "atlas7-ioc",
4111 .of_match_table = atlas7_pinmux_ids, 4311 .of_match_table = atlas7_pinmux_ids,
4312#ifdef CONFIG_PM_SLEEP
4313 .pm = &atlas7_pinmux_pm_ops,
4314#endif
4112 }, 4315 },
4113 .probe = atlas7_pinmux_probe, 4316 .probe = atlas7_pinmux_probe,
4114}; 4317};
@@ -4286,14 +4489,15 @@ static struct irq_chip atlas7_gpio_irq_chip = {
4286 .irq_set_type = atlas7_gpio_irq_type, 4489 .irq_set_type = atlas7_gpio_irq_type,
4287}; 4490};
4288 4491
4289static void atlas7_gpio_handle_irq(unsigned int irq, struct irq_desc *desc) 4492static void atlas7_gpio_handle_irq(unsigned int __irq, struct irq_desc *desc)
4290{ 4493{
4291 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 4494 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
4292 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(gc); 4495 struct atlas7_gpio_chip *a7gc = to_atlas7_gpio(gc);
4293 struct atlas7_gpio_bank *bank = NULL; 4496 struct atlas7_gpio_bank *bank = NULL;
4294 u32 status, ctrl; 4497 u32 status, ctrl;
4295 int pin_in_bank = 0, idx; 4498 int pin_in_bank = 0, idx;
4296 struct irq_chip *chip = irq_get_chip(irq); 4499 struct irq_chip *chip = irq_desc_get_chip(desc);
4500 unsigned int irq = irq_desc_get_irq(desc);
4297 4501
4298 for (idx = 0; idx < a7gc->nbank; idx++) { 4502 for (idx = 0; idx < a7gc->nbank; idx++) {
4299 bank = &a7gc->banks[idx]; 4503 bank = &a7gc->banks[idx];
@@ -4496,6 +4700,7 @@ static void atlas7_gpio_set_value(struct gpio_chip *chip,
4496 4700
4497static const struct of_device_id atlas7_gpio_ids[] = { 4701static const struct of_device_id atlas7_gpio_ids[] = {
4498 { .compatible = "sirf,atlas7-gpio", }, 4702 { .compatible = "sirf,atlas7-gpio", },
4703 {},
4499}; 4704};
4500 4705
4501static int atlas7_gpio_probe(struct platform_device *pdev) 4706static int atlas7_gpio_probe(struct platform_device *pdev)
@@ -4612,17 +4817,65 @@ static int atlas7_gpio_probe(struct platform_device *pdev)
4612 BUG_ON(!bank->pctldev); 4817 BUG_ON(!bank->pctldev);
4613 } 4818 }
4614 4819
4820 platform_set_drvdata(pdev, a7gc);
4615 dev_info(&pdev->dev, "add to system.\n"); 4821 dev_info(&pdev->dev, "add to system.\n");
4616 return 0; 4822 return 0;
4617failed: 4823failed:
4618 return ret; 4824 return ret;
4619} 4825}
4620 4826
4827#ifdef CONFIG_PM_SLEEP
4828static int atlas7_gpio_suspend_noirq(struct device *dev)
4829{
4830 struct atlas7_gpio_chip *a7gc = dev_get_drvdata(dev);
4831 struct atlas7_gpio_bank *bank;
4832 void __iomem *ctrl_reg;
4833 u32 idx, pin;
4834
4835 for (idx = 0; idx < a7gc->nbank; idx++) {
4836 bank = &a7gc->banks[idx];
4837 for (pin = 0; pin < bank->ngpio; pin++) {
4838 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin);
4839 bank->sleep_data[pin] = readl(ctrl_reg);
4840 }
4841 }
4842
4843 return 0;
4844}
4845
4846static int atlas7_gpio_resume_noirq(struct device *dev)
4847{
4848 struct atlas7_gpio_chip *a7gc = dev_get_drvdata(dev);
4849 struct atlas7_gpio_bank *bank;
4850 void __iomem *ctrl_reg;
4851 u32 idx, pin;
4852
4853 for (idx = 0; idx < a7gc->nbank; idx++) {
4854 bank = &a7gc->banks[idx];
4855 for (pin = 0; pin < bank->ngpio; pin++) {
4856 ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin);
4857 writel(bank->sleep_data[pin], ctrl_reg);
4858 }
4859 }
4860
4861 return 0;
4862}
4863
4864static const struct dev_pm_ops atlas7_gpio_pm_ops = {
4865 .suspend_noirq = atlas7_gpio_suspend_noirq,
4866 .resume_noirq = atlas7_gpio_resume_noirq,
4867 .freeze_noirq = atlas7_gpio_suspend_noirq,
4868 .restore_noirq = atlas7_gpio_resume_noirq,
4869};
4870#endif
4871
4621static struct platform_driver atlas7_gpio_driver = { 4872static struct platform_driver atlas7_gpio_driver = {
4622 .driver = { 4873 .driver = {
4623 .name = "atlas7-gpio", 4874 .name = "atlas7-gpio",
4624 .owner = THIS_MODULE,
4625 .of_match_table = atlas7_gpio_ids, 4875 .of_match_table = atlas7_gpio_ids,
4876#ifdef CONFIG_PM_SLEEP
4877 .pm = &atlas7_gpio_pm_ops,
4878#endif
4626 }, 4879 },
4627 .probe = atlas7_gpio_probe, 4880 .probe = atlas7_gpio_probe,
4628}; 4881};
diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c
index 8ba26e45499a..f8bd9fb52033 100644
--- a/drivers/pinctrl/sirf/pinctrl-sirf.c
+++ b/drivers/pinctrl/sirf/pinctrl-sirf.c
@@ -545,14 +545,15 @@ static struct irq_chip sirfsoc_irq_chip = {
545 .irq_set_type = sirfsoc_gpio_irq_type, 545 .irq_set_type = sirfsoc_gpio_irq_type,
546}; 546};
547 547
548static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc) 548static void sirfsoc_gpio_handle_irq(unsigned int __irq, struct irq_desc *desc)
549{ 549{
550 unsigned int irq = irq_desc_get_irq(desc);
550 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 551 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
551 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc); 552 struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(gc);
552 struct sirfsoc_gpio_bank *bank; 553 struct sirfsoc_gpio_bank *bank;
553 u32 status, ctrl; 554 u32 status, ctrl;
554 int idx = 0; 555 int idx = 0;
555 struct irq_chip *chip = irq_get_chip(irq); 556 struct irq_chip *chip = irq_desc_get_chip(desc);
556 int i; 557 int i;
557 558
558 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { 559 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
index 7376a97b5e65..862a096c5dba 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
@@ -135,7 +135,14 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
135 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), 135 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
136 SUNXI_FUNCTION(0x0, "gpio_in"), 136 SUNXI_FUNCTION(0x0, "gpio_in"),
137 SUNXI_FUNCTION(0x1, "gpio_out"), 137 SUNXI_FUNCTION(0x1, "gpio_out"),
138 SUNXI_FUNCTION(0x2, "ir0")), /* TX */ 138 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
139 /*
140 * The SPDIF block is not referenced at all in the A10 user
141 * manual. However it is described in the code leaked and the
142 * pin descriptions are declared in the A20 user manual which
143 * is pin compatible with this device.
144 */
145 SUNXI_FUNCTION(0x4, "spdif")), /* SPDIF MCLK */
139 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), 146 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
140 SUNXI_FUNCTION(0x0, "gpio_in"), 147 SUNXI_FUNCTION(0x0, "gpio_in"),
141 SUNXI_FUNCTION(0x1, "gpio_out"), 148 SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -176,11 +183,15 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
176 SUNXI_FUNCTION(0x0, "gpio_in"), 183 SUNXI_FUNCTION(0x0, "gpio_in"),
177 SUNXI_FUNCTION(0x1, "gpio_out"), 184 SUNXI_FUNCTION(0x1, "gpio_out"),
178 SUNXI_FUNCTION(0x2, "i2s"), /* DI */ 185 SUNXI_FUNCTION(0x2, "i2s"), /* DI */
179 SUNXI_FUNCTION(0x3, "ac97")), /* DI */ 186 SUNXI_FUNCTION(0x3, "ac97"), /* DI */
187 /* Undocumented mux function - See SPDIF MCLK above */
188 SUNXI_FUNCTION(0x4, "spdif")), /* SPDIF IN */
180 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13), 189 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
181 SUNXI_FUNCTION(0x0, "gpio_in"), 190 SUNXI_FUNCTION(0x0, "gpio_in"),
182 SUNXI_FUNCTION(0x1, "gpio_out"), 191 SUNXI_FUNCTION(0x1, "gpio_out"),
183 SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */ 192 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
193 /* Undocumented mux function - See SPDIF MCLK above */
194 SUNXI_FUNCTION(0x4, "spdif")), /* SPDIF OUT */
184 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14), 195 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14),
185 SUNXI_FUNCTION(0x0, "gpio_in"), 196 SUNXI_FUNCTION(0x0, "gpio_in"),
186 SUNXI_FUNCTION(0x1, "gpio_out"), 197 SUNXI_FUNCTION(0x1, "gpio_out"),
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index f09573e13203..fb4669c0ce0e 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -588,7 +588,6 @@ static void sunxi_pinctrl_irq_release_resources(struct irq_data *d)
588static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type) 588static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
589{ 589{
590 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 590 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
591 struct irq_desc *desc = container_of(d, struct irq_desc, irq_data);
592 u32 reg = sunxi_irq_cfg_reg(d->hwirq); 591 u32 reg = sunxi_irq_cfg_reg(d->hwirq);
593 u8 index = sunxi_irq_cfg_offset(d->hwirq); 592 u8 index = sunxi_irq_cfg_offset(d->hwirq);
594 unsigned long flags; 593 unsigned long flags;
@@ -615,16 +614,17 @@ static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
615 return -EINVAL; 614 return -EINVAL;
616 } 615 }
617 616
618 if (type & IRQ_TYPE_LEVEL_MASK) {
619 d->chip = &sunxi_pinctrl_level_irq_chip;
620 desc->handle_irq = handle_fasteoi_irq;
621 } else {
622 d->chip = &sunxi_pinctrl_edge_irq_chip;
623 desc->handle_irq = handle_edge_irq;
624 }
625
626 spin_lock_irqsave(&pctl->lock, flags); 617 spin_lock_irqsave(&pctl->lock, flags);
627 618
619 if (type & IRQ_TYPE_LEVEL_MASK)
620 __irq_set_chip_handler_name_locked(d->irq,
621 &sunxi_pinctrl_level_irq_chip,
622 handle_fasteoi_irq, NULL);
623 else
624 __irq_set_chip_handler_name_locked(d->irq,
625 &sunxi_pinctrl_edge_irq_chip,
626 handle_edge_irq, NULL);
627
628 regval = readl(pctl->membase + reg); 628 regval = readl(pctl->membase + reg);
629 regval &= ~(IRQ_CFG_IRQ_MASK << index); 629 regval &= ~(IRQ_CFG_IRQ_MASK << index);
630 writel(regval | (mode << index), pctl->membase + reg); 630 writel(regval | (mode << index), pctl->membase + reg);
@@ -685,6 +685,7 @@ static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d)
685} 685}
686 686
687static struct irq_chip sunxi_pinctrl_edge_irq_chip = { 687static struct irq_chip sunxi_pinctrl_edge_irq_chip = {
688 .name = "sunxi_pio_edge",
688 .irq_ack = sunxi_pinctrl_irq_ack, 689 .irq_ack = sunxi_pinctrl_irq_ack,
689 .irq_mask = sunxi_pinctrl_irq_mask, 690 .irq_mask = sunxi_pinctrl_irq_mask,
690 .irq_unmask = sunxi_pinctrl_irq_unmask, 691 .irq_unmask = sunxi_pinctrl_irq_unmask,
@@ -695,6 +696,7 @@ static struct irq_chip sunxi_pinctrl_edge_irq_chip = {
695}; 696};
696 697
697static struct irq_chip sunxi_pinctrl_level_irq_chip = { 698static struct irq_chip sunxi_pinctrl_level_irq_chip = {
699 .name = "sunxi_pio_level",
698 .irq_eoi = sunxi_pinctrl_irq_ack, 700 .irq_eoi = sunxi_pinctrl_irq_ack,
699 .irq_mask = sunxi_pinctrl_irq_mask, 701 .irq_mask = sunxi_pinctrl_irq_mask,
700 .irq_unmask = sunxi_pinctrl_irq_unmask, 702 .irq_unmask = sunxi_pinctrl_irq_unmask,
@@ -709,10 +711,42 @@ static struct irq_chip sunxi_pinctrl_level_irq_chip = {
709 IRQCHIP_EOI_IF_HANDLED, 711 IRQCHIP_EOI_IF_HANDLED,
710}; 712};
711 713
712static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc) 714static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d,
715 struct device_node *node,
716 const u32 *intspec,
717 unsigned int intsize,
718 unsigned long *out_hwirq,
719 unsigned int *out_type)
720{
721 struct sunxi_desc_function *desc;
722 int pin, base;
723
724 if (intsize < 3)
725 return -EINVAL;
726
727 base = PINS_PER_BANK * intspec[0];
728 pin = base + intspec[1];
729
730 desc = sunxi_pinctrl_desc_find_function_by_pin(d->host_data,
731 pin, "irq");
732 if (!desc)
733 return -EINVAL;
734
735 *out_hwirq = desc->irqbank * PINS_PER_BANK + desc->irqnum;
736 *out_type = intspec[2];
737
738 return 0;
739}
740
741static struct irq_domain_ops sunxi_pinctrl_irq_domain_ops = {
742 .xlate = sunxi_pinctrl_irq_of_xlate,
743};
744
745static void sunxi_pinctrl_irq_handler(unsigned __irq, struct irq_desc *desc)
713{ 746{
714 struct irq_chip *chip = irq_get_chip(irq); 747 unsigned int irq = irq_desc_get_irq(desc);
715 struct sunxi_pinctrl *pctl = irq_get_handler_data(irq); 748 struct irq_chip *chip = irq_desc_get_chip(desc);
749 struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc);
716 unsigned long bank, reg, val; 750 unsigned long bank, reg, val;
717 751
718 for (bank = 0; bank < pctl->desc->irq_banks; bank++) 752 for (bank = 0; bank < pctl->desc->irq_banks; bank++)
@@ -983,8 +1017,8 @@ int sunxi_pinctrl_init(struct platform_device *pdev,
983 1017
984 pctl->domain = irq_domain_add_linear(node, 1018 pctl->domain = irq_domain_add_linear(node,
985 pctl->desc->irq_banks * IRQ_PER_BANK, 1019 pctl->desc->irq_banks * IRQ_PER_BANK,
986 &irq_domain_simple_ops, 1020 &sunxi_pinctrl_irq_domain_ops,
987 NULL); 1021 pctl);
988 if (!pctl->domain) { 1022 if (!pctl->domain) {
989 dev_err(&pdev->dev, "Couldn't register IRQ domain\n"); 1023 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
990 ret = -ENOMEM; 1024 ret = -ENOMEM;
diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig
new file mode 100644
index 000000000000..eab23ef9ddbf
--- /dev/null
+++ b/drivers/pinctrl/uniphier/Kconfig
@@ -0,0 +1,32 @@
1if ARCH_UNIPHIER
2
3config PINCTRL_UNIPHIER_CORE
4 bool
5 select PINMUX
6 select GENERIC_PINCONF
7
8config PINCTRL_UNIPHIER_PH1_LD4
9 tristate "UniPhier PH1-LD4 SoC pinctrl driver"
10 select PINCTRL_UNIPHIER_CORE
11
12config PINCTRL_UNIPHIER_PH1_PRO4
13 tristate "UniPhier PH1-Pro4 SoC pinctrl driver"
14 select PINCTRL_UNIPHIER_CORE
15
16config PINCTRL_UNIPHIER_PH1_SLD8
17 tristate "UniPhier PH1-sLD8 SoC pinctrl driver"
18 select PINCTRL_UNIPHIER_CORE
19
20config PINCTRL_UNIPHIER_PH1_PRO5
21 tristate "UniPhier PH1-Pro5 SoC pinctrl driver"
22 select PINCTRL_UNIPHIER_CORE
23
24config PINCTRL_UNIPHIER_PROXSTREAM2
25 tristate "UniPhier ProXstream2 SoC pinctrl driver"
26 select PINCTRL_UNIPHIER_CORE
27
28config PINCTRL_UNIPHIER_PH1_LD6B
29 tristate "UniPhier PH1-LD6b SoC pinctrl driver"
30 select PINCTRL_UNIPHIER_CORE
31
32endif
diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile
new file mode 100644
index 000000000000..e215b1097297
--- /dev/null
+++ b/drivers/pinctrl/uniphier/Makefile
@@ -0,0 +1,8 @@
1obj-$(CONFIG_PINCTRL_UNIPHIER_CORE) += pinctrl-uniphier-core.o
2
3obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o
4obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO4) += pinctrl-ph1-pro4.o
5obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_SLD8) += pinctrl-ph1-sld8.o
6obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_PRO5) += pinctrl-ph1-pro5.o
7obj-$(CONFIG_PINCTRL_UNIPHIER_PROXSTREAM2) += pinctrl-proxstream2.o
8obj-$(CONFIG_PINCTRL_UNIPHIER_PH1_LD6B) += pinctrl-ph1-ld6b.o
diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c b/drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c
new file mode 100644
index 000000000000..7beb87e8f499
--- /dev/null
+++ b/drivers/pinctrl/uniphier/pinctrl-ph1-ld4.c
@@ -0,0 +1,886 @@
1/*
2 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/pinctrl/pinctrl.h>
18#include <linux/platform_device.h>
19
20#include "pinctrl-uniphier.h"
21
22#define DRIVER_NAME "ph1-ld4-pinctrl"
23
24static const struct pinctrl_pin_desc ph1_ld4_pins[] = {
25 UNIPHIER_PINCTRL_PIN(0, "EA1", UNIPHIER_PIN_IECTRL_NONE,
26 8, UNIPHIER_PIN_DRV_4_8,
27 8, UNIPHIER_PIN_PULL_DOWN),
28 UNIPHIER_PINCTRL_PIN(1, "EA2", UNIPHIER_PIN_IECTRL_NONE,
29 9, UNIPHIER_PIN_DRV_4_8,
30 9, UNIPHIER_PIN_PULL_DOWN),
31 UNIPHIER_PINCTRL_PIN(2, "EA3", UNIPHIER_PIN_IECTRL_NONE,
32 10, UNIPHIER_PIN_DRV_4_8,
33 10, UNIPHIER_PIN_PULL_DOWN),
34 UNIPHIER_PINCTRL_PIN(3, "EA4", UNIPHIER_PIN_IECTRL_NONE,
35 11, UNIPHIER_PIN_DRV_4_8,
36 11, UNIPHIER_PIN_PULL_DOWN),
37 UNIPHIER_PINCTRL_PIN(4, "EA5", UNIPHIER_PIN_IECTRL_NONE,
38 12, UNIPHIER_PIN_DRV_4_8,
39 12, UNIPHIER_PIN_PULL_DOWN),
40 UNIPHIER_PINCTRL_PIN(5, "EA6", UNIPHIER_PIN_IECTRL_NONE,
41 13, UNIPHIER_PIN_DRV_4_8,
42 13, UNIPHIER_PIN_PULL_DOWN),
43 UNIPHIER_PINCTRL_PIN(6, "EA7", UNIPHIER_PIN_IECTRL_NONE,
44 14, UNIPHIER_PIN_DRV_4_8,
45 14, UNIPHIER_PIN_PULL_DOWN),
46 UNIPHIER_PINCTRL_PIN(7, "EA8", 0,
47 15, UNIPHIER_PIN_DRV_4_8,
48 15, UNIPHIER_PIN_PULL_DOWN),
49 UNIPHIER_PINCTRL_PIN(8, "EA9", 0,
50 16, UNIPHIER_PIN_DRV_4_8,
51 16, UNIPHIER_PIN_PULL_DOWN),
52 UNIPHIER_PINCTRL_PIN(9, "EA10", 0,
53 17, UNIPHIER_PIN_DRV_4_8,
54 17, UNIPHIER_PIN_PULL_DOWN),
55 UNIPHIER_PINCTRL_PIN(10, "EA11", 0,
56 18, UNIPHIER_PIN_DRV_4_8,
57 18, UNIPHIER_PIN_PULL_DOWN),
58 UNIPHIER_PINCTRL_PIN(11, "EA12", 0,
59 19, UNIPHIER_PIN_DRV_4_8,
60 19, UNIPHIER_PIN_PULL_DOWN),
61 UNIPHIER_PINCTRL_PIN(12, "EA13", 0,
62 20, UNIPHIER_PIN_DRV_4_8,
63 20, UNIPHIER_PIN_PULL_DOWN),
64 UNIPHIER_PINCTRL_PIN(13, "EA14", 0,
65 21, UNIPHIER_PIN_DRV_4_8,
66 21, UNIPHIER_PIN_PULL_DOWN),
67 UNIPHIER_PINCTRL_PIN(14, "EA15", 0,
68 22, UNIPHIER_PIN_DRV_4_8,
69 22, UNIPHIER_PIN_PULL_DOWN),
70 UNIPHIER_PINCTRL_PIN(15, "ECLK", UNIPHIER_PIN_IECTRL_NONE,
71 23, UNIPHIER_PIN_DRV_4_8,
72 23, UNIPHIER_PIN_PULL_DOWN),
73 UNIPHIER_PINCTRL_PIN(16, "XERWE0", UNIPHIER_PIN_IECTRL_NONE,
74 24, UNIPHIER_PIN_DRV_4_8,
75 24, UNIPHIER_PIN_PULL_UP),
76 UNIPHIER_PINCTRL_PIN(17, "XERWE1", UNIPHIER_PIN_IECTRL_NONE,
77 25, UNIPHIER_PIN_DRV_4_8,
78 25, UNIPHIER_PIN_PULL_UP),
79 UNIPHIER_PINCTRL_PIN(18, "ES0", UNIPHIER_PIN_IECTRL_NONE,
80 27, UNIPHIER_PIN_DRV_4_8,
81 27, UNIPHIER_PIN_PULL_UP),
82 UNIPHIER_PINCTRL_PIN(19, "ES1", UNIPHIER_PIN_IECTRL_NONE,
83 28, UNIPHIER_PIN_DRV_4_8,
84 28, UNIPHIER_PIN_PULL_UP),
85 UNIPHIER_PINCTRL_PIN(20, "ES2", UNIPHIER_PIN_IECTRL_NONE,
86 29, UNIPHIER_PIN_DRV_4_8,
87 29, UNIPHIER_PIN_PULL_UP),
88 UNIPHIER_PINCTRL_PIN(21, "XERST", UNIPHIER_PIN_IECTRL_NONE,
89 38, UNIPHIER_PIN_DRV_4_8,
90 38, UNIPHIER_PIN_PULL_UP),
91 UNIPHIER_PINCTRL_PIN(22, "MMCCLK", UNIPHIER_PIN_IECTRL_NONE,
92 0, UNIPHIER_PIN_DRV_8_12_16_20,
93 146, UNIPHIER_PIN_PULL_UP),
94 UNIPHIER_PINCTRL_PIN(23, "MMCCMD", UNIPHIER_PIN_IECTRL_NONE,
95 4, UNIPHIER_PIN_DRV_8_12_16_20,
96 147, UNIPHIER_PIN_PULL_UP),
97 UNIPHIER_PINCTRL_PIN(24, "MMCDAT0", UNIPHIER_PIN_IECTRL_NONE,
98 8, UNIPHIER_PIN_DRV_8_12_16_20,
99 148, UNIPHIER_PIN_PULL_UP),
100 UNIPHIER_PINCTRL_PIN(25, "MMCDAT1", UNIPHIER_PIN_IECTRL_NONE,
101 12, UNIPHIER_PIN_DRV_8_12_16_20,
102 149, UNIPHIER_PIN_PULL_UP),
103 UNIPHIER_PINCTRL_PIN(26, "MMCDAT2", UNIPHIER_PIN_IECTRL_NONE,
104 16, UNIPHIER_PIN_DRV_8_12_16_20,
105 150, UNIPHIER_PIN_PULL_UP),
106 UNIPHIER_PINCTRL_PIN(27, "MMCDAT3", UNIPHIER_PIN_IECTRL_NONE,
107 20, UNIPHIER_PIN_DRV_8_12_16_20,
108 151, UNIPHIER_PIN_PULL_UP),
109 UNIPHIER_PINCTRL_PIN(28, "MMCDAT4", UNIPHIER_PIN_IECTRL_NONE,
110 24, UNIPHIER_PIN_DRV_8_12_16_20,
111 152, UNIPHIER_PIN_PULL_UP),
112 UNIPHIER_PINCTRL_PIN(29, "MMCDAT5", UNIPHIER_PIN_IECTRL_NONE,
113 28, UNIPHIER_PIN_DRV_8_12_16_20,
114 153, UNIPHIER_PIN_PULL_UP),
115 UNIPHIER_PINCTRL_PIN(30, "MMCDAT6", UNIPHIER_PIN_IECTRL_NONE,
116 32, UNIPHIER_PIN_DRV_8_12_16_20,
117 154, UNIPHIER_PIN_PULL_UP),
118 UNIPHIER_PINCTRL_PIN(31, "MMCDAT7", UNIPHIER_PIN_IECTRL_NONE,
119 36, UNIPHIER_PIN_DRV_8_12_16_20,
120 155, UNIPHIER_PIN_PULL_UP),
121 UNIPHIER_PINCTRL_PIN(32, "RMII_RXD0", 6,
122 39, UNIPHIER_PIN_DRV_4_8,
123 39, UNIPHIER_PIN_PULL_DOWN),
124 UNIPHIER_PINCTRL_PIN(33, "RMII_RXD1", 6,
125 40, UNIPHIER_PIN_DRV_4_8,
126 40, UNIPHIER_PIN_PULL_DOWN),
127 UNIPHIER_PINCTRL_PIN(34, "RMII_CRS_DV", 6,
128 41, UNIPHIER_PIN_DRV_4_8,
129 41, UNIPHIER_PIN_PULL_DOWN),
130 UNIPHIER_PINCTRL_PIN(35, "RMII_RXER", 6,
131 42, UNIPHIER_PIN_DRV_4_8,
132 42, UNIPHIER_PIN_PULL_DOWN),
133 UNIPHIER_PINCTRL_PIN(36, "RMII_REFCLK", 6,
134 43, UNIPHIER_PIN_DRV_4_8,
135 43, UNIPHIER_PIN_PULL_DOWN),
136 UNIPHIER_PINCTRL_PIN(37, "RMII_TXD0", 6,
137 44, UNIPHIER_PIN_DRV_4_8,
138 44, UNIPHIER_PIN_PULL_DOWN),
139 UNIPHIER_PINCTRL_PIN(38, "RMII_TXD1", 6,
140 45, UNIPHIER_PIN_DRV_4_8,
141 45, UNIPHIER_PIN_PULL_DOWN),
142 UNIPHIER_PINCTRL_PIN(39, "RMII_TXEN", 6,
143 46, UNIPHIER_PIN_DRV_4_8,
144 46, UNIPHIER_PIN_PULL_DOWN),
145 UNIPHIER_PINCTRL_PIN(40, "MDC", 6,
146 47, UNIPHIER_PIN_DRV_4_8,
147 47, UNIPHIER_PIN_PULL_DOWN),
148 UNIPHIER_PINCTRL_PIN(41, "MDIO", 6,
149 48, UNIPHIER_PIN_DRV_4_8,
150 48, UNIPHIER_PIN_PULL_DOWN),
151 UNIPHIER_PINCTRL_PIN(42, "MDIO_INTL", 6,
152 49, UNIPHIER_PIN_DRV_4_8,
153 49, UNIPHIER_PIN_PULL_DOWN),
154 UNIPHIER_PINCTRL_PIN(43, "PHYRSTL", 6,
155 50, UNIPHIER_PIN_DRV_4_8,
156 50, UNIPHIER_PIN_PULL_DOWN),
157 UNIPHIER_PINCTRL_PIN(44, "SDCLK", UNIPHIER_PIN_IECTRL_NONE,
158 40, UNIPHIER_PIN_DRV_8_12_16_20,
159 156, UNIPHIER_PIN_PULL_UP),
160 UNIPHIER_PINCTRL_PIN(45, "SDCMD", UNIPHIER_PIN_IECTRL_NONE,
161 44, UNIPHIER_PIN_DRV_8_12_16_20,
162 157, UNIPHIER_PIN_PULL_UP),
163 UNIPHIER_PINCTRL_PIN(46, "SDDAT0", UNIPHIER_PIN_IECTRL_NONE,
164 48, UNIPHIER_PIN_DRV_8_12_16_20,
165 158, UNIPHIER_PIN_PULL_UP),
166 UNIPHIER_PINCTRL_PIN(47, "SDDAT1", UNIPHIER_PIN_IECTRL_NONE,
167 52, UNIPHIER_PIN_DRV_8_12_16_20,
168 159, UNIPHIER_PIN_PULL_UP),
169 UNIPHIER_PINCTRL_PIN(48, "SDDAT2", UNIPHIER_PIN_IECTRL_NONE,
170 56, UNIPHIER_PIN_DRV_8_12_16_20,
171 160, UNIPHIER_PIN_PULL_UP),
172 UNIPHIER_PINCTRL_PIN(49, "SDDAT3", UNIPHIER_PIN_IECTRL_NONE,
173 60, UNIPHIER_PIN_DRV_8_12_16_20,
174 161, UNIPHIER_PIN_PULL_UP),
175 UNIPHIER_PINCTRL_PIN(50, "SDCD", UNIPHIER_PIN_IECTRL_NONE,
176 51, UNIPHIER_PIN_DRV_4_8,
177 51, UNIPHIER_PIN_PULL_UP),
178 UNIPHIER_PINCTRL_PIN(51, "SDWP", UNIPHIER_PIN_IECTRL_NONE,
179 52, UNIPHIER_PIN_DRV_4_8,
180 52, UNIPHIER_PIN_PULL_UP),
181 UNIPHIER_PINCTRL_PIN(52, "SDVOLC", UNIPHIER_PIN_IECTRL_NONE,
182 53, UNIPHIER_PIN_DRV_4_8,
183 53, UNIPHIER_PIN_PULL_UP),
184 UNIPHIER_PINCTRL_PIN(53, "USB0VBUS", 0,
185 54, UNIPHIER_PIN_DRV_4_8,
186 54, UNIPHIER_PIN_PULL_DOWN),
187 UNIPHIER_PINCTRL_PIN(54, "USB0OD", 0,
188 55, UNIPHIER_PIN_DRV_4_8,
189 55, UNIPHIER_PIN_PULL_DOWN),
190 UNIPHIER_PINCTRL_PIN(55, "USB1VBUS", 0,
191 56, UNIPHIER_PIN_DRV_4_8,
192 56, UNIPHIER_PIN_PULL_DOWN),
193 UNIPHIER_PINCTRL_PIN(56, "USB1OD", 0,
194 57, UNIPHIER_PIN_DRV_4_8,
195 57, UNIPHIER_PIN_PULL_DOWN),
196 UNIPHIER_PINCTRL_PIN(57, "PCRESET", 0,
197 58, UNIPHIER_PIN_DRV_4_8,
198 58, UNIPHIER_PIN_PULL_DOWN),
199 UNIPHIER_PINCTRL_PIN(58, "PCREG", 0,
200 59, UNIPHIER_PIN_DRV_4_8,
201 59, UNIPHIER_PIN_PULL_DOWN),
202 UNIPHIER_PINCTRL_PIN(59, "PCCE2", 0,
203 60, UNIPHIER_PIN_DRV_4_8,
204 60, UNIPHIER_PIN_PULL_DOWN),
205 UNIPHIER_PINCTRL_PIN(60, "PCVS1", 0,
206 61, UNIPHIER_PIN_DRV_4_8,
207 61, UNIPHIER_PIN_PULL_DOWN),
208 UNIPHIER_PINCTRL_PIN(61, "PCCD2", 0,
209 62, UNIPHIER_PIN_DRV_4_8,
210 62, UNIPHIER_PIN_PULL_DOWN),
211 UNIPHIER_PINCTRL_PIN(62, "PCCD1", 0,
212 63, UNIPHIER_PIN_DRV_4_8,
213 63, UNIPHIER_PIN_PULL_DOWN),
214 UNIPHIER_PINCTRL_PIN(63, "PCREADY", 0,
215 64, UNIPHIER_PIN_DRV_4_8,
216 64, UNIPHIER_PIN_PULL_DOWN),
217 UNIPHIER_PINCTRL_PIN(64, "PCDOE", 0,
218 65, UNIPHIER_PIN_DRV_4_8,
219 65, UNIPHIER_PIN_PULL_DOWN),
220 UNIPHIER_PINCTRL_PIN(65, "PCCE1", 0,
221 66, UNIPHIER_PIN_DRV_4_8,
222 66, UNIPHIER_PIN_PULL_DOWN),
223 UNIPHIER_PINCTRL_PIN(66, "PCWE", 0,
224 67, UNIPHIER_PIN_DRV_4_8,
225 67, UNIPHIER_PIN_PULL_DOWN),
226 UNIPHIER_PINCTRL_PIN(67, "PCOE", 0,
227 68, UNIPHIER_PIN_DRV_4_8,
228 68, UNIPHIER_PIN_PULL_DOWN),
229 UNIPHIER_PINCTRL_PIN(68, "PCWAIT", 0,
230 69, UNIPHIER_PIN_DRV_4_8,
231 69, UNIPHIER_PIN_PULL_DOWN),
232 UNIPHIER_PINCTRL_PIN(69, "PCIOWR", 0,
233 70, UNIPHIER_PIN_DRV_4_8,
234 70, UNIPHIER_PIN_PULL_DOWN),
235 UNIPHIER_PINCTRL_PIN(70, "PCIORD", 0,
236 71, UNIPHIER_PIN_DRV_4_8,
237 71, UNIPHIER_PIN_PULL_DOWN),
238 UNIPHIER_PINCTRL_PIN(71, "HS0DIN0", 0,
239 72, UNIPHIER_PIN_DRV_4_8,
240 72, UNIPHIER_PIN_PULL_DOWN),
241 UNIPHIER_PINCTRL_PIN(72, "HS0DIN1", 0,
242 73, UNIPHIER_PIN_DRV_4_8,
243 73, UNIPHIER_PIN_PULL_DOWN),
244 UNIPHIER_PINCTRL_PIN(73, "HS0DIN2", 0,
245 74, UNIPHIER_PIN_DRV_4_8,
246 74, UNIPHIER_PIN_PULL_DOWN),
247 UNIPHIER_PINCTRL_PIN(74, "HS0DIN3", 0,
248 75, UNIPHIER_PIN_DRV_4_8,
249 75, UNIPHIER_PIN_PULL_DOWN),
250 UNIPHIER_PINCTRL_PIN(75, "HS0DIN4", 0,
251 76, UNIPHIER_PIN_DRV_4_8,
252 76, UNIPHIER_PIN_PULL_DOWN),
253 UNIPHIER_PINCTRL_PIN(76, "HS0DIN5", 0,
254 77, UNIPHIER_PIN_DRV_4_8,
255 77, UNIPHIER_PIN_PULL_DOWN),
256 UNIPHIER_PINCTRL_PIN(77, "HS0DIN6", 0,
257 78, UNIPHIER_PIN_DRV_4_8,
258 78, UNIPHIER_PIN_PULL_DOWN),
259 UNIPHIER_PINCTRL_PIN(78, "HS0DIN7", 0,
260 79, UNIPHIER_PIN_DRV_4_8,
261 79, UNIPHIER_PIN_PULL_DOWN),
262 UNIPHIER_PINCTRL_PIN(79, "HS0BCLKIN", 0,
263 80, UNIPHIER_PIN_DRV_4_8,
264 80, UNIPHIER_PIN_PULL_DOWN),
265 UNIPHIER_PINCTRL_PIN(80, "HS0VALIN", 0,
266 81, UNIPHIER_PIN_DRV_4_8,
267 81, UNIPHIER_PIN_PULL_DOWN),
268 UNIPHIER_PINCTRL_PIN(81, "HS0SYNCIN", 0,
269 82, UNIPHIER_PIN_DRV_4_8,
270 82, UNIPHIER_PIN_PULL_DOWN),
271 UNIPHIER_PINCTRL_PIN(82, "HSDOUT0", 0,
272 83, UNIPHIER_PIN_DRV_4_8,
273 83, UNIPHIER_PIN_PULL_DOWN),
274 UNIPHIER_PINCTRL_PIN(83, "HSDOUT1", 0,
275 84, UNIPHIER_PIN_DRV_4_8,
276 84, UNIPHIER_PIN_PULL_DOWN),
277 UNIPHIER_PINCTRL_PIN(84, "HSDOUT2", 0,
278 85, UNIPHIER_PIN_DRV_4_8,
279 85, UNIPHIER_PIN_PULL_DOWN),
280 UNIPHIER_PINCTRL_PIN(85, "HSDOUT3", 0,
281 86, UNIPHIER_PIN_DRV_4_8,
282 86, UNIPHIER_PIN_PULL_DOWN),
283 UNIPHIER_PINCTRL_PIN(86, "HSDOUT4", 0,
284 87, UNIPHIER_PIN_DRV_4_8,
285 87, UNIPHIER_PIN_PULL_DOWN),
286 UNIPHIER_PINCTRL_PIN(87, "HSDOUT5", 0,
287 88, UNIPHIER_PIN_DRV_4_8,
288 88, UNIPHIER_PIN_PULL_DOWN),
289 UNIPHIER_PINCTRL_PIN(88, "HSDOUT6", 0,
290 89, UNIPHIER_PIN_DRV_4_8,
291 89, UNIPHIER_PIN_PULL_DOWN),
292 UNIPHIER_PINCTRL_PIN(89, "HSDOUT7", 0,
293 90, UNIPHIER_PIN_DRV_4_8,
294 90, UNIPHIER_PIN_PULL_DOWN),
295 UNIPHIER_PINCTRL_PIN(90, "HSBCLKOUT", 0,
296 91, UNIPHIER_PIN_DRV_4_8,
297 91, UNIPHIER_PIN_PULL_DOWN),
298 UNIPHIER_PINCTRL_PIN(91, "HSVALOUT", 0,
299 92, UNIPHIER_PIN_DRV_4_8,
300 92, UNIPHIER_PIN_PULL_DOWN),
301 UNIPHIER_PINCTRL_PIN(92, "HSSYNCOUT", 0,
302 93, UNIPHIER_PIN_DRV_4_8,
303 93, UNIPHIER_PIN_PULL_DOWN),
304 UNIPHIER_PINCTRL_PIN(93, "AGCI", 3,
305 -1, UNIPHIER_PIN_DRV_FIXED_4,
306 162, UNIPHIER_PIN_PULL_DOWN),
307 UNIPHIER_PINCTRL_PIN(94, "AGCR", 4,
308 -1, UNIPHIER_PIN_DRV_FIXED_4,
309 163, UNIPHIER_PIN_PULL_DOWN),
310 UNIPHIER_PINCTRL_PIN(95, "AGCBS", 5,
311 -1, UNIPHIER_PIN_DRV_FIXED_4,
312 164, UNIPHIER_PIN_PULL_DOWN),
313 UNIPHIER_PINCTRL_PIN(96, "IECOUT", 0,
314 94, UNIPHIER_PIN_DRV_4_8,
315 94, UNIPHIER_PIN_PULL_DOWN),
316 UNIPHIER_PINCTRL_PIN(97, "ASMCK", 0,
317 95, UNIPHIER_PIN_DRV_4_8,
318 95, UNIPHIER_PIN_PULL_DOWN),
319 UNIPHIER_PINCTRL_PIN(98, "ABCKO", UNIPHIER_PIN_IECTRL_NONE,
320 96, UNIPHIER_PIN_DRV_4_8,
321 96, UNIPHIER_PIN_PULL_DOWN),
322 UNIPHIER_PINCTRL_PIN(99, "ALRCKO", UNIPHIER_PIN_IECTRL_NONE,
323 97, UNIPHIER_PIN_DRV_4_8,
324 97, UNIPHIER_PIN_PULL_DOWN),
325 UNIPHIER_PINCTRL_PIN(100, "ASDOUT0", UNIPHIER_PIN_IECTRL_NONE,
326 98, UNIPHIER_PIN_DRV_4_8,
327 98, UNIPHIER_PIN_PULL_DOWN),
328 UNIPHIER_PINCTRL_PIN(101, "ARCOUT", 0,
329 99, UNIPHIER_PIN_DRV_4_8,
330 99, UNIPHIER_PIN_PULL_DOWN),
331 UNIPHIER_PINCTRL_PIN(102, "SDA0", UNIPHIER_PIN_IECTRL_NONE,
332 -1, UNIPHIER_PIN_DRV_FIXED_4,
333 -1, UNIPHIER_PIN_PULL_NONE),
334 UNIPHIER_PINCTRL_PIN(103, "SCL0", UNIPHIER_PIN_IECTRL_NONE,
335 -1, UNIPHIER_PIN_DRV_FIXED_4,
336 -1, UNIPHIER_PIN_PULL_NONE),
337 UNIPHIER_PINCTRL_PIN(104, "SDA1", UNIPHIER_PIN_IECTRL_NONE,
338 -1, UNIPHIER_PIN_DRV_FIXED_4,
339 -1, UNIPHIER_PIN_PULL_NONE),
340 UNIPHIER_PINCTRL_PIN(105, "SCL1", UNIPHIER_PIN_IECTRL_NONE,
341 -1, UNIPHIER_PIN_DRV_FIXED_4,
342 -1, UNIPHIER_PIN_PULL_NONE),
343 UNIPHIER_PINCTRL_PIN(106, "DMDSDA0", UNIPHIER_PIN_IECTRL_NONE,
344 -1, UNIPHIER_PIN_DRV_FIXED_4,
345 -1, UNIPHIER_PIN_PULL_NONE),
346 UNIPHIER_PINCTRL_PIN(107, "DMDSCL0", UNIPHIER_PIN_IECTRL_NONE,
347 -1, UNIPHIER_PIN_DRV_FIXED_4,
348 -1, UNIPHIER_PIN_PULL_NONE),
349 UNIPHIER_PINCTRL_PIN(108, "DMDSDA1", UNIPHIER_PIN_IECTRL_NONE,
350 -1, UNIPHIER_PIN_DRV_FIXED_4,
351 -1, UNIPHIER_PIN_PULL_NONE),
352 UNIPHIER_PINCTRL_PIN(109, "DMDSCL1", UNIPHIER_PIN_IECTRL_NONE,
353 -1, UNIPHIER_PIN_DRV_FIXED_4,
354 -1, UNIPHIER_PIN_PULL_NONE),
355 UNIPHIER_PINCTRL_PIN(110, "SBO0", UNIPHIER_PIN_IECTRL_NONE,
356 100, UNIPHIER_PIN_DRV_4_8,
357 100, UNIPHIER_PIN_PULL_UP),
358 UNIPHIER_PINCTRL_PIN(111, "SBI0", UNIPHIER_PIN_IECTRL_NONE,
359 101, UNIPHIER_PIN_DRV_4_8,
360 101, UNIPHIER_PIN_PULL_UP),
361 UNIPHIER_PINCTRL_PIN(112, "HIN", 1,
362 -1, UNIPHIER_PIN_DRV_FIXED_5,
363 -1, UNIPHIER_PIN_PULL_NONE),
364 UNIPHIER_PINCTRL_PIN(113, "VIN", 2,
365 -1, UNIPHIER_PIN_DRV_FIXED_5,
366 -1, UNIPHIER_PIN_PULL_NONE),
367 UNIPHIER_PINCTRL_PIN(114, "TCON0", UNIPHIER_PIN_IECTRL_NONE,
368 102, UNIPHIER_PIN_DRV_4_8,
369 102, UNIPHIER_PIN_PULL_DOWN),
370 UNIPHIER_PINCTRL_PIN(115, "TCON1", UNIPHIER_PIN_IECTRL_NONE,
371 103, UNIPHIER_PIN_DRV_4_8,
372 103, UNIPHIER_PIN_PULL_DOWN),
373 UNIPHIER_PINCTRL_PIN(116, "TCON2", UNIPHIER_PIN_IECTRL_NONE,
374 104, UNIPHIER_PIN_DRV_4_8,
375 104, UNIPHIER_PIN_PULL_DOWN),
376 UNIPHIER_PINCTRL_PIN(117, "TCON3", UNIPHIER_PIN_IECTRL_NONE,
377 105, UNIPHIER_PIN_DRV_4_8,
378 105, UNIPHIER_PIN_PULL_DOWN),
379 UNIPHIER_PINCTRL_PIN(118, "TCON4", UNIPHIER_PIN_IECTRL_NONE,
380 106, UNIPHIER_PIN_DRV_4_8,
381 106, UNIPHIER_PIN_PULL_DOWN),
382 UNIPHIER_PINCTRL_PIN(119, "TCON5", UNIPHIER_PIN_IECTRL_NONE,
383 107, UNIPHIER_PIN_DRV_4_8,
384 107, UNIPHIER_PIN_PULL_DOWN),
385 UNIPHIER_PINCTRL_PIN(120, "TCON6", 0,
386 108, UNIPHIER_PIN_DRV_4_8,
387 108, UNIPHIER_PIN_PULL_DOWN),
388 UNIPHIER_PINCTRL_PIN(121, "TCON7", 0,
389 109, UNIPHIER_PIN_DRV_4_8,
390 109, UNIPHIER_PIN_PULL_DOWN),
391 UNIPHIER_PINCTRL_PIN(122, "PWMA", 0,
392 110, UNIPHIER_PIN_DRV_4_8,
393 110, UNIPHIER_PIN_PULL_DOWN),
394 UNIPHIER_PINCTRL_PIN(123, "XIRQ1", 0,
395 111, UNIPHIER_PIN_DRV_4_8,
396 111, UNIPHIER_PIN_PULL_DOWN),
397 UNIPHIER_PINCTRL_PIN(124, "XIRQ2", 0,
398 112, UNIPHIER_PIN_DRV_4_8,
399 112, UNIPHIER_PIN_PULL_DOWN),
400 UNIPHIER_PINCTRL_PIN(125, "XIRQ3", 0,
401 113, UNIPHIER_PIN_DRV_4_8,
402 113, UNIPHIER_PIN_PULL_DOWN),
403 UNIPHIER_PINCTRL_PIN(126, "XIRQ4", 0,
404 114, UNIPHIER_PIN_DRV_4_8,
405 114, UNIPHIER_PIN_PULL_DOWN),
406 UNIPHIER_PINCTRL_PIN(127, "XIRQ5", 0,
407 115, UNIPHIER_PIN_DRV_4_8,
408 115, UNIPHIER_PIN_PULL_DOWN),
409 UNIPHIER_PINCTRL_PIN(128, "XIRQ6", 0,
410 116, UNIPHIER_PIN_DRV_4_8,
411 116, UNIPHIER_PIN_PULL_DOWN),
412 UNIPHIER_PINCTRL_PIN(129, "XIRQ7", 0,
413 117, UNIPHIER_PIN_DRV_4_8,
414 117, UNIPHIER_PIN_PULL_DOWN),
415 UNIPHIER_PINCTRL_PIN(130, "XIRQ8", 0,
416 118, UNIPHIER_PIN_DRV_4_8,
417 118, UNIPHIER_PIN_PULL_DOWN),
418 UNIPHIER_PINCTRL_PIN(131, "XIRQ9", 0,
419 119, UNIPHIER_PIN_DRV_4_8,
420 119, UNIPHIER_PIN_PULL_DOWN),
421 UNIPHIER_PINCTRL_PIN(132, "XIRQ10", 0,
422 120, UNIPHIER_PIN_DRV_4_8,
423 120, UNIPHIER_PIN_PULL_DOWN),
424 UNIPHIER_PINCTRL_PIN(133, "XIRQ11", 0,
425 121, UNIPHIER_PIN_DRV_4_8,
426 121, UNIPHIER_PIN_PULL_DOWN),
427 UNIPHIER_PINCTRL_PIN(134, "XIRQ14", 0,
428 122, UNIPHIER_PIN_DRV_4_8,
429 122, UNIPHIER_PIN_PULL_DOWN),
430 UNIPHIER_PINCTRL_PIN(135, "PORT00", 0,
431 123, UNIPHIER_PIN_DRV_4_8,
432 123, UNIPHIER_PIN_PULL_DOWN),
433 UNIPHIER_PINCTRL_PIN(136, "PORT01", 0,
434 124, UNIPHIER_PIN_DRV_4_8,
435 124, UNIPHIER_PIN_PULL_DOWN),
436 UNIPHIER_PINCTRL_PIN(137, "PORT02", 0,
437 125, UNIPHIER_PIN_DRV_4_8,
438 125, UNIPHIER_PIN_PULL_DOWN),
439 UNIPHIER_PINCTRL_PIN(138, "PORT03", 0,
440 126, UNIPHIER_PIN_DRV_4_8,
441 126, UNIPHIER_PIN_PULL_DOWN),
442 UNIPHIER_PINCTRL_PIN(139, "PORT04", 0,
443 127, UNIPHIER_PIN_DRV_4_8,
444 127, UNIPHIER_PIN_PULL_DOWN),
445 UNIPHIER_PINCTRL_PIN(140, "PORT05", 0,
446 128, UNIPHIER_PIN_DRV_4_8,
447 128, UNIPHIER_PIN_PULL_DOWN),
448 UNIPHIER_PINCTRL_PIN(141, "PORT06", 0,
449 129, UNIPHIER_PIN_DRV_4_8,
450 129, UNIPHIER_PIN_PULL_DOWN),
451 UNIPHIER_PINCTRL_PIN(142, "PORT07", 0,
452 130, UNIPHIER_PIN_DRV_4_8,
453 130, UNIPHIER_PIN_PULL_DOWN),
454 UNIPHIER_PINCTRL_PIN(143, "PORT10", 0,
455 131, UNIPHIER_PIN_DRV_4_8,
456 131, UNIPHIER_PIN_PULL_DOWN),
457 UNIPHIER_PINCTRL_PIN(144, "PORT11", 0,
458 132, UNIPHIER_PIN_DRV_4_8,
459 132, UNIPHIER_PIN_PULL_DOWN),
460 UNIPHIER_PINCTRL_PIN(145, "PORT12", 0,
461 133, UNIPHIER_PIN_DRV_4_8,
462 133, UNIPHIER_PIN_PULL_DOWN),
463 UNIPHIER_PINCTRL_PIN(146, "PORT13", 0,
464 134, UNIPHIER_PIN_DRV_4_8,
465 134, UNIPHIER_PIN_PULL_DOWN),
466 UNIPHIER_PINCTRL_PIN(147, "PORT14", 0,
467 135, UNIPHIER_PIN_DRV_4_8,
468 135, UNIPHIER_PIN_PULL_DOWN),
469 UNIPHIER_PINCTRL_PIN(148, "PORT15", 0,
470 136, UNIPHIER_PIN_DRV_4_8,
471 136, UNIPHIER_PIN_PULL_DOWN),
472 UNIPHIER_PINCTRL_PIN(149, "PORT16", 0,
473 137, UNIPHIER_PIN_DRV_4_8,
474 137, UNIPHIER_PIN_PULL_DOWN),
475 UNIPHIER_PINCTRL_PIN(150, "PORT17", UNIPHIER_PIN_IECTRL_NONE,
476 138, UNIPHIER_PIN_DRV_4_8,
477 138, UNIPHIER_PIN_PULL_DOWN),
478 UNIPHIER_PINCTRL_PIN(151, "PORT20", 0,
479 139, UNIPHIER_PIN_DRV_4_8,
480 139, UNIPHIER_PIN_PULL_DOWN),
481 UNIPHIER_PINCTRL_PIN(152, "PORT21", 0,
482 140, UNIPHIER_PIN_DRV_4_8,
483 140, UNIPHIER_PIN_PULL_DOWN),
484 UNIPHIER_PINCTRL_PIN(153, "PORT22", 0,
485 141, UNIPHIER_PIN_DRV_4_8,
486 141, UNIPHIER_PIN_PULL_DOWN),
487 UNIPHIER_PINCTRL_PIN(154, "PORT23", 0,
488 142, UNIPHIER_PIN_DRV_4_8,
489 142, UNIPHIER_PIN_PULL_DOWN),
490 UNIPHIER_PINCTRL_PIN(155, "PORT24", UNIPHIER_PIN_IECTRL_NONE,
491 143, UNIPHIER_PIN_DRV_4_8,
492 143, UNIPHIER_PIN_PULL_DOWN),
493 UNIPHIER_PINCTRL_PIN(156, "PORT25", 0,
494 144, UNIPHIER_PIN_DRV_4_8,
495 144, UNIPHIER_PIN_PULL_DOWN),
496 UNIPHIER_PINCTRL_PIN(157, "PORT26", 0,
497 145, UNIPHIER_PIN_DRV_4_8,
498 145, UNIPHIER_PIN_PULL_DOWN),
499 UNIPHIER_PINCTRL_PIN(158, "XNFRE", UNIPHIER_PIN_IECTRL_NONE,
500 31, UNIPHIER_PIN_DRV_4_8,
501 31, UNIPHIER_PIN_PULL_UP),
502 UNIPHIER_PINCTRL_PIN(159, "XNFWE", UNIPHIER_PIN_IECTRL_NONE,
503 32, UNIPHIER_PIN_DRV_4_8,
504 32, UNIPHIER_PIN_PULL_UP),
505 UNIPHIER_PINCTRL_PIN(160, "NFALE", UNIPHIER_PIN_IECTRL_NONE,
506 33, UNIPHIER_PIN_DRV_4_8,
507 33, UNIPHIER_PIN_PULL_DOWN),
508 UNIPHIER_PINCTRL_PIN(161, "NFCLE", UNIPHIER_PIN_IECTRL_NONE,
509 34, UNIPHIER_PIN_DRV_4_8,
510 34, UNIPHIER_PIN_PULL_DOWN),
511 UNIPHIER_PINCTRL_PIN(162, "XNFWP", UNIPHIER_PIN_IECTRL_NONE,
512 35, UNIPHIER_PIN_DRV_4_8,
513 35, UNIPHIER_PIN_PULL_DOWN),
514 UNIPHIER_PINCTRL_PIN(163, "XNFCE0", UNIPHIER_PIN_IECTRL_NONE,
515 36, UNIPHIER_PIN_DRV_4_8,
516 36, UNIPHIER_PIN_PULL_UP),
517 UNIPHIER_PINCTRL_PIN(164, "NANDRYBY0", UNIPHIER_PIN_IECTRL_NONE,
518 37, UNIPHIER_PIN_DRV_4_8,
519 37, UNIPHIER_PIN_PULL_UP),
520};
521
522static const unsigned emmc_pins[] = {21, 22, 23, 24, 25, 26, 27};
523static const unsigned emmc_muxvals[] = {0, 1, 1, 1, 1, 1, 1};
524static const unsigned emmc_dat8_pins[] = {28, 29, 30, 31};
525static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
526static const unsigned i2c0_pins[] = {102, 103};
527static const unsigned i2c0_muxvals[] = {0, 0};
528static const unsigned i2c1_pins[] = {104, 105};
529static const unsigned i2c1_muxvals[] = {0, 0};
530static const unsigned i2c2_pins[] = {108, 109};
531static const unsigned i2c2_muxvals[] = {2, 2};
532static const unsigned i2c3_pins[] = {108, 109};
533static const unsigned i2c3_muxvals[] = {3, 3};
534static const unsigned nand_pins[] = {24, 25, 26, 27, 28, 29, 30, 31, 158, 159,
535 160, 161, 162, 163, 164};
536static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
537 0, 0};
538static const unsigned nand_cs1_pins[] = {22, 23};
539static const unsigned nand_cs1_muxvals[] = {0, 0};
540static const unsigned uart0_pins[] = {85, 88};
541static const unsigned uart0_muxvals[] = {1, 1};
542static const unsigned uart1_pins[] = {155, 156};
543static const unsigned uart1_muxvals[] = {13, 13};
544static const unsigned uart1b_pins[] = {69, 70};
545static const unsigned uart1b_muxvals[] = {23, 23};
546static const unsigned uart2_pins[] = {128, 129};
547static const unsigned uart2_muxvals[] = {13, 13};
548static const unsigned uart3_pins[] = {110, 111};
549static const unsigned uart3_muxvals[] = {1, 1};
550static const unsigned usb0_pins[] = {53, 54};
551static const unsigned usb0_muxvals[] = {0, 0};
552static const unsigned usb1_pins[] = {55, 56};
553static const unsigned usb1_muxvals[] = {0, 0};
554static const unsigned usb2_pins[] = {155, 156};
555static const unsigned usb2_muxvals[] = {4, 4};
556static const unsigned usb2b_pins[] = {67, 68};
557static const unsigned usb2b_muxvals[] = {23, 23};
558static const unsigned port_range0_pins[] = {
559 135, 136, 137, 138, 139, 140, 141, 142, /* PORT0x */
560 143, 144, 145, 146, 147, 148, 149, 150, /* PORT1x */
561 151, 152, 153, 154, 155, 156, 157, 0, /* PORT2x */
562 1, 2, 3, 4, 5, 120, 121, 122, /* PORT3x */
563 24, 25, 26, 27, 28, 29, 30, 31, /* PORT4x */
564 40, 41, 42, 43, 44, 45, 46, 47, /* PORT5x */
565 48, 49, 50, 51, 52, 53, 54, 55, /* PORT6x */
566 56, 85, 84, 59, 82, 61, 64, 65, /* PORT7x */
567 8, 9, 10, 11, 12, 13, 14, 15, /* PORT8x */
568 66, 67, 68, 69, 70, 71, 72, 73, /* PORT9x */
569 74, 75, 89, 86, 78, 79, 80, 81, /* PORT10x */
570 60, 83, 58, 57, 88, 87, 77, 76, /* PORT11x */
571 90, 91, 92, 93, 94, 95, 96, 97, /* PORT12x */
572 98, 99, 100, 6, 101, 114, 115, 116, /* PORT13x */
573 103, 108, 21, 22, 23, 117, 118, 119, /* PORT14x */
574};
575static const unsigned port_range0_muxvals[] = {
576 0, 0, 0, 0, 0, 0, 0, 0, /* PORT0x */
577 0, 0, 0, 0, 0, 0, 0, 0, /* PORT1x */
578 0, 0, 0, 0, 0, 0, 0, 15, /* PORT2x */
579 15, 15, 15, 15, 15, 15, 15, 15, /* PORT3x */
580 15, 15, 15, 15, 15, 15, 15, 15, /* PORT4x */
581 15, 15, 15, 15, 15, 15, 15, 15, /* PORT5x */
582 15, 15, 15, 15, 15, 15, 15, 15, /* PORT6x */
583 15, 15, 15, 15, 15, 15, 15, 15, /* PORT7x */
584 15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */
585 15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */
586 15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */
587 15, 15, 15, 15, 15, 15, 15, 15, /* PORT11x */
588 15, 15, 15, 15, 15, 15, 15, 15, /* PORT12x */
589 15, 15, 15, 15, 15, 15, 15, 15, /* PORT13x */
590 15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */
591};
592static const unsigned port_range1_pins[] = {
593 7, /* PORT166 */
594};
595static const unsigned port_range1_muxvals[] = {
596 15, /* PORT166 */
597};
598static const unsigned xirq_range0_pins[] = {
599 151, 123, 124, 125, 126, 127, 128, 129, /* XIRQ0-7 */
600 130, 131, 132, 133, 62, /* XIRQ8-12 */
601};
602static const unsigned xirq_range0_muxvals[] = {
603 14, 0, 0, 0, 0, 0, 0, 0, /* XIRQ0-7 */
604 0, 0, 0, 0, 14, /* XIRQ8-12 */
605};
606static const unsigned xirq_range1_pins[] = {
607 134, 63, /* XIRQ14-15 */
608};
609static const unsigned xirq_range1_muxvals[] = {
610 0, 14, /* XIRQ14-15 */
611};
612
613static const struct uniphier_pinctrl_group ph1_ld4_groups[] = {
614 UNIPHIER_PINCTRL_GROUP(emmc),
615 UNIPHIER_PINCTRL_GROUP(emmc_dat8),
616 UNIPHIER_PINCTRL_GROUP(i2c0),
617 UNIPHIER_PINCTRL_GROUP(i2c1),
618 UNIPHIER_PINCTRL_GROUP(i2c2),
619 UNIPHIER_PINCTRL_GROUP(i2c3),
620 UNIPHIER_PINCTRL_GROUP(nand),
621 UNIPHIER_PINCTRL_GROUP(nand_cs1),
622 UNIPHIER_PINCTRL_GROUP(uart0),
623 UNIPHIER_PINCTRL_GROUP(uart1),
624 UNIPHIER_PINCTRL_GROUP(uart1b),
625 UNIPHIER_PINCTRL_GROUP(uart2),
626 UNIPHIER_PINCTRL_GROUP(uart3),
627 UNIPHIER_PINCTRL_GROUP(usb0),
628 UNIPHIER_PINCTRL_GROUP(usb1),
629 UNIPHIER_PINCTRL_GROUP(usb2),
630 UNIPHIER_PINCTRL_GROUP(usb2b),
631 UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0),
632 UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1),
633 UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_range0),
634 UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_range1),
635 UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0),
636 UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1),
637 UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2),
638 UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3),
639 UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4),
640 UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5),
641 UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6),
642 UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7),
643 UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8),
644 UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9),
645 UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10),
646 UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11),
647 UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12),
648 UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13),
649 UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14),
650 UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15),
651 UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16),
652 UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17),
653 UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18),
654 UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19),
655 UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20),
656 UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21),
657 UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22),
658 UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23),
659 UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24),
660 UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25),
661 UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26),
662 UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27),
663 UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28),
664 UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29),
665 UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30),
666 UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31),
667 UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32),
668 UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33),
669 UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34),
670 UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35),
671 UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36),
672 UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37),
673 UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38),
674 UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39),
675 UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40),
676 UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41),
677 UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42),
678 UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43),
679 UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44),
680 UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45),
681 UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46),
682 UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47),
683 UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48),
684 UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49),
685 UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50),
686 UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51),
687 UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52),
688 UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53),
689 UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54),
690 UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55),
691 UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56),
692 UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57),
693 UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58),
694 UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59),
695 UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60),
696 UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61),
697 UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62),
698 UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63),
699 UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64),
700 UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65),
701 UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66),
702 UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67),
703 UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68),
704 UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69),
705 UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70),
706 UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71),
707 UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72),
708 UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73),
709 UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74),
710 UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75),
711 UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76),
712 UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77),
713 UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78),
714 UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79),
715 UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80),
716 UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81),
717 UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82),
718 UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83),
719 UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84),
720 UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85),
721 UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86),
722 UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87),
723 UNIPHIER_PINCTRL_GROUP_SINGLE(port110, port_range0, 88),
724 UNIPHIER_PINCTRL_GROUP_SINGLE(port111, port_range0, 89),
725 UNIPHIER_PINCTRL_GROUP_SINGLE(port112, port_range0, 90),
726 UNIPHIER_PINCTRL_GROUP_SINGLE(port113, port_range0, 91),
727 UNIPHIER_PINCTRL_GROUP_SINGLE(port114, port_range0, 92),
728 UNIPHIER_PINCTRL_GROUP_SINGLE(port115, port_range0, 93),
729 UNIPHIER_PINCTRL_GROUP_SINGLE(port116, port_range0, 94),
730 UNIPHIER_PINCTRL_GROUP_SINGLE(port117, port_range0, 95),
731 UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range0, 96),
732 UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range0, 97),
733 UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range0, 98),
734 UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range0, 99),
735 UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range0, 100),
736 UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range0, 101),
737 UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range0, 102),
738 UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range0, 103),
739 UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range0, 104),
740 UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range0, 105),
741 UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range0, 106),
742 UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range0, 107),
743 UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range0, 108),
744 UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range0, 109),
745 UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range0, 110),
746 UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range0, 111),
747 UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range0, 112),
748 UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range0, 113),
749 UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range0, 114),
750 UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range0, 115),
751 UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range0, 116),
752 UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range0, 117),
753 UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range0, 118),
754 UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range0, 119),
755 UNIPHIER_PINCTRL_GROUP_SINGLE(port165, port_range1, 0),
756 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq_range0, 0),
757 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq_range0, 1),
758 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq_range0, 2),
759 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq_range0, 3),
760 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq_range0, 4),
761 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq_range0, 5),
762 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq_range0, 6),
763 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq_range0, 7),
764 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq_range0, 8),
765 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq_range0, 9),
766 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq_range0, 10),
767 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq_range0, 11),
768 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq_range0, 12),
769 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq_range1, 0),
770 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq_range1, 1),
771};
772
773static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
774static const char * const i2c0_groups[] = {"i2c0"};
775static const char * const i2c1_groups[] = {"i2c1"};
776static const char * const i2c2_groups[] = {"i2c2"};
777static const char * const i2c3_groups[] = {"i2c3"};
778static const char * const nand_groups[] = {"nand", "nand_cs1"};
779static const char * const uart0_groups[] = {"uart0"};
780static const char * const uart1_groups[] = {"uart1", "uart1b"};
781static const char * const uart2_groups[] = {"uart2"};
782static const char * const uart3_groups[] = {"uart3"};
783static const char * const usb0_groups[] = {"usb0"};
784static const char * const usb1_groups[] = {"usb1"};
785static const char * const usb2_groups[] = {"usb2", "usb2b"};
786static const char * const port_groups[] = {
787 "port00", "port01", "port02", "port03",
788 "port04", "port05", "port06", "port07",
789 "port10", "port11", "port12", "port13",
790 "port14", "port15", "port16", "port17",
791 "port20", "port21", "port22", "port23",
792 "port24", "port25", "port26", "port27",
793 "port30", "port31", "port32", "port33",
794 "port34", "port35", "port36", "port37",
795 "port40", "port41", "port42", "port43",
796 "port44", "port45", "port46", "port47",
797 "port50", "port51", "port52", "port53",
798 "port54", "port55", "port56", "port57",
799 "port60", "port61", "port62", "port63",
800 "port64", "port65", "port66", "port67",
801 "port70", "port71", "port72", "port73",
802 "port74", "port75", "port76", "port77",
803 "port80", "port81", "port82", "port83",
804 "port84", "port85", "port86", "port87",
805 "port90", "port91", "port92", "port93",
806 "port94", "port95", "port96", "port97",
807 "port100", "port101", "port102", "port103",
808 "port104", "port105", "port106", "port107",
809 "port110", "port111", "port112", "port113",
810 "port114", "port115", "port116", "port117",
811 "port120", "port121", "port122", "port123",
812 "port124", "port125", "port126", "port127",
813 "port130", "port131", "port132", "port133",
814 "port134", "port135", "port136", "port137",
815 "port140", "port141", "port142", "port143",
816 "port144", "port145", "port146", "port147",
817 /* port150-164 missing */
818 /* none */ "port165",
819};
820static const char * const xirq_groups[] = {
821 "xirq0", "xirq1", "xirq2", "xirq3",
822 "xirq4", "xirq5", "xirq6", "xirq7",
823 "xirq8", "xirq9", "xirq10", "xirq11",
824 "xirq12", /* none*/ "xirq14", "xirq15",
825};
826
827static const struct uniphier_pinmux_function ph1_ld4_functions[] = {
828 UNIPHIER_PINMUX_FUNCTION(emmc),
829 UNIPHIER_PINMUX_FUNCTION(i2c0),
830 UNIPHIER_PINMUX_FUNCTION(i2c1),
831 UNIPHIER_PINMUX_FUNCTION(i2c2),
832 UNIPHIER_PINMUX_FUNCTION(i2c3),
833 UNIPHIER_PINMUX_FUNCTION(nand),
834 UNIPHIER_PINMUX_FUNCTION(uart0),
835 UNIPHIER_PINMUX_FUNCTION(uart1),
836 UNIPHIER_PINMUX_FUNCTION(uart2),
837 UNIPHIER_PINMUX_FUNCTION(uart3),
838 UNIPHIER_PINMUX_FUNCTION(usb0),
839 UNIPHIER_PINMUX_FUNCTION(usb1),
840 UNIPHIER_PINMUX_FUNCTION(usb2),
841 UNIPHIER_PINMUX_FUNCTION(port),
842 UNIPHIER_PINMUX_FUNCTION(xirq),
843};
844
845static struct uniphier_pinctrl_socdata ph1_ld4_pindata = {
846 .groups = ph1_ld4_groups,
847 .groups_count = ARRAY_SIZE(ph1_ld4_groups),
848 .functions = ph1_ld4_functions,
849 .functions_count = ARRAY_SIZE(ph1_ld4_functions),
850 .mux_bits = 8,
851 .reg_stride = 4,
852 .load_pinctrl = false,
853};
854
855static struct pinctrl_desc ph1_ld4_pinctrl_desc = {
856 .name = DRIVER_NAME,
857 .pins = ph1_ld4_pins,
858 .npins = ARRAY_SIZE(ph1_ld4_pins),
859 .owner = THIS_MODULE,
860};
861
862static int ph1_ld4_pinctrl_probe(struct platform_device *pdev)
863{
864 return uniphier_pinctrl_probe(pdev, &ph1_ld4_pinctrl_desc,
865 &ph1_ld4_pindata);
866}
867
868static const struct of_device_id ph1_ld4_pinctrl_match[] = {
869 { .compatible = "socionext,ph1-ld4-pinctrl" },
870 { /* sentinel */ }
871};
872MODULE_DEVICE_TABLE(of, ph1_ld4_pinctrl_match);
873
874static struct platform_driver ph1_ld4_pinctrl_driver = {
875 .probe = ph1_ld4_pinctrl_probe,
876 .remove = uniphier_pinctrl_remove,
877 .driver = {
878 .name = DRIVER_NAME,
879 .of_match_table = ph1_ld4_pinctrl_match,
880 },
881};
882module_platform_driver(ph1_ld4_pinctrl_driver);
883
884MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
885MODULE_DESCRIPTION("UniPhier PH1-LD4 pinctrl driver");
886MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c b/drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c
new file mode 100644
index 000000000000..9720e697fbc1
--- /dev/null
+++ b/drivers/pinctrl/uniphier/pinctrl-ph1-ld6b.c
@@ -0,0 +1,1274 @@
1/*
2 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/pinctrl/pinctrl.h>
18#include <linux/platform_device.h>
19
20#include "pinctrl-uniphier.h"
21
22#define DRIVER_NAME "ph1-ld6b-pinctrl"
23
24static const struct pinctrl_pin_desc ph1_ld6b_pins[] = {
25 UNIPHIER_PINCTRL_PIN(0, "ED0", UNIPHIER_PIN_IECTRL_NONE,
26 0, UNIPHIER_PIN_DRV_4_8,
27 0, UNIPHIER_PIN_PULL_DOWN),
28 UNIPHIER_PINCTRL_PIN(1, "ED1", UNIPHIER_PIN_IECTRL_NONE,
29 1, UNIPHIER_PIN_DRV_4_8,
30 1, UNIPHIER_PIN_PULL_DOWN),
31 UNIPHIER_PINCTRL_PIN(2, "ED2", UNIPHIER_PIN_IECTRL_NONE,
32 2, UNIPHIER_PIN_DRV_4_8,
33 2, UNIPHIER_PIN_PULL_DOWN),
34 UNIPHIER_PINCTRL_PIN(3, "ED3", UNIPHIER_PIN_IECTRL_NONE,
35 3, UNIPHIER_PIN_DRV_4_8,
36 3, UNIPHIER_PIN_PULL_DOWN),
37 UNIPHIER_PINCTRL_PIN(4, "ED4", UNIPHIER_PIN_IECTRL_NONE,
38 4, UNIPHIER_PIN_DRV_4_8,
39 4, UNIPHIER_PIN_PULL_DOWN),
40 UNIPHIER_PINCTRL_PIN(5, "ED5", UNIPHIER_PIN_IECTRL_NONE,
41 5, UNIPHIER_PIN_DRV_4_8,
42 5, UNIPHIER_PIN_PULL_DOWN),
43 UNIPHIER_PINCTRL_PIN(6, "ED6", UNIPHIER_PIN_IECTRL_NONE,
44 6, UNIPHIER_PIN_DRV_4_8,
45 6, UNIPHIER_PIN_PULL_DOWN),
46 UNIPHIER_PINCTRL_PIN(7, "ED7", UNIPHIER_PIN_IECTRL_NONE,
47 7, UNIPHIER_PIN_DRV_4_8,
48 7, UNIPHIER_PIN_PULL_DOWN),
49 UNIPHIER_PINCTRL_PIN(8, "XERWE0", UNIPHIER_PIN_IECTRL_NONE,
50 8, UNIPHIER_PIN_DRV_4_8,
51 8, UNIPHIER_PIN_PULL_DOWN),
52 UNIPHIER_PINCTRL_PIN(9, "XERWE1", UNIPHIER_PIN_IECTRL_NONE,
53 9, UNIPHIER_PIN_DRV_4_8,
54 9, UNIPHIER_PIN_PULL_DOWN),
55 UNIPHIER_PINCTRL_PIN(10, "ERXW", UNIPHIER_PIN_IECTRL_NONE,
56 10, UNIPHIER_PIN_DRV_4_8,
57 10, UNIPHIER_PIN_PULL_DOWN),
58 UNIPHIER_PINCTRL_PIN(11, "ES0", UNIPHIER_PIN_IECTRL_NONE,
59 11, UNIPHIER_PIN_DRV_4_8,
60 11, UNIPHIER_PIN_PULL_DOWN),
61 UNIPHIER_PINCTRL_PIN(12, "ES1", UNIPHIER_PIN_IECTRL_NONE,
62 12, UNIPHIER_PIN_DRV_4_8,
63 12, UNIPHIER_PIN_PULL_DOWN),
64 UNIPHIER_PINCTRL_PIN(13, "ES2", UNIPHIER_PIN_IECTRL_NONE,
65 13, UNIPHIER_PIN_DRV_4_8,
66 13, UNIPHIER_PIN_PULL_DOWN),
67 UNIPHIER_PINCTRL_PIN(14, "XECS1", UNIPHIER_PIN_IECTRL_NONE,
68 14, UNIPHIER_PIN_DRV_4_8,
69 14, UNIPHIER_PIN_PULL_DOWN),
70 UNIPHIER_PINCTRL_PIN(15, "PCA00", UNIPHIER_PIN_IECTRL_NONE,
71 -1, UNIPHIER_PIN_DRV_FIXED_8,
72 15, UNIPHIER_PIN_PULL_DOWN),
73 UNIPHIER_PINCTRL_PIN(16, "PCA01", UNIPHIER_PIN_IECTRL_NONE,
74 -1, UNIPHIER_PIN_DRV_FIXED_8,
75 16, UNIPHIER_PIN_PULL_DOWN),
76 UNIPHIER_PINCTRL_PIN(17, "PCA02", UNIPHIER_PIN_IECTRL_NONE,
77 -1, UNIPHIER_PIN_DRV_FIXED_8,
78 17, UNIPHIER_PIN_PULL_DOWN),
79 UNIPHIER_PINCTRL_PIN(18, "PCA03", UNIPHIER_PIN_IECTRL_NONE,
80 -1, UNIPHIER_PIN_DRV_FIXED_8,
81 18, UNIPHIER_PIN_PULL_DOWN),
82 UNIPHIER_PINCTRL_PIN(19, "PCA04", UNIPHIER_PIN_IECTRL_NONE,
83 -1, UNIPHIER_PIN_DRV_FIXED_8,
84 19, UNIPHIER_PIN_PULL_DOWN),
85 UNIPHIER_PINCTRL_PIN(20, "PCA05", UNIPHIER_PIN_IECTRL_NONE,
86 -1, UNIPHIER_PIN_DRV_FIXED_8,
87 20, UNIPHIER_PIN_PULL_DOWN),
88 UNIPHIER_PINCTRL_PIN(21, "PCA06", UNIPHIER_PIN_IECTRL_NONE,
89 -1, UNIPHIER_PIN_DRV_FIXED_8,
90 21, UNIPHIER_PIN_PULL_DOWN),
91 UNIPHIER_PINCTRL_PIN(22, "PCA07", UNIPHIER_PIN_IECTRL_NONE,
92 -1, UNIPHIER_PIN_DRV_FIXED_8,
93 22, UNIPHIER_PIN_PULL_DOWN),
94 UNIPHIER_PINCTRL_PIN(23, "PCA08", UNIPHIER_PIN_IECTRL_NONE,
95 -1, UNIPHIER_PIN_DRV_FIXED_8,
96 23, UNIPHIER_PIN_PULL_DOWN),
97 UNIPHIER_PINCTRL_PIN(24, "PCA09", UNIPHIER_PIN_IECTRL_NONE,
98 -1, UNIPHIER_PIN_DRV_FIXED_8,
99 24, UNIPHIER_PIN_PULL_DOWN),
100 UNIPHIER_PINCTRL_PIN(25, "PCA10", UNIPHIER_PIN_IECTRL_NONE,
101 -1, UNIPHIER_PIN_DRV_FIXED_8,
102 25, UNIPHIER_PIN_PULL_DOWN),
103 UNIPHIER_PINCTRL_PIN(26, "PCA11", UNIPHIER_PIN_IECTRL_NONE,
104 -1, UNIPHIER_PIN_DRV_FIXED_8,
105 26, UNIPHIER_PIN_PULL_DOWN),
106 UNIPHIER_PINCTRL_PIN(27, "PCA12", UNIPHIER_PIN_IECTRL_NONE,
107 -1, UNIPHIER_PIN_DRV_FIXED_8,
108 27, UNIPHIER_PIN_PULL_DOWN),
109 UNIPHIER_PINCTRL_PIN(28, "PCA13", UNIPHIER_PIN_IECTRL_NONE,
110 -1, UNIPHIER_PIN_DRV_FIXED_8,
111 28, UNIPHIER_PIN_PULL_DOWN),
112 UNIPHIER_PINCTRL_PIN(29, "PCA14", UNIPHIER_PIN_IECTRL_NONE,
113 -1, UNIPHIER_PIN_DRV_FIXED_8,
114 29, UNIPHIER_PIN_PULL_DOWN),
115 UNIPHIER_PINCTRL_PIN(30, "XNFRE", UNIPHIER_PIN_IECTRL_NONE,
116 30, UNIPHIER_PIN_DRV_4_8,
117 30, UNIPHIER_PIN_PULL_UP),
118 UNIPHIER_PINCTRL_PIN(31, "XNFWE", UNIPHIER_PIN_IECTRL_NONE,
119 31, UNIPHIER_PIN_DRV_4_8,
120 31, UNIPHIER_PIN_PULL_UP),
121 UNIPHIER_PINCTRL_PIN(32, "NFALE", UNIPHIER_PIN_IECTRL_NONE,
122 32, UNIPHIER_PIN_DRV_4_8,
123 32, UNIPHIER_PIN_PULL_DOWN),
124 UNIPHIER_PINCTRL_PIN(33, "NFCLE", UNIPHIER_PIN_IECTRL_NONE,
125 33, UNIPHIER_PIN_DRV_4_8,
126 33, UNIPHIER_PIN_PULL_DOWN),
127 UNIPHIER_PINCTRL_PIN(34, "XNFWP", UNIPHIER_PIN_IECTRL_NONE,
128 34, UNIPHIER_PIN_DRV_4_8,
129 34, UNIPHIER_PIN_PULL_DOWN),
130 UNIPHIER_PINCTRL_PIN(35, "XNFCE0", UNIPHIER_PIN_IECTRL_NONE,
131 35, UNIPHIER_PIN_DRV_4_8,
132 35, UNIPHIER_PIN_PULL_UP),
133 UNIPHIER_PINCTRL_PIN(36, "NFRYBY0", UNIPHIER_PIN_IECTRL_NONE,
134 36, UNIPHIER_PIN_DRV_4_8,
135 36, UNIPHIER_PIN_PULL_UP),
136 UNIPHIER_PINCTRL_PIN(37, "XNFCE1", UNIPHIER_PIN_IECTRL_NONE,
137 37, UNIPHIER_PIN_DRV_4_8,
138 37, UNIPHIER_PIN_PULL_UP),
139 UNIPHIER_PINCTRL_PIN(38, "NFRYBY1", UNIPHIER_PIN_IECTRL_NONE,
140 38, UNIPHIER_PIN_DRV_4_8,
141 38, UNIPHIER_PIN_PULL_UP),
142 UNIPHIER_PINCTRL_PIN(39, "NFD0", UNIPHIER_PIN_IECTRL_NONE,
143 39, UNIPHIER_PIN_DRV_4_8,
144 39, UNIPHIER_PIN_PULL_DOWN),
145 UNIPHIER_PINCTRL_PIN(40, "NFD1", UNIPHIER_PIN_IECTRL_NONE,
146 40, UNIPHIER_PIN_DRV_4_8,
147 40, UNIPHIER_PIN_PULL_DOWN),
148 UNIPHIER_PINCTRL_PIN(41, "NFD2", UNIPHIER_PIN_IECTRL_NONE,
149 41, UNIPHIER_PIN_DRV_4_8,
150 41, UNIPHIER_PIN_PULL_DOWN),
151 UNIPHIER_PINCTRL_PIN(42, "NFD3", UNIPHIER_PIN_IECTRL_NONE,
152 42, UNIPHIER_PIN_DRV_4_8,
153 42, UNIPHIER_PIN_PULL_DOWN),
154 UNIPHIER_PINCTRL_PIN(43, "NFD4", UNIPHIER_PIN_IECTRL_NONE,
155 43, UNIPHIER_PIN_DRV_4_8,
156 43, UNIPHIER_PIN_PULL_DOWN),
157 UNIPHIER_PINCTRL_PIN(44, "NFD5", UNIPHIER_PIN_IECTRL_NONE,
158 44, UNIPHIER_PIN_DRV_4_8,
159 44, UNIPHIER_PIN_PULL_DOWN),
160 UNIPHIER_PINCTRL_PIN(45, "NFD6", UNIPHIER_PIN_IECTRL_NONE,
161 45, UNIPHIER_PIN_DRV_4_8,
162 45, UNIPHIER_PIN_PULL_DOWN),
163 UNIPHIER_PINCTRL_PIN(46, "NFD7", UNIPHIER_PIN_IECTRL_NONE,
164 46, UNIPHIER_PIN_DRV_4_8,
165 46, UNIPHIER_PIN_PULL_DOWN),
166 UNIPHIER_PINCTRL_PIN(47, "SDCLK", UNIPHIER_PIN_IECTRL_NONE,
167 0, UNIPHIER_PIN_DRV_8_12_16_20,
168 -1, UNIPHIER_PIN_PULL_UP_FIXED),
169 UNIPHIER_PINCTRL_PIN(48, "SDCMD", UNIPHIER_PIN_IECTRL_NONE,
170 4, UNIPHIER_PIN_DRV_8_12_16_20,
171 -1, UNIPHIER_PIN_PULL_UP_FIXED),
172 UNIPHIER_PINCTRL_PIN(49, "SDDAT0", UNIPHIER_PIN_IECTRL_NONE,
173 8, UNIPHIER_PIN_DRV_8_12_16_20,
174 -1, UNIPHIER_PIN_PULL_UP_FIXED),
175 UNIPHIER_PINCTRL_PIN(50, "SDDAT1", UNIPHIER_PIN_IECTRL_NONE,
176 12, UNIPHIER_PIN_DRV_8_12_16_20,
177 -1, UNIPHIER_PIN_PULL_UP_FIXED),
178 UNIPHIER_PINCTRL_PIN(51, "SDDAT2", UNIPHIER_PIN_IECTRL_NONE,
179 16, UNIPHIER_PIN_DRV_8_12_16_20,
180 -1, UNIPHIER_PIN_PULL_UP_FIXED),
181 UNIPHIER_PINCTRL_PIN(52, "SDDAT3", UNIPHIER_PIN_IECTRL_NONE,
182 20, UNIPHIER_PIN_DRV_8_12_16_20,
183 -1, UNIPHIER_PIN_PULL_UP_FIXED),
184 UNIPHIER_PINCTRL_PIN(53, "SDCD", UNIPHIER_PIN_IECTRL_NONE,
185 -1, UNIPHIER_PIN_DRV_FIXED_8,
186 53, UNIPHIER_PIN_PULL_DOWN),
187 UNIPHIER_PINCTRL_PIN(54, "SDWP", UNIPHIER_PIN_IECTRL_NONE,
188 -1, UNIPHIER_PIN_DRV_FIXED_8,
189 54, UNIPHIER_PIN_PULL_DOWN),
190 UNIPHIER_PINCTRL_PIN(55, "SDVOLC", UNIPHIER_PIN_IECTRL_NONE,
191 -1, UNIPHIER_PIN_DRV_FIXED_8,
192 55, UNIPHIER_PIN_PULL_DOWN),
193 UNIPHIER_PINCTRL_PIN(56, "USB0VBUS", UNIPHIER_PIN_IECTRL_NONE,
194 -1, UNIPHIER_PIN_DRV_FIXED_8,
195 56, UNIPHIER_PIN_PULL_DOWN),
196 UNIPHIER_PINCTRL_PIN(57, "USB0OD", UNIPHIER_PIN_IECTRL_NONE,
197 -1, UNIPHIER_PIN_DRV_FIXED_8,
198 57, UNIPHIER_PIN_PULL_DOWN),
199 UNIPHIER_PINCTRL_PIN(58, "USB1VBUS", UNIPHIER_PIN_IECTRL_NONE,
200 -1, UNIPHIER_PIN_DRV_FIXED_8,
201 58, UNIPHIER_PIN_PULL_DOWN),
202 UNIPHIER_PINCTRL_PIN(59, "USB1OD", UNIPHIER_PIN_IECTRL_NONE,
203 -1, UNIPHIER_PIN_DRV_FIXED_8,
204 59, UNIPHIER_PIN_PULL_DOWN),
205 UNIPHIER_PINCTRL_PIN(60, "USB2VBUS", UNIPHIER_PIN_IECTRL_NONE,
206 -1, UNIPHIER_PIN_DRV_FIXED_8,
207 60, UNIPHIER_PIN_PULL_DOWN),
208 UNIPHIER_PINCTRL_PIN(61, "USB2OD", UNIPHIER_PIN_IECTRL_NONE,
209 -1, UNIPHIER_PIN_DRV_FIXED_8,
210 61, UNIPHIER_PIN_PULL_DOWN),
211 UNIPHIER_PINCTRL_PIN(62, "USB3VBUS", UNIPHIER_PIN_IECTRL_NONE,
212 -1, UNIPHIER_PIN_DRV_FIXED_8,
213 62, UNIPHIER_PIN_PULL_DOWN),
214 UNIPHIER_PINCTRL_PIN(63, "USB3OD", UNIPHIER_PIN_IECTRL_NONE,
215 -1, UNIPHIER_PIN_DRV_FIXED_8,
216 63, UNIPHIER_PIN_PULL_DOWN),
217 UNIPHIER_PINCTRL_PIN(64, "HS0BCLKOUT", UNIPHIER_PIN_IECTRL_NONE,
218 -1, UNIPHIER_PIN_DRV_FIXED_8,
219 64, UNIPHIER_PIN_PULL_DOWN),
220 UNIPHIER_PINCTRL_PIN(65, "HS0SYNCOUT", UNIPHIER_PIN_IECTRL_NONE,
221 -1, UNIPHIER_PIN_DRV_FIXED_8,
222 65, UNIPHIER_PIN_PULL_DOWN),
223 UNIPHIER_PINCTRL_PIN(66, "HS0VALOUT", UNIPHIER_PIN_IECTRL_NONE,
224 -1, UNIPHIER_PIN_DRV_FIXED_8,
225 66, UNIPHIER_PIN_PULL_DOWN),
226 UNIPHIER_PINCTRL_PIN(67, "HS0DOUT0", UNIPHIER_PIN_IECTRL_NONE,
227 -1, UNIPHIER_PIN_DRV_FIXED_8,
228 67, UNIPHIER_PIN_PULL_DOWN),
229 UNIPHIER_PINCTRL_PIN(68, "HS0DOUT1", UNIPHIER_PIN_IECTRL_NONE,
230 -1, UNIPHIER_PIN_DRV_FIXED_8,
231 68, UNIPHIER_PIN_PULL_DOWN),
232 UNIPHIER_PINCTRL_PIN(69, "HS0DOUT2", UNIPHIER_PIN_IECTRL_NONE,
233 -1, UNIPHIER_PIN_DRV_FIXED_8,
234 69, UNIPHIER_PIN_PULL_DOWN),
235 UNIPHIER_PINCTRL_PIN(70, "HS0DOUT3", UNIPHIER_PIN_IECTRL_NONE,
236 -1, UNIPHIER_PIN_DRV_FIXED_8,
237 70, UNIPHIER_PIN_PULL_DOWN),
238 UNIPHIER_PINCTRL_PIN(71, "HS0DOUT4", UNIPHIER_PIN_IECTRL_NONE,
239 -1, UNIPHIER_PIN_DRV_FIXED_8,
240 71, UNIPHIER_PIN_PULL_DOWN),
241 UNIPHIER_PINCTRL_PIN(72, "HS0DOUT5", UNIPHIER_PIN_IECTRL_NONE,
242 -1, UNIPHIER_PIN_DRV_FIXED_8,
243 72, UNIPHIER_PIN_PULL_DOWN),
244 UNIPHIER_PINCTRL_PIN(73, "HS0DOUT6", UNIPHIER_PIN_IECTRL_NONE,
245 -1, UNIPHIER_PIN_DRV_FIXED_8,
246 73, UNIPHIER_PIN_PULL_DOWN),
247 UNIPHIER_PINCTRL_PIN(74, "HS0DOUT7", UNIPHIER_PIN_IECTRL_NONE,
248 -1, UNIPHIER_PIN_DRV_FIXED_8,
249 74, UNIPHIER_PIN_PULL_DOWN),
250 UNIPHIER_PINCTRL_PIN(75, "HS1BCLKIN", UNIPHIER_PIN_IECTRL_NONE,
251 -1, UNIPHIER_PIN_DRV_FIXED_8,
252 75, UNIPHIER_PIN_PULL_DOWN),
253 UNIPHIER_PINCTRL_PIN(76, "HS1SYNCIN", UNIPHIER_PIN_IECTRL_NONE,
254 -1, UNIPHIER_PIN_DRV_FIXED_8,
255 76, UNIPHIER_PIN_PULL_DOWN),
256 UNIPHIER_PINCTRL_PIN(77, "HS1VALIN", UNIPHIER_PIN_IECTRL_NONE,
257 -1, UNIPHIER_PIN_DRV_FIXED_8,
258 77, UNIPHIER_PIN_PULL_DOWN),
259 UNIPHIER_PINCTRL_PIN(78, "HS1DIN0", UNIPHIER_PIN_IECTRL_NONE,
260 -1, UNIPHIER_PIN_DRV_FIXED_8,
261 78, UNIPHIER_PIN_PULL_DOWN),
262 UNIPHIER_PINCTRL_PIN(79, "HS1DIN1", UNIPHIER_PIN_IECTRL_NONE,
263 -1, UNIPHIER_PIN_DRV_FIXED_8,
264 79, UNIPHIER_PIN_PULL_DOWN),
265 UNIPHIER_PINCTRL_PIN(80, "HS1DIN2", UNIPHIER_PIN_IECTRL_NONE,
266 -1, UNIPHIER_PIN_DRV_FIXED_8,
267 80, UNIPHIER_PIN_PULL_DOWN),
268 UNIPHIER_PINCTRL_PIN(81, "HS1DIN3", UNIPHIER_PIN_IECTRL_NONE,
269 -1, UNIPHIER_PIN_DRV_FIXED_8,
270 81, UNIPHIER_PIN_PULL_DOWN),
271 UNIPHIER_PINCTRL_PIN(82, "HS1DIN4", UNIPHIER_PIN_IECTRL_NONE,
272 -1, UNIPHIER_PIN_DRV_FIXED_8,
273 82, UNIPHIER_PIN_PULL_DOWN),
274 UNIPHIER_PINCTRL_PIN(83, "HS1DIN5", UNIPHIER_PIN_IECTRL_NONE,
275 -1, UNIPHIER_PIN_DRV_FIXED_8,
276 83, UNIPHIER_PIN_PULL_DOWN),
277 UNIPHIER_PINCTRL_PIN(84, "HS1DIN6", UNIPHIER_PIN_IECTRL_NONE,
278 -1, UNIPHIER_PIN_DRV_FIXED_8,
279 84, UNIPHIER_PIN_PULL_DOWN),
280 UNIPHIER_PINCTRL_PIN(85, "HS1DIN7", UNIPHIER_PIN_IECTRL_NONE,
281 -1, UNIPHIER_PIN_DRV_FIXED_8,
282 85, UNIPHIER_PIN_PULL_DOWN),
283 UNIPHIER_PINCTRL_PIN(86, "HS2BCLKIN", UNIPHIER_PIN_IECTRL_NONE,
284 -1, UNIPHIER_PIN_DRV_FIXED_8,
285 86, UNIPHIER_PIN_PULL_DOWN),
286 UNIPHIER_PINCTRL_PIN(87, "HS2SYNCIN", UNIPHIER_PIN_IECTRL_NONE,
287 -1, UNIPHIER_PIN_DRV_FIXED_8,
288 87, UNIPHIER_PIN_PULL_DOWN),
289 UNIPHIER_PINCTRL_PIN(88, "HS2VALIN", UNIPHIER_PIN_IECTRL_NONE,
290 -1, UNIPHIER_PIN_DRV_FIXED_8,
291 88, UNIPHIER_PIN_PULL_DOWN),
292 UNIPHIER_PINCTRL_PIN(89, "HS2DIN0", UNIPHIER_PIN_IECTRL_NONE,
293 -1, UNIPHIER_PIN_DRV_FIXED_8,
294 89, UNIPHIER_PIN_PULL_DOWN),
295 UNIPHIER_PINCTRL_PIN(90, "HS2DIN1", UNIPHIER_PIN_IECTRL_NONE,
296 -1, UNIPHIER_PIN_DRV_FIXED_8,
297 90, UNIPHIER_PIN_PULL_DOWN),
298 UNIPHIER_PINCTRL_PIN(91, "HS2DIN2", UNIPHIER_PIN_IECTRL_NONE,
299 -1, UNIPHIER_PIN_DRV_FIXED_8,
300 91, UNIPHIER_PIN_PULL_DOWN),
301 UNIPHIER_PINCTRL_PIN(92, "HS2DIN3", UNIPHIER_PIN_IECTRL_NONE,
302 -1, UNIPHIER_PIN_DRV_FIXED_8,
303 92, UNIPHIER_PIN_PULL_DOWN),
304 UNIPHIER_PINCTRL_PIN(93, "HS2DIN4", UNIPHIER_PIN_IECTRL_NONE,
305 -1, UNIPHIER_PIN_DRV_FIXED_8,
306 93, UNIPHIER_PIN_PULL_DOWN),
307 UNIPHIER_PINCTRL_PIN(94, "HS2DIN5", UNIPHIER_PIN_IECTRL_NONE,
308 -1, UNIPHIER_PIN_DRV_FIXED_8,
309 94, UNIPHIER_PIN_PULL_DOWN),
310 UNIPHIER_PINCTRL_PIN(95, "HS2DIN6", UNIPHIER_PIN_IECTRL_NONE,
311 -1, UNIPHIER_PIN_DRV_FIXED_8,
312 95, UNIPHIER_PIN_PULL_DOWN),
313 UNIPHIER_PINCTRL_PIN(96, "HS2DIN7", UNIPHIER_PIN_IECTRL_NONE,
314 -1, UNIPHIER_PIN_DRV_FIXED_8,
315 96, UNIPHIER_PIN_PULL_DOWN),
316 UNIPHIER_PINCTRL_PIN(97, "AO1IEC", UNIPHIER_PIN_IECTRL_NONE,
317 -1, UNIPHIER_PIN_DRV_FIXED_8,
318 97, UNIPHIER_PIN_PULL_DOWN),
319 UNIPHIER_PINCTRL_PIN(98, "AO1DACCK", UNIPHIER_PIN_IECTRL_NONE,
320 -1, UNIPHIER_PIN_DRV_FIXED_8,
321 98, UNIPHIER_PIN_PULL_DOWN),
322 UNIPHIER_PINCTRL_PIN(99, "AO1BCK", UNIPHIER_PIN_IECTRL_NONE,
323 -1, UNIPHIER_PIN_DRV_FIXED_8,
324 99, UNIPHIER_PIN_PULL_DOWN),
325 UNIPHIER_PINCTRL_PIN(100, "AO1LRCK", UNIPHIER_PIN_IECTRL_NONE,
326 -1, UNIPHIER_PIN_DRV_FIXED_8,
327 100, UNIPHIER_PIN_PULL_DOWN),
328 UNIPHIER_PINCTRL_PIN(101, "AO1D0", UNIPHIER_PIN_IECTRL_NONE,
329 -1, UNIPHIER_PIN_DRV_FIXED_8,
330 101, UNIPHIER_PIN_PULL_DOWN),
331 UNIPHIER_PINCTRL_PIN(102, "AO1D1", UNIPHIER_PIN_IECTRL_NONE,
332 -1, UNIPHIER_PIN_DRV_FIXED_8,
333 102, UNIPHIER_PIN_PULL_DOWN),
334 UNIPHIER_PINCTRL_PIN(103, "AO1D2", UNIPHIER_PIN_IECTRL_NONE,
335 -1, UNIPHIER_PIN_DRV_FIXED_8,
336 103, UNIPHIER_PIN_PULL_DOWN),
337 UNIPHIER_PINCTRL_PIN(104, "AO1D3", UNIPHIER_PIN_IECTRL_NONE,
338 -1, UNIPHIER_PIN_DRV_FIXED_8,
339 104, UNIPHIER_PIN_PULL_DOWN),
340 UNIPHIER_PINCTRL_PIN(105, "AO2DACCK", UNIPHIER_PIN_IECTRL_NONE,
341 -1, UNIPHIER_PIN_DRV_FIXED_8,
342 105, UNIPHIER_PIN_PULL_DOWN),
343 UNIPHIER_PINCTRL_PIN(106, "AO2BCK", UNIPHIER_PIN_IECTRL_NONE,
344 -1, UNIPHIER_PIN_DRV_FIXED_8,
345 106, UNIPHIER_PIN_PULL_DOWN),
346 UNIPHIER_PINCTRL_PIN(107, "AO2LRCK", UNIPHIER_PIN_IECTRL_NONE,
347 -1, UNIPHIER_PIN_DRV_FIXED_8,
348 107, UNIPHIER_PIN_PULL_DOWN),
349 UNIPHIER_PINCTRL_PIN(108, "AO2D0", UNIPHIER_PIN_IECTRL_NONE,
350 -1, UNIPHIER_PIN_DRV_FIXED_8,
351 108, UNIPHIER_PIN_PULL_DOWN),
352 UNIPHIER_PINCTRL_PIN(109, "SDA0", UNIPHIER_PIN_IECTRL_NONE,
353 -1, UNIPHIER_PIN_DRV_FIXED_8,
354 109, UNIPHIER_PIN_PULL_DOWN),
355 UNIPHIER_PINCTRL_PIN(110, "SCL0", UNIPHIER_PIN_IECTRL_NONE,
356 -1, UNIPHIER_PIN_DRV_FIXED_8,
357 110, UNIPHIER_PIN_PULL_DOWN),
358 UNIPHIER_PINCTRL_PIN(111, "SDA1", UNIPHIER_PIN_IECTRL_NONE,
359 -1, UNIPHIER_PIN_DRV_FIXED_8,
360 111, UNIPHIER_PIN_PULL_DOWN),
361 UNIPHIER_PINCTRL_PIN(112, "SCL1", UNIPHIER_PIN_IECTRL_NONE,
362 -1, UNIPHIER_PIN_DRV_FIXED_8,
363 112, UNIPHIER_PIN_PULL_DOWN),
364 UNIPHIER_PINCTRL_PIN(113, "SBO0", 0,
365 113, UNIPHIER_PIN_DRV_4_8,
366 113, UNIPHIER_PIN_PULL_UP),
367 UNIPHIER_PINCTRL_PIN(114, "SBI0", 0,
368 114, UNIPHIER_PIN_DRV_4_8,
369 114, UNIPHIER_PIN_PULL_UP),
370 UNIPHIER_PINCTRL_PIN(115, "TXD1", 0,
371 115, UNIPHIER_PIN_DRV_4_8,
372 115, UNIPHIER_PIN_PULL_UP),
373 UNIPHIER_PINCTRL_PIN(116, "RXD1", 0,
374 116, UNIPHIER_PIN_DRV_4_8,
375 116, UNIPHIER_PIN_PULL_UP),
376 UNIPHIER_PINCTRL_PIN(117, "PWSRA", UNIPHIER_PIN_IECTRL_NONE,
377 -1, UNIPHIER_PIN_DRV_FIXED_8,
378 117, UNIPHIER_PIN_PULL_DOWN),
379 UNIPHIER_PINCTRL_PIN(118, "XIRQ0", UNIPHIER_PIN_IECTRL_NONE,
380 -1, UNIPHIER_PIN_DRV_FIXED_8,
381 118, UNIPHIER_PIN_PULL_DOWN),
382 UNIPHIER_PINCTRL_PIN(119, "XIRQ1", UNIPHIER_PIN_IECTRL_NONE,
383 -1, UNIPHIER_PIN_DRV_FIXED_8,
384 119, UNIPHIER_PIN_PULL_DOWN),
385 UNIPHIER_PINCTRL_PIN(120, "XIRQ2", UNIPHIER_PIN_IECTRL_NONE,
386 -1, UNIPHIER_PIN_DRV_FIXED_8,
387 120, UNIPHIER_PIN_PULL_DOWN),
388 UNIPHIER_PINCTRL_PIN(121, "XIRQ3", UNIPHIER_PIN_IECTRL_NONE,
389 -1, UNIPHIER_PIN_DRV_FIXED_8,
390 121, UNIPHIER_PIN_PULL_DOWN),
391 UNIPHIER_PINCTRL_PIN(122, "XIRQ4", UNIPHIER_PIN_IECTRL_NONE,
392 -1, UNIPHIER_PIN_DRV_FIXED_8,
393 122, UNIPHIER_PIN_PULL_DOWN),
394 UNIPHIER_PINCTRL_PIN(123, "XIRQ5", UNIPHIER_PIN_IECTRL_NONE,
395 -1, UNIPHIER_PIN_DRV_FIXED_8,
396 123, UNIPHIER_PIN_PULL_DOWN),
397 UNIPHIER_PINCTRL_PIN(124, "XIRQ6", UNIPHIER_PIN_IECTRL_NONE,
398 -1, UNIPHIER_PIN_DRV_FIXED_8,
399 124, UNIPHIER_PIN_PULL_DOWN),
400 UNIPHIER_PINCTRL_PIN(125, "XIRQ7", UNIPHIER_PIN_IECTRL_NONE,
401 -1, UNIPHIER_PIN_DRV_FIXED_8,
402 125, UNIPHIER_PIN_PULL_DOWN),
403 UNIPHIER_PINCTRL_PIN(126, "XIRQ8", UNIPHIER_PIN_IECTRL_NONE,
404 -1, UNIPHIER_PIN_DRV_FIXED_8,
405 126, UNIPHIER_PIN_PULL_DOWN),
406 UNIPHIER_PINCTRL_PIN(127, "PORT00", UNIPHIER_PIN_IECTRL_NONE,
407 -1, UNIPHIER_PIN_DRV_FIXED_8,
408 127, UNIPHIER_PIN_PULL_DOWN),
409 UNIPHIER_PINCTRL_PIN(128, "PORT01", UNIPHIER_PIN_IECTRL_NONE,
410 -1, UNIPHIER_PIN_DRV_FIXED_8,
411 128, UNIPHIER_PIN_PULL_DOWN),
412 UNIPHIER_PINCTRL_PIN(129, "PORT02", UNIPHIER_PIN_IECTRL_NONE,
413 -1, UNIPHIER_PIN_DRV_FIXED_8,
414 129, UNIPHIER_PIN_PULL_DOWN),
415 UNIPHIER_PINCTRL_PIN(130, "PORT03", UNIPHIER_PIN_IECTRL_NONE,
416 -1, UNIPHIER_PIN_DRV_FIXED_8,
417 130, UNIPHIER_PIN_PULL_DOWN),
418 UNIPHIER_PINCTRL_PIN(131, "PORT04", UNIPHIER_PIN_IECTRL_NONE,
419 -1, UNIPHIER_PIN_DRV_FIXED_8,
420 131, UNIPHIER_PIN_PULL_DOWN),
421 UNIPHIER_PINCTRL_PIN(132, "PORT05", UNIPHIER_PIN_IECTRL_NONE,
422 -1, UNIPHIER_PIN_DRV_FIXED_8,
423 132, UNIPHIER_PIN_PULL_DOWN),
424 UNIPHIER_PINCTRL_PIN(133, "PORT06", UNIPHIER_PIN_IECTRL_NONE,
425 -1, UNIPHIER_PIN_DRV_FIXED_8,
426 133, UNIPHIER_PIN_PULL_DOWN),
427 UNIPHIER_PINCTRL_PIN(134, "PORT07", UNIPHIER_PIN_IECTRL_NONE,
428 -1, UNIPHIER_PIN_DRV_FIXED_8,
429 134, UNIPHIER_PIN_PULL_DOWN),
430 UNIPHIER_PINCTRL_PIN(135, "PORT10", UNIPHIER_PIN_IECTRL_NONE,
431 -1, UNIPHIER_PIN_DRV_FIXED_8,
432 135, UNIPHIER_PIN_PULL_DOWN),
433 UNIPHIER_PINCTRL_PIN(136, "PORT11", UNIPHIER_PIN_IECTRL_NONE,
434 -1, UNIPHIER_PIN_DRV_FIXED_8,
435 136, UNIPHIER_PIN_PULL_DOWN),
436 UNIPHIER_PINCTRL_PIN(137, "PORT12", UNIPHIER_PIN_IECTRL_NONE,
437 -1, UNIPHIER_PIN_DRV_FIXED_8,
438 137, UNIPHIER_PIN_PULL_DOWN),
439 UNIPHIER_PINCTRL_PIN(138, "PORT13", UNIPHIER_PIN_IECTRL_NONE,
440 -1, UNIPHIER_PIN_DRV_FIXED_8,
441 138, UNIPHIER_PIN_PULL_DOWN),
442 UNIPHIER_PINCTRL_PIN(139, "PORT14", UNIPHIER_PIN_IECTRL_NONE,
443 -1, UNIPHIER_PIN_DRV_FIXED_8,
444 139, UNIPHIER_PIN_PULL_DOWN),
445 UNIPHIER_PINCTRL_PIN(140, "PORT15", UNIPHIER_PIN_IECTRL_NONE,
446 -1, UNIPHIER_PIN_DRV_FIXED_8,
447 140, UNIPHIER_PIN_PULL_DOWN),
448 UNIPHIER_PINCTRL_PIN(141, "PORT16", UNIPHIER_PIN_IECTRL_NONE,
449 -1, UNIPHIER_PIN_DRV_FIXED_8,
450 141, UNIPHIER_PIN_PULL_DOWN),
451 UNIPHIER_PINCTRL_PIN(142, "LPST", UNIPHIER_PIN_IECTRL_NONE,
452 142, UNIPHIER_PIN_DRV_4_8,
453 142, UNIPHIER_PIN_PULL_DOWN),
454 UNIPHIER_PINCTRL_PIN(143, "MDC", 0,
455 143, UNIPHIER_PIN_DRV_4_8,
456 143, UNIPHIER_PIN_PULL_DOWN),
457 UNIPHIER_PINCTRL_PIN(144, "MDIO", 0,
458 144, UNIPHIER_PIN_DRV_4_8,
459 144, UNIPHIER_PIN_PULL_DOWN),
460 UNIPHIER_PINCTRL_PIN(145, "MDIO_INTL", 0,
461 145, UNIPHIER_PIN_DRV_4_8,
462 145, UNIPHIER_PIN_PULL_DOWN),
463 UNIPHIER_PINCTRL_PIN(146, "PHYRSTL", 0,
464 146, UNIPHIER_PIN_DRV_4_8,
465 146, UNIPHIER_PIN_PULL_DOWN),
466 UNIPHIER_PINCTRL_PIN(147, "RGMII_RXCLK", 0,
467 147, UNIPHIER_PIN_DRV_4_8,
468 147, UNIPHIER_PIN_PULL_DOWN),
469 UNIPHIER_PINCTRL_PIN(148, "RGMII_RXD0", 0,
470 148, UNIPHIER_PIN_DRV_4_8,
471 148, UNIPHIER_PIN_PULL_DOWN),
472 UNIPHIER_PINCTRL_PIN(149, "RGMII_RXD1", 0,
473 149, UNIPHIER_PIN_DRV_4_8,
474 149, UNIPHIER_PIN_PULL_DOWN),
475 UNIPHIER_PINCTRL_PIN(150, "RGMII_RXD2", 0,
476 150, UNIPHIER_PIN_DRV_4_8,
477 150, UNIPHIER_PIN_PULL_DOWN),
478 UNIPHIER_PINCTRL_PIN(151, "RGMII_RXD3", 0,
479 151, UNIPHIER_PIN_DRV_4_8,
480 151, UNIPHIER_PIN_PULL_DOWN),
481 UNIPHIER_PINCTRL_PIN(152, "RGMII_RXCTL", 0,
482 152, UNIPHIER_PIN_DRV_4_8,
483 152, UNIPHIER_PIN_PULL_DOWN),
484 UNIPHIER_PINCTRL_PIN(153, "RGMII_TXCLK", 0,
485 153, UNIPHIER_PIN_DRV_4_8,
486 153, UNIPHIER_PIN_PULL_DOWN),
487 UNIPHIER_PINCTRL_PIN(154, "RGMII_TXD0", 0,
488 154, UNIPHIER_PIN_DRV_4_8,
489 154, UNIPHIER_PIN_PULL_DOWN),
490 UNIPHIER_PINCTRL_PIN(155, "RGMII_TXD1", 0,
491 155, UNIPHIER_PIN_DRV_4_8,
492 155, UNIPHIER_PIN_PULL_DOWN),
493 UNIPHIER_PINCTRL_PIN(156, "RGMII_TXD2", 0,
494 156, UNIPHIER_PIN_DRV_4_8,
495 156, UNIPHIER_PIN_PULL_DOWN),
496 UNIPHIER_PINCTRL_PIN(157, "RGMII_TXD3", 0,
497 157, UNIPHIER_PIN_DRV_4_8,
498 157, UNIPHIER_PIN_PULL_DOWN),
499 UNIPHIER_PINCTRL_PIN(158, "RGMII_TXCTL", 0,
500 158, UNIPHIER_PIN_DRV_4_8,
501 158, UNIPHIER_PIN_PULL_DOWN),
502 UNIPHIER_PINCTRL_PIN(159, "A_D_PCD00OUT", UNIPHIER_PIN_IECTRL_NONE,
503 -1, UNIPHIER_PIN_DRV_FIXED_8,
504 159, UNIPHIER_PIN_PULL_DOWN),
505 UNIPHIER_PINCTRL_PIN(160, "A_D_PCD01OUT", UNIPHIER_PIN_IECTRL_NONE,
506 -1, UNIPHIER_PIN_DRV_FIXED_8,
507 160, UNIPHIER_PIN_PULL_DOWN),
508 UNIPHIER_PINCTRL_PIN(161, "A_D_PCD02OUT", UNIPHIER_PIN_IECTRL_NONE,
509 -1, UNIPHIER_PIN_DRV_FIXED_8,
510 161, UNIPHIER_PIN_PULL_DOWN),
511 UNIPHIER_PINCTRL_PIN(162, "A_D_PCD03OUT", UNIPHIER_PIN_IECTRL_NONE,
512 -1, UNIPHIER_PIN_DRV_FIXED_8,
513 162, UNIPHIER_PIN_PULL_DOWN),
514 UNIPHIER_PINCTRL_PIN(163, "A_D_PCD04OUT", UNIPHIER_PIN_IECTRL_NONE,
515 -1, UNIPHIER_PIN_DRV_FIXED_8,
516 163, UNIPHIER_PIN_PULL_DOWN),
517 UNIPHIER_PINCTRL_PIN(164, "A_D_PCD05OUT", UNIPHIER_PIN_IECTRL_NONE,
518 -1, UNIPHIER_PIN_DRV_FIXED_8,
519 164, UNIPHIER_PIN_PULL_DOWN),
520 UNIPHIER_PINCTRL_PIN(165, "A_D_PCD06OUT", UNIPHIER_PIN_IECTRL_NONE,
521 -1, UNIPHIER_PIN_DRV_FIXED_8,
522 165, UNIPHIER_PIN_PULL_DOWN),
523 UNIPHIER_PINCTRL_PIN(166, "A_D_PCD07OUT", UNIPHIER_PIN_IECTRL_NONE,
524 -1, UNIPHIER_PIN_DRV_FIXED_8,
525 166, UNIPHIER_PIN_PULL_DOWN),
526 UNIPHIER_PINCTRL_PIN(167, "A_D_PCD00IN", UNIPHIER_PIN_IECTRL_NONE,
527 -1, UNIPHIER_PIN_DRV_FIXED_8,
528 167, UNIPHIER_PIN_PULL_DOWN),
529 UNIPHIER_PINCTRL_PIN(168, "A_D_PCD01IN", UNIPHIER_PIN_IECTRL_NONE,
530 -1, UNIPHIER_PIN_DRV_FIXED_8,
531 168, UNIPHIER_PIN_PULL_DOWN),
532 UNIPHIER_PINCTRL_PIN(169, "A_D_PCD02IN", UNIPHIER_PIN_IECTRL_NONE,
533 -1, UNIPHIER_PIN_DRV_FIXED_8,
534 169, UNIPHIER_PIN_PULL_DOWN),
535 UNIPHIER_PINCTRL_PIN(170, "A_D_PCD03IN", UNIPHIER_PIN_IECTRL_NONE,
536 -1, UNIPHIER_PIN_DRV_FIXED_8,
537 170, UNIPHIER_PIN_PULL_DOWN),
538 UNIPHIER_PINCTRL_PIN(171, "A_D_PCD04IN", UNIPHIER_PIN_IECTRL_NONE,
539 -1, UNIPHIER_PIN_DRV_FIXED_8,
540 171, UNIPHIER_PIN_PULL_DOWN),
541 UNIPHIER_PINCTRL_PIN(172, "A_D_PCD05IN", UNIPHIER_PIN_IECTRL_NONE,
542 -1, UNIPHIER_PIN_DRV_FIXED_8,
543 172, UNIPHIER_PIN_PULL_DOWN),
544 UNIPHIER_PINCTRL_PIN(173, "A_D_PCD06IN", UNIPHIER_PIN_IECTRL_NONE,
545 -1, UNIPHIER_PIN_DRV_FIXED_8,
546 173, UNIPHIER_PIN_PULL_DOWN),
547 UNIPHIER_PINCTRL_PIN(174, "A_D_PCD07IN", UNIPHIER_PIN_IECTRL_NONE,
548 -1, UNIPHIER_PIN_DRV_FIXED_8,
549 174, UNIPHIER_PIN_PULL_DOWN),
550 UNIPHIER_PINCTRL_PIN(175, "A_D_PCDNOE", UNIPHIER_PIN_IECTRL_NONE,
551 -1, UNIPHIER_PIN_DRV_FIXED_8,
552 175, UNIPHIER_PIN_PULL_DOWN),
553 UNIPHIER_PINCTRL_PIN(176, "A_D_PC0READY", UNIPHIER_PIN_IECTRL_NONE,
554 -1, UNIPHIER_PIN_DRV_FIXED_8,
555 176, UNIPHIER_PIN_PULL_DOWN),
556 UNIPHIER_PINCTRL_PIN(177, "A_D_PC0CD1", UNIPHIER_PIN_IECTRL_NONE,
557 -1, UNIPHIER_PIN_DRV_FIXED_8,
558 177, UNIPHIER_PIN_PULL_DOWN),
559 UNIPHIER_PINCTRL_PIN(178, "A_D_PC0CD2", UNIPHIER_PIN_IECTRL_NONE,
560 -1, UNIPHIER_PIN_DRV_FIXED_8,
561 178, UNIPHIER_PIN_PULL_DOWN),
562 UNIPHIER_PINCTRL_PIN(179, "A_D_PC0WAIT", UNIPHIER_PIN_IECTRL_NONE,
563 -1, UNIPHIER_PIN_DRV_FIXED_8,
564 179, UNIPHIER_PIN_PULL_DOWN),
565 UNIPHIER_PINCTRL_PIN(180, "A_D_PC0RESET", UNIPHIER_PIN_IECTRL_NONE,
566 -1, UNIPHIER_PIN_DRV_FIXED_8,
567 180, UNIPHIER_PIN_PULL_DOWN),
568 UNIPHIER_PINCTRL_PIN(181, "A_D_PC0CE1", UNIPHIER_PIN_IECTRL_NONE,
569 -1, UNIPHIER_PIN_DRV_FIXED_8,
570 181, UNIPHIER_PIN_PULL_DOWN),
571 UNIPHIER_PINCTRL_PIN(182, "A_D_PC0WE", UNIPHIER_PIN_IECTRL_NONE,
572 -1, UNIPHIER_PIN_DRV_FIXED_8,
573 182, UNIPHIER_PIN_PULL_DOWN),
574 UNIPHIER_PINCTRL_PIN(183, "A_D_PC0OE", UNIPHIER_PIN_IECTRL_NONE,
575 -1, UNIPHIER_PIN_DRV_FIXED_8,
576 183, UNIPHIER_PIN_PULL_DOWN),
577 UNIPHIER_PINCTRL_PIN(184, "A_D_PC0IOWR", UNIPHIER_PIN_IECTRL_NONE,
578 -1, UNIPHIER_PIN_DRV_FIXED_8,
579 184, UNIPHIER_PIN_PULL_DOWN),
580 UNIPHIER_PINCTRL_PIN(185, "A_D_PC0IORD", UNIPHIER_PIN_IECTRL_NONE,
581 -1, UNIPHIER_PIN_DRV_FIXED_8,
582 185, UNIPHIER_PIN_PULL_DOWN),
583 UNIPHIER_PINCTRL_PIN(186, "A_D_PC0NOE", UNIPHIER_PIN_IECTRL_NONE,
584 -1, UNIPHIER_PIN_DRV_FIXED_8,
585 186, UNIPHIER_PIN_PULL_DOWN),
586 UNIPHIER_PINCTRL_PIN(187, "A_D_HS0BCLKIN", 0,
587 187, UNIPHIER_PIN_DRV_4_8,
588 187, UNIPHIER_PIN_PULL_DOWN),
589 UNIPHIER_PINCTRL_PIN(188, "A_D_HS0SYNCIN", 0,
590 188, UNIPHIER_PIN_DRV_4_8,
591 188, UNIPHIER_PIN_PULL_DOWN),
592 UNIPHIER_PINCTRL_PIN(189, "A_D_HS0VALIN", 0,
593 189, UNIPHIER_PIN_DRV_4_8,
594 189, UNIPHIER_PIN_PULL_DOWN),
595 UNIPHIER_PINCTRL_PIN(190, "A_D_HS0DIN0", 0,
596 190, UNIPHIER_PIN_DRV_4_8,
597 190, UNIPHIER_PIN_PULL_DOWN),
598 UNIPHIER_PINCTRL_PIN(191, "A_D_HS0DIN1", 0,
599 191, UNIPHIER_PIN_DRV_4_8,
600 191, UNIPHIER_PIN_PULL_DOWN),
601 UNIPHIER_PINCTRL_PIN(192, "A_D_HS0DIN2", 0,
602 192, UNIPHIER_PIN_DRV_4_8,
603 192, UNIPHIER_PIN_PULL_DOWN),
604 UNIPHIER_PINCTRL_PIN(193, "A_D_HS0DIN3", 0,
605 193, UNIPHIER_PIN_DRV_4_8,
606 193, UNIPHIER_PIN_PULL_DOWN),
607 UNIPHIER_PINCTRL_PIN(194, "A_D_HS0DIN4", 0,
608 194, UNIPHIER_PIN_DRV_4_8,
609 194, UNIPHIER_PIN_PULL_DOWN),
610 UNIPHIER_PINCTRL_PIN(195, "A_D_HS0DIN5", 0,
611 195, UNIPHIER_PIN_DRV_4_8,
612 195, UNIPHIER_PIN_PULL_DOWN),
613 UNIPHIER_PINCTRL_PIN(196, "A_D_HS0DIN6", 0,
614 196, UNIPHIER_PIN_DRV_4_8,
615 196, UNIPHIER_PIN_PULL_DOWN),
616 UNIPHIER_PINCTRL_PIN(197, "A_D_HS0DIN7", 0,
617 197, UNIPHIER_PIN_DRV_4_8,
618 197, UNIPHIER_PIN_PULL_DOWN),
619 UNIPHIER_PINCTRL_PIN(198, "A_D_AO1ARC", 0,
620 198, UNIPHIER_PIN_DRV_4_8,
621 198, UNIPHIER_PIN_PULL_DOWN),
622 UNIPHIER_PINCTRL_PIN(199, "A_D_SPIXRST", UNIPHIER_PIN_IECTRL_NONE,
623 199, UNIPHIER_PIN_DRV_4_8,
624 199, UNIPHIER_PIN_PULL_DOWN),
625 UNIPHIER_PINCTRL_PIN(200, "A_D_SPISCLK0", UNIPHIER_PIN_IECTRL_NONE,
626 200, UNIPHIER_PIN_DRV_4_8,
627 200, UNIPHIER_PIN_PULL_DOWN),
628 UNIPHIER_PINCTRL_PIN(201, "A_D_SPITXD0", UNIPHIER_PIN_IECTRL_NONE,
629 201, UNIPHIER_PIN_DRV_4_8,
630 201, UNIPHIER_PIN_PULL_DOWN),
631 UNIPHIER_PINCTRL_PIN(202, "A_D_SPIRXD0", UNIPHIER_PIN_IECTRL_NONE,
632 202, UNIPHIER_PIN_DRV_4_8,
633 202, UNIPHIER_PIN_PULL_DOWN),
634 UNIPHIER_PINCTRL_PIN(203, "A_D_DMDCLK", UNIPHIER_PIN_IECTRL_NONE,
635 -1, UNIPHIER_PIN_DRV_FIXED_8,
636 203, UNIPHIER_PIN_PULL_DOWN),
637 UNIPHIER_PINCTRL_PIN(204, "A_D_DMDPSYNC", UNIPHIER_PIN_IECTRL_NONE,
638 -1, UNIPHIER_PIN_DRV_FIXED_8,
639 204, UNIPHIER_PIN_PULL_DOWN),
640 UNIPHIER_PINCTRL_PIN(205, "A_D_DMDVAL", UNIPHIER_PIN_IECTRL_NONE,
641 -1, UNIPHIER_PIN_DRV_FIXED_8,
642 205, UNIPHIER_PIN_PULL_DOWN),
643 UNIPHIER_PINCTRL_PIN(206, "A_D_DMDDATA", UNIPHIER_PIN_IECTRL_NONE,
644 -1, UNIPHIER_PIN_DRV_FIXED_8,
645 206, UNIPHIER_PIN_PULL_DOWN),
646 UNIPHIER_PINCTRL_PIN(207, "A_D_HDMIRXXIRQ", 0,
647 207, UNIPHIER_PIN_DRV_4_8,
648 207, UNIPHIER_PIN_PULL_DOWN),
649 UNIPHIER_PINCTRL_PIN(208, "A_D_VBIXIRQ", 0,
650 208, UNIPHIER_PIN_DRV_4_8,
651 208, UNIPHIER_PIN_PULL_DOWN),
652 UNIPHIER_PINCTRL_PIN(209, "A_D_HDMITXXIRQ", 0,
653 209, UNIPHIER_PIN_DRV_4_8,
654 209, UNIPHIER_PIN_PULL_DOWN),
655 UNIPHIER_PINCTRL_PIN(210, "A_D_DMDIRQ", UNIPHIER_PIN_IECTRL_NONE,
656 210, UNIPHIER_PIN_DRV_4_8,
657 210, UNIPHIER_PIN_PULL_DOWN),
658 UNIPHIER_PINCTRL_PIN(211, "A_D_SPICIRQ", UNIPHIER_PIN_IECTRL_NONE,
659 211, UNIPHIER_PIN_DRV_4_8,
660 211, UNIPHIER_PIN_PULL_DOWN),
661 UNIPHIER_PINCTRL_PIN(212, "A_D_SPIBIRQ", UNIPHIER_PIN_IECTRL_NONE,
662 212, UNIPHIER_PIN_DRV_4_8,
663 212, UNIPHIER_PIN_PULL_DOWN),
664 UNIPHIER_PINCTRL_PIN(213, "A_D_BESDAOUT", UNIPHIER_PIN_IECTRL_NONE,
665 -1, UNIPHIER_PIN_DRV_FIXED_4,
666 213, UNIPHIER_PIN_PULL_DOWN),
667 UNIPHIER_PINCTRL_PIN(214, "A_D_BESDAIN", UNIPHIER_PIN_IECTRL_NONE,
668 -1, UNIPHIER_PIN_DRV_FIXED_4,
669 214, UNIPHIER_PIN_PULL_DOWN),
670 UNIPHIER_PINCTRL_PIN(215, "A_D_BESCLOUT", UNIPHIER_PIN_IECTRL_NONE,
671 215, UNIPHIER_PIN_DRV_4_8,
672 215, UNIPHIER_PIN_PULL_DOWN),
673 UNIPHIER_PINCTRL_PIN(216, "A_D_VDACCLKOUT", 0,
674 216, UNIPHIER_PIN_DRV_4_8,
675 216, UNIPHIER_PIN_PULL_DOWN),
676 UNIPHIER_PINCTRL_PIN(217, "A_D_VDACDOUT5", 0,
677 217, UNIPHIER_PIN_DRV_4_8,
678 217, UNIPHIER_PIN_PULL_DOWN),
679 UNIPHIER_PINCTRL_PIN(218, "A_D_VDACDOUT6", 0,
680 218, UNIPHIER_PIN_DRV_4_8,
681 218, UNIPHIER_PIN_PULL_DOWN),
682 UNIPHIER_PINCTRL_PIN(219, "A_D_VDACDOUT7", 0,
683 219, UNIPHIER_PIN_DRV_4_8,
684 219, UNIPHIER_PIN_PULL_DOWN),
685 UNIPHIER_PINCTRL_PIN(220, "A_D_VDACDOUT8", 0,
686 220, UNIPHIER_PIN_DRV_4_8,
687 220, UNIPHIER_PIN_PULL_DOWN),
688 UNIPHIER_PINCTRL_PIN(221, "A_D_VDACDOUT9", 0,
689 221, UNIPHIER_PIN_DRV_4_8,
690 221, UNIPHIER_PIN_PULL_DOWN),
691 UNIPHIER_PINCTRL_PIN(222, "A_D_SIFBCKIN", 0,
692 222, UNIPHIER_PIN_DRV_4_8,
693 222, UNIPHIER_PIN_PULL_DOWN),
694 UNIPHIER_PINCTRL_PIN(223, "A_D_SIFLRCKIN", 0,
695 223, UNIPHIER_PIN_DRV_4_8,
696 223, UNIPHIER_PIN_PULL_DOWN),
697 UNIPHIER_PINCTRL_PIN(224, "A_D_SIFDIN", 0,
698 224, UNIPHIER_PIN_DRV_4_8,
699 224, UNIPHIER_PIN_PULL_DOWN),
700 UNIPHIER_PINCTRL_PIN(225, "A_D_LIBCKOUT", 0,
701 225, UNIPHIER_PIN_DRV_4_8,
702 225, UNIPHIER_PIN_PULL_DOWN),
703 UNIPHIER_PINCTRL_PIN(226, "A_D_LILRCKOUT", 0,
704 226, UNIPHIER_PIN_DRV_4_8,
705 226, UNIPHIER_PIN_PULL_DOWN),
706 UNIPHIER_PINCTRL_PIN(227, "A_D_LIDIN", 0,
707 227, UNIPHIER_PIN_DRV_4_8,
708 227, UNIPHIER_PIN_PULL_DOWN),
709 UNIPHIER_PINCTRL_PIN(228, "A_D_LODOUT", 0,
710 228, UNIPHIER_PIN_DRV_4_8,
711 228, UNIPHIER_PIN_PULL_DOWN),
712 UNIPHIER_PINCTRL_PIN(229, "A_D_HPDOUT", 0,
713 229, UNIPHIER_PIN_DRV_4_8,
714 229, UNIPHIER_PIN_PULL_DOWN),
715 UNIPHIER_PINCTRL_PIN(230, "A_D_MCLK", 0,
716 230, UNIPHIER_PIN_DRV_4_8,
717 230, UNIPHIER_PIN_PULL_DOWN),
718 UNIPHIER_PINCTRL_PIN(231, "A_D_A2PLLREFOUT", 0,
719 231, UNIPHIER_PIN_DRV_4_8,
720 231, UNIPHIER_PIN_PULL_DOWN),
721 UNIPHIER_PINCTRL_PIN(232, "A_D_HDMI3DSDAOUT", 0,
722 232, UNIPHIER_PIN_DRV_4_8,
723 232, UNIPHIER_PIN_PULL_DOWN),
724 UNIPHIER_PINCTRL_PIN(233, "A_D_HDMI3DSDAIN", 0,
725 233, UNIPHIER_PIN_DRV_4_8,
726 233, UNIPHIER_PIN_PULL_DOWN),
727 UNIPHIER_PINCTRL_PIN(234, "A_D_HDMI3DSCLIN", 0,
728 234, UNIPHIER_PIN_DRV_4_8,
729 234, UNIPHIER_PIN_PULL_DOWN),
730};
731
732static const unsigned adinter_pins[] = {
733 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172,
734 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186,
735 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200,
736 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214,
737 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228,
738 229, 230, 231, 232, 233, 234,
739};
740static const unsigned adinter_muxvals[] = {
741 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
742 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
743 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
744 0, 0, 0, 0,
745};
746static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
747static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
748static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
749static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
750static const unsigned i2c0_pins[] = {109, 110};
751static const unsigned i2c0_muxvals[] = {0, 0};
752static const unsigned i2c1_pins[] = {111, 112};
753static const unsigned i2c1_muxvals[] = {0, 0};
754static const unsigned i2c2_pins[] = {115, 116};
755static const unsigned i2c2_muxvals[] = {1, 1};
756static const unsigned i2c3_pins[] = {118, 119};
757static const unsigned i2c3_muxvals[] = {1, 1};
758static const unsigned nand_pins[] = {30, 31, 32, 33, 34, 35, 36, 39, 40, 41,
759 42, 43, 44, 45, 46};
760static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
761 0, 0};
762static const unsigned nand_cs1_pins[] = {37, 38};
763static const unsigned nand_cs1_muxvals[] = {0, 0};
764static const unsigned uart0_pins[] = {135, 136};
765static const unsigned uart0_muxvals[] = {3, 3};
766static const unsigned uart0b_pins[] = {11, 12};
767static const unsigned uart0b_muxvals[] = {2, 2};
768static const unsigned uart1_pins[] = {115, 116};
769static const unsigned uart1_muxvals[] = {0, 0};
770static const unsigned uart1b_pins[] = {113, 114};
771static const unsigned uart1b_muxvals[] = {1, 1};
772static const unsigned uart2_pins[] = {113, 114};
773static const unsigned uart2_muxvals[] = {2, 2};
774static const unsigned uart2b_pins[] = {86, 87};
775static const unsigned uart2b_muxvals[] = {1, 1};
776static const unsigned usb0_pins[] = {56, 57};
777static const unsigned usb0_muxvals[] = {0, 0};
778static const unsigned usb1_pins[] = {58, 59};
779static const unsigned usb1_muxvals[] = {0, 0};
780static const unsigned usb2_pins[] = {60, 61};
781static const unsigned usb2_muxvals[] = {0, 0};
782static const unsigned usb3_pins[] = {62, 63};
783static const unsigned usb3_muxvals[] = {0, 0};
784static const unsigned port_range0_pins[] = {
785 127, 128, 129, 130, 131, 132, 133, 134, /* PORT0x */
786 135, 136, 137, 138, 139, 140, 141, 142, /* PORT1x */
787 0, 1, 2, 3, 4, 5, 6, 7, /* PORT2x */
788 8, 9, 10, 11, 12, 13, 14, 15, /* PORT3x */
789 16, 17, 18, 19, 21, 22, 23, 24, /* PORT4x */
790 25, 30, 31, 32, 33, 34, 35, 36, /* PORT5x */
791 37, 38, 39, 40, 41, 42, 43, 44, /* PORT6x */
792 45, 46, 47, 48, 49, 50, 51, 52, /* PORT7x */
793 53, 54, 55, 56, 57, 58, 59, 60, /* PORT8x */
794 61, 62, 63, 64, 65, 66, 67, 68, /* PORT9x */
795 69, 70, 71, 76, 77, 78, 79, 80, /* PORT10x */
796};
797static const unsigned port_range0_muxvals[] = {
798 15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */
799 15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */
800 15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */
801 15, 15, 15, 15, 15, 15, 15, 15, /* PORT3x */
802 15, 15, 15, 15, 15, 15, 15, 15, /* PORT4x */
803 15, 15, 15, 15, 15, 15, 15, 15, /* PORT5x */
804 15, 15, 15, 15, 15, 15, 15, 15, /* PORT6x */
805 15, 15, 15, 15, 15, 15, 15, 15, /* PORT7x */
806 15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */
807 15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */
808 15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */
809};
810static const unsigned port_range1_pins[] = {
811 81, 82, 83, 84, 85, 86, 87, 88, /* PORT12x */
812 89, 90, 95, 96, 97, 98, 99, 100, /* PORT13x */
813 101, 102, 103, 104, 105, 106, 107, 108, /* PORT14x */
814 118, 119, 120, 121, 122, 123, 124, 125, /* PORT15x */
815 126, 72, 73, 92, 177, 93, 94, 176, /* PORT16x */
816 74, 91, 27, 28, 29, 75, 20, 26, /* PORT17x */
817 109, 110, 111, 112, 113, 114, 115, 116, /* PORT18x */
818 117, 143, 144, 145, 146, 147, 148, 149, /* PORT19x */
819 150, 151, 152, 153, 154, 155, 156, 157, /* PORT20x */
820 158, 159, 160, 161, 162, 163, 164, 165, /* PORT21x */
821 166, 178, 179, 180, 181, 182, 183, 184, /* PORT22x */
822 185, 187, 188, 189, 190, 191, 192, 193, /* PORT23x */
823 194, 195, 196, 197, 198, 199, 200, 201, /* PORT24x */
824 202, 203, 204, 205, 206, 207, 208, 209, /* PORT25x */
825 210, 211, 212, 213, 214, 215, 216, 217, /* PORT26x */
826 218, 219, 220, 221, 223, 224, 225, 226, /* PORT27x */
827 227, 228, 229, 230, 231, 232, 233, 234, /* PORT28x */
828};
829static const unsigned port_range1_muxvals[] = {
830 15, 15, 15, 15, 15, 15, 15, 15, /* PORT12x */
831 15, 15, 15, 15, 15, 15, 15, 15, /* PORT13x */
832 15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */
833 15, 15, 15, 15, 15, 15, 15, 15, /* PORT15x */
834 15, 15, 15, 15, 15, 15, 15, 15, /* PORT16x */
835 15, 15, 15, 15, 15, 15, 15, 15, /* PORT17x */
836 15, 15, 15, 15, 15, 15, 15, 15, /* PORT18x */
837 15, 15, 15, 15, 15, 15, 15, 15, /* PORT19x */
838 15, 15, 15, 15, 15, 15, 15, 15, /* PORT20x */
839 15, 15, 15, 15, 15, 15, 15, 15, /* PORT21x */
840 15, 15, 15, 15, 15, 15, 15, 15, /* PORT22x */
841 15, 15, 15, 15, 15, 15, 15, 15, /* PORT23x */
842 15, 15, 15, 15, 15, 15, 15, 15, /* PORT24x */
843 15, 15, 15, 15, 15, 15, 15, 15, /* PORT25x */
844 15, 15, 15, 15, 15, 15, 15, 15, /* PORT26x */
845 15, 15, 15, 15, 15, 15, 15, 15, /* PORT27x */
846 15, 15, 15, 15, 15, 15, 15, 15, /* PORT28x */
847};
848static const unsigned xirq_pins[] = {
849 118, 119, 120, 121, 122, 123, 124, 125, /* XIRQ0-7 */
850 126, 72, 73, 92, 177, 93, 94, 176, /* XIRQ8-15 */
851 74, 91, 27, 28, 29, 75, 20, 26, /* XIRQ16-23 */
852};
853static const unsigned xirq_muxvals[] = {
854 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ0-7 */
855 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ8-15 */
856 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ16-23 */
857};
858
859static const struct uniphier_pinctrl_group ph1_ld6b_groups[] = {
860 UNIPHIER_PINCTRL_GROUP(adinter),
861 UNIPHIER_PINCTRL_GROUP(emmc),
862 UNIPHIER_PINCTRL_GROUP(emmc_dat8),
863 UNIPHIER_PINCTRL_GROUP(i2c0),
864 UNIPHIER_PINCTRL_GROUP(i2c1),
865 UNIPHIER_PINCTRL_GROUP(i2c2),
866 UNIPHIER_PINCTRL_GROUP(i2c3),
867 UNIPHIER_PINCTRL_GROUP(nand),
868 UNIPHIER_PINCTRL_GROUP(nand_cs1),
869 UNIPHIER_PINCTRL_GROUP(uart0),
870 UNIPHIER_PINCTRL_GROUP(uart0b),
871 UNIPHIER_PINCTRL_GROUP(uart1),
872 UNIPHIER_PINCTRL_GROUP(uart1b),
873 UNIPHIER_PINCTRL_GROUP(uart2),
874 UNIPHIER_PINCTRL_GROUP(uart2b),
875 UNIPHIER_PINCTRL_GROUP(usb0),
876 UNIPHIER_PINCTRL_GROUP(usb1),
877 UNIPHIER_PINCTRL_GROUP(usb2),
878 UNIPHIER_PINCTRL_GROUP(usb3),
879 UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0),
880 UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1),
881 UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq),
882 UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0),
883 UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1),
884 UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2),
885 UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3),
886 UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4),
887 UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5),
888 UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6),
889 UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7),
890 UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8),
891 UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9),
892 UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10),
893 UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11),
894 UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12),
895 UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13),
896 UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14),
897 UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15),
898 UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16),
899 UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17),
900 UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18),
901 UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19),
902 UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20),
903 UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21),
904 UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22),
905 UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23),
906 UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24),
907 UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25),
908 UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26),
909 UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27),
910 UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28),
911 UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29),
912 UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30),
913 UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31),
914 UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32),
915 UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33),
916 UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34),
917 UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35),
918 UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36),
919 UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37),
920 UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38),
921 UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39),
922 UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40),
923 UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41),
924 UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42),
925 UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43),
926 UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44),
927 UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45),
928 UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46),
929 UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47),
930 UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48),
931 UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49),
932 UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50),
933 UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51),
934 UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52),
935 UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53),
936 UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54),
937 UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55),
938 UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56),
939 UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57),
940 UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58),
941 UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59),
942 UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60),
943 UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61),
944 UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62),
945 UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63),
946 UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64),
947 UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65),
948 UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66),
949 UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67),
950 UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68),
951 UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69),
952 UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70),
953 UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71),
954 UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72),
955 UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73),
956 UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74),
957 UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75),
958 UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76),
959 UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77),
960 UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78),
961 UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79),
962 UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80),
963 UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81),
964 UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82),
965 UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83),
966 UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84),
967 UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85),
968 UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86),
969 UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87),
970 UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range1, 0),
971 UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range1, 1),
972 UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range1, 2),
973 UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range1, 3),
974 UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range1, 4),
975 UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range1, 5),
976 UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range1, 6),
977 UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range1, 7),
978 UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range1, 8),
979 UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range1, 9),
980 UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range1, 10),
981 UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range1, 11),
982 UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range1, 12),
983 UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range1, 13),
984 UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range1, 14),
985 UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range1, 15),
986 UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range1, 16),
987 UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range1, 17),
988 UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range1, 18),
989 UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range1, 19),
990 UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range1, 20),
991 UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range1, 21),
992 UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range1, 22),
993 UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range1, 23),
994 UNIPHIER_PINCTRL_GROUP_SINGLE(port150, port_range1, 24),
995 UNIPHIER_PINCTRL_GROUP_SINGLE(port151, port_range1, 25),
996 UNIPHIER_PINCTRL_GROUP_SINGLE(port152, port_range1, 26),
997 UNIPHIER_PINCTRL_GROUP_SINGLE(port153, port_range1, 27),
998 UNIPHIER_PINCTRL_GROUP_SINGLE(port154, port_range1, 28),
999 UNIPHIER_PINCTRL_GROUP_SINGLE(port155, port_range1, 29),
1000 UNIPHIER_PINCTRL_GROUP_SINGLE(port156, port_range1, 30),
1001 UNIPHIER_PINCTRL_GROUP_SINGLE(port157, port_range1, 31),
1002 UNIPHIER_PINCTRL_GROUP_SINGLE(port160, port_range1, 32),
1003 UNIPHIER_PINCTRL_GROUP_SINGLE(port161, port_range1, 33),
1004 UNIPHIER_PINCTRL_GROUP_SINGLE(port162, port_range1, 34),
1005 UNIPHIER_PINCTRL_GROUP_SINGLE(port163, port_range1, 35),
1006 UNIPHIER_PINCTRL_GROUP_SINGLE(port164, port_range1, 36),
1007 UNIPHIER_PINCTRL_GROUP_SINGLE(port165, port_range1, 37),
1008 UNIPHIER_PINCTRL_GROUP_SINGLE(port166, port_range1, 38),
1009 UNIPHIER_PINCTRL_GROUP_SINGLE(port167, port_range1, 39),
1010 UNIPHIER_PINCTRL_GROUP_SINGLE(port170, port_range1, 40),
1011 UNIPHIER_PINCTRL_GROUP_SINGLE(port171, port_range1, 41),
1012 UNIPHIER_PINCTRL_GROUP_SINGLE(port172, port_range1, 42),
1013 UNIPHIER_PINCTRL_GROUP_SINGLE(port173, port_range1, 43),
1014 UNIPHIER_PINCTRL_GROUP_SINGLE(port174, port_range1, 44),
1015 UNIPHIER_PINCTRL_GROUP_SINGLE(port175, port_range1, 45),
1016 UNIPHIER_PINCTRL_GROUP_SINGLE(port176, port_range1, 46),
1017 UNIPHIER_PINCTRL_GROUP_SINGLE(port177, port_range1, 47),
1018 UNIPHIER_PINCTRL_GROUP_SINGLE(port180, port_range1, 48),
1019 UNIPHIER_PINCTRL_GROUP_SINGLE(port181, port_range1, 49),
1020 UNIPHIER_PINCTRL_GROUP_SINGLE(port182, port_range1, 50),
1021 UNIPHIER_PINCTRL_GROUP_SINGLE(port183, port_range1, 51),
1022 UNIPHIER_PINCTRL_GROUP_SINGLE(port184, port_range1, 52),
1023 UNIPHIER_PINCTRL_GROUP_SINGLE(port185, port_range1, 53),
1024 UNIPHIER_PINCTRL_GROUP_SINGLE(port186, port_range1, 54),
1025 UNIPHIER_PINCTRL_GROUP_SINGLE(port187, port_range1, 55),
1026 UNIPHIER_PINCTRL_GROUP_SINGLE(port190, port_range1, 56),
1027 UNIPHIER_PINCTRL_GROUP_SINGLE(port191, port_range1, 57),
1028 UNIPHIER_PINCTRL_GROUP_SINGLE(port192, port_range1, 58),
1029 UNIPHIER_PINCTRL_GROUP_SINGLE(port193, port_range1, 59),
1030 UNIPHIER_PINCTRL_GROUP_SINGLE(port194, port_range1, 60),
1031 UNIPHIER_PINCTRL_GROUP_SINGLE(port195, port_range1, 61),
1032 UNIPHIER_PINCTRL_GROUP_SINGLE(port196, port_range1, 62),
1033 UNIPHIER_PINCTRL_GROUP_SINGLE(port197, port_range1, 63),
1034 UNIPHIER_PINCTRL_GROUP_SINGLE(port200, port_range1, 64),
1035 UNIPHIER_PINCTRL_GROUP_SINGLE(port201, port_range1, 65),
1036 UNIPHIER_PINCTRL_GROUP_SINGLE(port202, port_range1, 66),
1037 UNIPHIER_PINCTRL_GROUP_SINGLE(port203, port_range1, 67),
1038 UNIPHIER_PINCTRL_GROUP_SINGLE(port204, port_range1, 68),
1039 UNIPHIER_PINCTRL_GROUP_SINGLE(port205, port_range1, 69),
1040 UNIPHIER_PINCTRL_GROUP_SINGLE(port206, port_range1, 70),
1041 UNIPHIER_PINCTRL_GROUP_SINGLE(port207, port_range1, 71),
1042 UNIPHIER_PINCTRL_GROUP_SINGLE(port210, port_range1, 72),
1043 UNIPHIER_PINCTRL_GROUP_SINGLE(port211, port_range1, 73),
1044 UNIPHIER_PINCTRL_GROUP_SINGLE(port212, port_range1, 74),
1045 UNIPHIER_PINCTRL_GROUP_SINGLE(port213, port_range1, 75),
1046 UNIPHIER_PINCTRL_GROUP_SINGLE(port214, port_range1, 76),
1047 UNIPHIER_PINCTRL_GROUP_SINGLE(port215, port_range1, 77),
1048 UNIPHIER_PINCTRL_GROUP_SINGLE(port216, port_range1, 78),
1049 UNIPHIER_PINCTRL_GROUP_SINGLE(port217, port_range1, 79),
1050 UNIPHIER_PINCTRL_GROUP_SINGLE(port220, port_range1, 80),
1051 UNIPHIER_PINCTRL_GROUP_SINGLE(port221, port_range1, 81),
1052 UNIPHIER_PINCTRL_GROUP_SINGLE(port222, port_range1, 82),
1053 UNIPHIER_PINCTRL_GROUP_SINGLE(port223, port_range1, 83),
1054 UNIPHIER_PINCTRL_GROUP_SINGLE(port224, port_range1, 84),
1055 UNIPHIER_PINCTRL_GROUP_SINGLE(port225, port_range1, 85),
1056 UNIPHIER_PINCTRL_GROUP_SINGLE(port226, port_range1, 86),
1057 UNIPHIER_PINCTRL_GROUP_SINGLE(port227, port_range1, 87),
1058 UNIPHIER_PINCTRL_GROUP_SINGLE(port230, port_range1, 88),
1059 UNIPHIER_PINCTRL_GROUP_SINGLE(port231, port_range1, 89),
1060 UNIPHIER_PINCTRL_GROUP_SINGLE(port232, port_range1, 90),
1061 UNIPHIER_PINCTRL_GROUP_SINGLE(port233, port_range1, 91),
1062 UNIPHIER_PINCTRL_GROUP_SINGLE(port234, port_range1, 92),
1063 UNIPHIER_PINCTRL_GROUP_SINGLE(port235, port_range1, 93),
1064 UNIPHIER_PINCTRL_GROUP_SINGLE(port236, port_range1, 94),
1065 UNIPHIER_PINCTRL_GROUP_SINGLE(port237, port_range1, 95),
1066 UNIPHIER_PINCTRL_GROUP_SINGLE(port240, port_range1, 96),
1067 UNIPHIER_PINCTRL_GROUP_SINGLE(port241, port_range1, 97),
1068 UNIPHIER_PINCTRL_GROUP_SINGLE(port242, port_range1, 98),
1069 UNIPHIER_PINCTRL_GROUP_SINGLE(port243, port_range1, 99),
1070 UNIPHIER_PINCTRL_GROUP_SINGLE(port244, port_range1, 100),
1071 UNIPHIER_PINCTRL_GROUP_SINGLE(port245, port_range1, 101),
1072 UNIPHIER_PINCTRL_GROUP_SINGLE(port246, port_range1, 102),
1073 UNIPHIER_PINCTRL_GROUP_SINGLE(port247, port_range1, 103),
1074 UNIPHIER_PINCTRL_GROUP_SINGLE(port250, port_range1, 104),
1075 UNIPHIER_PINCTRL_GROUP_SINGLE(port251, port_range1, 105),
1076 UNIPHIER_PINCTRL_GROUP_SINGLE(port252, port_range1, 106),
1077 UNIPHIER_PINCTRL_GROUP_SINGLE(port253, port_range1, 107),
1078 UNIPHIER_PINCTRL_GROUP_SINGLE(port254, port_range1, 108),
1079 UNIPHIER_PINCTRL_GROUP_SINGLE(port255, port_range1, 109),
1080 UNIPHIER_PINCTRL_GROUP_SINGLE(port256, port_range1, 110),
1081 UNIPHIER_PINCTRL_GROUP_SINGLE(port257, port_range1, 111),
1082 UNIPHIER_PINCTRL_GROUP_SINGLE(port260, port_range1, 112),
1083 UNIPHIER_PINCTRL_GROUP_SINGLE(port261, port_range1, 113),
1084 UNIPHIER_PINCTRL_GROUP_SINGLE(port262, port_range1, 114),
1085 UNIPHIER_PINCTRL_GROUP_SINGLE(port263, port_range1, 115),
1086 UNIPHIER_PINCTRL_GROUP_SINGLE(port264, port_range1, 116),
1087 UNIPHIER_PINCTRL_GROUP_SINGLE(port265, port_range1, 117),
1088 UNIPHIER_PINCTRL_GROUP_SINGLE(port266, port_range1, 118),
1089 UNIPHIER_PINCTRL_GROUP_SINGLE(port267, port_range1, 119),
1090 UNIPHIER_PINCTRL_GROUP_SINGLE(port270, port_range1, 120),
1091 UNIPHIER_PINCTRL_GROUP_SINGLE(port271, port_range1, 121),
1092 UNIPHIER_PINCTRL_GROUP_SINGLE(port272, port_range1, 122),
1093 UNIPHIER_PINCTRL_GROUP_SINGLE(port273, port_range1, 123),
1094 UNIPHIER_PINCTRL_GROUP_SINGLE(port274, port_range1, 124),
1095 UNIPHIER_PINCTRL_GROUP_SINGLE(port275, port_range1, 125),
1096 UNIPHIER_PINCTRL_GROUP_SINGLE(port276, port_range1, 126),
1097 UNIPHIER_PINCTRL_GROUP_SINGLE(port277, port_range1, 127),
1098 UNIPHIER_PINCTRL_GROUP_SINGLE(port280, port_range1, 128),
1099 UNIPHIER_PINCTRL_GROUP_SINGLE(port281, port_range1, 129),
1100 UNIPHIER_PINCTRL_GROUP_SINGLE(port282, port_range1, 130),
1101 UNIPHIER_PINCTRL_GROUP_SINGLE(port283, port_range1, 131),
1102 UNIPHIER_PINCTRL_GROUP_SINGLE(port284, port_range1, 132),
1103 UNIPHIER_PINCTRL_GROUP_SINGLE(port285, port_range1, 133),
1104 UNIPHIER_PINCTRL_GROUP_SINGLE(port286, port_range1, 134),
1105 UNIPHIER_PINCTRL_GROUP_SINGLE(port287, port_range1, 135),
1106 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq, 0),
1107 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq, 1),
1108 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq, 2),
1109 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq, 3),
1110 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq, 4),
1111 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq, 5),
1112 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq, 6),
1113 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq, 7),
1114 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq, 8),
1115 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq, 9),
1116 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq, 10),
1117 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq, 11),
1118 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq, 12),
1119 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq13, xirq, 13),
1120 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq, 14),
1121 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq, 15),
1122 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16, xirq, 16),
1123 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17, xirq, 17),
1124 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18, xirq, 18),
1125 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19, xirq, 19),
1126 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20, xirq, 20),
1127 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq21, xirq, 21),
1128 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq22, xirq, 22),
1129 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq23, xirq, 23),
1130};
1131
1132static const char * const adinter_groups[] = {"adinter"};
1133static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
1134static const char * const i2c0_groups[] = {"i2c0"};
1135static const char * const i2c1_groups[] = {"i2c1"};
1136static const char * const i2c2_groups[] = {"i2c2"};
1137static const char * const i2c3_groups[] = {"i2c3"};
1138static const char * const nand_groups[] = {"nand", "nand_cs1"};
1139static const char * const uart0_groups[] = {"uart0", "uart0b"};
1140static const char * const uart1_groups[] = {"uart1", "uart1b"};
1141static const char * const uart2_groups[] = {"uart2", "uart2b"};
1142static const char * const usb0_groups[] = {"usb0"};
1143static const char * const usb1_groups[] = {"usb1"};
1144static const char * const usb2_groups[] = {"usb2"};
1145static const char * const usb3_groups[] = {"usb3"};
1146static const char * const port_groups[] = {
1147 "port00", "port01", "port02", "port03",
1148 "port04", "port05", "port06", "port07",
1149 "port10", "port11", "port12", "port13",
1150 "port14", "port15", "port16", "port17",
1151 "port20", "port21", "port22", "port23",
1152 "port24", "port25", "port26", "port27",
1153 "port30", "port31", "port32", "port33",
1154 "port34", "port35", "port36", "port37",
1155 "port40", "port41", "port42", "port43",
1156 "port44", "port45", "port46", "port47",
1157 "port50", "port51", "port52", "port53",
1158 "port54", "port55", "port56", "port57",
1159 "port60", "port61", "port62", "port63",
1160 "port64", "port65", "port66", "port67",
1161 "port70", "port71", "port72", "port73",
1162 "port74", "port75", "port76", "port77",
1163 "port80", "port81", "port82", "port83",
1164 "port84", "port85", "port86", "port87",
1165 "port90", "port91", "port92", "port93",
1166 "port94", "port95", "port96", "port97",
1167 "port100", "port101", "port102", "port103",
1168 "port104", "port105", "port106", "port107",
1169 /* port110-117 missing */
1170 "port120", "port121", "port122", "port123",
1171 "port124", "port125", "port126", "port127",
1172 "port130", "port131", "port132", "port133",
1173 "port134", "port135", "port136", "port137",
1174 "port140", "port141", "port142", "port143",
1175 "port144", "port145", "port146", "port147",
1176 "port150", "port151", "port152", "port153",
1177 "port154", "port155", "port156", "port157",
1178 "port160", "port161", "port162", "port163",
1179 "port164", "port165", "port166", "port167",
1180 "port170", "port171", "port172", "port173",
1181 "port174", "port175", "port176", "port177",
1182 "port180", "port181", "port182", "port183",
1183 "port184", "port185", "port186", "port187",
1184 "port190", "port191", "port192", "port193",
1185 "port194", "port195", "port196", "port197",
1186 "port200", "port201", "port202", "port203",
1187 "port204", "port205", "port206", "port207",
1188 "port210", "port211", "port212", "port213",
1189 "port214", "port215", "port216", "port217",
1190 "port220", "port221", "port222", "port223",
1191 "port224", "port225", "port226", "port227",
1192 "port230", "port231", "port232", "port233",
1193 "port234", "port235", "port236", "port237",
1194 "port240", "port241", "port242", "port243",
1195 "port244", "port245", "port246", "port247",
1196 "port250", "port251", "port252", "port253",
1197 "port254", "port255", "port256", "port257",
1198 "port260", "port261", "port262", "port263",
1199 "port264", "port265", "port266", "port267",
1200 "port270", "port271", "port272", "port273",
1201 "port274", "port275", "port276", "port277",
1202 "port280", "port281", "port282", "port283",
1203 "port284", "port285", "port286", "port287",
1204};
1205static const char * const xirq_groups[] = {
1206 "xirq0", "xirq1", "xirq2", "xirq3",
1207 "xirq4", "xirq5", "xirq6", "xirq7",
1208 "xirq8", "xirq9", "xirq10", "xirq11",
1209 "xirq12", "xirq13", "xirq14", "xirq15",
1210 "xirq16", "xirq17", "xirq18", "xirq19",
1211 "xirq20", "xirq21", "xirq22", "xirq23",
1212};
1213
1214static const struct uniphier_pinmux_function ph1_ld6b_functions[] = {
1215 UNIPHIER_PINMUX_FUNCTION(adinter), /* Achip-Dchip interconnect */
1216 UNIPHIER_PINMUX_FUNCTION(emmc),
1217 UNIPHIER_PINMUX_FUNCTION(i2c0),
1218 UNIPHIER_PINMUX_FUNCTION(i2c1),
1219 UNIPHIER_PINMUX_FUNCTION(i2c2),
1220 UNIPHIER_PINMUX_FUNCTION(i2c3),
1221 UNIPHIER_PINMUX_FUNCTION(nand),
1222 UNIPHIER_PINMUX_FUNCTION(uart0),
1223 UNIPHIER_PINMUX_FUNCTION(uart1),
1224 UNIPHIER_PINMUX_FUNCTION(uart2),
1225 UNIPHIER_PINMUX_FUNCTION(usb0),
1226 UNIPHIER_PINMUX_FUNCTION(usb1),
1227 UNIPHIER_PINMUX_FUNCTION(usb2),
1228 UNIPHIER_PINMUX_FUNCTION(usb3),
1229 UNIPHIER_PINMUX_FUNCTION(port),
1230 UNIPHIER_PINMUX_FUNCTION(xirq),
1231};
1232
1233static struct uniphier_pinctrl_socdata ph1_ld6b_pindata = {
1234 .groups = ph1_ld6b_groups,
1235 .groups_count = ARRAY_SIZE(ph1_ld6b_groups),
1236 .functions = ph1_ld6b_functions,
1237 .functions_count = ARRAY_SIZE(ph1_ld6b_functions),
1238 .mux_bits = 8,
1239 .reg_stride = 4,
1240 .load_pinctrl = false,
1241};
1242
1243static struct pinctrl_desc ph1_ld6b_pinctrl_desc = {
1244 .name = DRIVER_NAME,
1245 .pins = ph1_ld6b_pins,
1246 .npins = ARRAY_SIZE(ph1_ld6b_pins),
1247 .owner = THIS_MODULE,
1248};
1249
1250static int ph1_ld6b_pinctrl_probe(struct platform_device *pdev)
1251{
1252 return uniphier_pinctrl_probe(pdev, &ph1_ld6b_pinctrl_desc,
1253 &ph1_ld6b_pindata);
1254}
1255
1256static const struct of_device_id ph1_ld6b_pinctrl_match[] = {
1257 { .compatible = "socionext,ph1-ld6b-pinctrl" },
1258 { /* sentinel */ }
1259};
1260MODULE_DEVICE_TABLE(of, ph1_ld6b_pinctrl_match);
1261
1262static struct platform_driver ph1_ld6b_pinctrl_driver = {
1263 .probe = ph1_ld6b_pinctrl_probe,
1264 .remove = uniphier_pinctrl_remove,
1265 .driver = {
1266 .name = DRIVER_NAME,
1267 .of_match_table = ph1_ld6b_pinctrl_match,
1268 },
1269};
1270module_platform_driver(ph1_ld6b_pinctrl_driver);
1271
1272MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
1273MODULE_DESCRIPTION("UniPhier PH1-LD6b pinctrl driver");
1274MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c b/drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c
new file mode 100644
index 000000000000..96921e40da5f
--- /dev/null
+++ b/drivers/pinctrl/uniphier/pinctrl-ph1-pro4.c
@@ -0,0 +1,1554 @@
1/*
2 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program5 is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/pinctrl/pinctrl.h>
18#include <linux/platform_device.h>
19
20#include "pinctrl-uniphier.h"
21
22#define DRIVER_NAME "ph1-pro4-pinctrl"
23
24static const struct pinctrl_pin_desc ph1_pro4_pins[] = {
25 UNIPHIER_PINCTRL_PIN(0, "CK24O", UNIPHIER_PIN_IECTRL_NONE,
26 0, UNIPHIER_PIN_DRV_4_8,
27 0, UNIPHIER_PIN_PULL_DOWN),
28 UNIPHIER_PINCTRL_PIN(1, "VC27A", UNIPHIER_PIN_IECTRL_NONE,
29 1, UNIPHIER_PIN_DRV_4_8,
30 1, UNIPHIER_PIN_PULL_DOWN),
31 UNIPHIER_PINCTRL_PIN(2, "CK27AI", UNIPHIER_PIN_IECTRL_NONE,
32 2, UNIPHIER_PIN_DRV_4_8,
33 2, UNIPHIER_PIN_PULL_DOWN),
34 UNIPHIER_PINCTRL_PIN(3, "CK27AO", UNIPHIER_PIN_IECTRL_NONE,
35 3, UNIPHIER_PIN_DRV_4_8,
36 3, UNIPHIER_PIN_PULL_DOWN),
37 UNIPHIER_PINCTRL_PIN(4, "CKSEL", UNIPHIER_PIN_IECTRL_NONE,
38 4, UNIPHIER_PIN_DRV_4_8,
39 4, UNIPHIER_PIN_PULL_UP),
40 UNIPHIER_PINCTRL_PIN(5, "CK27AV", UNIPHIER_PIN_IECTRL_NONE,
41 5, UNIPHIER_PIN_DRV_4_8,
42 5, UNIPHIER_PIN_PULL_DOWN),
43 UNIPHIER_PINCTRL_PIN(6, "AEXCKA", UNIPHIER_PIN_IECTRL_NONE,
44 6, UNIPHIER_PIN_DRV_4_8,
45 6, UNIPHIER_PIN_PULL_DOWN),
46 UNIPHIER_PINCTRL_PIN(7, "ASEL", UNIPHIER_PIN_IECTRL_NONE,
47 7, UNIPHIER_PIN_DRV_4_8,
48 7, UNIPHIER_PIN_PULL_DOWN),
49 UNIPHIER_PINCTRL_PIN(8, "ARCRESET", UNIPHIER_PIN_IECTRL_NONE,
50 8, UNIPHIER_PIN_DRV_4_8,
51 8, UNIPHIER_PIN_PULL_DOWN),
52 UNIPHIER_PINCTRL_PIN(9, "ARCUNLOCK", UNIPHIER_PIN_IECTRL_NONE,
53 9, UNIPHIER_PIN_DRV_4_8,
54 9, UNIPHIER_PIN_PULL_DOWN),
55 UNIPHIER_PINCTRL_PIN(10, "XSRST", UNIPHIER_PIN_IECTRL_NONE,
56 10, UNIPHIER_PIN_DRV_4_8,
57 10, UNIPHIER_PIN_PULL_DOWN),
58 UNIPHIER_PINCTRL_PIN(11, "XNMIRQ", UNIPHIER_PIN_IECTRL_NONE,
59 11, UNIPHIER_PIN_DRV_4_8,
60 11, UNIPHIER_PIN_PULL_UP),
61 UNIPHIER_PINCTRL_PIN(12, "XSCIRQ", UNIPHIER_PIN_IECTRL_NONE,
62 12, UNIPHIER_PIN_DRV_4_8,
63 12, UNIPHIER_PIN_PULL_UP),
64 UNIPHIER_PINCTRL_PIN(13, "EXTRG", UNIPHIER_PIN_IECTRL_NONE,
65 13, UNIPHIER_PIN_DRV_4_8,
66 13, UNIPHIER_PIN_PULL_DOWN),
67 UNIPHIER_PINCTRL_PIN(14, "TRCCLK", UNIPHIER_PIN_IECTRL_NONE,
68 14, UNIPHIER_PIN_DRV_4_8,
69 14, UNIPHIER_PIN_PULL_DOWN),
70 UNIPHIER_PINCTRL_PIN(15, "TRCCTL", UNIPHIER_PIN_IECTRL_NONE,
71 15, UNIPHIER_PIN_DRV_4_8,
72 15, UNIPHIER_PIN_PULL_DOWN),
73 UNIPHIER_PINCTRL_PIN(16, "TRCD0", UNIPHIER_PIN_IECTRL_NONE,
74 16, UNIPHIER_PIN_DRV_4_8,
75 16, UNIPHIER_PIN_PULL_DOWN),
76 UNIPHIER_PINCTRL_PIN(17, "TRCD1", UNIPHIER_PIN_IECTRL_NONE,
77 17, UNIPHIER_PIN_DRV_4_8,
78 17, UNIPHIER_PIN_PULL_DOWN),
79 UNIPHIER_PINCTRL_PIN(18, "TRCD2", UNIPHIER_PIN_IECTRL_NONE,
80 18, UNIPHIER_PIN_DRV_4_8,
81 18, UNIPHIER_PIN_PULL_DOWN),
82 UNIPHIER_PINCTRL_PIN(19, "TRCD3", UNIPHIER_PIN_IECTRL_NONE,
83 19, UNIPHIER_PIN_DRV_4_8,
84 19, UNIPHIER_PIN_PULL_DOWN),
85 UNIPHIER_PINCTRL_PIN(20, "TRCD4", UNIPHIER_PIN_IECTRL_NONE,
86 20, UNIPHIER_PIN_DRV_4_8,
87 20, UNIPHIER_PIN_PULL_DOWN),
88 UNIPHIER_PINCTRL_PIN(21, "TRCD5", UNIPHIER_PIN_IECTRL_NONE,
89 21, UNIPHIER_PIN_DRV_4_8,
90 21, UNIPHIER_PIN_PULL_DOWN),
91 UNIPHIER_PINCTRL_PIN(22, "TRCD6", UNIPHIER_PIN_IECTRL_NONE,
92 22, UNIPHIER_PIN_DRV_4_8,
93 22, UNIPHIER_PIN_PULL_DOWN),
94 UNIPHIER_PINCTRL_PIN(23, "TRCD7", UNIPHIER_PIN_IECTRL_NONE,
95 23, UNIPHIER_PIN_DRV_4_8,
96 23, UNIPHIER_PIN_PULL_DOWN),
97 UNIPHIER_PINCTRL_PIN(24, "XECS1", UNIPHIER_PIN_IECTRL_NONE,
98 24, UNIPHIER_PIN_DRV_4_8,
99 24, UNIPHIER_PIN_PULL_UP),
100 UNIPHIER_PINCTRL_PIN(25, "ERXW", UNIPHIER_PIN_IECTRL_NONE,
101 25, UNIPHIER_PIN_DRV_4_8,
102 25, UNIPHIER_PIN_PULL_UP),
103 UNIPHIER_PINCTRL_PIN(26, "XERWE0", UNIPHIER_PIN_IECTRL_NONE,
104 26, UNIPHIER_PIN_DRV_4_8,
105 26, UNIPHIER_PIN_PULL_UP),
106 UNIPHIER_PINCTRL_PIN(27, "XERWE1", UNIPHIER_PIN_IECTRL_NONE,
107 27, UNIPHIER_PIN_DRV_4_8,
108 27, UNIPHIER_PIN_PULL_UP),
109 UNIPHIER_PINCTRL_PIN(28, "ES0", UNIPHIER_PIN_IECTRL_NONE,
110 28, UNIPHIER_PIN_DRV_4_8,
111 28, UNIPHIER_PIN_PULL_DOWN),
112 UNIPHIER_PINCTRL_PIN(29, "ES1", UNIPHIER_PIN_IECTRL_NONE,
113 29, UNIPHIER_PIN_DRV_4_8,
114 29, UNIPHIER_PIN_PULL_DOWN),
115 UNIPHIER_PINCTRL_PIN(30, "ES2", UNIPHIER_PIN_IECTRL_NONE,
116 30, UNIPHIER_PIN_DRV_4_8,
117 30, UNIPHIER_PIN_PULL_DOWN),
118 UNIPHIER_PINCTRL_PIN(31, "ED0", UNIPHIER_PIN_IECTRL_NONE,
119 31, UNIPHIER_PIN_DRV_4_8,
120 31, UNIPHIER_PIN_PULL_DOWN),
121 UNIPHIER_PINCTRL_PIN(32, "ED1", UNIPHIER_PIN_IECTRL_NONE,
122 32, UNIPHIER_PIN_DRV_4_8,
123 32, UNIPHIER_PIN_PULL_DOWN),
124 UNIPHIER_PINCTRL_PIN(33, "ED2", UNIPHIER_PIN_IECTRL_NONE,
125 33, UNIPHIER_PIN_DRV_4_8,
126 33, UNIPHIER_PIN_PULL_DOWN),
127 UNIPHIER_PINCTRL_PIN(34, "ED3", UNIPHIER_PIN_IECTRL_NONE,
128 34, UNIPHIER_PIN_DRV_4_8,
129 34, UNIPHIER_PIN_PULL_DOWN),
130 UNIPHIER_PINCTRL_PIN(35, "ED4", UNIPHIER_PIN_IECTRL_NONE,
131 35, UNIPHIER_PIN_DRV_4_8,
132 35, UNIPHIER_PIN_PULL_DOWN),
133 UNIPHIER_PINCTRL_PIN(36, "ED5", UNIPHIER_PIN_IECTRL_NONE,
134 36, UNIPHIER_PIN_DRV_4_8,
135 36, UNIPHIER_PIN_PULL_DOWN),
136 UNIPHIER_PINCTRL_PIN(37, "ED6", UNIPHIER_PIN_IECTRL_NONE,
137 37, UNIPHIER_PIN_DRV_4_8,
138 37, UNIPHIER_PIN_PULL_DOWN),
139 UNIPHIER_PINCTRL_PIN(38, "ED7", UNIPHIER_PIN_IECTRL_NONE,
140 38, UNIPHIER_PIN_DRV_4_8,
141 38, UNIPHIER_PIN_PULL_DOWN),
142 UNIPHIER_PINCTRL_PIN(39, "BOOTSWAP", UNIPHIER_PIN_IECTRL_NONE,
143 39, UNIPHIER_PIN_DRV_NONE,
144 39, UNIPHIER_PIN_PULL_UP),
145 UNIPHIER_PINCTRL_PIN(40, "NFD0", UNIPHIER_PIN_IECTRL_NONE,
146 2, UNIPHIER_PIN_DRV_8_12_16_20,
147 40, UNIPHIER_PIN_PULL_UP),
148 UNIPHIER_PINCTRL_PIN(41, "NFD1", UNIPHIER_PIN_IECTRL_NONE,
149 3, UNIPHIER_PIN_DRV_8_12_16_20,
150 41, UNIPHIER_PIN_PULL_UP),
151 UNIPHIER_PINCTRL_PIN(42, "NFD2", UNIPHIER_PIN_IECTRL_NONE,
152 4, UNIPHIER_PIN_DRV_8_12_16_20,
153 42, UNIPHIER_PIN_PULL_UP),
154 UNIPHIER_PINCTRL_PIN(43, "NFD3", UNIPHIER_PIN_IECTRL_NONE,
155 5, UNIPHIER_PIN_DRV_8_12_16_20,
156 43, UNIPHIER_PIN_PULL_UP),
157 UNIPHIER_PINCTRL_PIN(44, "NFD4", UNIPHIER_PIN_IECTRL_NONE,
158 6, UNIPHIER_PIN_DRV_8_12_16_20,
159 44, UNIPHIER_PIN_PULL_UP),
160 UNIPHIER_PINCTRL_PIN(45, "NFD5", UNIPHIER_PIN_IECTRL_NONE,
161 7, UNIPHIER_PIN_DRV_8_12_16_20,
162 45, UNIPHIER_PIN_PULL_UP),
163 UNIPHIER_PINCTRL_PIN(46, "NFD6", UNIPHIER_PIN_IECTRL_NONE,
164 8, UNIPHIER_PIN_DRV_8_12_16_20,
165 46, UNIPHIER_PIN_PULL_UP),
166 UNIPHIER_PINCTRL_PIN(47, "NFD7", UNIPHIER_PIN_IECTRL_NONE,
167 9, UNIPHIER_PIN_DRV_8_12_16_20,
168 47, UNIPHIER_PIN_PULL_UP),
169 UNIPHIER_PINCTRL_PIN(48, "NFALE", UNIPHIER_PIN_IECTRL_NONE,
170 48, UNIPHIER_PIN_DRV_4_8,
171 48, UNIPHIER_PIN_PULL_DOWN),
172 UNIPHIER_PINCTRL_PIN(49, "NFCLE", UNIPHIER_PIN_IECTRL_NONE,
173 49, UNIPHIER_PIN_DRV_4_8,
174 49, UNIPHIER_PIN_PULL_DOWN),
175 UNIPHIER_PINCTRL_PIN(50, "XNFRE", UNIPHIER_PIN_IECTRL_NONE,
176 50, UNIPHIER_PIN_DRV_4_8,
177 50, UNIPHIER_PIN_PULL_UP),
178 UNIPHIER_PINCTRL_PIN(51, "XNFWE", UNIPHIER_PIN_IECTRL_NONE,
179 0, UNIPHIER_PIN_DRV_8_12_16_20,
180 51, UNIPHIER_PIN_PULL_UP),
181 UNIPHIER_PINCTRL_PIN(52, "XNFWP", UNIPHIER_PIN_IECTRL_NONE,
182 52, UNIPHIER_PIN_DRV_4_8,
183 52, UNIPHIER_PIN_PULL_DOWN),
184 UNIPHIER_PINCTRL_PIN(53, "XNFCE0", UNIPHIER_PIN_IECTRL_NONE,
185 1, UNIPHIER_PIN_DRV_8_12_16_20,
186 53, UNIPHIER_PIN_PULL_UP),
187 UNIPHIER_PINCTRL_PIN(54, "NRYBY0", UNIPHIER_PIN_IECTRL_NONE,
188 54, UNIPHIER_PIN_DRV_4_8,
189 54, UNIPHIER_PIN_PULL_UP),
190 UNIPHIER_PINCTRL_PIN(55, "DMDSCLTST", UNIPHIER_PIN_IECTRL_NONE,
191 -1, UNIPHIER_PIN_DRV_NONE,
192 -1, UNIPHIER_PIN_PULL_NONE),
193 UNIPHIER_PINCTRL_PIN(56, "DMDSDATST", UNIPHIER_PIN_IECTRL_NONE,
194 -1, UNIPHIER_PIN_DRV_FIXED_4,
195 -1, UNIPHIER_PIN_PULL_NONE),
196 UNIPHIER_PINCTRL_PIN(57, "AGCI0", 3,
197 -1, UNIPHIER_PIN_DRV_FIXED_4,
198 55, UNIPHIER_PIN_PULL_DOWN),
199 UNIPHIER_PINCTRL_PIN(58, "DMDSCL0", UNIPHIER_PIN_IECTRL_NONE,
200 -1, UNIPHIER_PIN_DRV_FIXED_4,
201 -1, UNIPHIER_PIN_PULL_NONE),
202 UNIPHIER_PINCTRL_PIN(59, "DMDSDA0", UNIPHIER_PIN_IECTRL_NONE,
203 -1, UNIPHIER_PIN_DRV_FIXED_4,
204 -1, UNIPHIER_PIN_PULL_NONE),
205 UNIPHIER_PINCTRL_PIN(60, "AGCBS0", 5,
206 -1, UNIPHIER_PIN_DRV_FIXED_4,
207 56, UNIPHIER_PIN_PULL_DOWN),
208 UNIPHIER_PINCTRL_PIN(61, "DMDSCL1", UNIPHIER_PIN_IECTRL_NONE,
209 -1, UNIPHIER_PIN_DRV_FIXED_4,
210 -1, UNIPHIER_PIN_PULL_NONE),
211 UNIPHIER_PINCTRL_PIN(62, "DMDSDA1", UNIPHIER_PIN_IECTRL_NONE,
212 -1, UNIPHIER_PIN_DRV_FIXED_4,
213 -1, UNIPHIER_PIN_PULL_NONE),
214 UNIPHIER_PINCTRL_PIN(63, "ANTSHORT", UNIPHIER_PIN_IECTRL_NONE,
215 57, UNIPHIER_PIN_DRV_4_8,
216 57, UNIPHIER_PIN_PULL_UP),
217 UNIPHIER_PINCTRL_PIN(64, "CH0CLK", UNIPHIER_PIN_IECTRL_NONE,
218 58, UNIPHIER_PIN_DRV_4_8,
219 58, UNIPHIER_PIN_PULL_DOWN),
220 UNIPHIER_PINCTRL_PIN(65, "CH0VAL", UNIPHIER_PIN_IECTRL_NONE,
221 59, UNIPHIER_PIN_DRV_4_8,
222 59, UNIPHIER_PIN_PULL_DOWN),
223 UNIPHIER_PINCTRL_PIN(66, "CH0PSYNC", UNIPHIER_PIN_IECTRL_NONE,
224 60, UNIPHIER_PIN_DRV_4_8,
225 60, UNIPHIER_PIN_PULL_DOWN),
226 UNIPHIER_PINCTRL_PIN(67, "CH0DATA", UNIPHIER_PIN_IECTRL_NONE,
227 61, UNIPHIER_PIN_DRV_4_8,
228 61, UNIPHIER_PIN_PULL_DOWN),
229 UNIPHIER_PINCTRL_PIN(68, "CH1CLK", UNIPHIER_PIN_IECTRL_NONE,
230 62, UNIPHIER_PIN_DRV_4_8,
231 62, UNIPHIER_PIN_PULL_DOWN),
232 UNIPHIER_PINCTRL_PIN(69, "CH1VAL", UNIPHIER_PIN_IECTRL_NONE,
233 63, UNIPHIER_PIN_DRV_4_8,
234 63, UNIPHIER_PIN_PULL_DOWN),
235 UNIPHIER_PINCTRL_PIN(70, "CH1PSYNC", UNIPHIER_PIN_IECTRL_NONE,
236 64, UNIPHIER_PIN_DRV_4_8,
237 64, UNIPHIER_PIN_PULL_DOWN),
238 UNIPHIER_PINCTRL_PIN(71, "CH1DATA", UNIPHIER_PIN_IECTRL_NONE,
239 65, UNIPHIER_PIN_DRV_4_8,
240 65, UNIPHIER_PIN_PULL_DOWN),
241 UNIPHIER_PINCTRL_PIN(72, "CH2CLK", UNIPHIER_PIN_IECTRL_NONE,
242 66, UNIPHIER_PIN_DRV_4_8,
243 66, UNIPHIER_PIN_PULL_DOWN),
244 UNIPHIER_PINCTRL_PIN(73, "CH2VAL", UNIPHIER_PIN_IECTRL_NONE,
245 67, UNIPHIER_PIN_DRV_4_8,
246 67, UNIPHIER_PIN_PULL_DOWN),
247 UNIPHIER_PINCTRL_PIN(74, "CH2PSYNC", UNIPHIER_PIN_IECTRL_NONE,
248 68, UNIPHIER_PIN_DRV_4_8,
249 68, UNIPHIER_PIN_PULL_DOWN),
250 UNIPHIER_PINCTRL_PIN(75, "CH2DATA", UNIPHIER_PIN_IECTRL_NONE,
251 69, UNIPHIER_PIN_DRV_4_8,
252 69, UNIPHIER_PIN_PULL_DOWN),
253 UNIPHIER_PINCTRL_PIN(76, "CH3CLK", UNIPHIER_PIN_IECTRL_NONE,
254 70, UNIPHIER_PIN_DRV_4_8,
255 70, UNIPHIER_PIN_PULL_DOWN),
256 UNIPHIER_PINCTRL_PIN(77, "CH3VAL", UNIPHIER_PIN_IECTRL_NONE,
257 71, UNIPHIER_PIN_DRV_4_8,
258 71, UNIPHIER_PIN_PULL_DOWN),
259 UNIPHIER_PINCTRL_PIN(78, "CH3PSYNC", UNIPHIER_PIN_IECTRL_NONE,
260 72, UNIPHIER_PIN_DRV_4_8,
261 72, UNIPHIER_PIN_PULL_DOWN),
262 UNIPHIER_PINCTRL_PIN(79, "CH3DATA", UNIPHIER_PIN_IECTRL_NONE,
263 73, UNIPHIER_PIN_DRV_4_8,
264 73, UNIPHIER_PIN_PULL_DOWN),
265 UNIPHIER_PINCTRL_PIN(80, "CH4CLK", UNIPHIER_PIN_IECTRL_NONE,
266 74, UNIPHIER_PIN_DRV_4_8,
267 74, UNIPHIER_PIN_PULL_DOWN),
268 UNIPHIER_PINCTRL_PIN(81, "CH4VAL", UNIPHIER_PIN_IECTRL_NONE,
269 75, UNIPHIER_PIN_DRV_4_8,
270 75, UNIPHIER_PIN_PULL_DOWN),
271 UNIPHIER_PINCTRL_PIN(82, "CH4PSYNC", UNIPHIER_PIN_IECTRL_NONE,
272 76, UNIPHIER_PIN_DRV_4_8,
273 76, UNIPHIER_PIN_PULL_DOWN),
274 UNIPHIER_PINCTRL_PIN(83, "CH4DATA", UNIPHIER_PIN_IECTRL_NONE,
275 77, UNIPHIER_PIN_DRV_4_8,
276 77, UNIPHIER_PIN_PULL_DOWN),
277 UNIPHIER_PINCTRL_PIN(84, "CH5CLK", UNIPHIER_PIN_IECTRL_NONE,
278 78, UNIPHIER_PIN_DRV_4_8,
279 78, UNIPHIER_PIN_PULL_DOWN),
280 UNIPHIER_PINCTRL_PIN(85, "CH5VAL", UNIPHIER_PIN_IECTRL_NONE,
281 79, UNIPHIER_PIN_DRV_4_8,
282 79, UNIPHIER_PIN_PULL_DOWN),
283 UNIPHIER_PINCTRL_PIN(86, "CH5PSYNC", UNIPHIER_PIN_IECTRL_NONE,
284 80, UNIPHIER_PIN_DRV_4_8,
285 80, UNIPHIER_PIN_PULL_DOWN),
286 UNIPHIER_PINCTRL_PIN(87, "CH5DATA", UNIPHIER_PIN_IECTRL_NONE,
287 81, UNIPHIER_PIN_DRV_4_8,
288 81, UNIPHIER_PIN_PULL_DOWN),
289 UNIPHIER_PINCTRL_PIN(88, "CH6CLK", UNIPHIER_PIN_IECTRL_NONE,
290 82, UNIPHIER_PIN_DRV_4_8,
291 82, UNIPHIER_PIN_PULL_DOWN),
292 UNIPHIER_PINCTRL_PIN(89, "CH6VAL", UNIPHIER_PIN_IECTRL_NONE,
293 83, UNIPHIER_PIN_DRV_4_8,
294 83, UNIPHIER_PIN_PULL_DOWN),
295 UNIPHIER_PINCTRL_PIN(90, "CH6PSYNC", UNIPHIER_PIN_IECTRL_NONE,
296 84, UNIPHIER_PIN_DRV_4_8,
297 84, UNIPHIER_PIN_PULL_DOWN),
298 UNIPHIER_PINCTRL_PIN(91, "CH6DATA", UNIPHIER_PIN_IECTRL_NONE,
299 85, UNIPHIER_PIN_DRV_4_8,
300 85, UNIPHIER_PIN_PULL_DOWN),
301 UNIPHIER_PINCTRL_PIN(92, "CKFEO", UNIPHIER_PIN_IECTRL_NONE,
302 86, UNIPHIER_PIN_DRV_4_8,
303 86, UNIPHIER_PIN_PULL_DOWN),
304 UNIPHIER_PINCTRL_PIN(93, "XFERST", UNIPHIER_PIN_IECTRL_NONE,
305 87, UNIPHIER_PIN_DRV_4_8,
306 87, UNIPHIER_PIN_PULL_DOWN),
307 UNIPHIER_PINCTRL_PIN(94, "P_FE_ON", UNIPHIER_PIN_IECTRL_NONE,
308 88, UNIPHIER_PIN_DRV_4_8,
309 88, UNIPHIER_PIN_PULL_DOWN),
310 UNIPHIER_PINCTRL_PIN(95, "P_TU0_ON", UNIPHIER_PIN_IECTRL_NONE,
311 89, UNIPHIER_PIN_DRV_4_8,
312 89, UNIPHIER_PIN_PULL_DOWN),
313 UNIPHIER_PINCTRL_PIN(96, "XFEIRQ0", UNIPHIER_PIN_IECTRL_NONE,
314 90, UNIPHIER_PIN_DRV_4_8,
315 90, UNIPHIER_PIN_PULL_DOWN),
316 UNIPHIER_PINCTRL_PIN(97, "XFEIRQ1", UNIPHIER_PIN_IECTRL_NONE,
317 91, UNIPHIER_PIN_DRV_4_8,
318 91, UNIPHIER_PIN_PULL_DOWN),
319 UNIPHIER_PINCTRL_PIN(98, "XFEIRQ2", UNIPHIER_PIN_IECTRL_NONE,
320 92, UNIPHIER_PIN_DRV_4_8,
321 92, UNIPHIER_PIN_PULL_DOWN),
322 UNIPHIER_PINCTRL_PIN(99, "XFEIRQ3", UNIPHIER_PIN_IECTRL_NONE,
323 93, UNIPHIER_PIN_DRV_4_8,
324 93, UNIPHIER_PIN_PULL_DOWN),
325 UNIPHIER_PINCTRL_PIN(100, "XFEIRQ4", UNIPHIER_PIN_IECTRL_NONE,
326 94, UNIPHIER_PIN_DRV_4_8,
327 94, UNIPHIER_PIN_PULL_DOWN),
328 UNIPHIER_PINCTRL_PIN(101, "XFEIRQ5", UNIPHIER_PIN_IECTRL_NONE,
329 95, UNIPHIER_PIN_DRV_4_8,
330 95, UNIPHIER_PIN_PULL_DOWN),
331 UNIPHIER_PINCTRL_PIN(102, "XFEIRQ6", UNIPHIER_PIN_IECTRL_NONE,
332 96, UNIPHIER_PIN_DRV_4_8,
333 96, UNIPHIER_PIN_PULL_DOWN),
334 UNIPHIER_PINCTRL_PIN(103, "SMTCLK0", UNIPHIER_PIN_IECTRL_NONE,
335 97, UNIPHIER_PIN_DRV_4_8,
336 97, UNIPHIER_PIN_PULL_DOWN),
337 UNIPHIER_PINCTRL_PIN(104, "SMTRST0", UNIPHIER_PIN_IECTRL_NONE,
338 98, UNIPHIER_PIN_DRV_4_8,
339 98, UNIPHIER_PIN_PULL_DOWN),
340 UNIPHIER_PINCTRL_PIN(105, "SMTCMD0", UNIPHIER_PIN_IECTRL_NONE,
341 99, UNIPHIER_PIN_DRV_4_8,
342 99, UNIPHIER_PIN_PULL_UP),
343 UNIPHIER_PINCTRL_PIN(106, "SMTD0", UNIPHIER_PIN_IECTRL_NONE,
344 100, UNIPHIER_PIN_DRV_4_8,
345 100, UNIPHIER_PIN_PULL_UP),
346 UNIPHIER_PINCTRL_PIN(107, "SMTSEL0", UNIPHIER_PIN_IECTRL_NONE,
347 101, UNIPHIER_PIN_DRV_4_8,
348 101, UNIPHIER_PIN_PULL_DOWN),
349 UNIPHIER_PINCTRL_PIN(108, "SMTDET0", UNIPHIER_PIN_IECTRL_NONE,
350 102, UNIPHIER_PIN_DRV_4_8,
351 102, UNIPHIER_PIN_PULL_UP),
352 UNIPHIER_PINCTRL_PIN(109, "SMTCLK1", UNIPHIER_PIN_IECTRL_NONE,
353 103, UNIPHIER_PIN_DRV_4_8,
354 103, UNIPHIER_PIN_PULL_DOWN),
355 UNIPHIER_PINCTRL_PIN(110, "SMTRST1", UNIPHIER_PIN_IECTRL_NONE,
356 104, UNIPHIER_PIN_DRV_4_8,
357 104, UNIPHIER_PIN_PULL_DOWN),
358 UNIPHIER_PINCTRL_PIN(111, "SMTCMD1", UNIPHIER_PIN_IECTRL_NONE,
359 105, UNIPHIER_PIN_DRV_4_8,
360 105, UNIPHIER_PIN_PULL_UP),
361 UNIPHIER_PINCTRL_PIN(112, "SMTD1", UNIPHIER_PIN_IECTRL_NONE,
362 106, UNIPHIER_PIN_DRV_4_8,
363 106, UNIPHIER_PIN_PULL_UP),
364 UNIPHIER_PINCTRL_PIN(113, "SMTSEL1", UNIPHIER_PIN_IECTRL_NONE,
365 107, UNIPHIER_PIN_DRV_4_8,
366 107, UNIPHIER_PIN_PULL_DOWN),
367 UNIPHIER_PINCTRL_PIN(114, "SMTDET1", UNIPHIER_PIN_IECTRL_NONE,
368 108, UNIPHIER_PIN_DRV_4_8,
369 108, UNIPHIER_PIN_PULL_UP),
370 UNIPHIER_PINCTRL_PIN(115, "XINTM", UNIPHIER_PIN_IECTRL_NONE,
371 109, UNIPHIER_PIN_DRV_4_8,
372 109, UNIPHIER_PIN_PULL_UP),
373 UNIPHIER_PINCTRL_PIN(116, "SCLKM", UNIPHIER_PIN_IECTRL_NONE,
374 110, UNIPHIER_PIN_DRV_4_8,
375 110, UNIPHIER_PIN_PULL_UP),
376 UNIPHIER_PINCTRL_PIN(117, "SBMTP", UNIPHIER_PIN_IECTRL_NONE,
377 111, UNIPHIER_PIN_DRV_4_8,
378 111, UNIPHIER_PIN_PULL_UP),
379 UNIPHIER_PINCTRL_PIN(118, "SBPTM", UNIPHIER_PIN_IECTRL_NONE,
380 112, UNIPHIER_PIN_DRV_4_8,
381 112, UNIPHIER_PIN_PULL_UP),
382 UNIPHIER_PINCTRL_PIN(119, "XMPREQ", UNIPHIER_PIN_IECTRL_NONE,
383 113, UNIPHIER_PIN_DRV_4_8,
384 113, UNIPHIER_PIN_PULL_UP),
385 UNIPHIER_PINCTRL_PIN(120, "XINTP", UNIPHIER_PIN_IECTRL_NONE,
386 114, UNIPHIER_PIN_DRV_4_8,
387 114, UNIPHIER_PIN_PULL_UP),
388 UNIPHIER_PINCTRL_PIN(121, "LPST", UNIPHIER_PIN_IECTRL_NONE,
389 115, UNIPHIER_PIN_DRV_4_8,
390 115, UNIPHIER_PIN_PULL_DOWN),
391 UNIPHIER_PINCTRL_PIN(122, "SDBOOT", UNIPHIER_PIN_IECTRL_NONE,
392 116, UNIPHIER_PIN_DRV_4_8,
393 116, UNIPHIER_PIN_PULL_UP),
394 UNIPHIER_PINCTRL_PIN(123, "BFAIL", UNIPHIER_PIN_IECTRL_NONE,
395 117, UNIPHIER_PIN_DRV_4_8,
396 117, UNIPHIER_PIN_PULL_DOWN),
397 UNIPHIER_PINCTRL_PIN(124, "XFWE", UNIPHIER_PIN_IECTRL_NONE,
398 118, UNIPHIER_PIN_DRV_4_8,
399 118, UNIPHIER_PIN_PULL_UP),
400 UNIPHIER_PINCTRL_PIN(125, "RF_COM_RDY", UNIPHIER_PIN_IECTRL_NONE,
401 119, UNIPHIER_PIN_DRV_4_8,
402 119, UNIPHIER_PIN_PULL_UP),
403 UNIPHIER_PINCTRL_PIN(126, "XDIAG0", UNIPHIER_PIN_IECTRL_NONE,
404 120, UNIPHIER_PIN_DRV_4_8,
405 120, UNIPHIER_PIN_PULL_UP),
406 UNIPHIER_PINCTRL_PIN(127, "RXD0", UNIPHIER_PIN_IECTRL_NONE,
407 121, UNIPHIER_PIN_DRV_4_8,
408 121, UNIPHIER_PIN_PULL_UP),
409 UNIPHIER_PINCTRL_PIN(128, "TXD0", UNIPHIER_PIN_IECTRL_NONE,
410 122, UNIPHIER_PIN_DRV_4_8,
411 122, UNIPHIER_PIN_PULL_UP),
412 UNIPHIER_PINCTRL_PIN(129, "RXD1", UNIPHIER_PIN_IECTRL_NONE,
413 123, UNIPHIER_PIN_DRV_4_8,
414 123, UNIPHIER_PIN_PULL_UP),
415 UNIPHIER_PINCTRL_PIN(130, "TXD1", UNIPHIER_PIN_IECTRL_NONE,
416 124, UNIPHIER_PIN_DRV_4_8,
417 124, UNIPHIER_PIN_PULL_UP),
418 UNIPHIER_PINCTRL_PIN(131, "RXD2", UNIPHIER_PIN_IECTRL_NONE,
419 125, UNIPHIER_PIN_DRV_4_8,
420 125, UNIPHIER_PIN_PULL_UP),
421 UNIPHIER_PINCTRL_PIN(132, "TXD2", UNIPHIER_PIN_IECTRL_NONE,
422 126, UNIPHIER_PIN_DRV_4_8,
423 126, UNIPHIER_PIN_PULL_UP),
424 UNIPHIER_PINCTRL_PIN(133, "SS0CS", UNIPHIER_PIN_IECTRL_NONE,
425 127, UNIPHIER_PIN_DRV_4_8,
426 127, UNIPHIER_PIN_PULL_UP),
427 UNIPHIER_PINCTRL_PIN(134, "SS0CLK", UNIPHIER_PIN_IECTRL_NONE,
428 128, UNIPHIER_PIN_DRV_4_8,
429 128, UNIPHIER_PIN_PULL_UP),
430 UNIPHIER_PINCTRL_PIN(135, "SS0DO", UNIPHIER_PIN_IECTRL_NONE,
431 129, UNIPHIER_PIN_DRV_4_8,
432 129, UNIPHIER_PIN_PULL_UP),
433 UNIPHIER_PINCTRL_PIN(136, "SS0DI", UNIPHIER_PIN_IECTRL_NONE,
434 130, UNIPHIER_PIN_DRV_4_8,
435 130, UNIPHIER_PIN_PULL_UP),
436 UNIPHIER_PINCTRL_PIN(137, "MS0CS0", UNIPHIER_PIN_IECTRL_NONE,
437 131, UNIPHIER_PIN_DRV_4_8,
438 131, UNIPHIER_PIN_PULL_UP),
439 UNIPHIER_PINCTRL_PIN(138, "MS0CLK", UNIPHIER_PIN_IECTRL_NONE,
440 132, UNIPHIER_PIN_DRV_4_8,
441 132, UNIPHIER_PIN_PULL_UP),
442 UNIPHIER_PINCTRL_PIN(139, "MS0DI", UNIPHIER_PIN_IECTRL_NONE,
443 133, UNIPHIER_PIN_DRV_4_8,
444 133, UNIPHIER_PIN_PULL_UP),
445 UNIPHIER_PINCTRL_PIN(140, "MS0DO", UNIPHIER_PIN_IECTRL_NONE,
446 134, UNIPHIER_PIN_DRV_4_8,
447 134, UNIPHIER_PIN_PULL_UP),
448 UNIPHIER_PINCTRL_PIN(141, "XMDMRST", UNIPHIER_PIN_IECTRL_NONE,
449 135, UNIPHIER_PIN_DRV_4_8,
450 135, UNIPHIER_PIN_PULL_DOWN),
451 UNIPHIER_PINCTRL_PIN(142, "SCL0", UNIPHIER_PIN_IECTRL_NONE,
452 -1, UNIPHIER_PIN_DRV_FIXED_4,
453 -1, UNIPHIER_PIN_PULL_NONE),
454 UNIPHIER_PINCTRL_PIN(143, "SDA0", UNIPHIER_PIN_IECTRL_NONE,
455 -1, UNIPHIER_PIN_DRV_FIXED_4,
456 -1, UNIPHIER_PIN_PULL_NONE),
457 UNIPHIER_PINCTRL_PIN(144, "SCL1", UNIPHIER_PIN_IECTRL_NONE,
458 -1, UNIPHIER_PIN_DRV_FIXED_4,
459 -1, UNIPHIER_PIN_PULL_NONE),
460 UNIPHIER_PINCTRL_PIN(145, "SDA1", UNIPHIER_PIN_IECTRL_NONE,
461 -1, UNIPHIER_PIN_DRV_FIXED_4,
462 -1, UNIPHIER_PIN_PULL_NONE),
463 UNIPHIER_PINCTRL_PIN(146, "SCL2", UNIPHIER_PIN_IECTRL_NONE,
464 -1, UNIPHIER_PIN_DRV_FIXED_4,
465 -1, UNIPHIER_PIN_PULL_NONE),
466 UNIPHIER_PINCTRL_PIN(147, "SDA2", UNIPHIER_PIN_IECTRL_NONE,
467 -1, UNIPHIER_PIN_DRV_FIXED_4,
468 -1, UNIPHIER_PIN_PULL_NONE),
469 UNIPHIER_PINCTRL_PIN(148, "SCL3", UNIPHIER_PIN_IECTRL_NONE,
470 -1, UNIPHIER_PIN_DRV_FIXED_4,
471 -1, UNIPHIER_PIN_PULL_NONE),
472 UNIPHIER_PINCTRL_PIN(149, "SDA3", UNIPHIER_PIN_IECTRL_NONE,
473 -1, UNIPHIER_PIN_DRV_FIXED_4,
474 -1, UNIPHIER_PIN_PULL_NONE),
475 UNIPHIER_PINCTRL_PIN(150, "SD0DAT0", UNIPHIER_PIN_IECTRL_NONE,
476 12, UNIPHIER_PIN_DRV_8_12_16_20,
477 136, UNIPHIER_PIN_PULL_UP),
478 UNIPHIER_PINCTRL_PIN(151, "SD0DAT1", UNIPHIER_PIN_IECTRL_NONE,
479 13, UNIPHIER_PIN_DRV_8_12_16_20,
480 137, UNIPHIER_PIN_PULL_UP),
481 UNIPHIER_PINCTRL_PIN(152, "SD0DAT2", UNIPHIER_PIN_IECTRL_NONE,
482 14, UNIPHIER_PIN_DRV_8_12_16_20,
483 138, UNIPHIER_PIN_PULL_UP),
484 UNIPHIER_PINCTRL_PIN(153, "SD0DAT3", UNIPHIER_PIN_IECTRL_NONE,
485 15, UNIPHIER_PIN_DRV_8_12_16_20,
486 139, UNIPHIER_PIN_PULL_UP),
487 UNIPHIER_PINCTRL_PIN(154, "SD0CMD", UNIPHIER_PIN_IECTRL_NONE,
488 11, UNIPHIER_PIN_DRV_8_12_16_20,
489 141, UNIPHIER_PIN_PULL_UP),
490 UNIPHIER_PINCTRL_PIN(155, "SD0CLK", UNIPHIER_PIN_IECTRL_NONE,
491 10, UNIPHIER_PIN_DRV_8_12_16_20,
492 140, UNIPHIER_PIN_PULL_UP),
493 UNIPHIER_PINCTRL_PIN(156, "SD0CD", UNIPHIER_PIN_IECTRL_NONE,
494 142, UNIPHIER_PIN_DRV_4_8,
495 142, UNIPHIER_PIN_PULL_UP),
496 UNIPHIER_PINCTRL_PIN(157, "SD0WP", UNIPHIER_PIN_IECTRL_NONE,
497 143, UNIPHIER_PIN_DRV_4_8,
498 143, UNIPHIER_PIN_PULL_UP),
499 UNIPHIER_PINCTRL_PIN(158, "SD0VTCG", UNIPHIER_PIN_IECTRL_NONE,
500 144, UNIPHIER_PIN_DRV_4_8,
501 144, UNIPHIER_PIN_PULL_UP),
502 UNIPHIER_PINCTRL_PIN(159, "CK25O", UNIPHIER_PIN_IECTRL_NONE,
503 145, UNIPHIER_PIN_DRV_4_8,
504 145, UNIPHIER_PIN_PULL_UP),
505 UNIPHIER_PINCTRL_PIN(160, "RGMII_TXCLK", 6,
506 146, UNIPHIER_PIN_DRV_4_8,
507 146, UNIPHIER_PIN_PULL_DOWN),
508 UNIPHIER_PINCTRL_PIN(161, "RGMII_TXD0", 6,
509 147, UNIPHIER_PIN_DRV_4_8,
510 147, UNIPHIER_PIN_PULL_DOWN),
511 UNIPHIER_PINCTRL_PIN(162, "RGMII_TXD1", 6,
512 148, UNIPHIER_PIN_DRV_4_8,
513 148, UNIPHIER_PIN_PULL_DOWN),
514 UNIPHIER_PINCTRL_PIN(163, "RGMII_TXD2", 6,
515 149, UNIPHIER_PIN_DRV_4_8,
516 149, UNIPHIER_PIN_PULL_DOWN),
517 UNIPHIER_PINCTRL_PIN(164, "RGMII_TXD3", 6,
518 150, UNIPHIER_PIN_DRV_4_8,
519 150, UNIPHIER_PIN_PULL_DOWN),
520 UNIPHIER_PINCTRL_PIN(165, "RGMII_TXCTL", 6,
521 151, UNIPHIER_PIN_DRV_4_8,
522 151, UNIPHIER_PIN_PULL_DOWN),
523 UNIPHIER_PINCTRL_PIN(166, "MII_TXER", UNIPHIER_PIN_IECTRL_NONE,
524 152, UNIPHIER_PIN_DRV_4_8,
525 152, UNIPHIER_PIN_PULL_DOWN),
526 UNIPHIER_PINCTRL_PIN(167, "RGMII_RXCLK", 6,
527 153, UNIPHIER_PIN_DRV_4_8,
528 153, UNIPHIER_PIN_PULL_DOWN),
529 UNIPHIER_PINCTRL_PIN(168, "RGMII_RXD0", 6,
530 154, UNIPHIER_PIN_DRV_4_8,
531 154, UNIPHIER_PIN_PULL_DOWN),
532 UNIPHIER_PINCTRL_PIN(169, "RGMII_RXD1", 6,
533 155, UNIPHIER_PIN_DRV_4_8,
534 155, UNIPHIER_PIN_PULL_DOWN),
535 UNIPHIER_PINCTRL_PIN(170, "RGMII_RXD2", 6,
536 156, UNIPHIER_PIN_DRV_4_8,
537 156, UNIPHIER_PIN_PULL_DOWN),
538 UNIPHIER_PINCTRL_PIN(171, "RGMII_RXD3", 6,
539 157, UNIPHIER_PIN_DRV_4_8,
540 157, UNIPHIER_PIN_PULL_DOWN),
541 UNIPHIER_PINCTRL_PIN(172, "RGMII_RXCTL", 6,
542 158, UNIPHIER_PIN_DRV_4_8,
543 158, UNIPHIER_PIN_PULL_DOWN),
544 UNIPHIER_PINCTRL_PIN(173, "MII_RXER", 6,
545 159, UNIPHIER_PIN_DRV_4_8,
546 159, UNIPHIER_PIN_PULL_DOWN),
547 UNIPHIER_PINCTRL_PIN(174, "MII_CRS", 6,
548 160, UNIPHIER_PIN_DRV_4_8,
549 160, UNIPHIER_PIN_PULL_DOWN),
550 UNIPHIER_PINCTRL_PIN(175, "MII_COL", 6,
551 161, UNIPHIER_PIN_DRV_4_8,
552 161, UNIPHIER_PIN_PULL_DOWN),
553 UNIPHIER_PINCTRL_PIN(176, "MDC", 6,
554 162, UNIPHIER_PIN_DRV_4_8,
555 162, UNIPHIER_PIN_PULL_UP),
556 UNIPHIER_PINCTRL_PIN(177, "MDIO", 6,
557 163, UNIPHIER_PIN_DRV_4_8,
558 163, UNIPHIER_PIN_PULL_UP),
559 UNIPHIER_PINCTRL_PIN(178, "MDIO_INTL", 6,
560 164, UNIPHIER_PIN_DRV_4_8,
561 164, UNIPHIER_PIN_PULL_UP),
562 UNIPHIER_PINCTRL_PIN(179, "XETH_RST", 6,
563 165, UNIPHIER_PIN_DRV_4_8,
564 165, UNIPHIER_PIN_PULL_DOWN),
565 UNIPHIER_PINCTRL_PIN(180, "USB0VBUS", UNIPHIER_PIN_IECTRL_NONE,
566 166, UNIPHIER_PIN_DRV_4_8,
567 166, UNIPHIER_PIN_PULL_DOWN),
568 UNIPHIER_PINCTRL_PIN(181, "USB0OD", UNIPHIER_PIN_IECTRL_NONE,
569 167, UNIPHIER_PIN_DRV_4_8,
570 167, UNIPHIER_PIN_PULL_UP),
571 UNIPHIER_PINCTRL_PIN(182, "USB1VBUS", UNIPHIER_PIN_IECTRL_NONE,
572 168, UNIPHIER_PIN_DRV_4_8,
573 168, UNIPHIER_PIN_PULL_DOWN),
574 UNIPHIER_PINCTRL_PIN(183, "USB1OD", UNIPHIER_PIN_IECTRL_NONE,
575 169, UNIPHIER_PIN_DRV_4_8,
576 169, UNIPHIER_PIN_PULL_UP),
577 UNIPHIER_PINCTRL_PIN(184, "USB2VBUS", UNIPHIER_PIN_IECTRL_NONE,
578 170, UNIPHIER_PIN_DRV_4_8,
579 170, UNIPHIER_PIN_PULL_DOWN),
580 UNIPHIER_PINCTRL_PIN(185, "USB2OD", UNIPHIER_PIN_IECTRL_NONE,
581 171, UNIPHIER_PIN_DRV_4_8,
582 171, UNIPHIER_PIN_PULL_UP),
583 UNIPHIER_PINCTRL_PIN(186, "USB2ID", UNIPHIER_PIN_IECTRL_NONE,
584 172, UNIPHIER_PIN_DRV_4_8,
585 172, UNIPHIER_PIN_PULL_UP),
586 UNIPHIER_PINCTRL_PIN(187, "USB3VBUS", UNIPHIER_PIN_IECTRL_NONE,
587 173, UNIPHIER_PIN_DRV_4_8,
588 173, UNIPHIER_PIN_PULL_DOWN),
589 UNIPHIER_PINCTRL_PIN(188, "USB3OD", UNIPHIER_PIN_IECTRL_NONE,
590 174, UNIPHIER_PIN_DRV_4_8,
591 174, UNIPHIER_PIN_PULL_UP),
592 UNIPHIER_PINCTRL_PIN(189, "LINKCLK", UNIPHIER_PIN_IECTRL_NONE,
593 175, UNIPHIER_PIN_DRV_4_8,
594 175, UNIPHIER_PIN_PULL_DOWN),
595 UNIPHIER_PINCTRL_PIN(190, "LINKREQ", UNIPHIER_PIN_IECTRL_NONE,
596 176, UNIPHIER_PIN_DRV_4_8,
597 176, UNIPHIER_PIN_PULL_DOWN),
598 UNIPHIER_PINCTRL_PIN(191, "LINKCTL0", UNIPHIER_PIN_IECTRL_NONE,
599 177, UNIPHIER_PIN_DRV_4_8,
600 177, UNIPHIER_PIN_PULL_DOWN),
601 UNIPHIER_PINCTRL_PIN(192, "LINKCTL1", UNIPHIER_PIN_IECTRL_NONE,
602 178, UNIPHIER_PIN_DRV_4_8,
603 178, UNIPHIER_PIN_PULL_DOWN),
604 UNIPHIER_PINCTRL_PIN(193, "LINKDT0", UNIPHIER_PIN_IECTRL_NONE,
605 179, UNIPHIER_PIN_DRV_4_8,
606 179, UNIPHIER_PIN_PULL_DOWN),
607 UNIPHIER_PINCTRL_PIN(194, "LINKDT1", UNIPHIER_PIN_IECTRL_NONE,
608 180, UNIPHIER_PIN_DRV_4_8,
609 180, UNIPHIER_PIN_PULL_DOWN),
610 UNIPHIER_PINCTRL_PIN(195, "LINKDT2", UNIPHIER_PIN_IECTRL_NONE,
611 181, UNIPHIER_PIN_DRV_4_8,
612 181, UNIPHIER_PIN_PULL_DOWN),
613 UNIPHIER_PINCTRL_PIN(196, "LINKDT3", UNIPHIER_PIN_IECTRL_NONE,
614 182, UNIPHIER_PIN_DRV_4_8,
615 182, UNIPHIER_PIN_PULL_DOWN),
616 UNIPHIER_PINCTRL_PIN(197, "LINKDT4", UNIPHIER_PIN_IECTRL_NONE,
617 183, UNIPHIER_PIN_DRV_4_8,
618 183, UNIPHIER_PIN_PULL_DOWN),
619 UNIPHIER_PINCTRL_PIN(198, "LINKDT5", UNIPHIER_PIN_IECTRL_NONE,
620 184, UNIPHIER_PIN_DRV_4_8,
621 184, UNIPHIER_PIN_PULL_DOWN),
622 UNIPHIER_PINCTRL_PIN(199, "LINKDT6", UNIPHIER_PIN_IECTRL_NONE,
623 185, UNIPHIER_PIN_DRV_4_8,
624 185, UNIPHIER_PIN_PULL_DOWN),
625 UNIPHIER_PINCTRL_PIN(200, "LINKDT7", UNIPHIER_PIN_IECTRL_NONE,
626 186, UNIPHIER_PIN_DRV_4_8,
627 186, UNIPHIER_PIN_PULL_DOWN),
628 UNIPHIER_PINCTRL_PIN(201, "CKDVO", UNIPHIER_PIN_IECTRL_NONE,
629 187, UNIPHIER_PIN_DRV_4_8,
630 187, UNIPHIER_PIN_PULL_DOWN),
631 UNIPHIER_PINCTRL_PIN(202, "PHY_PD", UNIPHIER_PIN_IECTRL_NONE,
632 188, UNIPHIER_PIN_DRV_4_8,
633 188, UNIPHIER_PIN_PULL_DOWN),
634 UNIPHIER_PINCTRL_PIN(203, "X1394_RST", UNIPHIER_PIN_IECTRL_NONE,
635 189, UNIPHIER_PIN_DRV_4_8,
636 189, UNIPHIER_PIN_PULL_DOWN),
637 UNIPHIER_PINCTRL_PIN(204, "VOUT_MUTE_L", UNIPHIER_PIN_IECTRL_NONE,
638 190, UNIPHIER_PIN_DRV_4_8,
639 190, UNIPHIER_PIN_PULL_DOWN),
640 UNIPHIER_PINCTRL_PIN(205, "CLK54O", UNIPHIER_PIN_IECTRL_NONE,
641 191, UNIPHIER_PIN_DRV_4_8,
642 191, UNIPHIER_PIN_PULL_DOWN),
643 UNIPHIER_PINCTRL_PIN(206, "CLK54I", UNIPHIER_PIN_IECTRL_NONE,
644 192, UNIPHIER_PIN_DRV_NONE,
645 192, UNIPHIER_PIN_PULL_DOWN),
646 UNIPHIER_PINCTRL_PIN(207, "YIN0", UNIPHIER_PIN_IECTRL_NONE,
647 193, UNIPHIER_PIN_DRV_4_8,
648 193, UNIPHIER_PIN_PULL_DOWN),
649 UNIPHIER_PINCTRL_PIN(208, "YIN1", UNIPHIER_PIN_IECTRL_NONE,
650 194, UNIPHIER_PIN_DRV_4_8,
651 194, UNIPHIER_PIN_PULL_DOWN),
652 UNIPHIER_PINCTRL_PIN(209, "YIN2", UNIPHIER_PIN_IECTRL_NONE,
653 195, UNIPHIER_PIN_DRV_4_8,
654 195, UNIPHIER_PIN_PULL_DOWN),
655 UNIPHIER_PINCTRL_PIN(210, "YIN3", UNIPHIER_PIN_IECTRL_NONE,
656 196, UNIPHIER_PIN_DRV_4_8,
657 196, UNIPHIER_PIN_PULL_DOWN),
658 UNIPHIER_PINCTRL_PIN(211, "YIN4", UNIPHIER_PIN_IECTRL_NONE,
659 197, UNIPHIER_PIN_DRV_4_8,
660 197, UNIPHIER_PIN_PULL_DOWN),
661 UNIPHIER_PINCTRL_PIN(212, "YIN5", UNIPHIER_PIN_IECTRL_NONE,
662 198, UNIPHIER_PIN_DRV_4_8,
663 198, UNIPHIER_PIN_PULL_DOWN),
664 UNIPHIER_PINCTRL_PIN(213, "CIN0", UNIPHIER_PIN_IECTRL_NONE,
665 199, UNIPHIER_PIN_DRV_4_8,
666 199, UNIPHIER_PIN_PULL_DOWN),
667 UNIPHIER_PINCTRL_PIN(214, "CIN1", UNIPHIER_PIN_IECTRL_NONE,
668 200, UNIPHIER_PIN_DRV_4_8,
669 200, UNIPHIER_PIN_PULL_DOWN),
670 UNIPHIER_PINCTRL_PIN(215, "CIN2", UNIPHIER_PIN_IECTRL_NONE,
671 201, UNIPHIER_PIN_DRV_4_8,
672 201, UNIPHIER_PIN_PULL_DOWN),
673 UNIPHIER_PINCTRL_PIN(216, "CIN3", UNIPHIER_PIN_IECTRL_NONE,
674 202, UNIPHIER_PIN_DRV_4_8,
675 202, UNIPHIER_PIN_PULL_DOWN),
676 UNIPHIER_PINCTRL_PIN(217, "CIN4", UNIPHIER_PIN_IECTRL_NONE,
677 203, UNIPHIER_PIN_DRV_4_8,
678 203, UNIPHIER_PIN_PULL_DOWN),
679 UNIPHIER_PINCTRL_PIN(218, "CIN5", UNIPHIER_PIN_IECTRL_NONE,
680 204, UNIPHIER_PIN_DRV_4_8,
681 204, UNIPHIER_PIN_PULL_DOWN),
682 UNIPHIER_PINCTRL_PIN(219, "GCP", UNIPHIER_PIN_IECTRL_NONE,
683 205, UNIPHIER_PIN_DRV_4_8,
684 205, UNIPHIER_PIN_PULL_DOWN),
685 UNIPHIER_PINCTRL_PIN(220, "ADFLG", UNIPHIER_PIN_IECTRL_NONE,
686 206, UNIPHIER_PIN_DRV_4_8,
687 206, UNIPHIER_PIN_PULL_DOWN),
688 UNIPHIER_PINCTRL_PIN(221, "CK27AIOF", UNIPHIER_PIN_IECTRL_NONE,
689 207, UNIPHIER_PIN_DRV_4_8,
690 207, UNIPHIER_PIN_PULL_DOWN),
691 UNIPHIER_PINCTRL_PIN(222, "DACOUT", UNIPHIER_PIN_IECTRL_NONE,
692 208, UNIPHIER_PIN_DRV_4_8,
693 208, UNIPHIER_PIN_PULL_DOWN),
694 UNIPHIER_PINCTRL_PIN(223, "DAFLG", UNIPHIER_PIN_IECTRL_NONE,
695 209, UNIPHIER_PIN_DRV_4_8,
696 209, UNIPHIER_PIN_PULL_DOWN),
697 UNIPHIER_PINCTRL_PIN(224, "VBIH", UNIPHIER_PIN_IECTRL_NONE,
698 210, UNIPHIER_PIN_DRV_4_8,
699 210, UNIPHIER_PIN_PULL_DOWN),
700 UNIPHIER_PINCTRL_PIN(225, "VBIL", UNIPHIER_PIN_IECTRL_NONE,
701 211, UNIPHIER_PIN_DRV_4_8,
702 211, UNIPHIER_PIN_PULL_DOWN),
703 UNIPHIER_PINCTRL_PIN(226, "XSUB_RST", UNIPHIER_PIN_IECTRL_NONE,
704 212, UNIPHIER_PIN_DRV_4_8,
705 212, UNIPHIER_PIN_PULL_DOWN),
706 UNIPHIER_PINCTRL_PIN(227, "XADC_PD", UNIPHIER_PIN_IECTRL_NONE,
707 213, UNIPHIER_PIN_DRV_4_8,
708 213, UNIPHIER_PIN_PULL_DOWN),
709 UNIPHIER_PINCTRL_PIN(228, "AI1ADCCK", UNIPHIER_PIN_IECTRL_NONE,
710 214, UNIPHIER_PIN_DRV_4_8,
711 214, UNIPHIER_PIN_PULL_DOWN),
712 UNIPHIER_PINCTRL_PIN(229, "AI1BCK", UNIPHIER_PIN_IECTRL_NONE,
713 215, UNIPHIER_PIN_DRV_4_8,
714 215, UNIPHIER_PIN_PULL_DOWN),
715 UNIPHIER_PINCTRL_PIN(230, "AI1LRCK", UNIPHIER_PIN_IECTRL_NONE,
716 216, UNIPHIER_PIN_DRV_4_8,
717 216, UNIPHIER_PIN_PULL_DOWN),
718 UNIPHIER_PINCTRL_PIN(231, "AI1DMIX", UNIPHIER_PIN_IECTRL_NONE,
719 217, UNIPHIER_PIN_DRV_4_8,
720 217, UNIPHIER_PIN_PULL_DOWN),
721 UNIPHIER_PINCTRL_PIN(232, "CK27HD", UNIPHIER_PIN_IECTRL_NONE,
722 218, UNIPHIER_PIN_DRV_4_8,
723 218, UNIPHIER_PIN_PULL_DOWN),
724 UNIPHIER_PINCTRL_PIN(233, "XHD_RST", UNIPHIER_PIN_IECTRL_NONE,
725 219, UNIPHIER_PIN_DRV_4_8,
726 219, UNIPHIER_PIN_PULL_DOWN),
727 UNIPHIER_PINCTRL_PIN(234, "INTHD", UNIPHIER_PIN_IECTRL_NONE,
728 220, UNIPHIER_PIN_DRV_4_8,
729 220, UNIPHIER_PIN_PULL_UP),
730 UNIPHIER_PINCTRL_PIN(235, "VO1HDCK", UNIPHIER_PIN_IECTRL_NONE,
731 221, UNIPHIER_PIN_DRV_4_8,
732 221, UNIPHIER_PIN_PULL_DOWN),
733 UNIPHIER_PINCTRL_PIN(236, "VO1HSYNC", UNIPHIER_PIN_IECTRL_NONE,
734 222, UNIPHIER_PIN_DRV_4_8,
735 222, UNIPHIER_PIN_PULL_DOWN),
736 UNIPHIER_PINCTRL_PIN(237, "VO1VSYNC", UNIPHIER_PIN_IECTRL_NONE,
737 223, UNIPHIER_PIN_DRV_4_8,
738 223, UNIPHIER_PIN_PULL_DOWN),
739 UNIPHIER_PINCTRL_PIN(238, "VO1DE", UNIPHIER_PIN_IECTRL_NONE,
740 224, UNIPHIER_PIN_DRV_4_8,
741 224, UNIPHIER_PIN_PULL_DOWN),
742 UNIPHIER_PINCTRL_PIN(239, "VO1Y0", UNIPHIER_PIN_IECTRL_NONE,
743 225, UNIPHIER_PIN_DRV_4_8,
744 225, UNIPHIER_PIN_PULL_DOWN),
745 UNIPHIER_PINCTRL_PIN(240, "VO1Y1", UNIPHIER_PIN_IECTRL_NONE,
746 226, UNIPHIER_PIN_DRV_4_8,
747 226, UNIPHIER_PIN_PULL_DOWN),
748 UNIPHIER_PINCTRL_PIN(241, "VO1Y2", UNIPHIER_PIN_IECTRL_NONE,
749 227, UNIPHIER_PIN_DRV_4_8,
750 227, UNIPHIER_PIN_PULL_DOWN),
751 UNIPHIER_PINCTRL_PIN(242, "VO1Y3", UNIPHIER_PIN_IECTRL_NONE,
752 228, UNIPHIER_PIN_DRV_4_8,
753 228, UNIPHIER_PIN_PULL_DOWN),
754 UNIPHIER_PINCTRL_PIN(243, "VO1Y4", UNIPHIER_PIN_IECTRL_NONE,
755 229, UNIPHIER_PIN_DRV_4_8,
756 229, UNIPHIER_PIN_PULL_DOWN),
757 UNIPHIER_PINCTRL_PIN(244, "VO1Y5", UNIPHIER_PIN_IECTRL_NONE,
758 230, UNIPHIER_PIN_DRV_4_8,
759 230, UNIPHIER_PIN_PULL_DOWN),
760 UNIPHIER_PINCTRL_PIN(245, "VO1Y6", UNIPHIER_PIN_IECTRL_NONE,
761 231, UNIPHIER_PIN_DRV_4_8,
762 231, UNIPHIER_PIN_PULL_DOWN),
763 UNIPHIER_PINCTRL_PIN(246, "VO1Y7", UNIPHIER_PIN_IECTRL_NONE,
764 232, UNIPHIER_PIN_DRV_4_8,
765 232, UNIPHIER_PIN_PULL_DOWN),
766 UNIPHIER_PINCTRL_PIN(247, "VO1Y8", UNIPHIER_PIN_IECTRL_NONE,
767 233, UNIPHIER_PIN_DRV_4_8,
768 233, UNIPHIER_PIN_PULL_DOWN),
769 UNIPHIER_PINCTRL_PIN(248, "VO1Y9", UNIPHIER_PIN_IECTRL_NONE,
770 234, UNIPHIER_PIN_DRV_4_8,
771 234, UNIPHIER_PIN_PULL_DOWN),
772 UNIPHIER_PINCTRL_PIN(249, "VO1Y10", UNIPHIER_PIN_IECTRL_NONE,
773 235, UNIPHIER_PIN_DRV_4_8,
774 235, UNIPHIER_PIN_PULL_DOWN),
775 UNIPHIER_PINCTRL_PIN(250, "VO1Y11", UNIPHIER_PIN_IECTRL_NONE,
776 236, UNIPHIER_PIN_DRV_4_8,
777 236, UNIPHIER_PIN_PULL_DOWN),
778 UNIPHIER_PINCTRL_PIN(251, "VO1CB0", UNIPHIER_PIN_IECTRL_NONE,
779 237, UNIPHIER_PIN_DRV_4_8,
780 237, UNIPHIER_PIN_PULL_DOWN),
781 UNIPHIER_PINCTRL_PIN(252, "VO1CB1", UNIPHIER_PIN_IECTRL_NONE,
782 238, UNIPHIER_PIN_DRV_4_8,
783 238, UNIPHIER_PIN_PULL_DOWN),
784 UNIPHIER_PINCTRL_PIN(253, "VO1CB2", UNIPHIER_PIN_IECTRL_NONE,
785 239, UNIPHIER_PIN_DRV_4_8,
786 239, UNIPHIER_PIN_PULL_DOWN),
787 UNIPHIER_PINCTRL_PIN(254, "VO1CB3", UNIPHIER_PIN_IECTRL_NONE,
788 240, UNIPHIER_PIN_DRV_4_8,
789 240, UNIPHIER_PIN_PULL_DOWN),
790 UNIPHIER_PINCTRL_PIN(255, "VO1CB4", UNIPHIER_PIN_IECTRL_NONE,
791 241, UNIPHIER_PIN_DRV_4_8,
792 241, UNIPHIER_PIN_PULL_DOWN),
793 UNIPHIER_PINCTRL_PIN(256, "VO1CB5", UNIPHIER_PIN_IECTRL_NONE,
794 242, UNIPHIER_PIN_DRV_4_8,
795 242, UNIPHIER_PIN_PULL_DOWN),
796 UNIPHIER_PINCTRL_PIN(257, "VO1CB6", UNIPHIER_PIN_IECTRL_NONE,
797 243, UNIPHIER_PIN_DRV_4_8,
798 243, UNIPHIER_PIN_PULL_DOWN),
799 UNIPHIER_PINCTRL_PIN(258, "VO1CB7", UNIPHIER_PIN_IECTRL_NONE,
800 244, UNIPHIER_PIN_DRV_4_8,
801 244, UNIPHIER_PIN_PULL_DOWN),
802 UNIPHIER_PINCTRL_PIN(259, "VO1CB8", UNIPHIER_PIN_IECTRL_NONE,
803 245, UNIPHIER_PIN_DRV_4_8,
804 245, UNIPHIER_PIN_PULL_DOWN),
805 UNIPHIER_PINCTRL_PIN(260, "VO1CB9", UNIPHIER_PIN_IECTRL_NONE,
806 246, UNIPHIER_PIN_DRV_4_8,
807 246, UNIPHIER_PIN_PULL_DOWN),
808 UNIPHIER_PINCTRL_PIN(261, "VO1CB10", UNIPHIER_PIN_IECTRL_NONE,
809 247, UNIPHIER_PIN_DRV_4_8,
810 247, UNIPHIER_PIN_PULL_DOWN),
811 UNIPHIER_PINCTRL_PIN(262, "VO1CB11", UNIPHIER_PIN_IECTRL_NONE,
812 248, UNIPHIER_PIN_DRV_4_8,
813 248, UNIPHIER_PIN_PULL_DOWN),
814 UNIPHIER_PINCTRL_PIN(263, "VO1CR0", UNIPHIER_PIN_IECTRL_NONE,
815 249, UNIPHIER_PIN_DRV_4_8,
816 249, UNIPHIER_PIN_PULL_DOWN),
817 UNIPHIER_PINCTRL_PIN(264, "VO1CR1", UNIPHIER_PIN_IECTRL_NONE,
818 250, UNIPHIER_PIN_DRV_4_8,
819 250, UNIPHIER_PIN_PULL_DOWN),
820 UNIPHIER_PINCTRL_PIN(265, "VO1CR2", UNIPHIER_PIN_IECTRL_NONE,
821 251, UNIPHIER_PIN_DRV_4_8,
822 251, UNIPHIER_PIN_PULL_DOWN),
823 UNIPHIER_PINCTRL_PIN(266, "VO1CR3", UNIPHIER_PIN_IECTRL_NONE,
824 252, UNIPHIER_PIN_DRV_4_8,
825 252, UNIPHIER_PIN_PULL_DOWN),
826 UNIPHIER_PINCTRL_PIN(267, "VO1CR4", UNIPHIER_PIN_IECTRL_NONE,
827 253, UNIPHIER_PIN_DRV_4_8,
828 253, UNIPHIER_PIN_PULL_DOWN),
829 UNIPHIER_PINCTRL_PIN(268, "VO1CR5", UNIPHIER_PIN_IECTRL_NONE,
830 254, UNIPHIER_PIN_DRV_4_8,
831 254, UNIPHIER_PIN_PULL_DOWN),
832 UNIPHIER_PINCTRL_PIN(269, "VO1CR6", UNIPHIER_PIN_IECTRL_NONE,
833 255, UNIPHIER_PIN_DRV_4_8,
834 255, UNIPHIER_PIN_PULL_DOWN),
835 UNIPHIER_PINCTRL_PIN(270, "VO1CR7", UNIPHIER_PIN_IECTRL_NONE,
836 256, UNIPHIER_PIN_DRV_4_8,
837 256, UNIPHIER_PIN_PULL_DOWN),
838 UNIPHIER_PINCTRL_PIN(271, "VO1CR8", UNIPHIER_PIN_IECTRL_NONE,
839 257, UNIPHIER_PIN_DRV_4_8,
840 257, UNIPHIER_PIN_PULL_DOWN),
841 UNIPHIER_PINCTRL_PIN(272, "VO1CR9", UNIPHIER_PIN_IECTRL_NONE,
842 258, UNIPHIER_PIN_DRV_4_8,
843 258, UNIPHIER_PIN_PULL_DOWN),
844 UNIPHIER_PINCTRL_PIN(273, "VO1CR10", UNIPHIER_PIN_IECTRL_NONE,
845 259, UNIPHIER_PIN_DRV_4_8,
846 259, UNIPHIER_PIN_PULL_DOWN),
847 UNIPHIER_PINCTRL_PIN(274, "VO1CR11", UNIPHIER_PIN_IECTRL_NONE,
848 260, UNIPHIER_PIN_DRV_4_8,
849 260, UNIPHIER_PIN_PULL_DOWN),
850 UNIPHIER_PINCTRL_PIN(275, "VO1EX0", UNIPHIER_PIN_IECTRL_NONE,
851 261, UNIPHIER_PIN_DRV_4_8,
852 261, UNIPHIER_PIN_PULL_DOWN),
853 UNIPHIER_PINCTRL_PIN(276, "VO1EX1", UNIPHIER_PIN_IECTRL_NONE,
854 262, UNIPHIER_PIN_DRV_4_8,
855 262, UNIPHIER_PIN_PULL_DOWN),
856 UNIPHIER_PINCTRL_PIN(277, "VO1EX2", UNIPHIER_PIN_IECTRL_NONE,
857 263, UNIPHIER_PIN_DRV_4_8,
858 263, UNIPHIER_PIN_PULL_DOWN),
859 UNIPHIER_PINCTRL_PIN(278, "VO1EX3", UNIPHIER_PIN_IECTRL_NONE,
860 264, UNIPHIER_PIN_DRV_4_8,
861 264, UNIPHIER_PIN_PULL_DOWN),
862 UNIPHIER_PINCTRL_PIN(279, "VEXCKA", UNIPHIER_PIN_IECTRL_NONE,
863 265, UNIPHIER_PIN_DRV_4_8,
864 265, UNIPHIER_PIN_PULL_DOWN),
865 UNIPHIER_PINCTRL_PIN(280, "VSEL0", UNIPHIER_PIN_IECTRL_NONE,
866 266, UNIPHIER_PIN_DRV_4_8,
867 266, UNIPHIER_PIN_PULL_DOWN),
868 UNIPHIER_PINCTRL_PIN(281, "VSEL1", UNIPHIER_PIN_IECTRL_NONE,
869 267, UNIPHIER_PIN_DRV_4_8,
870 267, UNIPHIER_PIN_PULL_DOWN),
871 UNIPHIER_PINCTRL_PIN(282, "AO1DACCK", UNIPHIER_PIN_IECTRL_NONE,
872 268, UNIPHIER_PIN_DRV_4_8,
873 268, UNIPHIER_PIN_PULL_DOWN),
874 UNIPHIER_PINCTRL_PIN(283, "AO1BCK", UNIPHIER_PIN_IECTRL_NONE,
875 269, UNIPHIER_PIN_DRV_4_8,
876 269, UNIPHIER_PIN_PULL_DOWN),
877 UNIPHIER_PINCTRL_PIN(284, "AO1LRCK", UNIPHIER_PIN_IECTRL_NONE,
878 270, UNIPHIER_PIN_DRV_4_8,
879 270, UNIPHIER_PIN_PULL_DOWN),
880 UNIPHIER_PINCTRL_PIN(285, "AO1D0", UNIPHIER_PIN_IECTRL_NONE,
881 271, UNIPHIER_PIN_DRV_4_8,
882 271, UNIPHIER_PIN_PULL_DOWN),
883 UNIPHIER_PINCTRL_PIN(286, "AO1D1", UNIPHIER_PIN_IECTRL_NONE,
884 272, UNIPHIER_PIN_DRV_4_8,
885 272, UNIPHIER_PIN_PULL_DOWN),
886 UNIPHIER_PINCTRL_PIN(287, "AO1D2", UNIPHIER_PIN_IECTRL_NONE,
887 273, UNIPHIER_PIN_DRV_4_8,
888 273, UNIPHIER_PIN_PULL_DOWN),
889 UNIPHIER_PINCTRL_PIN(288, "AO1D3", UNIPHIER_PIN_IECTRL_NONE,
890 274, UNIPHIER_PIN_DRV_4_8,
891 274, UNIPHIER_PIN_PULL_DOWN),
892 UNIPHIER_PINCTRL_PIN(289, "AO1IEC", UNIPHIER_PIN_IECTRL_NONE,
893 275, UNIPHIER_PIN_DRV_4_8,
894 275, UNIPHIER_PIN_PULL_DOWN),
895 UNIPHIER_PINCTRL_PIN(290, "XDAC_PD", UNIPHIER_PIN_IECTRL_NONE,
896 276, UNIPHIER_PIN_DRV_4_8,
897 276, UNIPHIER_PIN_PULL_DOWN),
898 UNIPHIER_PINCTRL_PIN(291, "EX_A_MUTE", UNIPHIER_PIN_IECTRL_NONE,
899 277, UNIPHIER_PIN_DRV_4_8,
900 277, UNIPHIER_PIN_PULL_UP),
901 UNIPHIER_PINCTRL_PIN(292, "AO2DACCK", UNIPHIER_PIN_IECTRL_NONE,
902 278, UNIPHIER_PIN_DRV_4_8,
903 278, UNIPHIER_PIN_PULL_DOWN),
904 UNIPHIER_PINCTRL_PIN(293, "AO2BCK", UNIPHIER_PIN_IECTRL_NONE,
905 279, UNIPHIER_PIN_DRV_4_8,
906 279, UNIPHIER_PIN_PULL_DOWN),
907 UNIPHIER_PINCTRL_PIN(294, "AO2LRCK", UNIPHIER_PIN_IECTRL_NONE,
908 280, UNIPHIER_PIN_DRV_4_8,
909 280, UNIPHIER_PIN_PULL_DOWN),
910 UNIPHIER_PINCTRL_PIN(295, "AO2DMIX", UNIPHIER_PIN_IECTRL_NONE,
911 281, UNIPHIER_PIN_DRV_4_8,
912 281, UNIPHIER_PIN_PULL_DOWN),
913 UNIPHIER_PINCTRL_PIN(296, "AO2IEC", UNIPHIER_PIN_IECTRL_NONE,
914 282, UNIPHIER_PIN_DRV_4_8,
915 282, UNIPHIER_PIN_PULL_DOWN),
916 UNIPHIER_PINCTRL_PIN(297, "HTHPD", UNIPHIER_PIN_IECTRL_NONE,
917 -1, UNIPHIER_PIN_DRV_FIXED_5,
918 -1, UNIPHIER_PIN_PULL_NONE),
919 UNIPHIER_PINCTRL_PIN(298, "HTSCL", UNIPHIER_PIN_IECTRL_NONE,
920 -1, UNIPHIER_PIN_DRV_FIXED_5,
921 -1, UNIPHIER_PIN_PULL_NONE),
922 UNIPHIER_PINCTRL_PIN(299, "HTSDA", UNIPHIER_PIN_IECTRL_NONE,
923 -1, UNIPHIER_PIN_DRV_FIXED_5,
924 -1, UNIPHIER_PIN_PULL_NONE),
925 UNIPHIER_PINCTRL_PIN(300, "PORT00", UNIPHIER_PIN_IECTRL_NONE,
926 284, UNIPHIER_PIN_DRV_4_8,
927 284, UNIPHIER_PIN_PULL_DOWN),
928 UNIPHIER_PINCTRL_PIN(301, "PORT01", UNIPHIER_PIN_IECTRL_NONE,
929 285, UNIPHIER_PIN_DRV_4_8,
930 285, UNIPHIER_PIN_PULL_DOWN),
931 UNIPHIER_PINCTRL_PIN(302, "PORT02", UNIPHIER_PIN_IECTRL_NONE,
932 286, UNIPHIER_PIN_DRV_4_8,
933 286, UNIPHIER_PIN_PULL_DOWN),
934 UNIPHIER_PINCTRL_PIN(303, "PORT03", UNIPHIER_PIN_IECTRL_NONE,
935 287, UNIPHIER_PIN_DRV_4_8,
936 287, UNIPHIER_PIN_PULL_DOWN),
937 UNIPHIER_PINCTRL_PIN(304, "PORT04", UNIPHIER_PIN_IECTRL_NONE,
938 288, UNIPHIER_PIN_DRV_4_8,
939 288, UNIPHIER_PIN_PULL_DOWN),
940 UNIPHIER_PINCTRL_PIN(305, "PORT05", UNIPHIER_PIN_IECTRL_NONE,
941 289, UNIPHIER_PIN_DRV_4_8,
942 289, UNIPHIER_PIN_PULL_DOWN),
943 UNIPHIER_PINCTRL_PIN(306, "PORT06", UNIPHIER_PIN_IECTRL_NONE,
944 290, UNIPHIER_PIN_DRV_4_8,
945 290, UNIPHIER_PIN_PULL_DOWN),
946 UNIPHIER_PINCTRL_PIN(307, "PORT07", UNIPHIER_PIN_IECTRL_NONE,
947 291, UNIPHIER_PIN_DRV_4_8,
948 291, UNIPHIER_PIN_PULL_DOWN),
949 UNIPHIER_PINCTRL_PIN(308, "PORT10", UNIPHIER_PIN_IECTRL_NONE,
950 292, UNIPHIER_PIN_DRV_4_8,
951 292, UNIPHIER_PIN_PULL_DOWN),
952 UNIPHIER_PINCTRL_PIN(309, "PORT11", UNIPHIER_PIN_IECTRL_NONE,
953 293, UNIPHIER_PIN_DRV_4_8,
954 293, UNIPHIER_PIN_PULL_DOWN),
955 UNIPHIER_PINCTRL_PIN(310, "PORT12", UNIPHIER_PIN_IECTRL_NONE,
956 294, UNIPHIER_PIN_DRV_4_8,
957 294, UNIPHIER_PIN_PULL_DOWN),
958 UNIPHIER_PINCTRL_PIN(311, "PORT13", UNIPHIER_PIN_IECTRL_NONE,
959 295, UNIPHIER_PIN_DRV_4_8,
960 295, UNIPHIER_PIN_PULL_DOWN),
961 UNIPHIER_PINCTRL_PIN(312, "PORT14", UNIPHIER_PIN_IECTRL_NONE,
962 296, UNIPHIER_PIN_DRV_4_8,
963 296, UNIPHIER_PIN_PULL_DOWN),
964 UNIPHIER_PINCTRL_PIN(313, "PORT15", UNIPHIER_PIN_IECTRL_NONE,
965 297, UNIPHIER_PIN_DRV_4_8,
966 297, UNIPHIER_PIN_PULL_DOWN),
967 UNIPHIER_PINCTRL_PIN(314, "PORT16", UNIPHIER_PIN_IECTRL_NONE,
968 298, UNIPHIER_PIN_DRV_4_8,
969 298, UNIPHIER_PIN_PULL_DOWN),
970 UNIPHIER_PINCTRL_PIN(315, "PORT17", UNIPHIER_PIN_IECTRL_NONE,
971 299, UNIPHIER_PIN_DRV_4_8,
972 299, UNIPHIER_PIN_PULL_DOWN),
973 UNIPHIER_PINCTRL_PIN(316, "PORT20", UNIPHIER_PIN_IECTRL_NONE,
974 300, UNIPHIER_PIN_DRV_4_8,
975 300, UNIPHIER_PIN_PULL_DOWN),
976 UNIPHIER_PINCTRL_PIN(317, "PORT21", UNIPHIER_PIN_IECTRL_NONE,
977 301, UNIPHIER_PIN_DRV_4_8,
978 301, UNIPHIER_PIN_PULL_DOWN),
979 UNIPHIER_PINCTRL_PIN(318, "PORT22", UNIPHIER_PIN_IECTRL_NONE,
980 302, UNIPHIER_PIN_DRV_4_8,
981 302, UNIPHIER_PIN_PULL_UP),
982 UNIPHIER_PINCTRL_PIN(319, "SD1DAT0", UNIPHIER_PIN_IECTRL_NONE,
983 303, UNIPHIER_PIN_DRV_4_8,
984 303, UNIPHIER_PIN_PULL_UP),
985 UNIPHIER_PINCTRL_PIN(320, "SD1DAT1", UNIPHIER_PIN_IECTRL_NONE,
986 304, UNIPHIER_PIN_DRV_4_8,
987 304, UNIPHIER_PIN_PULL_UP),
988 UNIPHIER_PINCTRL_PIN(321, "SD1DAT2", UNIPHIER_PIN_IECTRL_NONE,
989 305, UNIPHIER_PIN_DRV_4_8,
990 305, UNIPHIER_PIN_PULL_UP),
991 UNIPHIER_PINCTRL_PIN(322, "SD1DAT3", UNIPHIER_PIN_IECTRL_NONE,
992 306, UNIPHIER_PIN_DRV_4_8,
993 306, UNIPHIER_PIN_PULL_UP),
994 UNIPHIER_PINCTRL_PIN(323, "SD1CMD", UNIPHIER_PIN_IECTRL_NONE,
995 307, UNIPHIER_PIN_DRV_4_8,
996 307, UNIPHIER_PIN_PULL_UP),
997 UNIPHIER_PINCTRL_PIN(324, "SD1CLK", UNIPHIER_PIN_IECTRL_NONE,
998 308, UNIPHIER_PIN_DRV_4_8,
999 308, UNIPHIER_PIN_PULL_UP),
1000 UNIPHIER_PINCTRL_PIN(325, "SD1CD", UNIPHIER_PIN_IECTRL_NONE,
1001 309, UNIPHIER_PIN_DRV_4_8,
1002 309, UNIPHIER_PIN_PULL_UP),
1003 UNIPHIER_PINCTRL_PIN(326, "SD1WP", UNIPHIER_PIN_IECTRL_NONE,
1004 310, UNIPHIER_PIN_DRV_4_8,
1005 310, UNIPHIER_PIN_PULL_UP),
1006 UNIPHIER_PINCTRL_PIN(327, "SD1VTCG", UNIPHIER_PIN_IECTRL_NONE,
1007 311, UNIPHIER_PIN_DRV_4_8,
1008 311, UNIPHIER_PIN_PULL_UP),
1009 UNIPHIER_PINCTRL_PIN(328, "DMDISO", UNIPHIER_PIN_IECTRL_NONE,
1010 312, UNIPHIER_PIN_DRV_NONE,
1011 312, UNIPHIER_PIN_PULL_DOWN),
1012};
1013
1014static const unsigned emmc_pins[] = {40, 41, 42, 43, 51, 52, 53};
1015static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
1016static const unsigned emmc_dat8_pins[] = {44, 45, 46, 47};
1017static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
1018static const unsigned i2c0_pins[] = {142, 143};
1019static const unsigned i2c0_muxvals[] = {0, 0};
1020static const unsigned i2c1_pins[] = {144, 145};
1021static const unsigned i2c1_muxvals[] = {0, 0};
1022static const unsigned i2c2_pins[] = {146, 147};
1023static const unsigned i2c2_muxvals[] = {0, 0};
1024static const unsigned i2c3_pins[] = {148, 149};
1025static const unsigned i2c3_muxvals[] = {0, 0};
1026static const unsigned i2c6_pins[] = {308, 309};
1027static const unsigned i2c6_muxvals[] = {6, 6};
1028static const unsigned nand_pins[] = {40, 41, 42, 43, 44, 45, 46, 47, 48, 49,
1029 50, 51, 52, 53, 54};
1030static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1031 0, 0};
1032static const unsigned nand_cs1_pins[] = {131, 132};
1033static const unsigned nand_cs1_muxvals[] = {1, 1};
1034static const unsigned uart0_pins[] = {127, 128};
1035static const unsigned uart0_muxvals[] = {0, 0};
1036static const unsigned uart1_pins[] = {129, 130};
1037static const unsigned uart1_muxvals[] = {0, 0};
1038static const unsigned uart2_pins[] = {131, 132};
1039static const unsigned uart2_muxvals[] = {0, 0};
1040static const unsigned uart3_pins[] = {88, 89};
1041static const unsigned uart3_muxvals[] = {2, 2};
1042static const unsigned usb0_pins[] = {180, 181};
1043static const unsigned usb0_muxvals[] = {0, 0};
1044static const unsigned usb1_pins[] = {182, 183};
1045static const unsigned usb1_muxvals[] = {0, 0};
1046static const unsigned usb2_pins[] = {184, 185};
1047static const unsigned usb2_muxvals[] = {0, 0};
1048static const unsigned usb3_pins[] = {186, 187};
1049static const unsigned usb3_muxvals[] = {0, 0};
1050static const unsigned port_range0_pins[] = {
1051 300, 301, 302, 303, 304, 305, 306, 307, /* PORT0x */
1052 308, 309, 310, 311, 312, 313, 314, 315, /* PORT1x */
1053 316, 317, 318, 16, 17, 18, 19, 20, /* PORT2x */
1054 21, 22, 23, 4, 93, 94, 95, 63, /* PORT3x */
1055 123, 122, 124, 125, 126, 141, 202, 203, /* PORT4x */
1056 204, 226, 227, 290, 291, 233, 280, 281, /* PORT5x */
1057 8, 7, 10, 29, 30, 48, 49, 50, /* PORT6x */
1058 40, 41, 42, 43, 44, 45, 46, 47, /* PORT7x */
1059 54, 51, 52, 53, 127, 128, 129, 130, /* PORT8x */
1060 131, 132, 57, 60, 134, 133, 135, 136, /* PORT9x */
1061 138, 137, 140, 139, 64, 65, 66, 67, /* PORT10x */
1062 107, 106, 105, 104, 113, 112, 111, 110, /* PORT11x */
1063 68, 69, 70, 71, 72, 73, 74, 75, /* PORT12x */
1064 76, 77, 78, 79, 80, 81, 82, 83, /* PORT13x */
1065 84, 85, 86, 87, 88, 89, 90, 91, /* PORT14x */
1066};
1067static const unsigned port_range0_muxvals[] = {
1068 7, 7, 7, 7, 7, 7, 7, 7, /* PORT0x */
1069 7, 7, 7, 7, 7, 7, 7, 7, /* PORT1x */
1070 7, 7, 7, 7, 7, 7, 7, 7, /* PORT2x */
1071 7, 7, 7, 7, 7, 7, 7, 7, /* PORT3x */
1072 7, 7, 7, 7, 7, 7, 7, 7, /* PORT4x */
1073 7, 7, 7, 7, 7, 7, 7, 7, /* PORT5x */
1074 7, 7, 7, 7, 7, 7, 7, 7, /* PORT6x */
1075 7, 7, 7, 7, 7, 7, 7, 7, /* PORT7x */
1076 7, 7, 7, 7, 7, 7, 7, 7, /* PORT8x */
1077 7, 7, 7, 7, 7, 7, 7, 7, /* PORT9x */
1078 7, 7, 7, 7, 7, 7, 7, 7, /* PORT10x */
1079 7, 7, 7, 7, 7, 7, 7, 7, /* PORT11x */
1080 7, 7, 7, 7, 7, 7, 7, 7, /* PORT12x */
1081 7, 7, 7, 7, 7, 7, 7, 7, /* PORT13x */
1082 7, 7, 7, 7, 7, 7, 7, 7, /* PORT14x */
1083};
1084static const unsigned port_range1_pins[] = {
1085 13, 14, 15, /* PORT175-177 */
1086 157, 158, 156, 154, 150, 151, 152, 153, /* PORT18x */
1087 326, 327, 325, 323, 319, 320, 321, 322, /* PORT19x */
1088 160, 161, 162, 163, 164, 165, 166, 167, /* PORT20x */
1089 168, 169, 170, 171, 172, 173, 174, 175, /* PORT21x */
1090 180, 181, 182, 183, 184, 185, 187, 188, /* PORT22x */
1091 193, 194, 195, 196, 197, 198, 199, 200, /* PORT23x */
1092 191, 192, 215, 216, 217, 218, 219, 220, /* PORT24x */
1093 222, 223, 224, 225, 228, 229, 230, 231, /* PORT25x */
1094 282, 283, 284, 285, 286, 287, 288, 289, /* PORT26x */
1095 292, 293, 294, 295, 296, 236, 237, 238, /* PORT27x */
1096 275, 276, 277, 278, 239, 240, 249, 250, /* PORT28x */
1097 251, 252, 261, 262, 263, 264, 273, 274, /* PORT29x */
1098 31, 32, 33, 34, 35, 36, 37, 38, /* PORT30x */
1099};
1100static const unsigned port_range1_muxvals[] = {
1101 7, 7, 7, /* PORT175-177 */
1102 7, 7, 7, 7, 7, 7, 7, 7, /* PORT18x */
1103 7, 7, 7, 7, 7, 7, 7, 7, /* PORT19x */
1104 7, 7, 7, 7, 7, 7, 7, 7, /* PORT20x */
1105 7, 7, 7, 7, 7, 7, 7, 7, /* PORT21x */
1106 7, 7, 7, 7, 7, 7, 7, 7, /* PORT22x */
1107 7, 7, 7, 7, 7, 7, 7, 7, /* PORT23x */
1108 7, 7, 7, 7, 7, 7, 7, 7, /* PORT24x */
1109 7, 7, 7, 7, 7, 7, 7, 7, /* PORT25x */
1110 7, 7, 7, 7, 7, 7, 7, 7, /* PORT26x */
1111 7, 7, 7, 7, 7, 7, 7, 7, /* PORT27x */
1112 7, 7, 7, 7, 7, 7, 7, 7, /* PORT28x */
1113 7, 7, 7, 7, 7, 7, 7, 7, /* PORT29x */
1114 7, 7, 7, 7, 7, 7, 7, 7, /* PORT30x */
1115};
1116static const unsigned xirq_pins[] = {
1117 11, 9, 12, 96, 97, 98, 108, 114, /* XIRQ0-7 */
1118 234, 186, 99, 100, 101, 102, 184, 301, /* XIRQ8-15 */
1119 302, 303, 304, 305, 306, /* XIRQ16-20 */
1120};
1121static const unsigned xirq_muxvals[] = {
1122 7, 7, 7, 7, 7, 7, 7, 7, /* XIRQ0-7 */
1123 7, 7, 7, 7, 7, 7, 2, 2, /* XIRQ8-15 */
1124 2, 2, 2, 2, 2, /* XIRQ16-20 */
1125};
1126static const unsigned xirq_alternatives_pins[] = {
1127 184, 310, 316,
1128};
1129static const unsigned xirq_alternatives_muxvals[] = {
1130 2, 2, 2,
1131};
1132
1133static const struct uniphier_pinctrl_group ph1_pro4_groups[] = {
1134 UNIPHIER_PINCTRL_GROUP(emmc),
1135 UNIPHIER_PINCTRL_GROUP(emmc_dat8),
1136 UNIPHIER_PINCTRL_GROUP(i2c0),
1137 UNIPHIER_PINCTRL_GROUP(i2c1),
1138 UNIPHIER_PINCTRL_GROUP(i2c2),
1139 UNIPHIER_PINCTRL_GROUP(i2c3),
1140 UNIPHIER_PINCTRL_GROUP(i2c6),
1141 UNIPHIER_PINCTRL_GROUP(nand),
1142 UNIPHIER_PINCTRL_GROUP(nand_cs1),
1143 UNIPHIER_PINCTRL_GROUP(uart0),
1144 UNIPHIER_PINCTRL_GROUP(uart1),
1145 UNIPHIER_PINCTRL_GROUP(uart2),
1146 UNIPHIER_PINCTRL_GROUP(uart3),
1147 UNIPHIER_PINCTRL_GROUP(usb0),
1148 UNIPHIER_PINCTRL_GROUP(usb1),
1149 UNIPHIER_PINCTRL_GROUP(usb2),
1150 UNIPHIER_PINCTRL_GROUP(usb3),
1151 UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0),
1152 UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1),
1153 UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq),
1154 UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_alternatives),
1155 UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0),
1156 UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1),
1157 UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2),
1158 UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3),
1159 UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4),
1160 UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5),
1161 UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6),
1162 UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7),
1163 UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8),
1164 UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9),
1165 UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10),
1166 UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11),
1167 UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12),
1168 UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13),
1169 UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14),
1170 UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15),
1171 UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16),
1172 UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17),
1173 UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18),
1174 UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19),
1175 UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20),
1176 UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21),
1177 UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22),
1178 UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23),
1179 UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24),
1180 UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25),
1181 UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26),
1182 UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27),
1183 UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28),
1184 UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29),
1185 UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30),
1186 UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31),
1187 UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32),
1188 UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33),
1189 UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34),
1190 UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35),
1191 UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36),
1192 UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37),
1193 UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38),
1194 UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39),
1195 UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40),
1196 UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41),
1197 UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42),
1198 UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43),
1199 UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44),
1200 UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45),
1201 UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46),
1202 UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47),
1203 UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48),
1204 UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49),
1205 UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50),
1206 UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51),
1207 UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52),
1208 UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53),
1209 UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54),
1210 UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55),
1211 UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56),
1212 UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57),
1213 UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58),
1214 UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59),
1215 UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60),
1216 UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61),
1217 UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62),
1218 UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63),
1219 UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64),
1220 UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65),
1221 UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66),
1222 UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67),
1223 UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68),
1224 UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69),
1225 UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70),
1226 UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71),
1227 UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72),
1228 UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73),
1229 UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74),
1230 UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75),
1231 UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76),
1232 UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77),
1233 UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78),
1234 UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79),
1235 UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80),
1236 UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81),
1237 UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82),
1238 UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83),
1239 UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84),
1240 UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85),
1241 UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86),
1242 UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87),
1243 UNIPHIER_PINCTRL_GROUP_SINGLE(port110, port_range0, 88),
1244 UNIPHIER_PINCTRL_GROUP_SINGLE(port111, port_range0, 89),
1245 UNIPHIER_PINCTRL_GROUP_SINGLE(port112, port_range0, 90),
1246 UNIPHIER_PINCTRL_GROUP_SINGLE(port113, port_range0, 91),
1247 UNIPHIER_PINCTRL_GROUP_SINGLE(port114, port_range0, 92),
1248 UNIPHIER_PINCTRL_GROUP_SINGLE(port115, port_range0, 93),
1249 UNIPHIER_PINCTRL_GROUP_SINGLE(port116, port_range0, 94),
1250 UNIPHIER_PINCTRL_GROUP_SINGLE(port117, port_range0, 95),
1251 UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range0, 96),
1252 UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range0, 97),
1253 UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range0, 98),
1254 UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range0, 99),
1255 UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range0, 100),
1256 UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range0, 101),
1257 UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range0, 102),
1258 UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range0, 103),
1259 UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range0, 104),
1260 UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range0, 105),
1261 UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range0, 106),
1262 UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range0, 107),
1263 UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range0, 108),
1264 UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range0, 109),
1265 UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range0, 110),
1266 UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range0, 111),
1267 UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range0, 112),
1268 UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range0, 113),
1269 UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range0, 114),
1270 UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range0, 115),
1271 UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range0, 116),
1272 UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range0, 117),
1273 UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range0, 118),
1274 UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range0, 119),
1275 UNIPHIER_PINCTRL_GROUP_SINGLE(port175, port_range1, 0),
1276 UNIPHIER_PINCTRL_GROUP_SINGLE(port176, port_range1, 1),
1277 UNIPHIER_PINCTRL_GROUP_SINGLE(port177, port_range1, 2),
1278 UNIPHIER_PINCTRL_GROUP_SINGLE(port180, port_range1, 3),
1279 UNIPHIER_PINCTRL_GROUP_SINGLE(port181, port_range1, 4),
1280 UNIPHIER_PINCTRL_GROUP_SINGLE(port182, port_range1, 5),
1281 UNIPHIER_PINCTRL_GROUP_SINGLE(port183, port_range1, 6),
1282 UNIPHIER_PINCTRL_GROUP_SINGLE(port184, port_range1, 7),
1283 UNIPHIER_PINCTRL_GROUP_SINGLE(port185, port_range1, 8),
1284 UNIPHIER_PINCTRL_GROUP_SINGLE(port186, port_range1, 9),
1285 UNIPHIER_PINCTRL_GROUP_SINGLE(port187, port_range1, 10),
1286 UNIPHIER_PINCTRL_GROUP_SINGLE(port190, port_range1, 11),
1287 UNIPHIER_PINCTRL_GROUP_SINGLE(port191, port_range1, 12),
1288 UNIPHIER_PINCTRL_GROUP_SINGLE(port192, port_range1, 13),
1289 UNIPHIER_PINCTRL_GROUP_SINGLE(port193, port_range1, 14),
1290 UNIPHIER_PINCTRL_GROUP_SINGLE(port194, port_range1, 15),
1291 UNIPHIER_PINCTRL_GROUP_SINGLE(port195, port_range1, 16),
1292 UNIPHIER_PINCTRL_GROUP_SINGLE(port196, port_range1, 17),
1293 UNIPHIER_PINCTRL_GROUP_SINGLE(port197, port_range1, 18),
1294 UNIPHIER_PINCTRL_GROUP_SINGLE(port200, port_range1, 19),
1295 UNIPHIER_PINCTRL_GROUP_SINGLE(port201, port_range1, 20),
1296 UNIPHIER_PINCTRL_GROUP_SINGLE(port202, port_range1, 21),
1297 UNIPHIER_PINCTRL_GROUP_SINGLE(port203, port_range1, 22),
1298 UNIPHIER_PINCTRL_GROUP_SINGLE(port204, port_range1, 23),
1299 UNIPHIER_PINCTRL_GROUP_SINGLE(port205, port_range1, 24),
1300 UNIPHIER_PINCTRL_GROUP_SINGLE(port206, port_range1, 25),
1301 UNIPHIER_PINCTRL_GROUP_SINGLE(port207, port_range1, 26),
1302 UNIPHIER_PINCTRL_GROUP_SINGLE(port210, port_range1, 27),
1303 UNIPHIER_PINCTRL_GROUP_SINGLE(port211, port_range1, 28),
1304 UNIPHIER_PINCTRL_GROUP_SINGLE(port212, port_range1, 29),
1305 UNIPHIER_PINCTRL_GROUP_SINGLE(port213, port_range1, 30),
1306 UNIPHIER_PINCTRL_GROUP_SINGLE(port214, port_range1, 31),
1307 UNIPHIER_PINCTRL_GROUP_SINGLE(port215, port_range1, 32),
1308 UNIPHIER_PINCTRL_GROUP_SINGLE(port216, port_range1, 33),
1309 UNIPHIER_PINCTRL_GROUP_SINGLE(port217, port_range1, 34),
1310 UNIPHIER_PINCTRL_GROUP_SINGLE(port220, port_range1, 35),
1311 UNIPHIER_PINCTRL_GROUP_SINGLE(port221, port_range1, 36),
1312 UNIPHIER_PINCTRL_GROUP_SINGLE(port222, port_range1, 37),
1313 UNIPHIER_PINCTRL_GROUP_SINGLE(port223, port_range1, 38),
1314 UNIPHIER_PINCTRL_GROUP_SINGLE(port224, port_range1, 39),
1315 UNIPHIER_PINCTRL_GROUP_SINGLE(port225, port_range1, 40),
1316 UNIPHIER_PINCTRL_GROUP_SINGLE(port226, port_range1, 41),
1317 UNIPHIER_PINCTRL_GROUP_SINGLE(port227, port_range1, 42),
1318 UNIPHIER_PINCTRL_GROUP_SINGLE(port230, port_range1, 43),
1319 UNIPHIER_PINCTRL_GROUP_SINGLE(port231, port_range1, 44),
1320 UNIPHIER_PINCTRL_GROUP_SINGLE(port232, port_range1, 45),
1321 UNIPHIER_PINCTRL_GROUP_SINGLE(port233, port_range1, 46),
1322 UNIPHIER_PINCTRL_GROUP_SINGLE(port234, port_range1, 47),
1323 UNIPHIER_PINCTRL_GROUP_SINGLE(port235, port_range1, 48),
1324 UNIPHIER_PINCTRL_GROUP_SINGLE(port236, port_range1, 49),
1325 UNIPHIER_PINCTRL_GROUP_SINGLE(port237, port_range1, 50),
1326 UNIPHIER_PINCTRL_GROUP_SINGLE(port240, port_range1, 51),
1327 UNIPHIER_PINCTRL_GROUP_SINGLE(port241, port_range1, 52),
1328 UNIPHIER_PINCTRL_GROUP_SINGLE(port242, port_range1, 53),
1329 UNIPHIER_PINCTRL_GROUP_SINGLE(port243, port_range1, 54),
1330 UNIPHIER_PINCTRL_GROUP_SINGLE(port244, port_range1, 55),
1331 UNIPHIER_PINCTRL_GROUP_SINGLE(port245, port_range1, 56),
1332 UNIPHIER_PINCTRL_GROUP_SINGLE(port246, port_range1, 57),
1333 UNIPHIER_PINCTRL_GROUP_SINGLE(port247, port_range1, 58),
1334 UNIPHIER_PINCTRL_GROUP_SINGLE(port250, port_range1, 59),
1335 UNIPHIER_PINCTRL_GROUP_SINGLE(port251, port_range1, 60),
1336 UNIPHIER_PINCTRL_GROUP_SINGLE(port252, port_range1, 61),
1337 UNIPHIER_PINCTRL_GROUP_SINGLE(port253, port_range1, 62),
1338 UNIPHIER_PINCTRL_GROUP_SINGLE(port254, port_range1, 63),
1339 UNIPHIER_PINCTRL_GROUP_SINGLE(port255, port_range1, 64),
1340 UNIPHIER_PINCTRL_GROUP_SINGLE(port256, port_range1, 65),
1341 UNIPHIER_PINCTRL_GROUP_SINGLE(port257, port_range1, 66),
1342 UNIPHIER_PINCTRL_GROUP_SINGLE(port260, port_range1, 67),
1343 UNIPHIER_PINCTRL_GROUP_SINGLE(port261, port_range1, 68),
1344 UNIPHIER_PINCTRL_GROUP_SINGLE(port262, port_range1, 69),
1345 UNIPHIER_PINCTRL_GROUP_SINGLE(port263, port_range1, 70),
1346 UNIPHIER_PINCTRL_GROUP_SINGLE(port264, port_range1, 71),
1347 UNIPHIER_PINCTRL_GROUP_SINGLE(port265, port_range1, 72),
1348 UNIPHIER_PINCTRL_GROUP_SINGLE(port266, port_range1, 73),
1349 UNIPHIER_PINCTRL_GROUP_SINGLE(port267, port_range1, 74),
1350 UNIPHIER_PINCTRL_GROUP_SINGLE(port270, port_range1, 75),
1351 UNIPHIER_PINCTRL_GROUP_SINGLE(port271, port_range1, 76),
1352 UNIPHIER_PINCTRL_GROUP_SINGLE(port272, port_range1, 77),
1353 UNIPHIER_PINCTRL_GROUP_SINGLE(port273, port_range1, 78),
1354 UNIPHIER_PINCTRL_GROUP_SINGLE(port274, port_range1, 79),
1355 UNIPHIER_PINCTRL_GROUP_SINGLE(port275, port_range1, 80),
1356 UNIPHIER_PINCTRL_GROUP_SINGLE(port276, port_range1, 81),
1357 UNIPHIER_PINCTRL_GROUP_SINGLE(port277, port_range1, 82),
1358 UNIPHIER_PINCTRL_GROUP_SINGLE(port280, port_range1, 83),
1359 UNIPHIER_PINCTRL_GROUP_SINGLE(port281, port_range1, 84),
1360 UNIPHIER_PINCTRL_GROUP_SINGLE(port282, port_range1, 85),
1361 UNIPHIER_PINCTRL_GROUP_SINGLE(port283, port_range1, 86),
1362 UNIPHIER_PINCTRL_GROUP_SINGLE(port284, port_range1, 87),
1363 UNIPHIER_PINCTRL_GROUP_SINGLE(port285, port_range1, 88),
1364 UNIPHIER_PINCTRL_GROUP_SINGLE(port286, port_range1, 89),
1365 UNIPHIER_PINCTRL_GROUP_SINGLE(port287, port_range1, 90),
1366 UNIPHIER_PINCTRL_GROUP_SINGLE(port290, port_range1, 91),
1367 UNIPHIER_PINCTRL_GROUP_SINGLE(port291, port_range1, 92),
1368 UNIPHIER_PINCTRL_GROUP_SINGLE(port292, port_range1, 93),
1369 UNIPHIER_PINCTRL_GROUP_SINGLE(port293, port_range1, 94),
1370 UNIPHIER_PINCTRL_GROUP_SINGLE(port294, port_range1, 95),
1371 UNIPHIER_PINCTRL_GROUP_SINGLE(port295, port_range1, 96),
1372 UNIPHIER_PINCTRL_GROUP_SINGLE(port296, port_range1, 97),
1373 UNIPHIER_PINCTRL_GROUP_SINGLE(port297, port_range1, 98),
1374 UNIPHIER_PINCTRL_GROUP_SINGLE(port300, port_range1, 99),
1375 UNIPHIER_PINCTRL_GROUP_SINGLE(port301, port_range1, 100),
1376 UNIPHIER_PINCTRL_GROUP_SINGLE(port302, port_range1, 101),
1377 UNIPHIER_PINCTRL_GROUP_SINGLE(port303, port_range1, 102),
1378 UNIPHIER_PINCTRL_GROUP_SINGLE(port304, port_range1, 103),
1379 UNIPHIER_PINCTRL_GROUP_SINGLE(port305, port_range1, 104),
1380 UNIPHIER_PINCTRL_GROUP_SINGLE(port306, port_range1, 105),
1381 UNIPHIER_PINCTRL_GROUP_SINGLE(port307, port_range1, 106),
1382 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq, 0),
1383 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq, 1),
1384 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq, 2),
1385 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq, 3),
1386 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq, 4),
1387 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq, 5),
1388 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq, 6),
1389 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq, 7),
1390 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq, 8),
1391 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq, 9),
1392 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq, 10),
1393 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq, 11),
1394 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq, 12),
1395 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq13, xirq, 13),
1396 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq, 14),
1397 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq, 15),
1398 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16, xirq, 16),
1399 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17, xirq, 17),
1400 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18, xirq, 18),
1401 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19, xirq, 19),
1402 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20, xirq, 20),
1403 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14b, xirq_alternatives, 0),
1404 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17b, xirq_alternatives, 1),
1405 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18b, xirq_alternatives, 2),
1406};
1407
1408static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
1409static const char * const i2c0_groups[] = {"i2c0"};
1410static const char * const i2c1_groups[] = {"i2c1"};
1411static const char * const i2c2_groups[] = {"i2c2"};
1412static const char * const i2c3_groups[] = {"i2c3"};
1413static const char * const i2c6_groups[] = {"i2c6"};
1414static const char * const nand_groups[] = {"nand", "nand_cs1"};
1415static const char * const uart0_groups[] = {"uart0"};
1416static const char * const uart1_groups[] = {"uart1"};
1417static const char * const uart2_groups[] = {"uart2"};
1418static const char * const uart3_groups[] = {"uart3"};
1419static const char * const usb0_groups[] = {"usb0"};
1420static const char * const usb1_groups[] = {"usb1"};
1421static const char * const usb2_groups[] = {"usb2"};
1422static const char * const usb3_groups[] = {"usb3"};
1423static const char * const port_groups[] = {
1424 "port00", "port01", "port02", "port03",
1425 "port04", "port05", "port06", "port07",
1426 "port10", "port11", "port12", "port13",
1427 "port14", "port15", "port16", "port17",
1428 "port20", "port21", "port22", "port23",
1429 "port24", "port25", "port26", "port27",
1430 "port30", "port31", "port32", "port33",
1431 "port34", "port35", "port36", "port37",
1432 "port40", "port41", "port42", "port43",
1433 "port44", "port45", "port46", "port47",
1434 "port50", "port51", "port52", "port53",
1435 "port54", "port55", "port56", "port57",
1436 "port60", "port61", "port62", "port63",
1437 "port64", "port65", "port66", "port67",
1438 "port70", "port71", "port72", "port73",
1439 "port74", "port75", "port76", "port77",
1440 "port80", "port81", "port82", "port83",
1441 "port84", "port85", "port86", "port87",
1442 "port90", "port91", "port92", "port93",
1443 "port94", "port95", "port96", "port97",
1444 "port100", "port101", "port102", "port103",
1445 "port104", "port105", "port106", "port107",
1446 "port110", "port111", "port112", "port113",
1447 "port114", "port115", "port116", "port117",
1448 "port120", "port121", "port122", "port123",
1449 "port124", "port125", "port126", "port127",
1450 "port130", "port131", "port132", "port133",
1451 "port134", "port135", "port136", "port137",
1452 "port140", "port141", "port142", "port143",
1453 "port144", "port145", "port146", "port147",
1454 /* port150-174 missing */
1455 /* none */ "port175", "port176", "port177",
1456 "port180", "port181", "port182", "port183",
1457 "port184", "port185", "port186", "port187",
1458 "port190", "port191", "port192", "port193",
1459 "port194", "port195", "port196", "port197",
1460 "port200", "port201", "port202", "port203",
1461 "port204", "port205", "port206", "port207",
1462 "port210", "port211", "port212", "port213",
1463 "port214", "port215", "port216", "port217",
1464 "port220", "port221", "port222", "port223",
1465 "port224", "port225", "port226", "port227",
1466 "port230", "port231", "port232", "port233",
1467 "port234", "port235", "port236", "port237",
1468 "port240", "port241", "port242", "port243",
1469 "port244", "port245", "port246", "port247",
1470 "port250", "port251", "port252", "port253",
1471 "port254", "port255", "port256", "port257",
1472 "port260", "port261", "port262", "port263",
1473 "port264", "port265", "port266", "port267",
1474 "port270", "port271", "port272", "port273",
1475 "port274", "port275", "port276", "port277",
1476 "port280", "port281", "port282", "port283",
1477 "port284", "port285", "port286", "port287",
1478 "port290", "port291", "port292", "port293",
1479 "port294", "port295", "port296", "port297",
1480 "port300", "port301", "port302", "port303",
1481 "port304", "port305", "port306", "port307",
1482};
1483static const char * const xirq_groups[] = {
1484 "xirq0", "xirq1", "xirq2", "xirq3",
1485 "xirq4", "xirq5", "xirq6", "xirq7",
1486 "xirq8", "xirq9", "xirq10", "xirq11",
1487 "xirq12", "xirq13", "xirq14", "xirq15",
1488 "xirq16", "xirq17", "xirq18", "xirq19",
1489 "xirq20",
1490 "xirq14b", "xirq17b", "xirq18b",
1491};
1492
1493static const struct uniphier_pinmux_function ph1_pro4_functions[] = {
1494 UNIPHIER_PINMUX_FUNCTION(emmc),
1495 UNIPHIER_PINMUX_FUNCTION(i2c0),
1496 UNIPHIER_PINMUX_FUNCTION(i2c1),
1497 UNIPHIER_PINMUX_FUNCTION(i2c2),
1498 UNIPHIER_PINMUX_FUNCTION(i2c3),
1499 UNIPHIER_PINMUX_FUNCTION(i2c6),
1500 UNIPHIER_PINMUX_FUNCTION(nand),
1501 UNIPHIER_PINMUX_FUNCTION(uart0),
1502 UNIPHIER_PINMUX_FUNCTION(uart1),
1503 UNIPHIER_PINMUX_FUNCTION(uart2),
1504 UNIPHIER_PINMUX_FUNCTION(uart3),
1505 UNIPHIER_PINMUX_FUNCTION(usb0),
1506 UNIPHIER_PINMUX_FUNCTION(usb1),
1507 UNIPHIER_PINMUX_FUNCTION(usb2),
1508 UNIPHIER_PINMUX_FUNCTION(usb3),
1509 UNIPHIER_PINMUX_FUNCTION(port),
1510 UNIPHIER_PINMUX_FUNCTION(xirq),
1511};
1512
1513static struct uniphier_pinctrl_socdata ph1_pro4_pindata = {
1514 .groups = ph1_pro4_groups,
1515 .groups_count = ARRAY_SIZE(ph1_pro4_groups),
1516 .functions = ph1_pro4_functions,
1517 .functions_count = ARRAY_SIZE(ph1_pro4_functions),
1518 .mux_bits = 4,
1519 .reg_stride = 8,
1520 .load_pinctrl = true,
1521};
1522
1523static struct pinctrl_desc ph1_pro4_pinctrl_desc = {
1524 .name = DRIVER_NAME,
1525 .pins = ph1_pro4_pins,
1526 .npins = ARRAY_SIZE(ph1_pro4_pins),
1527 .owner = THIS_MODULE,
1528};
1529
1530static int ph1_pro4_pinctrl_probe(struct platform_device *pdev)
1531{
1532 return uniphier_pinctrl_probe(pdev, &ph1_pro4_pinctrl_desc,
1533 &ph1_pro4_pindata);
1534}
1535
1536static const struct of_device_id ph1_pro4_pinctrl_match[] = {
1537 { .compatible = "socionext,ph1-pro4-pinctrl" },
1538 { /* sentinel */ }
1539};
1540MODULE_DEVICE_TABLE(of, ph1_pro4_pinctrl_match);
1541
1542static struct platform_driver ph1_pro4_pinctrl_driver = {
1543 .probe = ph1_pro4_pinctrl_probe,
1544 .remove = uniphier_pinctrl_remove,
1545 .driver = {
1546 .name = DRIVER_NAME,
1547 .of_match_table = ph1_pro4_pinctrl_match,
1548 },
1549};
1550module_platform_driver(ph1_pro4_pinctrl_driver);
1551
1552MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
1553MODULE_DESCRIPTION("UniPhier PH1-Pro4 pinctrl driver");
1554MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c b/drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c
new file mode 100644
index 000000000000..9af455978058
--- /dev/null
+++ b/drivers/pinctrl/uniphier/pinctrl-ph1-pro5.c
@@ -0,0 +1,1351 @@
1/*
2 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program5 is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/pinctrl/pinctrl.h>
18#include <linux/platform_device.h>
19
20#include "pinctrl-uniphier.h"
21
22#define DRIVER_NAME "ph1-pro5-pinctrl"
23
24static const struct pinctrl_pin_desc ph1_pro5_pins[] = {
25 UNIPHIER_PINCTRL_PIN(0, "AEXCKA1", 0,
26 0, UNIPHIER_PIN_DRV_4_8,
27 0, UNIPHIER_PIN_PULL_DOWN),
28 UNIPHIER_PINCTRL_PIN(1, "AEXCKA2", 0,
29 1, UNIPHIER_PIN_DRV_4_8,
30 1, UNIPHIER_PIN_PULL_DOWN),
31 UNIPHIER_PINCTRL_PIN(2, "CK27EXI", 0,
32 2, UNIPHIER_PIN_DRV_4_8,
33 2, UNIPHIER_PIN_PULL_DOWN),
34 UNIPHIER_PINCTRL_PIN(3, "CK54EXI", 0,
35 3, UNIPHIER_PIN_DRV_4_8,
36 3, UNIPHIER_PIN_PULL_DOWN),
37 UNIPHIER_PINCTRL_PIN(4, "ED0", UNIPHIER_PIN_IECTRL_NONE,
38 4, UNIPHIER_PIN_DRV_4_8,
39 4, UNIPHIER_PIN_PULL_DOWN),
40 UNIPHIER_PINCTRL_PIN(5, "ED1", UNIPHIER_PIN_IECTRL_NONE,
41 5, UNIPHIER_PIN_DRV_4_8,
42 5, UNIPHIER_PIN_PULL_DOWN),
43 UNIPHIER_PINCTRL_PIN(6, "ED2", UNIPHIER_PIN_IECTRL_NONE,
44 6, UNIPHIER_PIN_DRV_4_8,
45 6, UNIPHIER_PIN_PULL_DOWN),
46 UNIPHIER_PINCTRL_PIN(7, "ED3", UNIPHIER_PIN_IECTRL_NONE,
47 7, UNIPHIER_PIN_DRV_4_8,
48 7, UNIPHIER_PIN_PULL_DOWN),
49 UNIPHIER_PINCTRL_PIN(8, "ED4", UNIPHIER_PIN_IECTRL_NONE,
50 8, UNIPHIER_PIN_DRV_4_8,
51 8, UNIPHIER_PIN_PULL_DOWN),
52 UNIPHIER_PINCTRL_PIN(9, "ED5", UNIPHIER_PIN_IECTRL_NONE,
53 9, UNIPHIER_PIN_DRV_4_8,
54 9, UNIPHIER_PIN_PULL_DOWN),
55 UNIPHIER_PINCTRL_PIN(10, "ED6", UNIPHIER_PIN_IECTRL_NONE,
56 10, UNIPHIER_PIN_DRV_4_8,
57 10, UNIPHIER_PIN_PULL_DOWN),
58 UNIPHIER_PINCTRL_PIN(11, "ED7", UNIPHIER_PIN_IECTRL_NONE,
59 11, UNIPHIER_PIN_DRV_4_8,
60 11, UNIPHIER_PIN_PULL_DOWN),
61 UNIPHIER_PINCTRL_PIN(12, "XERWE0", UNIPHIER_PIN_IECTRL_NONE,
62 12, UNIPHIER_PIN_DRV_4_8,
63 12, UNIPHIER_PIN_PULL_UP),
64 UNIPHIER_PINCTRL_PIN(13, "XERWE1", UNIPHIER_PIN_IECTRL_NONE,
65 13, UNIPHIER_PIN_DRV_4_8,
66 13, UNIPHIER_PIN_PULL_UP),
67 UNIPHIER_PINCTRL_PIN(14, "ERXW", UNIPHIER_PIN_IECTRL_NONE,
68 14, UNIPHIER_PIN_DRV_4_8,
69 14, UNIPHIER_PIN_PULL_UP),
70 UNIPHIER_PINCTRL_PIN(15, "ES0", UNIPHIER_PIN_IECTRL_NONE,
71 15, UNIPHIER_PIN_DRV_4_8,
72 15, UNIPHIER_PIN_PULL_UP),
73 UNIPHIER_PINCTRL_PIN(16, "ES1", UNIPHIER_PIN_IECTRL_NONE,
74 16, UNIPHIER_PIN_DRV_4_8,
75 16, UNIPHIER_PIN_PULL_UP),
76 UNIPHIER_PINCTRL_PIN(17, "ES2", UNIPHIER_PIN_IECTRL_NONE,
77 17, UNIPHIER_PIN_DRV_4_8,
78 17, UNIPHIER_PIN_PULL_UP),
79 UNIPHIER_PINCTRL_PIN(18, "XECS1", UNIPHIER_PIN_IECTRL_NONE,
80 18, UNIPHIER_PIN_DRV_4_8,
81 18, UNIPHIER_PIN_PULL_UP),
82 UNIPHIER_PINCTRL_PIN(19, "XNFRE", UNIPHIER_PIN_IECTRL_NONE,
83 19, UNIPHIER_PIN_DRV_4_8,
84 19, UNIPHIER_PIN_PULL_UP),
85 UNIPHIER_PINCTRL_PIN(20, "XNFWE", UNIPHIER_PIN_IECTRL_NONE,
86 20, UNIPHIER_PIN_DRV_4_8,
87 20, UNIPHIER_PIN_PULL_UP),
88 UNIPHIER_PINCTRL_PIN(21, "NFALE", UNIPHIER_PIN_IECTRL_NONE,
89 21, UNIPHIER_PIN_DRV_4_8,
90 21, UNIPHIER_PIN_PULL_DOWN),
91 UNIPHIER_PINCTRL_PIN(22, "NFCLE", UNIPHIER_PIN_IECTRL_NONE,
92 22, UNIPHIER_PIN_DRV_4_8,
93 22, UNIPHIER_PIN_PULL_DOWN),
94 UNIPHIER_PINCTRL_PIN(23, "XNFWP", UNIPHIER_PIN_IECTRL_NONE,
95 23, UNIPHIER_PIN_DRV_4_8,
96 23, UNIPHIER_PIN_PULL_DOWN),
97 UNIPHIER_PINCTRL_PIN(24, "XNFCE0", UNIPHIER_PIN_IECTRL_NONE,
98 24, UNIPHIER_PIN_DRV_4_8,
99 24, UNIPHIER_PIN_PULL_UP),
100 UNIPHIER_PINCTRL_PIN(25, "NFRYBY0", UNIPHIER_PIN_IECTRL_NONE,
101 25, UNIPHIER_PIN_DRV_4_8,
102 25, UNIPHIER_PIN_PULL_UP),
103 UNIPHIER_PINCTRL_PIN(26, "XNFCE1", UNIPHIER_PIN_IECTRL_NONE,
104 26, UNIPHIER_PIN_DRV_4_8,
105 26, UNIPHIER_PIN_PULL_UP),
106 UNIPHIER_PINCTRL_PIN(27, "NFRYBY1", UNIPHIER_PIN_IECTRL_NONE,
107 27, UNIPHIER_PIN_DRV_4_8,
108 27, UNIPHIER_PIN_PULL_UP),
109 UNIPHIER_PINCTRL_PIN(28, "NFD0", UNIPHIER_PIN_IECTRL_NONE,
110 28, UNIPHIER_PIN_DRV_4_8,
111 28, UNIPHIER_PIN_PULL_UP),
112 UNIPHIER_PINCTRL_PIN(29, "NFD1", UNIPHIER_PIN_IECTRL_NONE,
113 29, UNIPHIER_PIN_DRV_4_8,
114 29, UNIPHIER_PIN_PULL_UP),
115 UNIPHIER_PINCTRL_PIN(30, "NFD2", UNIPHIER_PIN_IECTRL_NONE,
116 30, UNIPHIER_PIN_DRV_4_8,
117 30, UNIPHIER_PIN_PULL_UP),
118 UNIPHIER_PINCTRL_PIN(31, "NFD3", UNIPHIER_PIN_IECTRL_NONE,
119 31, UNIPHIER_PIN_DRV_4_8,
120 31, UNIPHIER_PIN_PULL_UP),
121 UNIPHIER_PINCTRL_PIN(32, "NFD4", UNIPHIER_PIN_IECTRL_NONE,
122 32, UNIPHIER_PIN_DRV_4_8,
123 32, UNIPHIER_PIN_PULL_UP),
124 UNIPHIER_PINCTRL_PIN(33, "NFD5", UNIPHIER_PIN_IECTRL_NONE,
125 33, UNIPHIER_PIN_DRV_4_8,
126 33, UNIPHIER_PIN_PULL_UP),
127 UNIPHIER_PINCTRL_PIN(34, "NFD6", UNIPHIER_PIN_IECTRL_NONE,
128 34, UNIPHIER_PIN_DRV_4_8,
129 34, UNIPHIER_PIN_PULL_UP),
130 UNIPHIER_PINCTRL_PIN(35, "NFD7", UNIPHIER_PIN_IECTRL_NONE,
131 35, UNIPHIER_PIN_DRV_4_8,
132 35, UNIPHIER_PIN_PULL_UP),
133 UNIPHIER_PINCTRL_PIN(36, "XERST", UNIPHIER_PIN_IECTRL_NONE,
134 36, UNIPHIER_PIN_DRV_4_8,
135 36, UNIPHIER_PIN_PULL_UP),
136 UNIPHIER_PINCTRL_PIN(37, "MMCCLK", UNIPHIER_PIN_IECTRL_NONE,
137 37, UNIPHIER_PIN_DRV_4_8,
138 37, UNIPHIER_PIN_PULL_UP),
139 UNIPHIER_PINCTRL_PIN(38, "MMCCMD", UNIPHIER_PIN_IECTRL_NONE,
140 38, UNIPHIER_PIN_DRV_4_8,
141 38, UNIPHIER_PIN_PULL_UP),
142 UNIPHIER_PINCTRL_PIN(39, "MMCDAT0", UNIPHIER_PIN_IECTRL_NONE,
143 39, UNIPHIER_PIN_DRV_4_8,
144 39, UNIPHIER_PIN_PULL_UP),
145 UNIPHIER_PINCTRL_PIN(40, "MMCDAT1", UNIPHIER_PIN_IECTRL_NONE,
146 40, UNIPHIER_PIN_DRV_4_8,
147 40, UNIPHIER_PIN_PULL_UP),
148 UNIPHIER_PINCTRL_PIN(41, "MMCDAT2", UNIPHIER_PIN_IECTRL_NONE,
149 41, UNIPHIER_PIN_DRV_4_8,
150 41, UNIPHIER_PIN_PULL_UP),
151 UNIPHIER_PINCTRL_PIN(42, "MMCDAT3", UNIPHIER_PIN_IECTRL_NONE,
152 42, UNIPHIER_PIN_DRV_4_8,
153 42, UNIPHIER_PIN_PULL_UP),
154 UNIPHIER_PINCTRL_PIN(43, "MMCDAT4", UNIPHIER_PIN_IECTRL_NONE,
155 43, UNIPHIER_PIN_DRV_4_8,
156 43, UNIPHIER_PIN_PULL_UP),
157 UNIPHIER_PINCTRL_PIN(44, "MMCDAT5", UNIPHIER_PIN_IECTRL_NONE,
158 44, UNIPHIER_PIN_DRV_4_8,
159 44, UNIPHIER_PIN_PULL_UP),
160 UNIPHIER_PINCTRL_PIN(45, "MMCDAT6", UNIPHIER_PIN_IECTRL_NONE,
161 45, UNIPHIER_PIN_DRV_4_8,
162 45, UNIPHIER_PIN_PULL_UP),
163 UNIPHIER_PINCTRL_PIN(46, "MMCDAT7", UNIPHIER_PIN_IECTRL_NONE,
164 46, UNIPHIER_PIN_DRV_4_8,
165 46, UNIPHIER_PIN_PULL_UP),
166 UNIPHIER_PINCTRL_PIN(47, "TXD0", 0,
167 47, UNIPHIER_PIN_DRV_4_8,
168 47, UNIPHIER_PIN_PULL_UP),
169 UNIPHIER_PINCTRL_PIN(48, "RXD0", 0,
170 48, UNIPHIER_PIN_DRV_4_8,
171 48, UNIPHIER_PIN_PULL_UP),
172 UNIPHIER_PINCTRL_PIN(49, "TXD1", 0,
173 49, UNIPHIER_PIN_DRV_4_8,
174 49, UNIPHIER_PIN_PULL_UP),
175 UNIPHIER_PINCTRL_PIN(50, "RXD1", 0,
176 50, UNIPHIER_PIN_DRV_4_8,
177 50, UNIPHIER_PIN_PULL_UP),
178 UNIPHIER_PINCTRL_PIN(51, "TXD2", UNIPHIER_PIN_IECTRL_NONE,
179 51, UNIPHIER_PIN_DRV_4_8,
180 51, UNIPHIER_PIN_PULL_UP),
181 UNIPHIER_PINCTRL_PIN(52, "RXD2", UNIPHIER_PIN_IECTRL_NONE,
182 52, UNIPHIER_PIN_DRV_4_8,
183 52, UNIPHIER_PIN_PULL_UP),
184 UNIPHIER_PINCTRL_PIN(53, "TXD3", 0,
185 53, UNIPHIER_PIN_DRV_4_8,
186 53, UNIPHIER_PIN_PULL_UP),
187 UNIPHIER_PINCTRL_PIN(54, "RXD3", 0,
188 54, UNIPHIER_PIN_DRV_4_8,
189 54, UNIPHIER_PIN_PULL_UP),
190 UNIPHIER_PINCTRL_PIN(55, "MS0CS0", 0,
191 55, UNIPHIER_PIN_DRV_4_8,
192 55, UNIPHIER_PIN_PULL_DOWN),
193 UNIPHIER_PINCTRL_PIN(56, "MS0DO", 0,
194 56, UNIPHIER_PIN_DRV_4_8,
195 56, UNIPHIER_PIN_PULL_DOWN),
196 UNIPHIER_PINCTRL_PIN(57, "MS0DI", 0,
197 57, UNIPHIER_PIN_DRV_4_8,
198 57, UNIPHIER_PIN_PULL_DOWN),
199 UNIPHIER_PINCTRL_PIN(58, "MS0CLK", 0,
200 58, UNIPHIER_PIN_DRV_4_8,
201 58, UNIPHIER_PIN_PULL_DOWN),
202 UNIPHIER_PINCTRL_PIN(59, "CSCLK", 0,
203 59, UNIPHIER_PIN_DRV_4_8,
204 59, UNIPHIER_PIN_PULL_DOWN),
205 UNIPHIER_PINCTRL_PIN(60, "CSBPTM", 0,
206 60, UNIPHIER_PIN_DRV_4_8,
207 60, UNIPHIER_PIN_PULL_DOWN),
208 UNIPHIER_PINCTRL_PIN(61, "CSBMTP", 0,
209 61, UNIPHIER_PIN_DRV_4_8,
210 61, UNIPHIER_PIN_PULL_DOWN),
211 UNIPHIER_PINCTRL_PIN(62, "XCINTP", 0,
212 62, UNIPHIER_PIN_DRV_4_8,
213 62, UNIPHIER_PIN_PULL_DOWN),
214 UNIPHIER_PINCTRL_PIN(63, "XCINTM", 0,
215 63, UNIPHIER_PIN_DRV_4_8,
216 63, UNIPHIER_PIN_PULL_DOWN),
217 UNIPHIER_PINCTRL_PIN(64, "XCMPREQ", 0,
218 64, UNIPHIER_PIN_DRV_4_8,
219 64, UNIPHIER_PIN_PULL_DOWN),
220 UNIPHIER_PINCTRL_PIN(65, "XSRST", 0,
221 65, UNIPHIER_PIN_DRV_4_8,
222 65, UNIPHIER_PIN_PULL_DOWN),
223 UNIPHIER_PINCTRL_PIN(66, "LPST", UNIPHIER_PIN_IECTRL_NONE,
224 66, UNIPHIER_PIN_DRV_4_8,
225 66, UNIPHIER_PIN_PULL_DOWN),
226 UNIPHIER_PINCTRL_PIN(67, "PWMA", 0,
227 67, UNIPHIER_PIN_DRV_4_8,
228 67, UNIPHIER_PIN_PULL_DOWN),
229 UNIPHIER_PINCTRL_PIN(68, "XIRQ0", 0,
230 68, UNIPHIER_PIN_DRV_4_8,
231 68, UNIPHIER_PIN_PULL_DOWN),
232 UNIPHIER_PINCTRL_PIN(69, "XIRQ1", 0,
233 69, UNIPHIER_PIN_DRV_4_8,
234 69, UNIPHIER_PIN_PULL_DOWN),
235 UNIPHIER_PINCTRL_PIN(70, "XIRQ2", 0,
236 70, UNIPHIER_PIN_DRV_4_8,
237 70, UNIPHIER_PIN_PULL_DOWN),
238 UNIPHIER_PINCTRL_PIN(71, "XIRQ3", 0,
239 71, UNIPHIER_PIN_DRV_4_8,
240 71, UNIPHIER_PIN_PULL_DOWN),
241 UNIPHIER_PINCTRL_PIN(72, "XIRQ4", 0,
242 72, UNIPHIER_PIN_DRV_4_8,
243 72, UNIPHIER_PIN_PULL_DOWN),
244 UNIPHIER_PINCTRL_PIN(73, "XIRQ5", 0,
245 73, UNIPHIER_PIN_DRV_4_8,
246 73, UNIPHIER_PIN_PULL_DOWN),
247 UNIPHIER_PINCTRL_PIN(74, "XIRQ6", 0,
248 74, UNIPHIER_PIN_DRV_4_8,
249 74, UNIPHIER_PIN_PULL_DOWN),
250 UNIPHIER_PINCTRL_PIN(75, "XIRQ7", 0,
251 75, UNIPHIER_PIN_DRV_4_8,
252 75, UNIPHIER_PIN_PULL_DOWN),
253 UNIPHIER_PINCTRL_PIN(76, "XIRQ8", 0,
254 76, UNIPHIER_PIN_DRV_4_8,
255 76, UNIPHIER_PIN_PULL_DOWN),
256 UNIPHIER_PINCTRL_PIN(77, "XIRQ9", 0,
257 77, UNIPHIER_PIN_DRV_4_8,
258 77, UNIPHIER_PIN_PULL_DOWN),
259 UNIPHIER_PINCTRL_PIN(78, "XIRQ10", 0,
260 78, UNIPHIER_PIN_DRV_4_8,
261 78, UNIPHIER_PIN_PULL_DOWN),
262 UNIPHIER_PINCTRL_PIN(79, "XIRQ11", UNIPHIER_PIN_IECTRL_NONE,
263 -1, UNIPHIER_PIN_DRV_FIXED_8,
264 79, UNIPHIER_PIN_PULL_DOWN),
265 UNIPHIER_PINCTRL_PIN(80, "XIRQ12", UNIPHIER_PIN_IECTRL_NONE,
266 -1, UNIPHIER_PIN_DRV_FIXED_8,
267 80, UNIPHIER_PIN_PULL_DOWN),
268 UNIPHIER_PINCTRL_PIN(81, "XIRQ13", UNIPHIER_PIN_IECTRL_NONE,
269 -1, UNIPHIER_PIN_DRV_FIXED_8,
270 81, UNIPHIER_PIN_PULL_DOWN),
271 UNIPHIER_PINCTRL_PIN(82, "XIRQ14", 0,
272 82, UNIPHIER_PIN_DRV_4_8,
273 82, UNIPHIER_PIN_PULL_DOWN),
274 UNIPHIER_PINCTRL_PIN(83, "XIRQ15", 0,
275 83, UNIPHIER_PIN_DRV_4_8,
276 83, UNIPHIER_PIN_PULL_DOWN),
277 UNIPHIER_PINCTRL_PIN(84, "XIRQ16", 0,
278 84, UNIPHIER_PIN_DRV_4_8,
279 84, UNIPHIER_PIN_PULL_DOWN),
280 UNIPHIER_PINCTRL_PIN(85, "XIRQ17", UNIPHIER_PIN_IECTRL_NONE,
281 -1, UNIPHIER_PIN_DRV_FIXED_8,
282 85, UNIPHIER_PIN_PULL_DOWN),
283 UNIPHIER_PINCTRL_PIN(86, "XIRQ18", UNIPHIER_PIN_IECTRL_NONE,
284 -1, UNIPHIER_PIN_DRV_FIXED_8,
285 86, UNIPHIER_PIN_PULL_DOWN),
286 UNIPHIER_PINCTRL_PIN(87, "XIRQ19", 0,
287 87, UNIPHIER_PIN_DRV_4_8,
288 87, UNIPHIER_PIN_PULL_DOWN),
289 UNIPHIER_PINCTRL_PIN(88, "XIRQ20", 0,
290 88, UNIPHIER_PIN_DRV_4_8,
291 88, UNIPHIER_PIN_PULL_DOWN),
292 UNIPHIER_PINCTRL_PIN(89, "PORT00", 0,
293 89, UNIPHIER_PIN_DRV_4_8,
294 89, UNIPHIER_PIN_PULL_DOWN),
295 UNIPHIER_PINCTRL_PIN(90, "PORT01", 0,
296 90, UNIPHIER_PIN_DRV_4_8,
297 90, UNIPHIER_PIN_PULL_DOWN),
298 UNIPHIER_PINCTRL_PIN(91, "PORT02", 0,
299 91, UNIPHIER_PIN_DRV_4_8,
300 91, UNIPHIER_PIN_PULL_DOWN),
301 UNIPHIER_PINCTRL_PIN(92, "PORT03", 0,
302 92, UNIPHIER_PIN_DRV_4_8,
303 92, UNIPHIER_PIN_PULL_DOWN),
304 UNIPHIER_PINCTRL_PIN(93, "PORT04", 0,
305 93, UNIPHIER_PIN_DRV_4_8,
306 93, UNIPHIER_PIN_PULL_DOWN),
307 UNIPHIER_PINCTRL_PIN(94, "PORT05", 0,
308 94, UNIPHIER_PIN_DRV_4_8,
309 94, UNIPHIER_PIN_PULL_DOWN),
310 UNIPHIER_PINCTRL_PIN(95, "PORT06", 0,
311 95, UNIPHIER_PIN_DRV_4_8,
312 95, UNIPHIER_PIN_PULL_DOWN),
313 UNIPHIER_PINCTRL_PIN(96, "PORT07", 0,
314 96, UNIPHIER_PIN_DRV_4_8,
315 96, UNIPHIER_PIN_PULL_DOWN),
316 UNIPHIER_PINCTRL_PIN(97, "PORT10", 0,
317 97, UNIPHIER_PIN_DRV_4_8,
318 97, UNIPHIER_PIN_PULL_DOWN),
319 UNIPHIER_PINCTRL_PIN(98, "PORT11", 0,
320 98, UNIPHIER_PIN_DRV_4_8,
321 98, UNIPHIER_PIN_PULL_DOWN),
322 UNIPHIER_PINCTRL_PIN(99, "PORT12", 0,
323 99, UNIPHIER_PIN_DRV_4_8,
324 99, UNIPHIER_PIN_PULL_DOWN),
325 UNIPHIER_PINCTRL_PIN(100, "PORT13", 0,
326 100, UNIPHIER_PIN_DRV_4_8,
327 100, UNIPHIER_PIN_PULL_DOWN),
328 UNIPHIER_PINCTRL_PIN(101, "PORT14", 0,
329 101, UNIPHIER_PIN_DRV_4_8,
330 101, UNIPHIER_PIN_PULL_DOWN),
331 UNIPHIER_PINCTRL_PIN(102, "PORT15", 0,
332 102, UNIPHIER_PIN_DRV_4_8,
333 102, UNIPHIER_PIN_PULL_DOWN),
334 UNIPHIER_PINCTRL_PIN(103, "PORT16", 0,
335 103, UNIPHIER_PIN_DRV_4_8,
336 103, UNIPHIER_PIN_PULL_DOWN),
337 UNIPHIER_PINCTRL_PIN(104, "PORT17", 0,
338 104, UNIPHIER_PIN_DRV_4_8,
339 104, UNIPHIER_PIN_PULL_DOWN),
340 UNIPHIER_PINCTRL_PIN(105, "T0HPD", 0,
341 105, UNIPHIER_PIN_DRV_4_8,
342 105, UNIPHIER_PIN_PULL_DOWN),
343 UNIPHIER_PINCTRL_PIN(106, "T1HPD", 0,
344 106, UNIPHIER_PIN_DRV_4_8,
345 106, UNIPHIER_PIN_PULL_DOWN),
346 UNIPHIER_PINCTRL_PIN(107, "R0HPD", 0,
347 107, UNIPHIER_PIN_DRV_4_8,
348 107, UNIPHIER_PIN_PULL_DOWN),
349 UNIPHIER_PINCTRL_PIN(108, "R1HPD", 0,
350 108, UNIPHIER_PIN_DRV_4_8,
351 108, UNIPHIER_PIN_PULL_DOWN),
352 UNIPHIER_PINCTRL_PIN(109, "XPERST", 0,
353 109, UNIPHIER_PIN_DRV_4_8,
354 109, UNIPHIER_PIN_PULL_UP),
355 UNIPHIER_PINCTRL_PIN(110, "XPEWAKE", 0,
356 110, UNIPHIER_PIN_DRV_4_8,
357 110, UNIPHIER_PIN_PULL_UP),
358 UNIPHIER_PINCTRL_PIN(111, "XPECLKRQ", 0,
359 111, UNIPHIER_PIN_DRV_4_8,
360 111, UNIPHIER_PIN_PULL_UP),
361 UNIPHIER_PINCTRL_PIN(112, "SDA0", UNIPHIER_PIN_IECTRL_NONE,
362 -1, UNIPHIER_PIN_DRV_FIXED_8,
363 112, UNIPHIER_PIN_PULL_UP),
364 UNIPHIER_PINCTRL_PIN(113, "SCL0", UNIPHIER_PIN_IECTRL_NONE,
365 -1, UNIPHIER_PIN_DRV_FIXED_8,
366 113, UNIPHIER_PIN_PULL_UP),
367 UNIPHIER_PINCTRL_PIN(114, "SDA1", UNIPHIER_PIN_IECTRL_NONE,
368 -1, UNIPHIER_PIN_DRV_FIXED_8,
369 114, UNIPHIER_PIN_PULL_UP),
370 UNIPHIER_PINCTRL_PIN(115, "SCL1", UNIPHIER_PIN_IECTRL_NONE,
371 -1, UNIPHIER_PIN_DRV_FIXED_8,
372 115, UNIPHIER_PIN_PULL_UP),
373 UNIPHIER_PINCTRL_PIN(116, "SDA2", UNIPHIER_PIN_IECTRL_NONE,
374 -1, UNIPHIER_PIN_DRV_FIXED_8,
375 116, UNIPHIER_PIN_PULL_UP),
376 UNIPHIER_PINCTRL_PIN(117, "SCL2", UNIPHIER_PIN_IECTRL_NONE,
377 -1, UNIPHIER_PIN_DRV_FIXED_8,
378 117, UNIPHIER_PIN_PULL_UP),
379 UNIPHIER_PINCTRL_PIN(118, "SDA3", UNIPHIER_PIN_IECTRL_NONE,
380 -1, UNIPHIER_PIN_DRV_FIXED_4,
381 118, UNIPHIER_PIN_PULL_UP),
382 UNIPHIER_PINCTRL_PIN(119, "SCL3", UNIPHIER_PIN_IECTRL_NONE,
383 -1, UNIPHIER_PIN_DRV_FIXED_4,
384 119, UNIPHIER_PIN_PULL_UP),
385 UNIPHIER_PINCTRL_PIN(120, "SPISYNC", UNIPHIER_PIN_IECTRL_NONE,
386 -1, UNIPHIER_PIN_DRV_FIXED_8,
387 120, UNIPHIER_PIN_PULL_DOWN),
388 UNIPHIER_PINCTRL_PIN(121, "SPISCLK", UNIPHIER_PIN_IECTRL_NONE,
389 -1, UNIPHIER_PIN_DRV_FIXED_8,
390 121, UNIPHIER_PIN_PULL_DOWN),
391 UNIPHIER_PINCTRL_PIN(122, "SPITXD", UNIPHIER_PIN_IECTRL_NONE,
392 -1, UNIPHIER_PIN_DRV_FIXED_8,
393 122, UNIPHIER_PIN_PULL_DOWN),
394 UNIPHIER_PINCTRL_PIN(123, "SPIRXD", UNIPHIER_PIN_IECTRL_NONE,
395 -1, UNIPHIER_PIN_DRV_FIXED_8,
396 123, UNIPHIER_PIN_PULL_DOWN),
397 UNIPHIER_PINCTRL_PIN(124, "USB0VBUS", UNIPHIER_PIN_IECTRL_NONE,
398 -1, UNIPHIER_PIN_DRV_FIXED_8,
399 124, UNIPHIER_PIN_PULL_DOWN),
400 UNIPHIER_PINCTRL_PIN(125, "USB0OD", UNIPHIER_PIN_IECTRL_NONE,
401 -1, UNIPHIER_PIN_DRV_FIXED_8,
402 125, UNIPHIER_PIN_PULL_UP),
403 UNIPHIER_PINCTRL_PIN(126, "USB1VBUS", UNIPHIER_PIN_IECTRL_NONE,
404 -1, UNIPHIER_PIN_DRV_FIXED_8,
405 126, UNIPHIER_PIN_PULL_DOWN),
406 UNIPHIER_PINCTRL_PIN(127, "USB1OD", UNIPHIER_PIN_IECTRL_NONE,
407 -1, UNIPHIER_PIN_DRV_FIXED_8,
408 127, UNIPHIER_PIN_PULL_UP),
409 UNIPHIER_PINCTRL_PIN(128, "USB2VBUS", UNIPHIER_PIN_IECTRL_NONE,
410 -1, UNIPHIER_PIN_DRV_FIXED_8,
411 128, UNIPHIER_PIN_PULL_DOWN),
412 UNIPHIER_PINCTRL_PIN(129, "USB2OD", UNIPHIER_PIN_IECTRL_NONE,
413 -1, UNIPHIER_PIN_DRV_FIXED_8,
414 129, UNIPHIER_PIN_PULL_UP),
415 UNIPHIER_PINCTRL_PIN(130, "SMTRST0", UNIPHIER_PIN_IECTRL_NONE,
416 -1, UNIPHIER_PIN_DRV_FIXED_8,
417 130, UNIPHIER_PIN_PULL_DOWN),
418 UNIPHIER_PINCTRL_PIN(131, "SMTCMD0", UNIPHIER_PIN_IECTRL_NONE,
419 -1, UNIPHIER_PIN_DRV_FIXED_8,
420 131, UNIPHIER_PIN_PULL_DOWN),
421 UNIPHIER_PINCTRL_PIN(132, "SMTD0", UNIPHIER_PIN_IECTRL_NONE,
422 -1, UNIPHIER_PIN_DRV_FIXED_8,
423 132, UNIPHIER_PIN_PULL_DOWN),
424 UNIPHIER_PINCTRL_PIN(133, "SMTSEL0", UNIPHIER_PIN_IECTRL_NONE,
425 -1, UNIPHIER_PIN_DRV_FIXED_8,
426 133, UNIPHIER_PIN_PULL_DOWN),
427 UNIPHIER_PINCTRL_PIN(134, "SMTCLK0", UNIPHIER_PIN_IECTRL_NONE,
428 -1, UNIPHIER_PIN_DRV_FIXED_8,
429 134, UNIPHIER_PIN_PULL_DOWN),
430 UNIPHIER_PINCTRL_PIN(135, "SMTRST1", UNIPHIER_PIN_IECTRL_NONE,
431 -1, UNIPHIER_PIN_DRV_FIXED_8,
432 135, UNIPHIER_PIN_PULL_DOWN),
433 UNIPHIER_PINCTRL_PIN(136, "SMTCMD1", UNIPHIER_PIN_IECTRL_NONE,
434 -1, UNIPHIER_PIN_DRV_FIXED_8,
435 136, UNIPHIER_PIN_PULL_DOWN),
436 UNIPHIER_PINCTRL_PIN(137, "SMTD1", UNIPHIER_PIN_IECTRL_NONE,
437 -1, UNIPHIER_PIN_DRV_FIXED_8,
438 137, UNIPHIER_PIN_PULL_DOWN),
439 UNIPHIER_PINCTRL_PIN(138, "SMTSEL1", UNIPHIER_PIN_IECTRL_NONE,
440 -1, UNIPHIER_PIN_DRV_FIXED_8,
441 138, UNIPHIER_PIN_PULL_DOWN),
442 UNIPHIER_PINCTRL_PIN(139, "SMTCLK1", UNIPHIER_PIN_IECTRL_NONE,
443 -1, UNIPHIER_PIN_DRV_FIXED_8,
444 139, UNIPHIER_PIN_PULL_DOWN),
445 UNIPHIER_PINCTRL_PIN(140, "CH0CLK", UNIPHIER_PIN_IECTRL_NONE,
446 -1, UNIPHIER_PIN_DRV_FIXED_8,
447 140, UNIPHIER_PIN_PULL_DOWN),
448 UNIPHIER_PINCTRL_PIN(141, "CH0PSYNC", UNIPHIER_PIN_IECTRL_NONE,
449 -1, UNIPHIER_PIN_DRV_FIXED_8,
450 141, UNIPHIER_PIN_PULL_DOWN),
451 UNIPHIER_PINCTRL_PIN(142, "CH0VAL", UNIPHIER_PIN_IECTRL_NONE,
452 -1, UNIPHIER_PIN_DRV_FIXED_8,
453 142, UNIPHIER_PIN_PULL_DOWN),
454 UNIPHIER_PINCTRL_PIN(143, "CH0DATA", UNIPHIER_PIN_IECTRL_NONE,
455 -1, UNIPHIER_PIN_DRV_FIXED_8,
456 143, UNIPHIER_PIN_PULL_DOWN),
457 UNIPHIER_PINCTRL_PIN(144, "CH1CLK", UNIPHIER_PIN_IECTRL_NONE,
458 -1, UNIPHIER_PIN_DRV_FIXED_8,
459 144, UNIPHIER_PIN_PULL_DOWN),
460 UNIPHIER_PINCTRL_PIN(145, "CH1PSYNC", UNIPHIER_PIN_IECTRL_NONE,
461 -1, UNIPHIER_PIN_DRV_FIXED_8,
462 145, UNIPHIER_PIN_PULL_DOWN),
463 UNIPHIER_PINCTRL_PIN(146, "CH1VAL", UNIPHIER_PIN_IECTRL_NONE,
464 -1, UNIPHIER_PIN_DRV_FIXED_8,
465 146, UNIPHIER_PIN_PULL_DOWN),
466 UNIPHIER_PINCTRL_PIN(147, "CH1DATA", UNIPHIER_PIN_IECTRL_NONE,
467 -1, UNIPHIER_PIN_DRV_FIXED_8,
468 147, UNIPHIER_PIN_PULL_DOWN),
469 UNIPHIER_PINCTRL_PIN(148, "CH2CLK", UNIPHIER_PIN_IECTRL_NONE,
470 -1, UNIPHIER_PIN_DRV_FIXED_8,
471 148, UNIPHIER_PIN_PULL_DOWN),
472 UNIPHIER_PINCTRL_PIN(149, "CH2PSYNC", UNIPHIER_PIN_IECTRL_NONE,
473 -1, UNIPHIER_PIN_DRV_FIXED_8,
474 149, UNIPHIER_PIN_PULL_DOWN),
475 UNIPHIER_PINCTRL_PIN(150, "CH2VAL", UNIPHIER_PIN_IECTRL_NONE,
476 -1, UNIPHIER_PIN_DRV_FIXED_8,
477 150, UNIPHIER_PIN_PULL_DOWN),
478 UNIPHIER_PINCTRL_PIN(151, "CH2DATA", UNIPHIER_PIN_IECTRL_NONE,
479 -1, UNIPHIER_PIN_DRV_FIXED_8,
480 151, UNIPHIER_PIN_PULL_DOWN),
481 UNIPHIER_PINCTRL_PIN(152, "CH3CLK", UNIPHIER_PIN_IECTRL_NONE,
482 -1, UNIPHIER_PIN_DRV_FIXED_8,
483 152, UNIPHIER_PIN_PULL_DOWN),
484 UNIPHIER_PINCTRL_PIN(153, "CH3PSYNC", UNIPHIER_PIN_IECTRL_NONE,
485 -1, UNIPHIER_PIN_DRV_FIXED_8,
486 153, UNIPHIER_PIN_PULL_DOWN),
487 UNIPHIER_PINCTRL_PIN(154, "CH3VAL", UNIPHIER_PIN_IECTRL_NONE,
488 -1, UNIPHIER_PIN_DRV_FIXED_8,
489 154, UNIPHIER_PIN_PULL_DOWN),
490 UNIPHIER_PINCTRL_PIN(155, "CH3DATA", UNIPHIER_PIN_IECTRL_NONE,
491 -1, UNIPHIER_PIN_DRV_FIXED_8,
492 155, UNIPHIER_PIN_PULL_DOWN),
493 UNIPHIER_PINCTRL_PIN(156, "CH4CLK", UNIPHIER_PIN_IECTRL_NONE,
494 -1, UNIPHIER_PIN_DRV_FIXED_8,
495 156, UNIPHIER_PIN_PULL_DOWN),
496 UNIPHIER_PINCTRL_PIN(157, "CH4PSYNC", UNIPHIER_PIN_IECTRL_NONE,
497 -1, UNIPHIER_PIN_DRV_FIXED_8,
498 157, UNIPHIER_PIN_PULL_DOWN),
499 UNIPHIER_PINCTRL_PIN(158, "CH4VAL", UNIPHIER_PIN_IECTRL_NONE,
500 -1, UNIPHIER_PIN_DRV_FIXED_8,
501 158, UNIPHIER_PIN_PULL_DOWN),
502 UNIPHIER_PINCTRL_PIN(159, "CH4DATA", UNIPHIER_PIN_IECTRL_NONE,
503 -1, UNIPHIER_PIN_DRV_FIXED_8,
504 159, UNIPHIER_PIN_PULL_DOWN),
505 UNIPHIER_PINCTRL_PIN(160, "CH5CLK", UNIPHIER_PIN_IECTRL_NONE,
506 -1, UNIPHIER_PIN_DRV_FIXED_8,
507 160, UNIPHIER_PIN_PULL_DOWN),
508 UNIPHIER_PINCTRL_PIN(161, "CH5PSYNC", UNIPHIER_PIN_IECTRL_NONE,
509 -1, UNIPHIER_PIN_DRV_FIXED_8,
510 161, UNIPHIER_PIN_PULL_DOWN),
511 UNIPHIER_PINCTRL_PIN(162, "CH5VAL", UNIPHIER_PIN_IECTRL_NONE,
512 -1, UNIPHIER_PIN_DRV_FIXED_8,
513 162, UNIPHIER_PIN_PULL_DOWN),
514 UNIPHIER_PINCTRL_PIN(163, "CH5DATA", UNIPHIER_PIN_IECTRL_NONE,
515 -1, UNIPHIER_PIN_DRV_FIXED_8,
516 163, UNIPHIER_PIN_PULL_DOWN),
517 UNIPHIER_PINCTRL_PIN(164, "CH6CLK", UNIPHIER_PIN_IECTRL_NONE,
518 -1, UNIPHIER_PIN_DRV_FIXED_8,
519 164, UNIPHIER_PIN_PULL_DOWN),
520 UNIPHIER_PINCTRL_PIN(165, "CH6PSYNC", UNIPHIER_PIN_IECTRL_NONE,
521 -1, UNIPHIER_PIN_DRV_FIXED_8,
522 165, UNIPHIER_PIN_PULL_DOWN),
523 UNIPHIER_PINCTRL_PIN(166, "CH6VAL", UNIPHIER_PIN_IECTRL_NONE,
524 -1, UNIPHIER_PIN_DRV_FIXED_8,
525 166, UNIPHIER_PIN_PULL_DOWN),
526 UNIPHIER_PINCTRL_PIN(167, "CH6DATA", UNIPHIER_PIN_IECTRL_NONE,
527 -1, UNIPHIER_PIN_DRV_FIXED_8,
528 167, UNIPHIER_PIN_PULL_DOWN),
529 UNIPHIER_PINCTRL_PIN(168, "CH7CLK", UNIPHIER_PIN_IECTRL_NONE,
530 -1, UNIPHIER_PIN_DRV_FIXED_8,
531 168, UNIPHIER_PIN_PULL_DOWN),
532 UNIPHIER_PINCTRL_PIN(169, "CH7PSYNC", UNIPHIER_PIN_IECTRL_NONE,
533 -1, UNIPHIER_PIN_DRV_FIXED_8,
534 169, UNIPHIER_PIN_PULL_DOWN),
535 UNIPHIER_PINCTRL_PIN(170, "CH7VAL", UNIPHIER_PIN_IECTRL_NONE,
536 -1, UNIPHIER_PIN_DRV_FIXED_8,
537 170, UNIPHIER_PIN_PULL_DOWN),
538 UNIPHIER_PINCTRL_PIN(171, "CH7DATA", UNIPHIER_PIN_IECTRL_NONE,
539 -1, UNIPHIER_PIN_DRV_FIXED_8,
540 171, UNIPHIER_PIN_PULL_DOWN),
541 UNIPHIER_PINCTRL_PIN(172, "AI1ADCCK", UNIPHIER_PIN_IECTRL_NONE,
542 -1, UNIPHIER_PIN_DRV_FIXED_8,
543 172, UNIPHIER_PIN_PULL_DOWN),
544 UNIPHIER_PINCTRL_PIN(173, "AI1BCK", UNIPHIER_PIN_IECTRL_NONE,
545 -1, UNIPHIER_PIN_DRV_FIXED_8,
546 173, UNIPHIER_PIN_PULL_DOWN),
547 UNIPHIER_PINCTRL_PIN(174, "AI1LRCK", UNIPHIER_PIN_IECTRL_NONE,
548 -1, UNIPHIER_PIN_DRV_FIXED_8,
549 174, UNIPHIER_PIN_PULL_DOWN),
550 UNIPHIER_PINCTRL_PIN(175, "AI1D0", UNIPHIER_PIN_IECTRL_NONE,
551 -1, UNIPHIER_PIN_DRV_FIXED_8,
552 175, UNIPHIER_PIN_PULL_DOWN),
553 UNIPHIER_PINCTRL_PIN(176, "AI1D1", UNIPHIER_PIN_IECTRL_NONE,
554 -1, UNIPHIER_PIN_DRV_FIXED_8,
555 176, UNIPHIER_PIN_PULL_DOWN),
556 UNIPHIER_PINCTRL_PIN(177, "AI1D2", UNIPHIER_PIN_IECTRL_NONE,
557 -1, UNIPHIER_PIN_DRV_FIXED_8,
558 177, UNIPHIER_PIN_PULL_DOWN),
559 UNIPHIER_PINCTRL_PIN(178, "AI1D3", UNIPHIER_PIN_IECTRL_NONE,
560 -1, UNIPHIER_PIN_DRV_FIXED_8,
561 178, UNIPHIER_PIN_PULL_DOWN),
562 UNIPHIER_PINCTRL_PIN(179, "AI2ADCCK", UNIPHIER_PIN_IECTRL_NONE,
563 -1, UNIPHIER_PIN_DRV_FIXED_8,
564 179, UNIPHIER_PIN_PULL_DOWN),
565 UNIPHIER_PINCTRL_PIN(180, "AI2BCK", UNIPHIER_PIN_IECTRL_NONE,
566 -1, UNIPHIER_PIN_DRV_FIXED_8,
567 180, UNIPHIER_PIN_PULL_DOWN),
568 UNIPHIER_PINCTRL_PIN(181, "AI2LRCK", UNIPHIER_PIN_IECTRL_NONE,
569 -1, UNIPHIER_PIN_DRV_FIXED_8,
570 181, UNIPHIER_PIN_PULL_DOWN),
571 UNIPHIER_PINCTRL_PIN(182, "AI2D0", UNIPHIER_PIN_IECTRL_NONE,
572 -1, UNIPHIER_PIN_DRV_FIXED_8,
573 182, UNIPHIER_PIN_PULL_DOWN),
574 UNIPHIER_PINCTRL_PIN(183, "AI2D1", UNIPHIER_PIN_IECTRL_NONE,
575 -1, UNIPHIER_PIN_DRV_FIXED_8,
576 183, UNIPHIER_PIN_PULL_DOWN),
577 UNIPHIER_PINCTRL_PIN(184, "AI2D2", UNIPHIER_PIN_IECTRL_NONE,
578 -1, UNIPHIER_PIN_DRV_FIXED_8,
579 184, UNIPHIER_PIN_PULL_DOWN),
580 UNIPHIER_PINCTRL_PIN(185, "AI2D3", UNIPHIER_PIN_IECTRL_NONE,
581 -1, UNIPHIER_PIN_DRV_FIXED_8,
582 185, UNIPHIER_PIN_PULL_DOWN),
583 UNIPHIER_PINCTRL_PIN(186, "AI3ADCCK", UNIPHIER_PIN_IECTRL_NONE,
584 -1, UNIPHIER_PIN_DRV_FIXED_8,
585 186, UNIPHIER_PIN_PULL_DOWN),
586 UNIPHIER_PINCTRL_PIN(187, "AI3BCK", UNIPHIER_PIN_IECTRL_NONE,
587 -1, UNIPHIER_PIN_DRV_FIXED_8,
588 187, UNIPHIER_PIN_PULL_DOWN),
589 UNIPHIER_PINCTRL_PIN(188, "AI3LRCK", UNIPHIER_PIN_IECTRL_NONE,
590 -1, UNIPHIER_PIN_DRV_FIXED_8,
591 188, UNIPHIER_PIN_PULL_DOWN),
592 UNIPHIER_PINCTRL_PIN(189, "AI3D0", UNIPHIER_PIN_IECTRL_NONE,
593 -1, UNIPHIER_PIN_DRV_FIXED_8,
594 189, UNIPHIER_PIN_PULL_DOWN),
595 UNIPHIER_PINCTRL_PIN(190, "AO1IEC", UNIPHIER_PIN_IECTRL_NONE,
596 -1, UNIPHIER_PIN_DRV_FIXED_8,
597 190, UNIPHIER_PIN_PULL_DOWN),
598 UNIPHIER_PINCTRL_PIN(191, "AO1DACCK", UNIPHIER_PIN_IECTRL_NONE,
599 -1, UNIPHIER_PIN_DRV_FIXED_8,
600 191, UNIPHIER_PIN_PULL_DOWN),
601 UNIPHIER_PINCTRL_PIN(192, "AO1BCK", UNIPHIER_PIN_IECTRL_NONE,
602 -1, UNIPHIER_PIN_DRV_FIXED_8,
603 192, UNIPHIER_PIN_PULL_DOWN),
604 UNIPHIER_PINCTRL_PIN(193, "AO1LRCK", UNIPHIER_PIN_IECTRL_NONE,
605 -1, UNIPHIER_PIN_DRV_FIXED_8,
606 193, UNIPHIER_PIN_PULL_DOWN),
607 UNIPHIER_PINCTRL_PIN(194, "AO1D0", UNIPHIER_PIN_IECTRL_NONE,
608 -1, UNIPHIER_PIN_DRV_FIXED_8,
609 194, UNIPHIER_PIN_PULL_DOWN),
610 UNIPHIER_PINCTRL_PIN(195, "AO1D1", UNIPHIER_PIN_IECTRL_NONE,
611 -1, UNIPHIER_PIN_DRV_FIXED_8,
612 195, UNIPHIER_PIN_PULL_DOWN),
613 UNIPHIER_PINCTRL_PIN(196, "AO1D2", UNIPHIER_PIN_IECTRL_NONE,
614 -1, UNIPHIER_PIN_DRV_FIXED_8,
615 196, UNIPHIER_PIN_PULL_UP),
616 UNIPHIER_PINCTRL_PIN(197, "AO1D3", UNIPHIER_PIN_IECTRL_NONE,
617 -1, UNIPHIER_PIN_DRV_FIXED_8,
618 197, UNIPHIER_PIN_PULL_UP),
619 UNIPHIER_PINCTRL_PIN(198, "AO2IEC", UNIPHIER_PIN_IECTRL_NONE,
620 -1, UNIPHIER_PIN_DRV_FIXED_8,
621 198, UNIPHIER_PIN_PULL_DOWN),
622 UNIPHIER_PINCTRL_PIN(199, "AO2DACCK", UNIPHIER_PIN_IECTRL_NONE,
623 -1, UNIPHIER_PIN_DRV_FIXED_8,
624 199, UNIPHIER_PIN_PULL_DOWN),
625 UNIPHIER_PINCTRL_PIN(200, "AO2BCK", UNIPHIER_PIN_IECTRL_NONE,
626 -1, UNIPHIER_PIN_DRV_FIXED_8,
627 200, UNIPHIER_PIN_PULL_DOWN),
628 UNIPHIER_PINCTRL_PIN(201, "AO2LRCK", UNIPHIER_PIN_IECTRL_NONE,
629 -1, UNIPHIER_PIN_DRV_FIXED_8,
630 201, UNIPHIER_PIN_PULL_DOWN),
631 UNIPHIER_PINCTRL_PIN(202, "AO2D0", UNIPHIER_PIN_IECTRL_NONE,
632 -1, UNIPHIER_PIN_DRV_FIXED_8,
633 202, UNIPHIER_PIN_PULL_DOWN),
634 UNIPHIER_PINCTRL_PIN(203, "AO2D1", UNIPHIER_PIN_IECTRL_NONE,
635 -1, UNIPHIER_PIN_DRV_FIXED_8,
636 203, UNIPHIER_PIN_PULL_DOWN),
637 UNIPHIER_PINCTRL_PIN(204, "AO2D2", UNIPHIER_PIN_IECTRL_NONE,
638 -1, UNIPHIER_PIN_DRV_FIXED_8,
639 204, UNIPHIER_PIN_PULL_DOWN),
640 UNIPHIER_PINCTRL_PIN(205, "AO2D3", UNIPHIER_PIN_IECTRL_NONE,
641 -1, UNIPHIER_PIN_DRV_FIXED_8,
642 205, UNIPHIER_PIN_PULL_DOWN),
643 UNIPHIER_PINCTRL_PIN(206, "AO3DACCK", UNIPHIER_PIN_IECTRL_NONE,
644 -1, UNIPHIER_PIN_DRV_FIXED_8,
645 206, UNIPHIER_PIN_PULL_DOWN),
646 UNIPHIER_PINCTRL_PIN(207, "AO3BCK", UNIPHIER_PIN_IECTRL_NONE,
647 -1, UNIPHIER_PIN_DRV_FIXED_8,
648 207, UNIPHIER_PIN_PULL_DOWN),
649 UNIPHIER_PINCTRL_PIN(208, "AO3LRCK", UNIPHIER_PIN_IECTRL_NONE,
650 -1, UNIPHIER_PIN_DRV_FIXED_8,
651 208, UNIPHIER_PIN_PULL_DOWN),
652 UNIPHIER_PINCTRL_PIN(209, "AO3DMIX", UNIPHIER_PIN_IECTRL_NONE,
653 -1, UNIPHIER_PIN_DRV_FIXED_8,
654 209, UNIPHIER_PIN_PULL_DOWN),
655 UNIPHIER_PINCTRL_PIN(210, "AO4DACCK", UNIPHIER_PIN_IECTRL_NONE,
656 -1, UNIPHIER_PIN_DRV_FIXED_8,
657 210, UNIPHIER_PIN_PULL_DOWN),
658 UNIPHIER_PINCTRL_PIN(211, "AO4BCK", UNIPHIER_PIN_IECTRL_NONE,
659 -1, UNIPHIER_PIN_DRV_FIXED_8,
660 211, UNIPHIER_PIN_PULL_DOWN),
661 UNIPHIER_PINCTRL_PIN(212, "AO4LRCK", UNIPHIER_PIN_IECTRL_NONE,
662 -1, UNIPHIER_PIN_DRV_FIXED_8,
663 212, UNIPHIER_PIN_PULL_DOWN),
664 UNIPHIER_PINCTRL_PIN(213, "AO4DMIX", UNIPHIER_PIN_IECTRL_NONE,
665 -1, UNIPHIER_PIN_DRV_FIXED_8,
666 213, UNIPHIER_PIN_PULL_DOWN),
667 UNIPHIER_PINCTRL_PIN(214, "VI1CLK", UNIPHIER_PIN_IECTRL_NONE,
668 -1, UNIPHIER_PIN_DRV_FIXED_8,
669 214, UNIPHIER_PIN_PULL_DOWN),
670 UNIPHIER_PINCTRL_PIN(215, "VI1C0", UNIPHIER_PIN_IECTRL_NONE,
671 -1, UNIPHIER_PIN_DRV_FIXED_8,
672 215, UNIPHIER_PIN_PULL_DOWN),
673 UNIPHIER_PINCTRL_PIN(216, "VI1C1", UNIPHIER_PIN_IECTRL_NONE,
674 -1, UNIPHIER_PIN_DRV_FIXED_8,
675 216, UNIPHIER_PIN_PULL_DOWN),
676 UNIPHIER_PINCTRL_PIN(217, "VI1C2", UNIPHIER_PIN_IECTRL_NONE,
677 -1, UNIPHIER_PIN_DRV_FIXED_8,
678 217, UNIPHIER_PIN_PULL_DOWN),
679 UNIPHIER_PINCTRL_PIN(218, "VI1C3", UNIPHIER_PIN_IECTRL_NONE,
680 -1, UNIPHIER_PIN_DRV_FIXED_8,
681 218, UNIPHIER_PIN_PULL_DOWN),
682 UNIPHIER_PINCTRL_PIN(219, "VI1C4", UNIPHIER_PIN_IECTRL_NONE,
683 -1, UNIPHIER_PIN_DRV_FIXED_8,
684 219, UNIPHIER_PIN_PULL_DOWN),
685 UNIPHIER_PINCTRL_PIN(220, "VI1C5", UNIPHIER_PIN_IECTRL_NONE,
686 -1, UNIPHIER_PIN_DRV_FIXED_8,
687 220, UNIPHIER_PIN_PULL_DOWN),
688 UNIPHIER_PINCTRL_PIN(221, "VI1C6", UNIPHIER_PIN_IECTRL_NONE,
689 -1, UNIPHIER_PIN_DRV_FIXED_8,
690 221, UNIPHIER_PIN_PULL_DOWN),
691 UNIPHIER_PINCTRL_PIN(222, "VI1C7", UNIPHIER_PIN_IECTRL_NONE,
692 -1, UNIPHIER_PIN_DRV_FIXED_8,
693 222, UNIPHIER_PIN_PULL_DOWN),
694 UNIPHIER_PINCTRL_PIN(223, "VI1C8", UNIPHIER_PIN_IECTRL_NONE,
695 -1, UNIPHIER_PIN_DRV_FIXED_8,
696 223, UNIPHIER_PIN_PULL_DOWN),
697 UNIPHIER_PINCTRL_PIN(224, "VI1C9", UNIPHIER_PIN_IECTRL_NONE,
698 -1, UNIPHIER_PIN_DRV_FIXED_8,
699 224, UNIPHIER_PIN_PULL_DOWN),
700 UNIPHIER_PINCTRL_PIN(225, "VI1Y0", UNIPHIER_PIN_IECTRL_NONE,
701 -1, UNIPHIER_PIN_DRV_FIXED_8,
702 225, UNIPHIER_PIN_PULL_DOWN),
703 UNIPHIER_PINCTRL_PIN(226, "VI1Y1", UNIPHIER_PIN_IECTRL_NONE,
704 -1, UNIPHIER_PIN_DRV_FIXED_8,
705 226, UNIPHIER_PIN_PULL_DOWN),
706 UNIPHIER_PINCTRL_PIN(227, "VI1Y2", UNIPHIER_PIN_IECTRL_NONE,
707 -1, UNIPHIER_PIN_DRV_FIXED_8,
708 227, UNIPHIER_PIN_PULL_DOWN),
709 UNIPHIER_PINCTRL_PIN(228, "VI1Y3", UNIPHIER_PIN_IECTRL_NONE,
710 -1, UNIPHIER_PIN_DRV_FIXED_8,
711 228, UNIPHIER_PIN_PULL_DOWN),
712 UNIPHIER_PINCTRL_PIN(229, "VI1Y4", UNIPHIER_PIN_IECTRL_NONE,
713 -1, UNIPHIER_PIN_DRV_FIXED_8,
714 229, UNIPHIER_PIN_PULL_DOWN),
715 UNIPHIER_PINCTRL_PIN(230, "VI1Y5", UNIPHIER_PIN_IECTRL_NONE,
716 -1, UNIPHIER_PIN_DRV_FIXED_8,
717 230, UNIPHIER_PIN_PULL_DOWN),
718 UNIPHIER_PINCTRL_PIN(231, "VI1Y6", UNIPHIER_PIN_IECTRL_NONE,
719 -1, UNIPHIER_PIN_DRV_FIXED_8,
720 231, UNIPHIER_PIN_PULL_DOWN),
721 UNIPHIER_PINCTRL_PIN(232, "VI1Y7", UNIPHIER_PIN_IECTRL_NONE,
722 -1, UNIPHIER_PIN_DRV_FIXED_8,
723 232, UNIPHIER_PIN_PULL_DOWN),
724 UNIPHIER_PINCTRL_PIN(233, "VI1Y8", UNIPHIER_PIN_IECTRL_NONE,
725 -1, UNIPHIER_PIN_DRV_FIXED_8,
726 233, UNIPHIER_PIN_PULL_DOWN),
727 UNIPHIER_PINCTRL_PIN(234, "VI1Y9", UNIPHIER_PIN_IECTRL_NONE,
728 -1, UNIPHIER_PIN_DRV_FIXED_8,
729 234, UNIPHIER_PIN_PULL_DOWN),
730 UNIPHIER_PINCTRL_PIN(235, "VI1DE", UNIPHIER_PIN_IECTRL_NONE,
731 -1, UNIPHIER_PIN_DRV_FIXED_8,
732 235, UNIPHIER_PIN_PULL_DOWN),
733 UNIPHIER_PINCTRL_PIN(236, "VI1HSYNC", UNIPHIER_PIN_IECTRL_NONE,
734 -1, UNIPHIER_PIN_DRV_FIXED_8,
735 236, UNIPHIER_PIN_PULL_DOWN),
736 UNIPHIER_PINCTRL_PIN(237, "VI1VSYNC", UNIPHIER_PIN_IECTRL_NONE,
737 -1, UNIPHIER_PIN_DRV_FIXED_8,
738 237, UNIPHIER_PIN_PULL_DOWN),
739 UNIPHIER_PINCTRL_PIN(238, "VO1CLK", UNIPHIER_PIN_IECTRL_NONE,
740 -1, UNIPHIER_PIN_DRV_FIXED_8,
741 238, UNIPHIER_PIN_PULL_DOWN),
742 UNIPHIER_PINCTRL_PIN(239, "VO1D0", UNIPHIER_PIN_IECTRL_NONE,
743 -1, UNIPHIER_PIN_DRV_FIXED_8,
744 239, UNIPHIER_PIN_PULL_DOWN),
745 UNIPHIER_PINCTRL_PIN(240, "VO1D1", UNIPHIER_PIN_IECTRL_NONE,
746 -1, UNIPHIER_PIN_DRV_FIXED_8,
747 240, UNIPHIER_PIN_PULL_DOWN),
748 UNIPHIER_PINCTRL_PIN(241, "VO1D2", UNIPHIER_PIN_IECTRL_NONE,
749 -1, UNIPHIER_PIN_DRV_FIXED_8,
750 241, UNIPHIER_PIN_PULL_DOWN),
751 UNIPHIER_PINCTRL_PIN(242, "VO1D3", UNIPHIER_PIN_IECTRL_NONE,
752 -1, UNIPHIER_PIN_DRV_FIXED_8,
753 242, UNIPHIER_PIN_PULL_DOWN),
754 UNIPHIER_PINCTRL_PIN(243, "VO1D4", UNIPHIER_PIN_IECTRL_NONE,
755 -1, UNIPHIER_PIN_DRV_FIXED_8,
756 243, UNIPHIER_PIN_PULL_DOWN),
757 UNIPHIER_PINCTRL_PIN(244, "VO1D5", UNIPHIER_PIN_IECTRL_NONE,
758 -1, UNIPHIER_PIN_DRV_FIXED_8,
759 244, UNIPHIER_PIN_PULL_DOWN),
760 UNIPHIER_PINCTRL_PIN(245, "VO1D6", UNIPHIER_PIN_IECTRL_NONE,
761 -1, UNIPHIER_PIN_DRV_FIXED_8,
762 245, UNIPHIER_PIN_PULL_DOWN),
763 UNIPHIER_PINCTRL_PIN(246, "VO1D7", UNIPHIER_PIN_IECTRL_NONE,
764 -1, UNIPHIER_PIN_DRV_FIXED_8,
765 246, UNIPHIER_PIN_PULL_DOWN),
766 UNIPHIER_PINCTRL_PIN(247, "SDCD", UNIPHIER_PIN_IECTRL_NONE,
767 -1, UNIPHIER_PIN_DRV_FIXED_8,
768 247, UNIPHIER_PIN_PULL_UP),
769 UNIPHIER_PINCTRL_PIN(248, "SDWP", UNIPHIER_PIN_IECTRL_NONE,
770 -1, UNIPHIER_PIN_DRV_FIXED_8,
771 248, UNIPHIER_PIN_PULL_UP),
772 UNIPHIER_PINCTRL_PIN(249, "SDVOLC", UNIPHIER_PIN_IECTRL_NONE,
773 -1, UNIPHIER_PIN_DRV_FIXED_8,
774 249, UNIPHIER_PIN_PULL_UP),
775 UNIPHIER_PINCTRL_PIN(250, "SDCLK", UNIPHIER_PIN_IECTRL_NONE,
776 40, UNIPHIER_PIN_DRV_8_12_16_20,
777 -1, UNIPHIER_PIN_PULL_UP_FIXED),
778 UNIPHIER_PINCTRL_PIN(251, "SDCMD", UNIPHIER_PIN_IECTRL_NONE,
779 44, UNIPHIER_PIN_DRV_8_12_16_20,
780 -1, UNIPHIER_PIN_PULL_UP_FIXED),
781 UNIPHIER_PINCTRL_PIN(252, "SDDAT0", UNIPHIER_PIN_IECTRL_NONE,
782 48, UNIPHIER_PIN_DRV_8_12_16_20,
783 -1, UNIPHIER_PIN_PULL_UP_FIXED),
784 UNIPHIER_PINCTRL_PIN(253, "SDDAT1", UNIPHIER_PIN_IECTRL_NONE,
785 52, UNIPHIER_PIN_DRV_8_12_16_20,
786 -1, UNIPHIER_PIN_PULL_UP_FIXED),
787 UNIPHIER_PINCTRL_PIN(254, "SDDAT2", UNIPHIER_PIN_IECTRL_NONE,
788 56, UNIPHIER_PIN_DRV_8_12_16_20,
789 -1, UNIPHIER_PIN_PULL_UP_FIXED),
790 UNIPHIER_PINCTRL_PIN(255, "SDDAT3", UNIPHIER_PIN_IECTRL_NONE,
791 60, UNIPHIER_PIN_DRV_8_12_16_20,
792 -1, UNIPHIER_PIN_PULL_UP_FIXED),
793};
794
795static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
796static const unsigned emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0};
797static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
798static const unsigned emmc_dat8_muxvals[] = {0, 0, 0, 0};
799static const unsigned i2c0_pins[] = {112, 113};
800static const unsigned i2c0_muxvals[] = {0, 0};
801static const unsigned i2c1_pins[] = {114, 115};
802static const unsigned i2c1_muxvals[] = {0, 0};
803static const unsigned i2c2_pins[] = {116, 117};
804static const unsigned i2c2_muxvals[] = {0, 0};
805static const unsigned i2c3_pins[] = {118, 119};
806static const unsigned i2c3_muxvals[] = {0, 0};
807static const unsigned i2c5_pins[] = {87, 88};
808static const unsigned i2c5_muxvals[] = {2, 2};
809static const unsigned i2c5b_pins[] = {196, 197};
810static const unsigned i2c5b_muxvals[] = {2, 2};
811static const unsigned i2c5c_pins[] = {215, 216};
812static const unsigned i2c5c_muxvals[] = {2, 2};
813static const unsigned i2c6_pins[] = {101, 102};
814static const unsigned i2c6_muxvals[] = {2, 2};
815static const unsigned nand_pins[] = {19, 20, 21, 22, 23, 24, 25, 28, 29, 30,
816 31, 32, 33, 34, 35};
817static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
818 0, 0};
819static const unsigned nand_cs1_pins[] = {26, 27};
820static const unsigned nand_cs1_muxvals[] = {0, 0};
821static const unsigned uart0_pins[] = {47, 48};
822static const unsigned uart0_muxvals[] = {0, 0};
823static const unsigned uart0b_pins[] = {227, 228};
824static const unsigned uart0b_muxvals[] = {3, 3};
825static const unsigned uart1_pins[] = {49, 50};
826static const unsigned uart1_muxvals[] = {0, 0};
827static const unsigned uart2_pins[] = {51, 52};
828static const unsigned uart2_muxvals[] = {0, 0};
829static const unsigned uart3_pins[] = {53, 54};
830static const unsigned uart3_muxvals[] = {0, 0};
831static const unsigned usb0_pins[] = {124, 125};
832static const unsigned usb0_muxvals[] = {0, 0};
833static const unsigned usb1_pins[] = {126, 127};
834static const unsigned usb1_muxvals[] = {0, 0};
835static const unsigned usb2_pins[] = {128, 129};
836static const unsigned usb2_muxvals[] = {0, 0};
837static const unsigned port_range0_pins[] = {
838 89, 90, 91, 92, 93, 94, 95, 96, /* PORT0x */
839 97, 98, 99, 100, 101, 102, 103, 104, /* PORT1x */
840 251, 252, 253, 254, 255, 247, 248, 249, /* PORT2x */
841 39, 40, 41, 42, 43, 44, 45, 46, /* PORT3x */
842 156, 157, 158, 159, 160, 161, 162, 163, /* PORT4x */
843 164, 165, 166, 167, 168, 169, 170, 171, /* PORT5x */
844 190, 191, 192, 193, 194, 195, 196, 197, /* PORT6x */
845 198, 199, 200, 201, 202, 203, 204, 205, /* PORT7x */
846 120, 121, 122, 123, 55, 56, 57, 58, /* PORT8x */
847 124, 125, 126, 127, 49, 50, 53, 54, /* PORT9x */
848 148, 149, 150, 151, 152, 153, 154, 155, /* PORT10x */
849 133, 134, 131, 130, 138, 139, 136, 135, /* PORT11x */
850 28, 29, 30, 31, 32, 33, 34, 35, /* PORT12x */
851 179, 180, 181, 182, 186, 187, 188, 189, /* PORT13x */
852 4, 5, 6, 7, 8, 9, 10, 11, /* PORT14x */
853};
854static const unsigned port_range0_muxvals[] = {
855 15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */
856 15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */
857 15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */
858 15, 15, 15, 15, 15, 15, 15, 15, /* PORT3x */
859 15, 15, 15, 15, 15, 15, 15, 15, /* PORT4x */
860 15, 15, 15, 15, 15, 15, 15, 15, /* PORT5x */
861 15, 15, 15, 15, 15, 15, 15, 15, /* PORT6x */
862 15, 15, 15, 15, 15, 15, 15, 15, /* PORT7x */
863 15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */
864 15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */
865 15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */
866 15, 15, 15, 15, 15, 15, 15, 15, /* PORT11x */
867 15, 15, 15, 15, 15, 15, 15, 15, /* PORT12x */
868 15, 15, 15, 15, 15, 15, 15, 15, /* PORT13x */
869 15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */
870};
871static const unsigned port_range1_pins[] = {
872 109, 110, 111, /* PORT175-177 */
873 206, 207, 208, 209, 210, 211, 212, 213, /* PORT18x */
874 12, 13, 14, 15, 16, 17, 107, 108, /* PORT19x */
875 140, 141, 142, 143, 144, 145, 146, 147, /* PORT20x */
876 59, 60, 61, 62, 63, 64, 65, 66, /* PORT21x */
877 214, 215, 216, 217, 218, 219, 220, 221, /* PORT22x */
878 222, 223, 224, 225, 226, 227, 228, 229, /* PORT23x */
879 19, 20, 21, 22, 23, 24, 25, 26, /* PORT24x */
880 230, 231, 232, 233, 234, 235, 236, 237, /* PORT25x */
881 239, 240, 241, 242, 243, 244, 245, 246, /* PORT26x */
882 172, 173, 174, 175, 176, 177, 178, 129, /* PORT27x */
883 0, 1, 2, 67, 85, 86, 87, 88, /* PORT28x */
884 105, 106, 18, 27, 36, 128, 132, 137, /* PORT29x */
885 183, 184, 185, 84, 47, 48, 51, 52, /* PORT30x */
886};
887static const unsigned port_range1_muxvals[] = {
888 15, 15, 15, /* PORT175-177 */
889 15, 15, 15, 15, 15, 15, 15, 15, /* PORT18x */
890 15, 15, 15, 15, 15, 15, 15, 15, /* PORT19x */
891 15, 15, 15, 15, 15, 15, 15, 15, /* PORT20x */
892 15, 15, 15, 15, 15, 15, 15, 15, /* PORT21x */
893 15, 15, 15, 15, 15, 15, 15, 15, /* PORT22x */
894 15, 15, 15, 15, 15, 15, 15, 15, /* PORT23x */
895 15, 15, 15, 15, 15, 15, 15, 15, /* PORT24x */
896 15, 15, 15, 15, 15, 15, 15, 15, /* PORT25x */
897 15, 15, 15, 15, 15, 15, 15, 15, /* PORT26x */
898 15, 15, 15, 15, 15, 15, 15, 15, /* PORT27x */
899 15, 15, 15, 15, 15, 15, 15, 15, /* PORT28x */
900 15, 15, 15, 15, 15, 15, 15, 15, /* PORT29x */
901 15, 15, 15, 15, 15, 15, 15, 15, /* PORT30x */
902};
903static const unsigned xirq_pins[] = {
904 68, 69, 70, 71, 72, 73, 74, 75, /* XIRQ0-7 */
905 76, 77, 78, 79, 80, 81, 82, 83, /* XIRQ8-15 */
906 84, 85, 86, 87, 88, /* XIRQ16-20 */
907};
908static const unsigned xirq_muxvals[] = {
909 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ0-7 */
910 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ8-15 */
911 14, 14, 14, 14, 14, /* XIRQ16-20 */
912};
913static const unsigned xirq_alternatives_pins[] = {
914 91, 92, 239, 144, 240, 156, 241, 106, 128,
915};
916static const unsigned xirq_alternatives_muxvals[] = {
917 14, 14, 14, 14, 14, 14, 14, 14, 14,
918};
919
920static const struct uniphier_pinctrl_group ph1_pro5_groups[] = {
921 UNIPHIER_PINCTRL_GROUP(nand),
922 UNIPHIER_PINCTRL_GROUP(nand_cs1),
923 UNIPHIER_PINCTRL_GROUP(emmc),
924 UNIPHIER_PINCTRL_GROUP(emmc_dat8),
925 UNIPHIER_PINCTRL_GROUP(i2c0),
926 UNIPHIER_PINCTRL_GROUP(i2c1),
927 UNIPHIER_PINCTRL_GROUP(i2c2),
928 UNIPHIER_PINCTRL_GROUP(i2c3),
929 UNIPHIER_PINCTRL_GROUP(i2c5),
930 UNIPHIER_PINCTRL_GROUP(i2c5b),
931 UNIPHIER_PINCTRL_GROUP(i2c5c),
932 UNIPHIER_PINCTRL_GROUP(i2c6),
933 UNIPHIER_PINCTRL_GROUP(uart0),
934 UNIPHIER_PINCTRL_GROUP(uart0b),
935 UNIPHIER_PINCTRL_GROUP(uart1),
936 UNIPHIER_PINCTRL_GROUP(uart2),
937 UNIPHIER_PINCTRL_GROUP(uart3),
938 UNIPHIER_PINCTRL_GROUP(usb0),
939 UNIPHIER_PINCTRL_GROUP(usb1),
940 UNIPHIER_PINCTRL_GROUP(usb2),
941 UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0),
942 UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1),
943 UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq),
944 UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_alternatives),
945 UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0),
946 UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1),
947 UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2),
948 UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3),
949 UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4),
950 UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5),
951 UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6),
952 UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7),
953 UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8),
954 UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9),
955 UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10),
956 UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11),
957 UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12),
958 UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13),
959 UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14),
960 UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15),
961 UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16),
962 UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17),
963 UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18),
964 UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19),
965 UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20),
966 UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21),
967 UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22),
968 UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23),
969 UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24),
970 UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25),
971 UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26),
972 UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27),
973 UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28),
974 UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29),
975 UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30),
976 UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31),
977 UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32),
978 UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33),
979 UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34),
980 UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35),
981 UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36),
982 UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37),
983 UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38),
984 UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39),
985 UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40),
986 UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41),
987 UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42),
988 UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43),
989 UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44),
990 UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45),
991 UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46),
992 UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47),
993 UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48),
994 UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49),
995 UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50),
996 UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51),
997 UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52),
998 UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53),
999 UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54),
1000 UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55),
1001 UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56),
1002 UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57),
1003 UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58),
1004 UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59),
1005 UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60),
1006 UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61),
1007 UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62),
1008 UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63),
1009 UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64),
1010 UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65),
1011 UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66),
1012 UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67),
1013 UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68),
1014 UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69),
1015 UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70),
1016 UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71),
1017 UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72),
1018 UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73),
1019 UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74),
1020 UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75),
1021 UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76),
1022 UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77),
1023 UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78),
1024 UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79),
1025 UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80),
1026 UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81),
1027 UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82),
1028 UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83),
1029 UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84),
1030 UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85),
1031 UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86),
1032 UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87),
1033 UNIPHIER_PINCTRL_GROUP_SINGLE(port110, port_range0, 88),
1034 UNIPHIER_PINCTRL_GROUP_SINGLE(port111, port_range0, 89),
1035 UNIPHIER_PINCTRL_GROUP_SINGLE(port112, port_range0, 90),
1036 UNIPHIER_PINCTRL_GROUP_SINGLE(port113, port_range0, 91),
1037 UNIPHIER_PINCTRL_GROUP_SINGLE(port114, port_range0, 92),
1038 UNIPHIER_PINCTRL_GROUP_SINGLE(port115, port_range0, 93),
1039 UNIPHIER_PINCTRL_GROUP_SINGLE(port116, port_range0, 94),
1040 UNIPHIER_PINCTRL_GROUP_SINGLE(port117, port_range0, 95),
1041 UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range0, 96),
1042 UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range0, 97),
1043 UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range0, 98),
1044 UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range0, 99),
1045 UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range0, 100),
1046 UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range0, 101),
1047 UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range0, 102),
1048 UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range0, 103),
1049 UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range0, 104),
1050 UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range0, 105),
1051 UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range0, 106),
1052 UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range0, 107),
1053 UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range0, 108),
1054 UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range0, 109),
1055 UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range0, 110),
1056 UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range0, 111),
1057 UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range0, 112),
1058 UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range0, 113),
1059 UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range0, 114),
1060 UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range0, 115),
1061 UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range0, 116),
1062 UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range0, 117),
1063 UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range0, 118),
1064 UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range0, 119),
1065 UNIPHIER_PINCTRL_GROUP_SINGLE(port175, port_range1, 0),
1066 UNIPHIER_PINCTRL_GROUP_SINGLE(port176, port_range1, 1),
1067 UNIPHIER_PINCTRL_GROUP_SINGLE(port177, port_range1, 2),
1068 UNIPHIER_PINCTRL_GROUP_SINGLE(port180, port_range1, 3),
1069 UNIPHIER_PINCTRL_GROUP_SINGLE(port181, port_range1, 4),
1070 UNIPHIER_PINCTRL_GROUP_SINGLE(port182, port_range1, 5),
1071 UNIPHIER_PINCTRL_GROUP_SINGLE(port183, port_range1, 6),
1072 UNIPHIER_PINCTRL_GROUP_SINGLE(port184, port_range1, 7),
1073 UNIPHIER_PINCTRL_GROUP_SINGLE(port185, port_range1, 8),
1074 UNIPHIER_PINCTRL_GROUP_SINGLE(port186, port_range1, 9),
1075 UNIPHIER_PINCTRL_GROUP_SINGLE(port187, port_range1, 10),
1076 UNIPHIER_PINCTRL_GROUP_SINGLE(port190, port_range1, 11),
1077 UNIPHIER_PINCTRL_GROUP_SINGLE(port191, port_range1, 12),
1078 UNIPHIER_PINCTRL_GROUP_SINGLE(port192, port_range1, 13),
1079 UNIPHIER_PINCTRL_GROUP_SINGLE(port193, port_range1, 14),
1080 UNIPHIER_PINCTRL_GROUP_SINGLE(port194, port_range1, 15),
1081 UNIPHIER_PINCTRL_GROUP_SINGLE(port195, port_range1, 16),
1082 UNIPHIER_PINCTRL_GROUP_SINGLE(port196, port_range1, 17),
1083 UNIPHIER_PINCTRL_GROUP_SINGLE(port197, port_range1, 18),
1084 UNIPHIER_PINCTRL_GROUP_SINGLE(port200, port_range1, 19),
1085 UNIPHIER_PINCTRL_GROUP_SINGLE(port201, port_range1, 20),
1086 UNIPHIER_PINCTRL_GROUP_SINGLE(port202, port_range1, 21),
1087 UNIPHIER_PINCTRL_GROUP_SINGLE(port203, port_range1, 22),
1088 UNIPHIER_PINCTRL_GROUP_SINGLE(port204, port_range1, 23),
1089 UNIPHIER_PINCTRL_GROUP_SINGLE(port205, port_range1, 24),
1090 UNIPHIER_PINCTRL_GROUP_SINGLE(port206, port_range1, 25),
1091 UNIPHIER_PINCTRL_GROUP_SINGLE(port207, port_range1, 26),
1092 UNIPHIER_PINCTRL_GROUP_SINGLE(port210, port_range1, 27),
1093 UNIPHIER_PINCTRL_GROUP_SINGLE(port211, port_range1, 28),
1094 UNIPHIER_PINCTRL_GROUP_SINGLE(port212, port_range1, 29),
1095 UNIPHIER_PINCTRL_GROUP_SINGLE(port213, port_range1, 30),
1096 UNIPHIER_PINCTRL_GROUP_SINGLE(port214, port_range1, 31),
1097 UNIPHIER_PINCTRL_GROUP_SINGLE(port215, port_range1, 32),
1098 UNIPHIER_PINCTRL_GROUP_SINGLE(port216, port_range1, 33),
1099 UNIPHIER_PINCTRL_GROUP_SINGLE(port217, port_range1, 34),
1100 UNIPHIER_PINCTRL_GROUP_SINGLE(port220, port_range1, 35),
1101 UNIPHIER_PINCTRL_GROUP_SINGLE(port221, port_range1, 36),
1102 UNIPHIER_PINCTRL_GROUP_SINGLE(port222, port_range1, 37),
1103 UNIPHIER_PINCTRL_GROUP_SINGLE(port223, port_range1, 38),
1104 UNIPHIER_PINCTRL_GROUP_SINGLE(port224, port_range1, 39),
1105 UNIPHIER_PINCTRL_GROUP_SINGLE(port225, port_range1, 40),
1106 UNIPHIER_PINCTRL_GROUP_SINGLE(port226, port_range1, 41),
1107 UNIPHIER_PINCTRL_GROUP_SINGLE(port227, port_range1, 42),
1108 UNIPHIER_PINCTRL_GROUP_SINGLE(port230, port_range1, 43),
1109 UNIPHIER_PINCTRL_GROUP_SINGLE(port231, port_range1, 44),
1110 UNIPHIER_PINCTRL_GROUP_SINGLE(port232, port_range1, 45),
1111 UNIPHIER_PINCTRL_GROUP_SINGLE(port233, port_range1, 46),
1112 UNIPHIER_PINCTRL_GROUP_SINGLE(port234, port_range1, 47),
1113 UNIPHIER_PINCTRL_GROUP_SINGLE(port235, port_range1, 48),
1114 UNIPHIER_PINCTRL_GROUP_SINGLE(port236, port_range1, 49),
1115 UNIPHIER_PINCTRL_GROUP_SINGLE(port237, port_range1, 50),
1116 UNIPHIER_PINCTRL_GROUP_SINGLE(port240, port_range1, 51),
1117 UNIPHIER_PINCTRL_GROUP_SINGLE(port241, port_range1, 52),
1118 UNIPHIER_PINCTRL_GROUP_SINGLE(port242, port_range1, 53),
1119 UNIPHIER_PINCTRL_GROUP_SINGLE(port243, port_range1, 54),
1120 UNIPHIER_PINCTRL_GROUP_SINGLE(port244, port_range1, 55),
1121 UNIPHIER_PINCTRL_GROUP_SINGLE(port245, port_range1, 56),
1122 UNIPHIER_PINCTRL_GROUP_SINGLE(port246, port_range1, 57),
1123 UNIPHIER_PINCTRL_GROUP_SINGLE(port247, port_range1, 58),
1124 UNIPHIER_PINCTRL_GROUP_SINGLE(port250, port_range1, 59),
1125 UNIPHIER_PINCTRL_GROUP_SINGLE(port251, port_range1, 60),
1126 UNIPHIER_PINCTRL_GROUP_SINGLE(port252, port_range1, 61),
1127 UNIPHIER_PINCTRL_GROUP_SINGLE(port253, port_range1, 62),
1128 UNIPHIER_PINCTRL_GROUP_SINGLE(port254, port_range1, 63),
1129 UNIPHIER_PINCTRL_GROUP_SINGLE(port255, port_range1, 64),
1130 UNIPHIER_PINCTRL_GROUP_SINGLE(port256, port_range1, 65),
1131 UNIPHIER_PINCTRL_GROUP_SINGLE(port257, port_range1, 66),
1132 UNIPHIER_PINCTRL_GROUP_SINGLE(port260, port_range1, 67),
1133 UNIPHIER_PINCTRL_GROUP_SINGLE(port261, port_range1, 68),
1134 UNIPHIER_PINCTRL_GROUP_SINGLE(port262, port_range1, 69),
1135 UNIPHIER_PINCTRL_GROUP_SINGLE(port263, port_range1, 70),
1136 UNIPHIER_PINCTRL_GROUP_SINGLE(port264, port_range1, 71),
1137 UNIPHIER_PINCTRL_GROUP_SINGLE(port265, port_range1, 72),
1138 UNIPHIER_PINCTRL_GROUP_SINGLE(port266, port_range1, 73),
1139 UNIPHIER_PINCTRL_GROUP_SINGLE(port267, port_range1, 74),
1140 UNIPHIER_PINCTRL_GROUP_SINGLE(port270, port_range1, 75),
1141 UNIPHIER_PINCTRL_GROUP_SINGLE(port271, port_range1, 76),
1142 UNIPHIER_PINCTRL_GROUP_SINGLE(port272, port_range1, 77),
1143 UNIPHIER_PINCTRL_GROUP_SINGLE(port273, port_range1, 78),
1144 UNIPHIER_PINCTRL_GROUP_SINGLE(port274, port_range1, 79),
1145 UNIPHIER_PINCTRL_GROUP_SINGLE(port275, port_range1, 80),
1146 UNIPHIER_PINCTRL_GROUP_SINGLE(port276, port_range1, 81),
1147 UNIPHIER_PINCTRL_GROUP_SINGLE(port277, port_range1, 82),
1148 UNIPHIER_PINCTRL_GROUP_SINGLE(port280, port_range1, 83),
1149 UNIPHIER_PINCTRL_GROUP_SINGLE(port281, port_range1, 84),
1150 UNIPHIER_PINCTRL_GROUP_SINGLE(port282, port_range1, 85),
1151 UNIPHIER_PINCTRL_GROUP_SINGLE(port283, port_range1, 86),
1152 UNIPHIER_PINCTRL_GROUP_SINGLE(port284, port_range1, 87),
1153 UNIPHIER_PINCTRL_GROUP_SINGLE(port285, port_range1, 88),
1154 UNIPHIER_PINCTRL_GROUP_SINGLE(port286, port_range1, 89),
1155 UNIPHIER_PINCTRL_GROUP_SINGLE(port287, port_range1, 90),
1156 UNIPHIER_PINCTRL_GROUP_SINGLE(port290, port_range1, 91),
1157 UNIPHIER_PINCTRL_GROUP_SINGLE(port291, port_range1, 92),
1158 UNIPHIER_PINCTRL_GROUP_SINGLE(port292, port_range1, 93),
1159 UNIPHIER_PINCTRL_GROUP_SINGLE(port293, port_range1, 94),
1160 UNIPHIER_PINCTRL_GROUP_SINGLE(port294, port_range1, 95),
1161 UNIPHIER_PINCTRL_GROUP_SINGLE(port295, port_range1, 96),
1162 UNIPHIER_PINCTRL_GROUP_SINGLE(port296, port_range1, 97),
1163 UNIPHIER_PINCTRL_GROUP_SINGLE(port297, port_range1, 98),
1164 UNIPHIER_PINCTRL_GROUP_SINGLE(port300, port_range1, 99),
1165 UNIPHIER_PINCTRL_GROUP_SINGLE(port301, port_range1, 100),
1166 UNIPHIER_PINCTRL_GROUP_SINGLE(port302, port_range1, 101),
1167 UNIPHIER_PINCTRL_GROUP_SINGLE(port303, port_range1, 102),
1168 UNIPHIER_PINCTRL_GROUP_SINGLE(port304, port_range1, 103),
1169 UNIPHIER_PINCTRL_GROUP_SINGLE(port305, port_range1, 104),
1170 UNIPHIER_PINCTRL_GROUP_SINGLE(port306, port_range1, 105),
1171 UNIPHIER_PINCTRL_GROUP_SINGLE(port307, port_range1, 106),
1172 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq, 0),
1173 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq, 1),
1174 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq, 2),
1175 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq, 3),
1176 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq, 4),
1177 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq, 5),
1178 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq, 6),
1179 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq, 7),
1180 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq, 8),
1181 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq, 9),
1182 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq, 10),
1183 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq, 11),
1184 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq, 12),
1185 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq13, xirq, 13),
1186 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq, 14),
1187 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq, 15),
1188 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16, xirq, 16),
1189 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17, xirq, 17),
1190 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18, xirq, 18),
1191 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19, xirq, 19),
1192 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20, xirq, 20),
1193 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3b, xirq_alternatives, 0),
1194 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4b, xirq_alternatives, 1),
1195 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16b, xirq_alternatives, 2),
1196 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17b, xirq_alternatives, 3),
1197 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17c, xirq_alternatives, 4),
1198 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18b, xirq_alternatives, 5),
1199 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18c, xirq_alternatives, 6),
1200 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19b, xirq_alternatives, 7),
1201 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20b, xirq_alternatives, 8),
1202};
1203
1204static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
1205static const char * const i2c0_groups[] = {"i2c0"};
1206static const char * const i2c1_groups[] = {"i2c1"};
1207static const char * const i2c2_groups[] = {"i2c2"};
1208static const char * const i2c3_groups[] = {"i2c3"};
1209static const char * const i2c5_groups[] = {"i2c5", "i2c5b", "i2c5c"};
1210static const char * const i2c6_groups[] = {"i2c6"};
1211static const char * const nand_groups[] = {"nand", "nand_cs1"};
1212static const char * const uart0_groups[] = {"uart0", "uart0b"};
1213static const char * const uart1_groups[] = {"uart1"};
1214static const char * const uart2_groups[] = {"uart2"};
1215static const char * const uart3_groups[] = {"uart3"};
1216static const char * const usb0_groups[] = {"usb0"};
1217static const char * const usb1_groups[] = {"usb1"};
1218static const char * const usb2_groups[] = {"usb2"};
1219static const char * const port_groups[] = {
1220 "port00", "port01", "port02", "port03",
1221 "port04", "port05", "port06", "port07",
1222 "port10", "port11", "port12", "port13",
1223 "port14", "port15", "port16", "port17",
1224 "port20", "port21", "port22", "port23",
1225 "port24", "port25", "port26", "port27",
1226 "port30", "port31", "port32", "port33",
1227 "port34", "port35", "port36", "port37",
1228 "port40", "port41", "port42", "port43",
1229 "port44", "port45", "port46", "port47",
1230 "port50", "port51", "port52", "port53",
1231 "port54", "port55", "port56", "port57",
1232 "port60", "port61", "port62", "port63",
1233 "port64", "port65", "port66", "port67",
1234 "port70", "port71", "port72", "port73",
1235 "port74", "port75", "port76", "port77",
1236 "port80", "port81", "port82", "port83",
1237 "port84", "port85", "port86", "port87",
1238 "port90", "port91", "port92", "port93",
1239 "port94", "port95", "port96", "port97",
1240 "port100", "port101", "port102", "port103",
1241 "port104", "port105", "port106", "port107",
1242 "port110", "port111", "port112", "port113",
1243 "port114", "port115", "port116", "port117",
1244 "port120", "port121", "port122", "port123",
1245 "port124", "port125", "port126", "port127",
1246 "port130", "port131", "port132", "port133",
1247 "port134", "port135", "port136", "port137",
1248 "port140", "port141", "port142", "port143",
1249 "port144", "port145", "port146", "port147",
1250 /* port150-174 missing */
1251 /* none */ "port175", "port176", "port177",
1252 "port180", "port181", "port182", "port183",
1253 "port184", "port185", "port186", "port187",
1254 "port190", "port191", "port192", "port193",
1255 "port194", "port195", "port196", "port197",
1256 "port200", "port201", "port202", "port203",
1257 "port204", "port205", "port206", "port207",
1258 "port210", "port211", "port212", "port213",
1259 "port214", "port215", "port216", "port217",
1260 "port220", "port221", "port222", "port223",
1261 "port224", "port225", "port226", "port227",
1262 "port230", "port231", "port232", "port233",
1263 "port234", "port235", "port236", "port237",
1264 "port240", "port241", "port242", "port243",
1265 "port244", "port245", "port246", "port247",
1266 "port250", "port251", "port252", "port253",
1267 "port254", "port255", "port256", "port257",
1268 "port260", "port261", "port262", "port263",
1269 "port264", "port265", "port266", "port267",
1270 "port270", "port271", "port272", "port273",
1271 "port274", "port275", "port276", "port277",
1272 "port280", "port281", "port282", "port283",
1273 "port284", "port285", "port286", "port287",
1274 "port290", "port291", "port292", "port293",
1275 "port294", "port295", "port296", "port297",
1276 "port300", "port301", "port302", "port303",
1277 "port304", "port305", "port306", "port307",
1278};
1279static const char * const xirq_groups[] = {
1280 "xirq0", "xirq1", "xirq2", "xirq3",
1281 "xirq4", "xirq5", "xirq6", "xirq7",
1282 "xirq8", "xirq9", "xirq10", "xirq11",
1283 "xirq12", "xirq13", "xirq14", "xirq15",
1284 "xirq16", "xirq17", "xirq18", "xirq19",
1285 "xirq20",
1286 "xirq3b", "xirq4b", "xirq16b", "xirq17b", "xirq17c",
1287 "xirq18b", "xirq18c", "xirq19b", "xirq20b",
1288};
1289
1290static const struct uniphier_pinmux_function ph1_pro5_functions[] = {
1291 UNIPHIER_PINMUX_FUNCTION(emmc),
1292 UNIPHIER_PINMUX_FUNCTION(i2c0),
1293 UNIPHIER_PINMUX_FUNCTION(i2c1),
1294 UNIPHIER_PINMUX_FUNCTION(i2c2),
1295 UNIPHIER_PINMUX_FUNCTION(i2c3),
1296 UNIPHIER_PINMUX_FUNCTION(i2c5),
1297 UNIPHIER_PINMUX_FUNCTION(i2c6),
1298 UNIPHIER_PINMUX_FUNCTION(nand),
1299 UNIPHIER_PINMUX_FUNCTION(uart0),
1300 UNIPHIER_PINMUX_FUNCTION(uart1),
1301 UNIPHIER_PINMUX_FUNCTION(uart2),
1302 UNIPHIER_PINMUX_FUNCTION(uart3),
1303 UNIPHIER_PINMUX_FUNCTION(usb0),
1304 UNIPHIER_PINMUX_FUNCTION(usb1),
1305 UNIPHIER_PINMUX_FUNCTION(usb2),
1306 UNIPHIER_PINMUX_FUNCTION(port),
1307 UNIPHIER_PINMUX_FUNCTION(xirq),
1308};
1309
1310static struct uniphier_pinctrl_socdata ph1_pro5_pindata = {
1311 .groups = ph1_pro5_groups,
1312 .groups_count = ARRAY_SIZE(ph1_pro5_groups),
1313 .functions = ph1_pro5_functions,
1314 .functions_count = ARRAY_SIZE(ph1_pro5_functions),
1315 .mux_bits = 4,
1316 .reg_stride = 8,
1317 .load_pinctrl = true,
1318};
1319
1320static struct pinctrl_desc ph1_pro5_pinctrl_desc = {
1321 .name = DRIVER_NAME,
1322 .pins = ph1_pro5_pins,
1323 .npins = ARRAY_SIZE(ph1_pro5_pins),
1324 .owner = THIS_MODULE,
1325};
1326
1327static int ph1_pro5_pinctrl_probe(struct platform_device *pdev)
1328{
1329 return uniphier_pinctrl_probe(pdev, &ph1_pro5_pinctrl_desc,
1330 &ph1_pro5_pindata);
1331}
1332
1333static const struct of_device_id ph1_pro5_pinctrl_match[] = {
1334 { .compatible = "socionext,ph1-pro5-pinctrl" },
1335 { /* sentinel */ }
1336};
1337MODULE_DEVICE_TABLE(of, ph1_pro5_pinctrl_match);
1338
1339static struct platform_driver ph1_pro5_pinctrl_driver = {
1340 .probe = ph1_pro5_pinctrl_probe,
1341 .remove = uniphier_pinctrl_remove,
1342 .driver = {
1343 .name = DRIVER_NAME,
1344 .of_match_table = ph1_pro5_pinctrl_match,
1345 },
1346};
1347module_platform_driver(ph1_pro5_pinctrl_driver);
1348
1349MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
1350MODULE_DESCRIPTION("UniPhier PH1-Pro5 pinctrl driver");
1351MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c b/drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c
new file mode 100644
index 000000000000..7e9dae54fcb2
--- /dev/null
+++ b/drivers/pinctrl/uniphier/pinctrl-ph1-sld8.c
@@ -0,0 +1,794 @@
1/*
2 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/pinctrl/pinctrl.h>
18#include <linux/platform_device.h>
19
20#include "pinctrl-uniphier.h"
21
22#define DRIVER_NAME "ph1-sld8-pinctrl"
23
24static const struct pinctrl_pin_desc ph1_sld8_pins[] = {
25 UNIPHIER_PINCTRL_PIN(0, "PCA00", UNIPHIER_PIN_IECTRL_NONE,
26 15, UNIPHIER_PIN_DRV_4_8,
27 15, UNIPHIER_PIN_PULL_DOWN),
28 UNIPHIER_PINCTRL_PIN(1, "PCA01", UNIPHIER_PIN_IECTRL_NONE,
29 16, UNIPHIER_PIN_DRV_4_8,
30 16, UNIPHIER_PIN_PULL_DOWN),
31 UNIPHIER_PINCTRL_PIN(2, "PCA02", UNIPHIER_PIN_IECTRL_NONE,
32 17, UNIPHIER_PIN_DRV_4_8,
33 17, UNIPHIER_PIN_PULL_DOWN),
34 UNIPHIER_PINCTRL_PIN(3, "PCA03", UNIPHIER_PIN_IECTRL_NONE,
35 18, UNIPHIER_PIN_DRV_4_8,
36 18, UNIPHIER_PIN_PULL_DOWN),
37 UNIPHIER_PINCTRL_PIN(4, "PCA04", UNIPHIER_PIN_IECTRL_NONE,
38 19, UNIPHIER_PIN_DRV_4_8,
39 19, UNIPHIER_PIN_PULL_DOWN),
40 UNIPHIER_PINCTRL_PIN(5, "PCA05", UNIPHIER_PIN_IECTRL_NONE,
41 20, UNIPHIER_PIN_DRV_4_8,
42 20, UNIPHIER_PIN_PULL_DOWN),
43 UNIPHIER_PINCTRL_PIN(6, "PCA06", UNIPHIER_PIN_IECTRL_NONE,
44 21, UNIPHIER_PIN_DRV_4_8,
45 21, UNIPHIER_PIN_PULL_DOWN),
46 UNIPHIER_PINCTRL_PIN(7, "PCA07", UNIPHIER_PIN_IECTRL_NONE,
47 22, UNIPHIER_PIN_DRV_4_8,
48 22, UNIPHIER_PIN_PULL_DOWN),
49 UNIPHIER_PINCTRL_PIN(8, "PCA08", UNIPHIER_PIN_IECTRL_NONE,
50 23, UNIPHIER_PIN_DRV_4_8,
51 23, UNIPHIER_PIN_PULL_DOWN),
52 UNIPHIER_PINCTRL_PIN(9, "PCA09", UNIPHIER_PIN_IECTRL_NONE,
53 24, UNIPHIER_PIN_DRV_4_8,
54 24, UNIPHIER_PIN_PULL_DOWN),
55 UNIPHIER_PINCTRL_PIN(10, "PCA10", UNIPHIER_PIN_IECTRL_NONE,
56 25, UNIPHIER_PIN_DRV_4_8,
57 25, UNIPHIER_PIN_PULL_DOWN),
58 UNIPHIER_PINCTRL_PIN(11, "PCA11", UNIPHIER_PIN_IECTRL_NONE,
59 26, UNIPHIER_PIN_DRV_4_8,
60 26, UNIPHIER_PIN_PULL_DOWN),
61 UNIPHIER_PINCTRL_PIN(12, "PCA12", UNIPHIER_PIN_IECTRL_NONE,
62 27, UNIPHIER_PIN_DRV_4_8,
63 27, UNIPHIER_PIN_PULL_DOWN),
64 UNIPHIER_PINCTRL_PIN(13, "PCA13", UNIPHIER_PIN_IECTRL_NONE,
65 28, UNIPHIER_PIN_DRV_4_8,
66 28, UNIPHIER_PIN_PULL_DOWN),
67 UNIPHIER_PINCTRL_PIN(14, "PCA14", UNIPHIER_PIN_IECTRL_NONE,
68 29, UNIPHIER_PIN_DRV_4_8,
69 29, UNIPHIER_PIN_PULL_DOWN),
70 UNIPHIER_PINCTRL_PIN(15, "XNFRE_GB", UNIPHIER_PIN_IECTRL_NONE,
71 30, UNIPHIER_PIN_DRV_4_8,
72 30, UNIPHIER_PIN_PULL_UP),
73 UNIPHIER_PINCTRL_PIN(16, "XNFWE_GB", UNIPHIER_PIN_IECTRL_NONE,
74 31, UNIPHIER_PIN_DRV_4_8,
75 31, UNIPHIER_PIN_PULL_UP),
76 UNIPHIER_PINCTRL_PIN(17, "NFALE_GB", UNIPHIER_PIN_IECTRL_NONE,
77 32, UNIPHIER_PIN_DRV_4_8,
78 32, UNIPHIER_PIN_PULL_DOWN),
79 UNIPHIER_PINCTRL_PIN(18, "NFCLE_GB", UNIPHIER_PIN_IECTRL_NONE,
80 33, UNIPHIER_PIN_DRV_4_8,
81 33, UNIPHIER_PIN_PULL_DOWN),
82 UNIPHIER_PINCTRL_PIN(19, "XNFWP_GB", UNIPHIER_PIN_IECTRL_NONE,
83 34, UNIPHIER_PIN_DRV_4_8,
84 34, UNIPHIER_PIN_PULL_DOWN),
85 UNIPHIER_PINCTRL_PIN(20, "XNFCE0_GB", UNIPHIER_PIN_IECTRL_NONE,
86 35, UNIPHIER_PIN_DRV_4_8,
87 35, UNIPHIER_PIN_PULL_UP),
88 UNIPHIER_PINCTRL_PIN(21, "NANDRYBY0_GB", UNIPHIER_PIN_IECTRL_NONE,
89 36, UNIPHIER_PIN_DRV_4_8,
90 36, UNIPHIER_PIN_PULL_UP),
91 UNIPHIER_PINCTRL_PIN(22, "XNFCE1_GB", UNIPHIER_PIN_IECTRL_NONE,
92 0, UNIPHIER_PIN_DRV_8_12_16_20,
93 119, UNIPHIER_PIN_PULL_UP),
94 UNIPHIER_PINCTRL_PIN(23, "NANDRYBY1_GB", UNIPHIER_PIN_IECTRL_NONE,
95 4, UNIPHIER_PIN_DRV_8_12_16_20,
96 120, UNIPHIER_PIN_PULL_UP),
97 UNIPHIER_PINCTRL_PIN(24, "NFD0_GB", UNIPHIER_PIN_IECTRL_NONE,
98 8, UNIPHIER_PIN_DRV_8_12_16_20,
99 121, UNIPHIER_PIN_PULL_UP),
100 UNIPHIER_PINCTRL_PIN(25, "NFD1_GB", UNIPHIER_PIN_IECTRL_NONE,
101 12, UNIPHIER_PIN_DRV_8_12_16_20,
102 122, UNIPHIER_PIN_PULL_UP),
103 UNIPHIER_PINCTRL_PIN(26, "NFD2_GB", UNIPHIER_PIN_IECTRL_NONE,
104 16, UNIPHIER_PIN_DRV_8_12_16_20,
105 123, UNIPHIER_PIN_PULL_UP),
106 UNIPHIER_PINCTRL_PIN(27, "NFD3_GB", UNIPHIER_PIN_IECTRL_NONE,
107 20, UNIPHIER_PIN_DRV_8_12_16_20,
108 124, UNIPHIER_PIN_PULL_UP),
109 UNIPHIER_PINCTRL_PIN(28, "NFD4_GB", UNIPHIER_PIN_IECTRL_NONE,
110 24, UNIPHIER_PIN_DRV_8_12_16_20,
111 125, UNIPHIER_PIN_PULL_UP),
112 UNIPHIER_PINCTRL_PIN(29, "NFD5_GB", UNIPHIER_PIN_IECTRL_NONE,
113 28, UNIPHIER_PIN_DRV_8_12_16_20,
114 126, UNIPHIER_PIN_PULL_UP),
115 UNIPHIER_PINCTRL_PIN(30, "NFD6_GB", UNIPHIER_PIN_IECTRL_NONE,
116 32, UNIPHIER_PIN_DRV_8_12_16_20,
117 127, UNIPHIER_PIN_PULL_UP),
118 UNIPHIER_PINCTRL_PIN(31, "NFD7_GB", UNIPHIER_PIN_IECTRL_NONE,
119 36, UNIPHIER_PIN_DRV_8_12_16_20,
120 128, UNIPHIER_PIN_PULL_UP),
121 UNIPHIER_PINCTRL_PIN(32, "SDCLK", UNIPHIER_PIN_IECTRL_NONE,
122 40, UNIPHIER_PIN_DRV_8_12_16_20,
123 -1, UNIPHIER_PIN_PULL_NONE),
124 UNIPHIER_PINCTRL_PIN(33, "SDCMD", UNIPHIER_PIN_IECTRL_NONE,
125 44, UNIPHIER_PIN_DRV_8_12_16_20,
126 -1, UNIPHIER_PIN_PULL_NONE),
127 UNIPHIER_PINCTRL_PIN(34, "SDDAT0", UNIPHIER_PIN_IECTRL_NONE,
128 48, UNIPHIER_PIN_DRV_8_12_16_20,
129 -1, UNIPHIER_PIN_PULL_NONE),
130 UNIPHIER_PINCTRL_PIN(35, "SDDAT1", UNIPHIER_PIN_IECTRL_NONE,
131 52, UNIPHIER_PIN_DRV_8_12_16_20,
132 -1, UNIPHIER_PIN_PULL_NONE),
133 UNIPHIER_PINCTRL_PIN(36, "SDDAT2", UNIPHIER_PIN_IECTRL_NONE,
134 56, UNIPHIER_PIN_DRV_8_12_16_20,
135 -1, UNIPHIER_PIN_PULL_NONE),
136 UNIPHIER_PINCTRL_PIN(37, "SDDAT3", UNIPHIER_PIN_IECTRL_NONE,
137 60, UNIPHIER_PIN_DRV_8_12_16_20,
138 -1, UNIPHIER_PIN_PULL_NONE),
139 UNIPHIER_PINCTRL_PIN(38, "SDCD", UNIPHIER_PIN_IECTRL_NONE,
140 -1, UNIPHIER_PIN_DRV_FIXED_4,
141 129, UNIPHIER_PIN_PULL_DOWN),
142 UNIPHIER_PINCTRL_PIN(39, "SDWP", UNIPHIER_PIN_IECTRL_NONE,
143 -1, UNIPHIER_PIN_DRV_FIXED_4,
144 130, UNIPHIER_PIN_PULL_DOWN),
145 UNIPHIER_PINCTRL_PIN(40, "SDVOLC", UNIPHIER_PIN_IECTRL_NONE,
146 -1, UNIPHIER_PIN_DRV_FIXED_4,
147 131, UNIPHIER_PIN_PULL_DOWN),
148 UNIPHIER_PINCTRL_PIN(41, "USB0VBUS", UNIPHIER_PIN_IECTRL_NONE,
149 37, UNIPHIER_PIN_DRV_4_8,
150 37, UNIPHIER_PIN_PULL_DOWN),
151 UNIPHIER_PINCTRL_PIN(42, "USB0OD", UNIPHIER_PIN_IECTRL_NONE,
152 38, UNIPHIER_PIN_DRV_4_8,
153 38, UNIPHIER_PIN_PULL_DOWN),
154 UNIPHIER_PINCTRL_PIN(43, "USB1VBUS", UNIPHIER_PIN_IECTRL_NONE,
155 39, UNIPHIER_PIN_DRV_4_8,
156 39, UNIPHIER_PIN_PULL_DOWN),
157 UNIPHIER_PINCTRL_PIN(44, "USB1OD", UNIPHIER_PIN_IECTRL_NONE,
158 40, UNIPHIER_PIN_DRV_4_8,
159 40, UNIPHIER_PIN_PULL_DOWN),
160 UNIPHIER_PINCTRL_PIN(45, "PCRESET", UNIPHIER_PIN_IECTRL_NONE,
161 41, UNIPHIER_PIN_DRV_4_8,
162 41, UNIPHIER_PIN_PULL_DOWN),
163 UNIPHIER_PINCTRL_PIN(46, "PCREG", UNIPHIER_PIN_IECTRL_NONE,
164 42, UNIPHIER_PIN_DRV_4_8,
165 42, UNIPHIER_PIN_PULL_DOWN),
166 UNIPHIER_PINCTRL_PIN(47, "PCCE2", UNIPHIER_PIN_IECTRL_NONE,
167 43, UNIPHIER_PIN_DRV_4_8,
168 43, UNIPHIER_PIN_PULL_DOWN),
169 UNIPHIER_PINCTRL_PIN(48, "PCVS1", UNIPHIER_PIN_IECTRL_NONE,
170 44, UNIPHIER_PIN_DRV_4_8,
171 44, UNIPHIER_PIN_PULL_DOWN),
172 UNIPHIER_PINCTRL_PIN(49, "PCCD2", UNIPHIER_PIN_IECTRL_NONE,
173 45, UNIPHIER_PIN_DRV_4_8,
174 45, UNIPHIER_PIN_PULL_DOWN),
175 UNIPHIER_PINCTRL_PIN(50, "PCCD1", UNIPHIER_PIN_IECTRL_NONE,
176 46, UNIPHIER_PIN_DRV_4_8,
177 46, UNIPHIER_PIN_PULL_DOWN),
178 UNIPHIER_PINCTRL_PIN(51, "PCREADY", UNIPHIER_PIN_IECTRL_NONE,
179 47, UNIPHIER_PIN_DRV_4_8,
180 47, UNIPHIER_PIN_PULL_DOWN),
181 UNIPHIER_PINCTRL_PIN(52, "PCDOE", UNIPHIER_PIN_IECTRL_NONE,
182 48, UNIPHIER_PIN_DRV_4_8,
183 48, UNIPHIER_PIN_PULL_DOWN),
184 UNIPHIER_PINCTRL_PIN(53, "PCCE1", UNIPHIER_PIN_IECTRL_NONE,
185 49, UNIPHIER_PIN_DRV_4_8,
186 49, UNIPHIER_PIN_PULL_DOWN),
187 UNIPHIER_PINCTRL_PIN(54, "PCWE", UNIPHIER_PIN_IECTRL_NONE,
188 50, UNIPHIER_PIN_DRV_4_8,
189 50, UNIPHIER_PIN_PULL_DOWN),
190 UNIPHIER_PINCTRL_PIN(55, "PCOE", UNIPHIER_PIN_IECTRL_NONE,
191 51, UNIPHIER_PIN_DRV_4_8,
192 51, UNIPHIER_PIN_PULL_DOWN),
193 UNIPHIER_PINCTRL_PIN(56, "PCWAIT", UNIPHIER_PIN_IECTRL_NONE,
194 52, UNIPHIER_PIN_DRV_4_8,
195 52, UNIPHIER_PIN_PULL_DOWN),
196 UNIPHIER_PINCTRL_PIN(57, "PCIOWR", UNIPHIER_PIN_IECTRL_NONE,
197 53, UNIPHIER_PIN_DRV_4_8,
198 53, UNIPHIER_PIN_PULL_DOWN),
199 UNIPHIER_PINCTRL_PIN(58, "PCIORD", UNIPHIER_PIN_IECTRL_NONE,
200 54, UNIPHIER_PIN_DRV_4_8,
201 54, UNIPHIER_PIN_PULL_DOWN),
202 UNIPHIER_PINCTRL_PIN(59, "HS0DIN0", UNIPHIER_PIN_IECTRL_NONE,
203 55, UNIPHIER_PIN_DRV_4_8,
204 55, UNIPHIER_PIN_PULL_DOWN),
205 UNIPHIER_PINCTRL_PIN(60, "HS0DIN1", UNIPHIER_PIN_IECTRL_NONE,
206 56, UNIPHIER_PIN_DRV_4_8,
207 56, UNIPHIER_PIN_PULL_DOWN),
208 UNIPHIER_PINCTRL_PIN(61, "HS0DIN2", UNIPHIER_PIN_IECTRL_NONE,
209 57, UNIPHIER_PIN_DRV_4_8,
210 57, UNIPHIER_PIN_PULL_DOWN),
211 UNIPHIER_PINCTRL_PIN(62, "HS0DIN3", UNIPHIER_PIN_IECTRL_NONE,
212 58, UNIPHIER_PIN_DRV_4_8,
213 58, UNIPHIER_PIN_PULL_DOWN),
214 UNIPHIER_PINCTRL_PIN(63, "HS0DIN4", UNIPHIER_PIN_IECTRL_NONE,
215 59, UNIPHIER_PIN_DRV_4_8,
216 59, UNIPHIER_PIN_PULL_DOWN),
217 UNIPHIER_PINCTRL_PIN(64, "HS0DIN5", UNIPHIER_PIN_IECTRL_NONE,
218 60, UNIPHIER_PIN_DRV_4_8,
219 60, UNIPHIER_PIN_PULL_DOWN),
220 UNIPHIER_PINCTRL_PIN(65, "HS0DIN6", UNIPHIER_PIN_IECTRL_NONE,
221 61, UNIPHIER_PIN_DRV_4_8,
222 61, UNIPHIER_PIN_PULL_DOWN),
223 UNIPHIER_PINCTRL_PIN(66, "HS0DIN7", UNIPHIER_PIN_IECTRL_NONE,
224 62, UNIPHIER_PIN_DRV_4_8,
225 62, UNIPHIER_PIN_PULL_DOWN),
226 UNIPHIER_PINCTRL_PIN(67, "HS0BCLKIN", UNIPHIER_PIN_IECTRL_NONE,
227 63, UNIPHIER_PIN_DRV_4_8,
228 63, UNIPHIER_PIN_PULL_DOWN),
229 UNIPHIER_PINCTRL_PIN(68, "HS0VALIN", UNIPHIER_PIN_IECTRL_NONE,
230 64, UNIPHIER_PIN_DRV_4_8,
231 64, UNIPHIER_PIN_PULL_DOWN),
232 UNIPHIER_PINCTRL_PIN(69, "HS0SYNCIN", UNIPHIER_PIN_IECTRL_NONE,
233 65, UNIPHIER_PIN_DRV_4_8,
234 65, UNIPHIER_PIN_PULL_DOWN),
235 UNIPHIER_PINCTRL_PIN(70, "HSDOUT0", UNIPHIER_PIN_IECTRL_NONE,
236 66, UNIPHIER_PIN_DRV_4_8,
237 66, UNIPHIER_PIN_PULL_DOWN),
238 UNIPHIER_PINCTRL_PIN(71, "HSDOUT1", UNIPHIER_PIN_IECTRL_NONE,
239 67, UNIPHIER_PIN_DRV_4_8,
240 67, UNIPHIER_PIN_PULL_DOWN),
241 UNIPHIER_PINCTRL_PIN(72, "HSDOUT2", UNIPHIER_PIN_IECTRL_NONE,
242 68, UNIPHIER_PIN_DRV_4_8,
243 68, UNIPHIER_PIN_PULL_DOWN),
244 UNIPHIER_PINCTRL_PIN(73, "HSDOUT3", UNIPHIER_PIN_IECTRL_NONE,
245 69, UNIPHIER_PIN_DRV_4_8,
246 69, UNIPHIER_PIN_PULL_DOWN),
247 UNIPHIER_PINCTRL_PIN(74, "HSDOUT4", UNIPHIER_PIN_IECTRL_NONE,
248 70, UNIPHIER_PIN_DRV_4_8,
249 70, UNIPHIER_PIN_PULL_DOWN),
250 UNIPHIER_PINCTRL_PIN(75, "HSDOUT5", UNIPHIER_PIN_IECTRL_NONE,
251 71, UNIPHIER_PIN_DRV_4_8,
252 71, UNIPHIER_PIN_PULL_DOWN),
253 UNIPHIER_PINCTRL_PIN(76, "HSDOUT6", UNIPHIER_PIN_IECTRL_NONE,
254 72, UNIPHIER_PIN_DRV_4_8,
255 72, UNIPHIER_PIN_PULL_DOWN),
256 UNIPHIER_PINCTRL_PIN(77, "HSDOUT7", UNIPHIER_PIN_IECTRL_NONE,
257 73, UNIPHIER_PIN_DRV_4_8,
258 73, UNIPHIER_PIN_PULL_DOWN),
259 UNIPHIER_PINCTRL_PIN(78, "HSBCLKOUT", UNIPHIER_PIN_IECTRL_NONE,
260 74, UNIPHIER_PIN_DRV_4_8,
261 74, UNIPHIER_PIN_PULL_DOWN),
262 UNIPHIER_PINCTRL_PIN(79, "HSVALOUT", UNIPHIER_PIN_IECTRL_NONE,
263 75, UNIPHIER_PIN_DRV_4_8,
264 75, UNIPHIER_PIN_PULL_DOWN),
265 UNIPHIER_PINCTRL_PIN(80, "HSSYNCOUT", UNIPHIER_PIN_IECTRL_NONE,
266 76, UNIPHIER_PIN_DRV_4_8,
267 76, UNIPHIER_PIN_PULL_DOWN),
268 UNIPHIER_PINCTRL_PIN(81, "HS1DIN0", UNIPHIER_PIN_IECTRL_NONE,
269 77, UNIPHIER_PIN_DRV_4_8,
270 77, UNIPHIER_PIN_PULL_DOWN),
271 UNIPHIER_PINCTRL_PIN(82, "HS1DIN1", UNIPHIER_PIN_IECTRL_NONE,
272 78, UNIPHIER_PIN_DRV_4_8,
273 78, UNIPHIER_PIN_PULL_DOWN),
274 UNIPHIER_PINCTRL_PIN(83, "HS1DIN2", UNIPHIER_PIN_IECTRL_NONE,
275 79, UNIPHIER_PIN_DRV_4_8,
276 79, UNIPHIER_PIN_PULL_DOWN),
277 UNIPHIER_PINCTRL_PIN(84, "HS1DIN3", UNIPHIER_PIN_IECTRL_NONE,
278 80, UNIPHIER_PIN_DRV_4_8,
279 80, UNIPHIER_PIN_PULL_DOWN),
280 UNIPHIER_PINCTRL_PIN(85, "HS1DIN4", UNIPHIER_PIN_IECTRL_NONE,
281 81, UNIPHIER_PIN_DRV_4_8,
282 81, UNIPHIER_PIN_PULL_DOWN),
283 UNIPHIER_PINCTRL_PIN(86, "HS1DIN5", UNIPHIER_PIN_IECTRL_NONE,
284 82, UNIPHIER_PIN_DRV_4_8,
285 82, UNIPHIER_PIN_PULL_DOWN),
286 UNIPHIER_PINCTRL_PIN(87, "HS1DIN6", UNIPHIER_PIN_IECTRL_NONE,
287 83, UNIPHIER_PIN_DRV_4_8,
288 83, UNIPHIER_PIN_PULL_DOWN),
289 UNIPHIER_PINCTRL_PIN(88, "HS1DIN7", UNIPHIER_PIN_IECTRL_NONE,
290 84, UNIPHIER_PIN_DRV_4_8,
291 84, UNIPHIER_PIN_PULL_DOWN),
292 UNIPHIER_PINCTRL_PIN(89, "HS1BCLKIN", UNIPHIER_PIN_IECTRL_NONE,
293 85, UNIPHIER_PIN_DRV_4_8,
294 85, UNIPHIER_PIN_PULL_DOWN),
295 UNIPHIER_PINCTRL_PIN(90, "HS1VALIN", UNIPHIER_PIN_IECTRL_NONE,
296 86, UNIPHIER_PIN_DRV_4_8,
297 86, UNIPHIER_PIN_PULL_DOWN),
298 UNIPHIER_PINCTRL_PIN(91, "HS1SYNCIN", UNIPHIER_PIN_IECTRL_NONE,
299 87, UNIPHIER_PIN_DRV_4_8,
300 87, UNIPHIER_PIN_PULL_DOWN),
301 UNIPHIER_PINCTRL_PIN(92, "AGCI", UNIPHIER_PIN_IECTRL_NONE,
302 -1, UNIPHIER_PIN_DRV_FIXED_4,
303 132, UNIPHIER_PIN_PULL_DOWN),
304 UNIPHIER_PINCTRL_PIN(93, "AGCR", UNIPHIER_PIN_IECTRL_NONE,
305 -1, UNIPHIER_PIN_DRV_FIXED_4,
306 133, UNIPHIER_PIN_PULL_DOWN),
307 UNIPHIER_PINCTRL_PIN(94, "AGCBS", UNIPHIER_PIN_IECTRL_NONE,
308 -1, UNIPHIER_PIN_DRV_FIXED_4,
309 134, UNIPHIER_PIN_PULL_DOWN),
310 UNIPHIER_PINCTRL_PIN(95, "IECOUT", UNIPHIER_PIN_IECTRL_NONE,
311 88, UNIPHIER_PIN_DRV_4_8,
312 88, UNIPHIER_PIN_PULL_DOWN),
313 UNIPHIER_PINCTRL_PIN(96, "ASMCK", UNIPHIER_PIN_IECTRL_NONE,
314 89, UNIPHIER_PIN_DRV_4_8,
315 89, UNIPHIER_PIN_PULL_DOWN),
316 UNIPHIER_PINCTRL_PIN(97, "ABCKO", UNIPHIER_PIN_IECTRL_NONE,
317 90, UNIPHIER_PIN_DRV_4_8,
318 90, UNIPHIER_PIN_PULL_DOWN),
319 UNIPHIER_PINCTRL_PIN(98, "ALRCKO", UNIPHIER_PIN_IECTRL_NONE,
320 91, UNIPHIER_PIN_DRV_4_8,
321 91, UNIPHIER_PIN_PULL_DOWN),
322 UNIPHIER_PINCTRL_PIN(99, "ASDOUT0", UNIPHIER_PIN_IECTRL_NONE,
323 92, UNIPHIER_PIN_DRV_4_8,
324 92, UNIPHIER_PIN_PULL_DOWN),
325 UNIPHIER_PINCTRL_PIN(100, "ASDOUT1", UNIPHIER_PIN_IECTRL_NONE,
326 93, UNIPHIER_PIN_DRV_4_8,
327 93, UNIPHIER_PIN_PULL_UP),
328 UNIPHIER_PINCTRL_PIN(101, "ARCOUT", UNIPHIER_PIN_IECTRL_NONE,
329 94, UNIPHIER_PIN_DRV_4_8,
330 94, UNIPHIER_PIN_PULL_DOWN),
331 UNIPHIER_PINCTRL_PIN(102, "SDA0", UNIPHIER_PIN_IECTRL_NONE,
332 -1, UNIPHIER_PIN_DRV_FIXED_4,
333 -1, UNIPHIER_PIN_PULL_NONE),
334 UNIPHIER_PINCTRL_PIN(103, "SCL0", UNIPHIER_PIN_IECTRL_NONE,
335 -1, UNIPHIER_PIN_DRV_FIXED_4,
336 -1, UNIPHIER_PIN_PULL_NONE),
337 UNIPHIER_PINCTRL_PIN(104, "SDA1", UNIPHIER_PIN_IECTRL_NONE,
338 -1, UNIPHIER_PIN_DRV_FIXED_4,
339 -1, UNIPHIER_PIN_PULL_NONE),
340 UNIPHIER_PINCTRL_PIN(105, "SCL1", UNIPHIER_PIN_IECTRL_NONE,
341 -1, UNIPHIER_PIN_DRV_FIXED_4,
342 -1, UNIPHIER_PIN_PULL_NONE),
343 UNIPHIER_PINCTRL_PIN(106, "DMDSDA0", UNIPHIER_PIN_IECTRL_NONE,
344 -1, UNIPHIER_PIN_DRV_FIXED_4,
345 -1, UNIPHIER_PIN_PULL_NONE),
346 UNIPHIER_PINCTRL_PIN(107, "DMDSCL0", UNIPHIER_PIN_IECTRL_NONE,
347 -1, UNIPHIER_PIN_DRV_FIXED_4,
348 -1, UNIPHIER_PIN_PULL_NONE),
349 UNIPHIER_PINCTRL_PIN(108, "DMDSDA1", UNIPHIER_PIN_IECTRL_NONE,
350 -1, UNIPHIER_PIN_DRV_FIXED_4,
351 -1, UNIPHIER_PIN_PULL_NONE),
352 UNIPHIER_PINCTRL_PIN(109, "DMDSCL1", UNIPHIER_PIN_IECTRL_NONE,
353 -1, UNIPHIER_PIN_DRV_FIXED_4,
354 -1, UNIPHIER_PIN_PULL_NONE),
355 UNIPHIER_PINCTRL_PIN(110, "SBO0", UNIPHIER_PIN_IECTRL_NONE,
356 95, UNIPHIER_PIN_DRV_4_8,
357 95, UNIPHIER_PIN_PULL_UP),
358 UNIPHIER_PINCTRL_PIN(111, "SBI0", UNIPHIER_PIN_IECTRL_NONE,
359 96, UNIPHIER_PIN_DRV_4_8,
360 96, UNIPHIER_PIN_PULL_UP),
361 UNIPHIER_PINCTRL_PIN(112, "SBO1", UNIPHIER_PIN_IECTRL_NONE,
362 97, UNIPHIER_PIN_DRV_4_8,
363 97, UNIPHIER_PIN_PULL_UP),
364 UNIPHIER_PINCTRL_PIN(113, "SBI1", UNIPHIER_PIN_IECTRL_NONE,
365 98, UNIPHIER_PIN_DRV_4_8,
366 98, UNIPHIER_PIN_PULL_UP),
367 UNIPHIER_PINCTRL_PIN(114, "TXD1", UNIPHIER_PIN_IECTRL_NONE,
368 99, UNIPHIER_PIN_DRV_4_8,
369 99, UNIPHIER_PIN_PULL_UP),
370 UNIPHIER_PINCTRL_PIN(115, "RXD1", UNIPHIER_PIN_IECTRL_NONE,
371 100, UNIPHIER_PIN_DRV_4_8,
372 100, UNIPHIER_PIN_PULL_UP),
373 UNIPHIER_PINCTRL_PIN(116, "HIN", UNIPHIER_PIN_IECTRL_NONE,
374 -1, UNIPHIER_PIN_DRV_FIXED_5,
375 -1, UNIPHIER_PIN_PULL_NONE),
376 UNIPHIER_PINCTRL_PIN(117, "VIN", UNIPHIER_PIN_IECTRL_NONE,
377 -1, UNIPHIER_PIN_DRV_FIXED_5,
378 -1, UNIPHIER_PIN_PULL_NONE),
379 UNIPHIER_PINCTRL_PIN(118, "TCON0", UNIPHIER_PIN_IECTRL_NONE,
380 101, UNIPHIER_PIN_DRV_4_8,
381 101, UNIPHIER_PIN_PULL_DOWN),
382 UNIPHIER_PINCTRL_PIN(119, "TCON1", UNIPHIER_PIN_IECTRL_NONE,
383 102, UNIPHIER_PIN_DRV_4_8,
384 102, UNIPHIER_PIN_PULL_DOWN),
385 UNIPHIER_PINCTRL_PIN(120, "TCON2", UNIPHIER_PIN_IECTRL_NONE,
386 103, UNIPHIER_PIN_DRV_4_8,
387 103, UNIPHIER_PIN_PULL_DOWN),
388 UNIPHIER_PINCTRL_PIN(121, "TCON3", UNIPHIER_PIN_IECTRL_NONE,
389 104, UNIPHIER_PIN_DRV_4_8,
390 104, UNIPHIER_PIN_PULL_DOWN),
391 UNIPHIER_PINCTRL_PIN(122, "TCON4", UNIPHIER_PIN_IECTRL_NONE,
392 105, UNIPHIER_PIN_DRV_4_8,
393 105, UNIPHIER_PIN_PULL_DOWN),
394 UNIPHIER_PINCTRL_PIN(123, "TCON5", UNIPHIER_PIN_IECTRL_NONE,
395 106, UNIPHIER_PIN_DRV_4_8,
396 106, UNIPHIER_PIN_PULL_DOWN),
397 UNIPHIER_PINCTRL_PIN(124, "TCON6", UNIPHIER_PIN_IECTRL_NONE,
398 107, UNIPHIER_PIN_DRV_4_8,
399 107, UNIPHIER_PIN_PULL_DOWN),
400 UNIPHIER_PINCTRL_PIN(125, "TCON7", UNIPHIER_PIN_IECTRL_NONE,
401 108, UNIPHIER_PIN_DRV_4_8,
402 108, UNIPHIER_PIN_PULL_DOWN),
403 UNIPHIER_PINCTRL_PIN(126, "TCON8", UNIPHIER_PIN_IECTRL_NONE,
404 109, UNIPHIER_PIN_DRV_4_8,
405 109, UNIPHIER_PIN_PULL_DOWN),
406 UNIPHIER_PINCTRL_PIN(127, "PWMA", UNIPHIER_PIN_IECTRL_NONE,
407 110, UNIPHIER_PIN_DRV_4_8,
408 110, UNIPHIER_PIN_PULL_DOWN),
409 UNIPHIER_PINCTRL_PIN(128, "XIRQ0", UNIPHIER_PIN_IECTRL_NONE,
410 111, UNIPHIER_PIN_DRV_4_8,
411 111, UNIPHIER_PIN_PULL_DOWN),
412 UNIPHIER_PINCTRL_PIN(129, "XIRQ1", UNIPHIER_PIN_IECTRL_NONE,
413 112, UNIPHIER_PIN_DRV_4_8,
414 112, UNIPHIER_PIN_PULL_DOWN),
415 UNIPHIER_PINCTRL_PIN(130, "XIRQ2", UNIPHIER_PIN_IECTRL_NONE,
416 113, UNIPHIER_PIN_DRV_4_8,
417 113, UNIPHIER_PIN_PULL_DOWN),
418 UNIPHIER_PINCTRL_PIN(131, "XIRQ3", UNIPHIER_PIN_IECTRL_NONE,
419 114, UNIPHIER_PIN_DRV_4_8,
420 114, UNIPHIER_PIN_PULL_DOWN),
421 UNIPHIER_PINCTRL_PIN(132, "XIRQ4", UNIPHIER_PIN_IECTRL_NONE,
422 115, UNIPHIER_PIN_DRV_4_8,
423 115, UNIPHIER_PIN_PULL_DOWN),
424 UNIPHIER_PINCTRL_PIN(133, "XIRQ5", UNIPHIER_PIN_IECTRL_NONE,
425 116, UNIPHIER_PIN_DRV_4_8,
426 116, UNIPHIER_PIN_PULL_DOWN),
427 UNIPHIER_PINCTRL_PIN(134, "XIRQ6", UNIPHIER_PIN_IECTRL_NONE,
428 117, UNIPHIER_PIN_DRV_4_8,
429 117, UNIPHIER_PIN_PULL_DOWN),
430 UNIPHIER_PINCTRL_PIN(135, "XIRQ7", UNIPHIER_PIN_IECTRL_NONE,
431 118, UNIPHIER_PIN_DRV_4_8,
432 118, UNIPHIER_PIN_PULL_DOWN),
433};
434
435static const unsigned emmc_pins[] = {21, 22, 23, 24, 25, 26, 27};
436static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
437static const unsigned emmc_dat8_pins[] = {28, 29, 30, 31};
438static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
439static const unsigned i2c0_pins[] = {102, 103};
440static const unsigned i2c0_muxvals[] = {0, 0};
441static const unsigned i2c1_pins[] = {104, 105};
442static const unsigned i2c1_muxvals[] = {0, 0};
443static const unsigned i2c2_pins[] = {108, 109};
444static const unsigned i2c2_muxvals[] = {2, 2};
445static const unsigned i2c3_pins[] = {108, 109};
446static const unsigned i2c3_muxvals[] = {3, 3};
447static const unsigned nand_pins[] = {15, 16, 17, 18, 19, 20, 21, 24, 25, 26,
448 27, 28, 29, 30, 31};
449static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
450 0, 0};
451static const unsigned nand_cs1_pins[] = {22, 23};
452static const unsigned nand_cs1_muxvals[] = {0, 0};
453static const unsigned uart0_pins[] = {70, 71};
454static const unsigned uart0_muxvals[] = {3, 3};
455static const unsigned uart1_pins[] = {114, 115};
456static const unsigned uart1_muxvals[] = {0, 0};
457static const unsigned uart2_pins[] = {112, 113};
458static const unsigned uart2_muxvals[] = {1, 1};
459static const unsigned uart3_pins[] = {110, 111};
460static const unsigned uart3_muxvals[] = {1, 1};
461static const unsigned usb0_pins[] = {41, 42};
462static const unsigned usb0_muxvals[] = {0, 0};
463static const unsigned usb1_pins[] = {43, 44};
464static const unsigned usb1_muxvals[] = {0, 0};
465static const unsigned usb2_pins[] = {114, 115};
466static const unsigned usb2_muxvals[] = {1, 1};
467static const unsigned port_range0_pins[] = {
468 0, 1, 2, 3, 4, 5, 6, 7, /* PORT0x */
469 8, 9, 10, 11, 12, 13, 14, 15, /* PORT1x */
470 32, 33, 34, 35, 36, 37, 38, 39, /* PORT2x */
471 59, 60, 61, 62, 63, 64, 65, 66, /* PORT3x */
472 95, 96, 97, 98, 99, 100, 101, 57, /* PORT4x */
473 70, 71, 72, 73, 74, 75, 76, 77, /* PORT5x */
474 81, 83, 84, 85, 86, 89, 90, 91, /* PORT6x */
475 118, 119, 120, 121, 122, 53, 54, 55, /* PORT7x */
476 41, 42, 43, 44, 79, 80, 18, 19, /* PORT8x */
477 110, 111, 112, 113, 114, 115, 16, 17, /* PORT9x */
478 40, 67, 68, 69, 78, 92, 93, 94, /* PORT10x */
479 48, 49, 46, 45, 123, 124, 125, 126, /* PORT11x */
480 47, 127, 20, 56, 22, /* PORT120-124 */
481};
482static const unsigned port_range0_muxvals[] = {
483 15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */
484 15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */
485 15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */
486 15, 15, 15, 15, 15, 15, 15, 15, /* PORT3x */
487 15, 15, 15, 15, 15, 15, 15, 15, /* PORT4x */
488 15, 15, 15, 15, 15, 15, 15, 15, /* PORT5x */
489 15, 15, 15, 15, 15, 15, 15, 15, /* PORT6x */
490 15, 15, 15, 15, 15, 15, 15, 15, /* PORT7x */
491 15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */
492 15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */
493 15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */
494 15, 15, 15, 15, 15, 15, 15, 15, /* PORT11x */
495 15, 15, 15, 15, 15, /* PORT120-124 */
496};
497static const unsigned port_range1_pins[] = {
498 116, 117, /* PORT130-131 */
499};
500static const unsigned port_range1_muxvals[] = {
501 15, 15, /* PORT130-131 */
502};
503static const unsigned port_range2_pins[] = {
504 102, 103, 104, 105, 106, 107, 108, 109, /* PORT14x */
505};
506static const unsigned port_range2_muxvals[] = {
507 15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */
508};
509static const unsigned port_range3_pins[] = {
510 23, /* PORT166 */
511};
512static const unsigned port_range3_muxvals[] = {
513 15, /* PORT166 */
514};
515static const unsigned xirq_range0_pins[] = {
516 128, 129, 130, 131, 132, 133, 134, 135, /* XIRQ0-7 */
517 82, 87, 88, 50, 51, /* XIRQ8-12 */
518};
519static const unsigned xirq_range0_muxvals[] = {
520 0, 0, 0, 0, 0, 0, 0, 0, /* XIRQ0-7 */
521 14, 14, 14, 14, 14, /* XIRQ8-12 */
522};
523static const unsigned xirq_range1_pins[] = {
524 52, 58, /* XIRQ14-15 */
525};
526static const unsigned xirq_range1_muxvals[] = {
527 14, 14, /* XIRQ14-15 */
528};
529
530static const struct uniphier_pinctrl_group ph1_sld8_groups[] = {
531 UNIPHIER_PINCTRL_GROUP(emmc),
532 UNIPHIER_PINCTRL_GROUP(emmc_dat8),
533 UNIPHIER_PINCTRL_GROUP(i2c0),
534 UNIPHIER_PINCTRL_GROUP(i2c1),
535 UNIPHIER_PINCTRL_GROUP(i2c2),
536 UNIPHIER_PINCTRL_GROUP(i2c3),
537 UNIPHIER_PINCTRL_GROUP(nand),
538 UNIPHIER_PINCTRL_GROUP(nand_cs1),
539 UNIPHIER_PINCTRL_GROUP(uart0),
540 UNIPHIER_PINCTRL_GROUP(uart1),
541 UNIPHIER_PINCTRL_GROUP(uart2),
542 UNIPHIER_PINCTRL_GROUP(uart3),
543 UNIPHIER_PINCTRL_GROUP(usb0),
544 UNIPHIER_PINCTRL_GROUP(usb1),
545 UNIPHIER_PINCTRL_GROUP(usb2),
546 UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0),
547 UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1),
548 UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range2),
549 UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range3),
550 UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_range0),
551 UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_range1),
552 UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0),
553 UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1),
554 UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2),
555 UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3),
556 UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4),
557 UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5),
558 UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6),
559 UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7),
560 UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8),
561 UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9),
562 UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10),
563 UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11),
564 UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12),
565 UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13),
566 UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14),
567 UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15),
568 UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16),
569 UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17),
570 UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18),
571 UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19),
572 UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20),
573 UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21),
574 UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22),
575 UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23),
576 UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24),
577 UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25),
578 UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26),
579 UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27),
580 UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28),
581 UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29),
582 UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30),
583 UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31),
584 UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32),
585 UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33),
586 UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34),
587 UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35),
588 UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36),
589 UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37),
590 UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38),
591 UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39),
592 UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40),
593 UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41),
594 UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42),
595 UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43),
596 UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44),
597 UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45),
598 UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46),
599 UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47),
600 UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48),
601 UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49),
602 UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50),
603 UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51),
604 UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52),
605 UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53),
606 UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54),
607 UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55),
608 UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56),
609 UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57),
610 UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58),
611 UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59),
612 UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60),
613 UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61),
614 UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62),
615 UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63),
616 UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64),
617 UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65),
618 UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66),
619 UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67),
620 UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68),
621 UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69),
622 UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70),
623 UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71),
624 UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72),
625 UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73),
626 UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74),
627 UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75),
628 UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76),
629 UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77),
630 UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78),
631 UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79),
632 UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80),
633 UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81),
634 UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82),
635 UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83),
636 UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84),
637 UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85),
638 UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86),
639 UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87),
640 UNIPHIER_PINCTRL_GROUP_SINGLE(port110, port_range0, 88),
641 UNIPHIER_PINCTRL_GROUP_SINGLE(port111, port_range0, 89),
642 UNIPHIER_PINCTRL_GROUP_SINGLE(port112, port_range0, 90),
643 UNIPHIER_PINCTRL_GROUP_SINGLE(port113, port_range0, 91),
644 UNIPHIER_PINCTRL_GROUP_SINGLE(port114, port_range0, 92),
645 UNIPHIER_PINCTRL_GROUP_SINGLE(port115, port_range0, 93),
646 UNIPHIER_PINCTRL_GROUP_SINGLE(port116, port_range0, 94),
647 UNIPHIER_PINCTRL_GROUP_SINGLE(port117, port_range0, 95),
648 UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range0, 96),
649 UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range0, 97),
650 UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range0, 98),
651 UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range0, 99),
652 UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range0, 100),
653 UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range1, 0),
654 UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range1, 1),
655 UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range2, 0),
656 UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range2, 1),
657 UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range2, 2),
658 UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range2, 3),
659 UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range2, 4),
660 UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range2, 5),
661 UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range2, 6),
662 UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range2, 7),
663 UNIPHIER_PINCTRL_GROUP_SINGLE(port166, port_range3, 0),
664 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq_range0, 0),
665 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq_range0, 1),
666 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq_range0, 2),
667 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq_range0, 3),
668 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq_range0, 4),
669 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq_range0, 5),
670 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq_range0, 6),
671 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq_range0, 7),
672 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq_range0, 8),
673 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq_range0, 9),
674 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq_range0, 10),
675 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq_range0, 11),
676 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq_range0, 12),
677 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq_range1, 0),
678 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq_range1, 1),
679};
680
681static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
682static const char * const i2c0_groups[] = {"i2c0"};
683static const char * const i2c1_groups[] = {"i2c1"};
684static const char * const i2c2_groups[] = {"i2c2"};
685static const char * const i2c3_groups[] = {"i2c3"};
686static const char * const nand_groups[] = {"nand", "nand_cs1"};
687static const char * const uart0_groups[] = {"uart0"};
688static const char * const uart1_groups[] = {"uart1"};
689static const char * const uart2_groups[] = {"uart2"};
690static const char * const uart3_groups[] = {"uart3"};
691static const char * const usb0_groups[] = {"usb0"};
692static const char * const usb1_groups[] = {"usb1"};
693static const char * const usb2_groups[] = {"usb2"};
694static const char * const port_groups[] = {
695 "port00", "port01", "port02", "port03",
696 "port04", "port05", "port06", "port07",
697 "port10", "port11", "port12", "port13",
698 "port14", "port15", "port16", "port17",
699 "port20", "port21", "port22", "port23",
700 "port24", "port25", "port26", "port27",
701 "port30", "port31", "port32", "port33",
702 "port34", "port35", "port36", "port37",
703 "port40", "port41", "port42", "port43",
704 "port44", "port45", "port46", "port47",
705 "port50", "port51", "port52", "port53",
706 "port54", "port55", "port56", "port57",
707 "port60", "port61", "port62", "port63",
708 "port64", "port65", "port66", "port67",
709 "port70", "port71", "port72", "port73",
710 "port74", "port75", "port76", "port77",
711 "port80", "port81", "port82", "port83",
712 "port84", "port85", "port86", "port87",
713 "port90", "port91", "port92", "port93",
714 "port94", "port95", "port96", "port97",
715 "port100", "port101", "port102", "port103",
716 "port104", "port105", "port106", "port107",
717 "port110", "port111", "port112", "port113",
718 "port114", "port115", "port116", "port117",
719 "port120", "port121", "port122", "port123",
720 "port124", "port125", "port126", "port127",
721 "port130", "port131", "port132", "port133",
722 "port134", "port135", "port136", "port137",
723 "port140", "port141", "port142", "port143",
724 "port144", "port145", "port146", "port147",
725 /* port150-164 missing */
726 /* none */ "port165",
727};
728static const char * const xirq_groups[] = {
729 "xirq0", "xirq1", "xirq2", "xirq3",
730 "xirq4", "xirq5", "xirq6", "xirq7",
731 "xirq8", "xirq9", "xirq10", "xirq11",
732 "xirq12", /* none*/ "xirq14", "xirq15",
733};
734
735static const struct uniphier_pinmux_function ph1_sld8_functions[] = {
736 UNIPHIER_PINMUX_FUNCTION(emmc),
737 UNIPHIER_PINMUX_FUNCTION(i2c0),
738 UNIPHIER_PINMUX_FUNCTION(i2c1),
739 UNIPHIER_PINMUX_FUNCTION(i2c2),
740 UNIPHIER_PINMUX_FUNCTION(i2c3),
741 UNIPHIER_PINMUX_FUNCTION(nand),
742 UNIPHIER_PINMUX_FUNCTION(uart0),
743 UNIPHIER_PINMUX_FUNCTION(uart1),
744 UNIPHIER_PINMUX_FUNCTION(uart2),
745 UNIPHIER_PINMUX_FUNCTION(uart3),
746 UNIPHIER_PINMUX_FUNCTION(usb0),
747 UNIPHIER_PINMUX_FUNCTION(usb1),
748 UNIPHIER_PINMUX_FUNCTION(usb2),
749 UNIPHIER_PINMUX_FUNCTION(port),
750 UNIPHIER_PINMUX_FUNCTION(xirq),
751};
752
753static struct uniphier_pinctrl_socdata ph1_sld8_pindata = {
754 .groups = ph1_sld8_groups,
755 .groups_count = ARRAY_SIZE(ph1_sld8_groups),
756 .functions = ph1_sld8_functions,
757 .functions_count = ARRAY_SIZE(ph1_sld8_functions),
758 .mux_bits = 8,
759 .reg_stride = 4,
760 .load_pinctrl = false,
761};
762
763static struct pinctrl_desc ph1_sld8_pinctrl_desc = {
764 .name = DRIVER_NAME,
765 .pins = ph1_sld8_pins,
766 .npins = ARRAY_SIZE(ph1_sld8_pins),
767 .owner = THIS_MODULE,
768};
769
770static int ph1_sld8_pinctrl_probe(struct platform_device *pdev)
771{
772 return uniphier_pinctrl_probe(pdev, &ph1_sld8_pinctrl_desc,
773 &ph1_sld8_pindata);
774}
775
776static const struct of_device_id ph1_sld8_pinctrl_match[] = {
777 { .compatible = "socionext,ph1-sld8-pinctrl" },
778 { /* sentinel */ }
779};
780MODULE_DEVICE_TABLE(of, ph1_sld8_pinctrl_match);
781
782static struct platform_driver ph1_sld8_pinctrl_driver = {
783 .probe = ph1_sld8_pinctrl_probe,
784 .remove = uniphier_pinctrl_remove,
785 .driver = {
786 .name = DRIVER_NAME,
787 .of_match_table = ph1_sld8_pinctrl_match,
788 },
789};
790module_platform_driver(ph1_sld8_pinctrl_driver);
791
792MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
793MODULE_DESCRIPTION("UniPhier PH1-sLD8 pinctrl driver");
794MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/uniphier/pinctrl-proxstream2.c b/drivers/pinctrl/uniphier/pinctrl-proxstream2.c
new file mode 100644
index 000000000000..3f036e236ad9
--- /dev/null
+++ b/drivers/pinctrl/uniphier/pinctrl-proxstream2.c
@@ -0,0 +1,1269 @@
1/*
2 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/pinctrl/pinctrl.h>
18#include <linux/platform_device.h>
19
20#include "pinctrl-uniphier.h"
21
22#define DRIVER_NAME "proxstream2-pinctrl"
23
24static const struct pinctrl_pin_desc proxstream2_pins[] = {
25 UNIPHIER_PINCTRL_PIN(0, "ED0", UNIPHIER_PIN_IECTRL_NONE,
26 0, UNIPHIER_PIN_DRV_4_8,
27 0, UNIPHIER_PIN_PULL_DOWN),
28 UNIPHIER_PINCTRL_PIN(1, "ED1", UNIPHIER_PIN_IECTRL_NONE,
29 1, UNIPHIER_PIN_DRV_4_8,
30 1, UNIPHIER_PIN_PULL_DOWN),
31 UNIPHIER_PINCTRL_PIN(2, "ED2", UNIPHIER_PIN_IECTRL_NONE,
32 2, UNIPHIER_PIN_DRV_4_8,
33 2, UNIPHIER_PIN_PULL_DOWN),
34 UNIPHIER_PINCTRL_PIN(3, "ED3", UNIPHIER_PIN_IECTRL_NONE,
35 3, UNIPHIER_PIN_DRV_4_8,
36 3, UNIPHIER_PIN_PULL_DOWN),
37 UNIPHIER_PINCTRL_PIN(4, "ED4", UNIPHIER_PIN_IECTRL_NONE,
38 4, UNIPHIER_PIN_DRV_4_8,
39 4, UNIPHIER_PIN_PULL_DOWN),
40 UNIPHIER_PINCTRL_PIN(5, "ED5", UNIPHIER_PIN_IECTRL_NONE,
41 5, UNIPHIER_PIN_DRV_4_8,
42 5, UNIPHIER_PIN_PULL_DOWN),
43 UNIPHIER_PINCTRL_PIN(6, "ED6", UNIPHIER_PIN_IECTRL_NONE,
44 6, UNIPHIER_PIN_DRV_4_8,
45 6, UNIPHIER_PIN_PULL_DOWN),
46 UNIPHIER_PINCTRL_PIN(7, "ED7", UNIPHIER_PIN_IECTRL_NONE,
47 7, UNIPHIER_PIN_DRV_4_8,
48 7, UNIPHIER_PIN_PULL_DOWN),
49 UNIPHIER_PINCTRL_PIN(8, "XERWE0", UNIPHIER_PIN_IECTRL_NONE,
50 8, UNIPHIER_PIN_DRV_4_8,
51 8, UNIPHIER_PIN_PULL_DOWN),
52 UNIPHIER_PINCTRL_PIN(9, "XERWE1", UNIPHIER_PIN_IECTRL_NONE,
53 9, UNIPHIER_PIN_DRV_4_8,
54 9, UNIPHIER_PIN_PULL_DOWN),
55 UNIPHIER_PINCTRL_PIN(10, "ERXW", UNIPHIER_PIN_IECTRL_NONE,
56 10, UNIPHIER_PIN_DRV_4_8,
57 10, UNIPHIER_PIN_PULL_DOWN),
58 UNIPHIER_PINCTRL_PIN(11, "ES0", UNIPHIER_PIN_IECTRL_NONE,
59 11, UNIPHIER_PIN_DRV_4_8,
60 11, UNIPHIER_PIN_PULL_DOWN),
61 UNIPHIER_PINCTRL_PIN(12, "ES1", UNIPHIER_PIN_IECTRL_NONE,
62 12, UNIPHIER_PIN_DRV_4_8,
63 12, UNIPHIER_PIN_PULL_DOWN),
64 UNIPHIER_PINCTRL_PIN(13, "ES2", UNIPHIER_PIN_IECTRL_NONE,
65 13, UNIPHIER_PIN_DRV_4_8,
66 13, UNIPHIER_PIN_PULL_DOWN),
67 UNIPHIER_PINCTRL_PIN(14, "XECS1", UNIPHIER_PIN_IECTRL_NONE,
68 14, UNIPHIER_PIN_DRV_4_8,
69 14, UNIPHIER_PIN_PULL_DOWN),
70 UNIPHIER_PINCTRL_PIN(15, "SMTRST0", UNIPHIER_PIN_IECTRL_NONE,
71 -1, UNIPHIER_PIN_DRV_FIXED_8,
72 15, UNIPHIER_PIN_PULL_DOWN),
73 UNIPHIER_PINCTRL_PIN(16, "SMTCMD0", UNIPHIER_PIN_IECTRL_NONE,
74 -1, UNIPHIER_PIN_DRV_FIXED_8,
75 16, UNIPHIER_PIN_PULL_DOWN),
76 UNIPHIER_PINCTRL_PIN(17, "SMTD0", UNIPHIER_PIN_IECTRL_NONE,
77 -1, UNIPHIER_PIN_DRV_FIXED_8,
78 17, UNIPHIER_PIN_PULL_DOWN),
79 UNIPHIER_PINCTRL_PIN(18, "SMTSEL0", UNIPHIER_PIN_IECTRL_NONE,
80 -1, UNIPHIER_PIN_DRV_FIXED_8,
81 18, UNIPHIER_PIN_PULL_DOWN),
82 UNIPHIER_PINCTRL_PIN(19, "SMTCLK0CG", UNIPHIER_PIN_IECTRL_NONE,
83 -1, UNIPHIER_PIN_DRV_FIXED_8,
84 19, UNIPHIER_PIN_PULL_DOWN),
85 UNIPHIER_PINCTRL_PIN(20, "SMTDET0", UNIPHIER_PIN_IECTRL_NONE,
86 -1, UNIPHIER_PIN_DRV_FIXED_8,
87 20, UNIPHIER_PIN_PULL_DOWN),
88 UNIPHIER_PINCTRL_PIN(21, "SMTRST1", UNIPHIER_PIN_IECTRL_NONE,
89 -1, UNIPHIER_PIN_DRV_FIXED_8,
90 21, UNIPHIER_PIN_PULL_DOWN),
91 UNIPHIER_PINCTRL_PIN(22, "SMTCMD1", UNIPHIER_PIN_IECTRL_NONE,
92 -1, UNIPHIER_PIN_DRV_FIXED_8,
93 22, UNIPHIER_PIN_PULL_DOWN),
94 UNIPHIER_PINCTRL_PIN(23, "SMTD1", UNIPHIER_PIN_IECTRL_NONE,
95 -1, UNIPHIER_PIN_DRV_FIXED_8,
96 23, UNIPHIER_PIN_PULL_DOWN),
97 UNIPHIER_PINCTRL_PIN(24, "SMTSEL1", UNIPHIER_PIN_IECTRL_NONE,
98 -1, UNIPHIER_PIN_DRV_FIXED_8,
99 24, UNIPHIER_PIN_PULL_DOWN),
100 UNIPHIER_PINCTRL_PIN(25, "SMTCLK1CG", UNIPHIER_PIN_IECTRL_NONE,
101 -1, UNIPHIER_PIN_DRV_FIXED_8,
102 25, UNIPHIER_PIN_PULL_DOWN),
103 UNIPHIER_PINCTRL_PIN(26, "SMTDET1", UNIPHIER_PIN_IECTRL_NONE,
104 -1, UNIPHIER_PIN_DRV_FIXED_8,
105 26, UNIPHIER_PIN_PULL_DOWN),
106 UNIPHIER_PINCTRL_PIN(27, "XIRQ18", UNIPHIER_PIN_IECTRL_NONE,
107 -1, UNIPHIER_PIN_DRV_FIXED_8,
108 27, UNIPHIER_PIN_PULL_DOWN),
109 UNIPHIER_PINCTRL_PIN(28, "XIRQ19", UNIPHIER_PIN_IECTRL_NONE,
110 -1, UNIPHIER_PIN_DRV_FIXED_8,
111 28, UNIPHIER_PIN_PULL_DOWN),
112 UNIPHIER_PINCTRL_PIN(29, "XIRQ20", UNIPHIER_PIN_IECTRL_NONE,
113 -1, UNIPHIER_PIN_DRV_FIXED_8,
114 29, UNIPHIER_PIN_PULL_DOWN),
115 UNIPHIER_PINCTRL_PIN(30, "XNFRE", UNIPHIER_PIN_IECTRL_NONE,
116 30, UNIPHIER_PIN_DRV_4_8,
117 30, UNIPHIER_PIN_PULL_UP),
118 UNIPHIER_PINCTRL_PIN(31, "XNFWE", UNIPHIER_PIN_IECTRL_NONE,
119 31, UNIPHIER_PIN_DRV_4_8,
120 31, UNIPHIER_PIN_PULL_UP),
121 UNIPHIER_PINCTRL_PIN(32, "NFALE", UNIPHIER_PIN_IECTRL_NONE,
122 32, UNIPHIER_PIN_DRV_4_8,
123 32, UNIPHIER_PIN_PULL_DOWN),
124 UNIPHIER_PINCTRL_PIN(33, "NFCLE", UNIPHIER_PIN_IECTRL_NONE,
125 33, UNIPHIER_PIN_DRV_4_8,
126 33, UNIPHIER_PIN_PULL_DOWN),
127 UNIPHIER_PINCTRL_PIN(34, "XNFWP", UNIPHIER_PIN_IECTRL_NONE,
128 34, UNIPHIER_PIN_DRV_4_8,
129 34, UNIPHIER_PIN_PULL_DOWN),
130 UNIPHIER_PINCTRL_PIN(35, "XNFCE0", UNIPHIER_PIN_IECTRL_NONE,
131 35, UNIPHIER_PIN_DRV_4_8,
132 35, UNIPHIER_PIN_PULL_UP),
133 UNIPHIER_PINCTRL_PIN(36, "NFRYBY0", UNIPHIER_PIN_IECTRL_NONE,
134 36, UNIPHIER_PIN_DRV_4_8,
135 36, UNIPHIER_PIN_PULL_UP),
136 UNIPHIER_PINCTRL_PIN(37, "XNFCE1", UNIPHIER_PIN_IECTRL_NONE,
137 37, UNIPHIER_PIN_DRV_4_8,
138 37, UNIPHIER_PIN_PULL_UP),
139 UNIPHIER_PINCTRL_PIN(38, "NFRYBY1", UNIPHIER_PIN_IECTRL_NONE,
140 38, UNIPHIER_PIN_DRV_4_8,
141 38, UNIPHIER_PIN_PULL_UP),
142 UNIPHIER_PINCTRL_PIN(39, "NFD0", UNIPHIER_PIN_IECTRL_NONE,
143 39, UNIPHIER_PIN_DRV_4_8,
144 39, UNIPHIER_PIN_PULL_DOWN),
145 UNIPHIER_PINCTRL_PIN(40, "NFD1", UNIPHIER_PIN_IECTRL_NONE,
146 40, UNIPHIER_PIN_DRV_4_8,
147 40, UNIPHIER_PIN_PULL_DOWN),
148 UNIPHIER_PINCTRL_PIN(41, "NFD2", UNIPHIER_PIN_IECTRL_NONE,
149 41, UNIPHIER_PIN_DRV_4_8,
150 41, UNIPHIER_PIN_PULL_DOWN),
151 UNIPHIER_PINCTRL_PIN(42, "NFD3", UNIPHIER_PIN_IECTRL_NONE,
152 42, UNIPHIER_PIN_DRV_4_8,
153 42, UNIPHIER_PIN_PULL_DOWN),
154 UNIPHIER_PINCTRL_PIN(43, "NFD4", UNIPHIER_PIN_IECTRL_NONE,
155 43, UNIPHIER_PIN_DRV_4_8,
156 43, UNIPHIER_PIN_PULL_DOWN),
157 UNIPHIER_PINCTRL_PIN(44, "NFD5", UNIPHIER_PIN_IECTRL_NONE,
158 44, UNIPHIER_PIN_DRV_4_8,
159 44, UNIPHIER_PIN_PULL_DOWN),
160 UNIPHIER_PINCTRL_PIN(45, "NFD6", UNIPHIER_PIN_IECTRL_NONE,
161 45, UNIPHIER_PIN_DRV_4_8,
162 45, UNIPHIER_PIN_PULL_DOWN),
163 UNIPHIER_PINCTRL_PIN(46, "NFD7", UNIPHIER_PIN_IECTRL_NONE,
164 46, UNIPHIER_PIN_DRV_4_8,
165 46, UNIPHIER_PIN_PULL_DOWN),
166 UNIPHIER_PINCTRL_PIN(47, "SDCLK", UNIPHIER_PIN_IECTRL_NONE,
167 0, UNIPHIER_PIN_DRV_8_12_16_20,
168 -1, UNIPHIER_PIN_PULL_UP_FIXED),
169 UNIPHIER_PINCTRL_PIN(48, "SDCMD", UNIPHIER_PIN_IECTRL_NONE,
170 4, UNIPHIER_PIN_DRV_8_12_16_20,
171 -1, UNIPHIER_PIN_PULL_UP_FIXED),
172 UNIPHIER_PINCTRL_PIN(49, "SDDAT0", UNIPHIER_PIN_IECTRL_NONE,
173 8, UNIPHIER_PIN_DRV_8_12_16_20,
174 -1, UNIPHIER_PIN_PULL_UP_FIXED),
175 UNIPHIER_PINCTRL_PIN(50, "SDDAT1", UNIPHIER_PIN_IECTRL_NONE,
176 12, UNIPHIER_PIN_DRV_8_12_16_20,
177 -1, UNIPHIER_PIN_PULL_UP_FIXED),
178 UNIPHIER_PINCTRL_PIN(51, "SDDAT2", UNIPHIER_PIN_IECTRL_NONE,
179 16, UNIPHIER_PIN_DRV_8_12_16_20,
180 -1, UNIPHIER_PIN_PULL_UP_FIXED),
181 UNIPHIER_PINCTRL_PIN(52, "SDDAT3", UNIPHIER_PIN_IECTRL_NONE,
182 20, UNIPHIER_PIN_DRV_8_12_16_20,
183 -1, UNIPHIER_PIN_PULL_UP_FIXED),
184 UNIPHIER_PINCTRL_PIN(53, "SDCD", UNIPHIER_PIN_IECTRL_NONE,
185 -1, UNIPHIER_PIN_DRV_FIXED_8,
186 53, UNIPHIER_PIN_PULL_DOWN),
187 UNIPHIER_PINCTRL_PIN(54, "SDWP", UNIPHIER_PIN_IECTRL_NONE,
188 -1, UNIPHIER_PIN_DRV_FIXED_8,
189 54, UNIPHIER_PIN_PULL_DOWN),
190 UNIPHIER_PINCTRL_PIN(55, "SDVOLC", UNIPHIER_PIN_IECTRL_NONE,
191 -1, UNIPHIER_PIN_DRV_FIXED_8,
192 55, UNIPHIER_PIN_PULL_DOWN),
193 UNIPHIER_PINCTRL_PIN(56, "USB0VBUS", UNIPHIER_PIN_IECTRL_NONE,
194 -1, UNIPHIER_PIN_DRV_FIXED_8,
195 56, UNIPHIER_PIN_PULL_DOWN),
196 UNIPHIER_PINCTRL_PIN(57, "USB0OD", UNIPHIER_PIN_IECTRL_NONE,
197 -1, UNIPHIER_PIN_DRV_FIXED_8,
198 57, UNIPHIER_PIN_PULL_DOWN),
199 UNIPHIER_PINCTRL_PIN(58, "USB1VBUS", UNIPHIER_PIN_IECTRL_NONE,
200 -1, UNIPHIER_PIN_DRV_FIXED_8,
201 58, UNIPHIER_PIN_PULL_DOWN),
202 UNIPHIER_PINCTRL_PIN(59, "USB1OD", UNIPHIER_PIN_IECTRL_NONE,
203 -1, UNIPHIER_PIN_DRV_FIXED_8,
204 59, UNIPHIER_PIN_PULL_DOWN),
205 UNIPHIER_PINCTRL_PIN(60, "USB2VBUS", UNIPHIER_PIN_IECTRL_NONE,
206 -1, UNIPHIER_PIN_DRV_FIXED_8,
207 60, UNIPHIER_PIN_PULL_DOWN),
208 UNIPHIER_PINCTRL_PIN(61, "USB2OD", UNIPHIER_PIN_IECTRL_NONE,
209 -1, UNIPHIER_PIN_DRV_FIXED_8,
210 61, UNIPHIER_PIN_PULL_DOWN),
211 UNIPHIER_PINCTRL_PIN(62, "USB3VBUS", UNIPHIER_PIN_IECTRL_NONE,
212 -1, UNIPHIER_PIN_DRV_FIXED_8,
213 62, UNIPHIER_PIN_PULL_DOWN),
214 UNIPHIER_PINCTRL_PIN(63, "USB3OD", UNIPHIER_PIN_IECTRL_NONE,
215 -1, UNIPHIER_PIN_DRV_FIXED_8,
216 63, UNIPHIER_PIN_PULL_DOWN),
217 UNIPHIER_PINCTRL_PIN(64, "CH0CLK", UNIPHIER_PIN_IECTRL_NONE,
218 -1, UNIPHIER_PIN_DRV_FIXED_8,
219 64, UNIPHIER_PIN_PULL_DOWN),
220 UNIPHIER_PINCTRL_PIN(65, "CH0PSYNC", UNIPHIER_PIN_IECTRL_NONE,
221 -1, UNIPHIER_PIN_DRV_FIXED_8,
222 65, UNIPHIER_PIN_PULL_DOWN),
223 UNIPHIER_PINCTRL_PIN(66, "CH0VAL", UNIPHIER_PIN_IECTRL_NONE,
224 -1, UNIPHIER_PIN_DRV_FIXED_8,
225 66, UNIPHIER_PIN_PULL_DOWN),
226 UNIPHIER_PINCTRL_PIN(67, "CH0DATA", UNIPHIER_PIN_IECTRL_NONE,
227 -1, UNIPHIER_PIN_DRV_FIXED_8,
228 67, UNIPHIER_PIN_PULL_DOWN),
229 UNIPHIER_PINCTRL_PIN(68, "CH1CLK", UNIPHIER_PIN_IECTRL_NONE,
230 -1, UNIPHIER_PIN_DRV_FIXED_8,
231 68, UNIPHIER_PIN_PULL_DOWN),
232 UNIPHIER_PINCTRL_PIN(69, "CH1PSYNC", UNIPHIER_PIN_IECTRL_NONE,
233 -1, UNIPHIER_PIN_DRV_FIXED_8,
234 69, UNIPHIER_PIN_PULL_DOWN),
235 UNIPHIER_PINCTRL_PIN(70, "CH1VAL", UNIPHIER_PIN_IECTRL_NONE,
236 -1, UNIPHIER_PIN_DRV_FIXED_8,
237 70, UNIPHIER_PIN_PULL_DOWN),
238 UNIPHIER_PINCTRL_PIN(71, "CH1DATA", UNIPHIER_PIN_IECTRL_NONE,
239 -1, UNIPHIER_PIN_DRV_FIXED_8,
240 71, UNIPHIER_PIN_PULL_DOWN),
241 UNIPHIER_PINCTRL_PIN(72, "XIRQ9", UNIPHIER_PIN_IECTRL_NONE,
242 -1, UNIPHIER_PIN_DRV_FIXED_8,
243 72, UNIPHIER_PIN_PULL_DOWN),
244 UNIPHIER_PINCTRL_PIN(73, "XIRQ10", UNIPHIER_PIN_IECTRL_NONE,
245 -1, UNIPHIER_PIN_DRV_FIXED_8,
246 73, UNIPHIER_PIN_PULL_DOWN),
247 UNIPHIER_PINCTRL_PIN(74, "XIRQ16", UNIPHIER_PIN_IECTRL_NONE,
248 -1, UNIPHIER_PIN_DRV_FIXED_8,
249 74, UNIPHIER_PIN_PULL_DOWN),
250 UNIPHIER_PINCTRL_PIN(75, "CH4CLK", UNIPHIER_PIN_IECTRL_NONE,
251 -1, UNIPHIER_PIN_DRV_FIXED_8,
252 75, UNIPHIER_PIN_PULL_DOWN),
253 UNIPHIER_PINCTRL_PIN(76, "CH4PSYNC", UNIPHIER_PIN_IECTRL_NONE,
254 -1, UNIPHIER_PIN_DRV_FIXED_8,
255 76, UNIPHIER_PIN_PULL_DOWN),
256 UNIPHIER_PINCTRL_PIN(77, "CH4VAL", UNIPHIER_PIN_IECTRL_NONE,
257 -1, UNIPHIER_PIN_DRV_FIXED_8,
258 77, UNIPHIER_PIN_PULL_DOWN),
259 UNIPHIER_PINCTRL_PIN(78, "CH4DATA", UNIPHIER_PIN_IECTRL_NONE,
260 -1, UNIPHIER_PIN_DRV_FIXED_8,
261 78, UNIPHIER_PIN_PULL_DOWN),
262 UNIPHIER_PINCTRL_PIN(79, "CH5CLK", UNIPHIER_PIN_IECTRL_NONE,
263 -1, UNIPHIER_PIN_DRV_FIXED_8,
264 79, UNIPHIER_PIN_PULL_DOWN),
265 UNIPHIER_PINCTRL_PIN(80, "CH5PSYNC", UNIPHIER_PIN_IECTRL_NONE,
266 -1, UNIPHIER_PIN_DRV_FIXED_8,
267 80, UNIPHIER_PIN_PULL_DOWN),
268 UNIPHIER_PINCTRL_PIN(81, "CH5VAL", UNIPHIER_PIN_IECTRL_NONE,
269 -1, UNIPHIER_PIN_DRV_FIXED_8,
270 81, UNIPHIER_PIN_PULL_DOWN),
271 UNIPHIER_PINCTRL_PIN(82, "CH5DATA", UNIPHIER_PIN_IECTRL_NONE,
272 -1, UNIPHIER_PIN_DRV_FIXED_8,
273 82, UNIPHIER_PIN_PULL_DOWN),
274 UNIPHIER_PINCTRL_PIN(83, "CH6CLK", UNIPHIER_PIN_IECTRL_NONE,
275 -1, UNIPHIER_PIN_DRV_FIXED_8,
276 83, UNIPHIER_PIN_PULL_DOWN),
277 UNIPHIER_PINCTRL_PIN(84, "CH6PSYNC", UNIPHIER_PIN_IECTRL_NONE,
278 -1, UNIPHIER_PIN_DRV_FIXED_8,
279 84, UNIPHIER_PIN_PULL_DOWN),
280 UNIPHIER_PINCTRL_PIN(85, "CH6VAL", UNIPHIER_PIN_IECTRL_NONE,
281 -1, UNIPHIER_PIN_DRV_FIXED_8,
282 85, UNIPHIER_PIN_PULL_DOWN),
283 UNIPHIER_PINCTRL_PIN(86, "CH6DATA", UNIPHIER_PIN_IECTRL_NONE,
284 -1, UNIPHIER_PIN_DRV_FIXED_8,
285 86, UNIPHIER_PIN_PULL_DOWN),
286 UNIPHIER_PINCTRL_PIN(87, "STS0CLKO", UNIPHIER_PIN_IECTRL_NONE,
287 -1, UNIPHIER_PIN_DRV_FIXED_8,
288 87, UNIPHIER_PIN_PULL_DOWN),
289 UNIPHIER_PINCTRL_PIN(88, "STS0SYNCO", UNIPHIER_PIN_IECTRL_NONE,
290 -1, UNIPHIER_PIN_DRV_FIXED_8,
291 88, UNIPHIER_PIN_PULL_DOWN),
292 UNIPHIER_PINCTRL_PIN(89, "STS0VALO", UNIPHIER_PIN_IECTRL_NONE,
293 -1, UNIPHIER_PIN_DRV_FIXED_8,
294 89, UNIPHIER_PIN_PULL_DOWN),
295 UNIPHIER_PINCTRL_PIN(90, "STS0DATAO", UNIPHIER_PIN_IECTRL_NONE,
296 -1, UNIPHIER_PIN_DRV_FIXED_8,
297 90, UNIPHIER_PIN_PULL_DOWN),
298 UNIPHIER_PINCTRL_PIN(91, "XIRQ17", UNIPHIER_PIN_IECTRL_NONE,
299 -1, UNIPHIER_PIN_DRV_FIXED_8,
300 91, UNIPHIER_PIN_PULL_DOWN),
301 UNIPHIER_PINCTRL_PIN(92, "PORT163", UNIPHIER_PIN_IECTRL_NONE,
302 -1, UNIPHIER_PIN_DRV_FIXED_8,
303 92, UNIPHIER_PIN_PULL_DOWN),
304 UNIPHIER_PINCTRL_PIN(93, "PORT165", UNIPHIER_PIN_IECTRL_NONE,
305 -1, UNIPHIER_PIN_DRV_FIXED_8,
306 93, UNIPHIER_PIN_PULL_DOWN),
307 UNIPHIER_PINCTRL_PIN(94, "PORT166", UNIPHIER_PIN_IECTRL_NONE,
308 -1, UNIPHIER_PIN_DRV_FIXED_8,
309 94, UNIPHIER_PIN_PULL_DOWN),
310 UNIPHIER_PINCTRL_PIN(95, "PORT132", UNIPHIER_PIN_IECTRL_NONE,
311 -1, UNIPHIER_PIN_DRV_FIXED_8,
312 95, UNIPHIER_PIN_PULL_DOWN),
313 UNIPHIER_PINCTRL_PIN(96, "PORT133", UNIPHIER_PIN_IECTRL_NONE,
314 -1, UNIPHIER_PIN_DRV_FIXED_8,
315 96, UNIPHIER_PIN_PULL_DOWN),
316 UNIPHIER_PINCTRL_PIN(97, "AO2IEC", UNIPHIER_PIN_IECTRL_NONE,
317 -1, UNIPHIER_PIN_DRV_FIXED_8,
318 97, UNIPHIER_PIN_PULL_DOWN),
319 UNIPHIER_PINCTRL_PIN(98, "AI2ADCCK", UNIPHIER_PIN_IECTRL_NONE,
320 -1, UNIPHIER_PIN_DRV_FIXED_8,
321 98, UNIPHIER_PIN_PULL_DOWN),
322 UNIPHIER_PINCTRL_PIN(99, "AI2BCK", UNIPHIER_PIN_IECTRL_NONE,
323 -1, UNIPHIER_PIN_DRV_FIXED_8,
324 99, UNIPHIER_PIN_PULL_DOWN),
325 UNIPHIER_PINCTRL_PIN(100, "AI2LRCK", UNIPHIER_PIN_IECTRL_NONE,
326 -1, UNIPHIER_PIN_DRV_FIXED_8,
327 100, UNIPHIER_PIN_PULL_DOWN),
328 UNIPHIER_PINCTRL_PIN(101, "AI2D0", UNIPHIER_PIN_IECTRL_NONE,
329 -1, UNIPHIER_PIN_DRV_FIXED_8,
330 101, UNIPHIER_PIN_PULL_DOWN),
331 UNIPHIER_PINCTRL_PIN(102, "AI2D1", UNIPHIER_PIN_IECTRL_NONE,
332 -1, UNIPHIER_PIN_DRV_FIXED_8,
333 102, UNIPHIER_PIN_PULL_DOWN),
334 UNIPHIER_PINCTRL_PIN(103, "AI2D2", UNIPHIER_PIN_IECTRL_NONE,
335 -1, UNIPHIER_PIN_DRV_FIXED_8,
336 103, UNIPHIER_PIN_PULL_DOWN),
337 UNIPHIER_PINCTRL_PIN(104, "AI2D3", UNIPHIER_PIN_IECTRL_NONE,
338 -1, UNIPHIER_PIN_DRV_FIXED_8,
339 104, UNIPHIER_PIN_PULL_DOWN),
340 UNIPHIER_PINCTRL_PIN(105, "AO3DACCK", UNIPHIER_PIN_IECTRL_NONE,
341 -1, UNIPHIER_PIN_DRV_FIXED_8,
342 105, UNIPHIER_PIN_PULL_DOWN),
343 UNIPHIER_PINCTRL_PIN(106, "AO3BCK", UNIPHIER_PIN_IECTRL_NONE,
344 -1, UNIPHIER_PIN_DRV_FIXED_8,
345 106, UNIPHIER_PIN_PULL_DOWN),
346 UNIPHIER_PINCTRL_PIN(107, "AO3LRCK", UNIPHIER_PIN_IECTRL_NONE,
347 -1, UNIPHIER_PIN_DRV_FIXED_8,
348 107, UNIPHIER_PIN_PULL_DOWN),
349 UNIPHIER_PINCTRL_PIN(108, "AO3DMIX", UNIPHIER_PIN_IECTRL_NONE,
350 -1, UNIPHIER_PIN_DRV_FIXED_8,
351 108, UNIPHIER_PIN_PULL_DOWN),
352 UNIPHIER_PINCTRL_PIN(109, "SDA0", UNIPHIER_PIN_IECTRL_NONE,
353 -1, UNIPHIER_PIN_DRV_FIXED_8,
354 109, UNIPHIER_PIN_PULL_DOWN),
355 UNIPHIER_PINCTRL_PIN(110, "SCL0", UNIPHIER_PIN_IECTRL_NONE,
356 -1, UNIPHIER_PIN_DRV_FIXED_8,
357 110, UNIPHIER_PIN_PULL_DOWN),
358 UNIPHIER_PINCTRL_PIN(111, "SDA1", UNIPHIER_PIN_IECTRL_NONE,
359 -1, UNIPHIER_PIN_DRV_FIXED_8,
360 111, UNIPHIER_PIN_PULL_DOWN),
361 UNIPHIER_PINCTRL_PIN(112, "SCL1", UNIPHIER_PIN_IECTRL_NONE,
362 -1, UNIPHIER_PIN_DRV_FIXED_8,
363 112, UNIPHIER_PIN_PULL_DOWN),
364 UNIPHIER_PINCTRL_PIN(113, "TXD2", 0,
365 113, UNIPHIER_PIN_DRV_4_8,
366 113, UNIPHIER_PIN_PULL_UP),
367 UNIPHIER_PINCTRL_PIN(114, "RXD2", 0,
368 114, UNIPHIER_PIN_DRV_4_8,
369 114, UNIPHIER_PIN_PULL_UP),
370 UNIPHIER_PINCTRL_PIN(115, "TXD1", 0,
371 115, UNIPHIER_PIN_DRV_4_8,
372 115, UNIPHIER_PIN_PULL_UP),
373 UNIPHIER_PINCTRL_PIN(116, "RXD1", 0,
374 116, UNIPHIER_PIN_DRV_4_8,
375 116, UNIPHIER_PIN_PULL_UP),
376 UNIPHIER_PINCTRL_PIN(117, "PORT190", UNIPHIER_PIN_IECTRL_NONE,
377 -1, UNIPHIER_PIN_DRV_FIXED_8,
378 117, UNIPHIER_PIN_PULL_DOWN),
379 UNIPHIER_PINCTRL_PIN(118, "VI1HSYNC", UNIPHIER_PIN_IECTRL_NONE,
380 -1, UNIPHIER_PIN_DRV_FIXED_8,
381 118, UNIPHIER_PIN_PULL_DOWN),
382 UNIPHIER_PINCTRL_PIN(119, "VI1VSYNC", UNIPHIER_PIN_IECTRL_NONE,
383 -1, UNIPHIER_PIN_DRV_FIXED_8,
384 119, UNIPHIER_PIN_PULL_DOWN),
385 UNIPHIER_PINCTRL_PIN(120, "VI1DE", UNIPHIER_PIN_IECTRL_NONE,
386 -1, UNIPHIER_PIN_DRV_FIXED_8,
387 120, UNIPHIER_PIN_PULL_DOWN),
388 UNIPHIER_PINCTRL_PIN(121, "XIRQ3", UNIPHIER_PIN_IECTRL_NONE,
389 -1, UNIPHIER_PIN_DRV_FIXED_8,
390 121, UNIPHIER_PIN_PULL_DOWN),
391 UNIPHIER_PINCTRL_PIN(122, "XIRQ4", UNIPHIER_PIN_IECTRL_NONE,
392 -1, UNIPHIER_PIN_DRV_FIXED_8,
393 122, UNIPHIER_PIN_PULL_DOWN),
394 UNIPHIER_PINCTRL_PIN(123, "VI1G2", UNIPHIER_PIN_IECTRL_NONE,
395 -1, UNIPHIER_PIN_DRV_FIXED_8,
396 123, UNIPHIER_PIN_PULL_DOWN),
397 UNIPHIER_PINCTRL_PIN(124, "VI1G3", UNIPHIER_PIN_IECTRL_NONE,
398 -1, UNIPHIER_PIN_DRV_FIXED_8,
399 124, UNIPHIER_PIN_PULL_DOWN),
400 UNIPHIER_PINCTRL_PIN(125, "VI1G4", UNIPHIER_PIN_IECTRL_NONE,
401 -1, UNIPHIER_PIN_DRV_FIXED_8,
402 125, UNIPHIER_PIN_PULL_DOWN),
403 UNIPHIER_PINCTRL_PIN(126, "VI1G5", UNIPHIER_PIN_IECTRL_NONE,
404 -1, UNIPHIER_PIN_DRV_FIXED_8,
405 126, UNIPHIER_PIN_PULL_DOWN),
406 UNIPHIER_PINCTRL_PIN(127, "VI1G6", UNIPHIER_PIN_IECTRL_NONE,
407 -1, UNIPHIER_PIN_DRV_FIXED_8,
408 127, UNIPHIER_PIN_PULL_DOWN),
409 UNIPHIER_PINCTRL_PIN(128, "VI1G7", UNIPHIER_PIN_IECTRL_NONE,
410 -1, UNIPHIER_PIN_DRV_FIXED_8,
411 128, UNIPHIER_PIN_PULL_DOWN),
412 UNIPHIER_PINCTRL_PIN(129, "VI1G8", UNIPHIER_PIN_IECTRL_NONE,
413 -1, UNIPHIER_PIN_DRV_FIXED_8,
414 129, UNIPHIER_PIN_PULL_DOWN),
415 UNIPHIER_PINCTRL_PIN(130, "VI1G9", UNIPHIER_PIN_IECTRL_NONE,
416 -1, UNIPHIER_PIN_DRV_FIXED_8,
417 130, UNIPHIER_PIN_PULL_DOWN),
418 UNIPHIER_PINCTRL_PIN(131, "VI1CLK", UNIPHIER_PIN_IECTRL_NONE,
419 -1, UNIPHIER_PIN_DRV_FIXED_8,
420 131, UNIPHIER_PIN_PULL_DOWN),
421 UNIPHIER_PINCTRL_PIN(132, "PORT05", UNIPHIER_PIN_IECTRL_NONE,
422 -1, UNIPHIER_PIN_DRV_FIXED_8,
423 132, UNIPHIER_PIN_PULL_DOWN),
424 UNIPHIER_PINCTRL_PIN(133, "PORT06", UNIPHIER_PIN_IECTRL_NONE,
425 -1, UNIPHIER_PIN_DRV_FIXED_8,
426 133, UNIPHIER_PIN_PULL_DOWN),
427 UNIPHIER_PINCTRL_PIN(134, "VI1R2", UNIPHIER_PIN_IECTRL_NONE,
428 -1, UNIPHIER_PIN_DRV_FIXED_8,
429 134, UNIPHIER_PIN_PULL_DOWN),
430 UNIPHIER_PINCTRL_PIN(135, "VI1R3", UNIPHIER_PIN_IECTRL_NONE,
431 -1, UNIPHIER_PIN_DRV_FIXED_8,
432 135, UNIPHIER_PIN_PULL_DOWN),
433 UNIPHIER_PINCTRL_PIN(136, "VI1R4", UNIPHIER_PIN_IECTRL_NONE,
434 -1, UNIPHIER_PIN_DRV_FIXED_8,
435 136, UNIPHIER_PIN_PULL_DOWN),
436 UNIPHIER_PINCTRL_PIN(137, "VI1R5", UNIPHIER_PIN_IECTRL_NONE,
437 -1, UNIPHIER_PIN_DRV_FIXED_8,
438 137, UNIPHIER_PIN_PULL_DOWN),
439 UNIPHIER_PINCTRL_PIN(138, "VI1R6", UNIPHIER_PIN_IECTRL_NONE,
440 -1, UNIPHIER_PIN_DRV_FIXED_8,
441 138, UNIPHIER_PIN_PULL_DOWN),
442 UNIPHIER_PINCTRL_PIN(139, "VI1R7", UNIPHIER_PIN_IECTRL_NONE,
443 -1, UNIPHIER_PIN_DRV_FIXED_8,
444 139, UNIPHIER_PIN_PULL_DOWN),
445 UNIPHIER_PINCTRL_PIN(140, "VI1R8", UNIPHIER_PIN_IECTRL_NONE,
446 -1, UNIPHIER_PIN_DRV_FIXED_8,
447 140, UNIPHIER_PIN_PULL_DOWN),
448 UNIPHIER_PINCTRL_PIN(141, "VI1R9", UNIPHIER_PIN_IECTRL_NONE,
449 -1, UNIPHIER_PIN_DRV_FIXED_8,
450 141, UNIPHIER_PIN_PULL_DOWN),
451 UNIPHIER_PINCTRL_PIN(142, "LPST", UNIPHIER_PIN_IECTRL_NONE,
452 142, UNIPHIER_PIN_DRV_4_8,
453 142, UNIPHIER_PIN_PULL_DOWN),
454 UNIPHIER_PINCTRL_PIN(143, "MDC", 0,
455 143, UNIPHIER_PIN_DRV_4_8,
456 143, UNIPHIER_PIN_PULL_DOWN),
457 UNIPHIER_PINCTRL_PIN(144, "MDIO", 0,
458 144, UNIPHIER_PIN_DRV_4_8,
459 144, UNIPHIER_PIN_PULL_DOWN),
460 UNIPHIER_PINCTRL_PIN(145, "MDIO_INTL", 0,
461 145, UNIPHIER_PIN_DRV_4_8,
462 145, UNIPHIER_PIN_PULL_DOWN),
463 UNIPHIER_PINCTRL_PIN(146, "PHYRSTL", 0,
464 146, UNIPHIER_PIN_DRV_4_8,
465 146, UNIPHIER_PIN_PULL_DOWN),
466 UNIPHIER_PINCTRL_PIN(147, "RGMII_RXCLK", 0,
467 147, UNIPHIER_PIN_DRV_4_8,
468 147, UNIPHIER_PIN_PULL_DOWN),
469 UNIPHIER_PINCTRL_PIN(148, "RGMII_RXD0", 0,
470 148, UNIPHIER_PIN_DRV_4_8,
471 148, UNIPHIER_PIN_PULL_DOWN),
472 UNIPHIER_PINCTRL_PIN(149, "RGMII_RXD1", 0,
473 149, UNIPHIER_PIN_DRV_4_8,
474 149, UNIPHIER_PIN_PULL_DOWN),
475 UNIPHIER_PINCTRL_PIN(150, "RGMII_RXD2", 0,
476 150, UNIPHIER_PIN_DRV_4_8,
477 150, UNIPHIER_PIN_PULL_DOWN),
478 UNIPHIER_PINCTRL_PIN(151, "RGMII_RXD3", 0,
479 151, UNIPHIER_PIN_DRV_4_8,
480 151, UNIPHIER_PIN_PULL_DOWN),
481 UNIPHIER_PINCTRL_PIN(152, "RGMII_RXCTL", 0,
482 152, UNIPHIER_PIN_DRV_4_8,
483 152, UNIPHIER_PIN_PULL_DOWN),
484 UNIPHIER_PINCTRL_PIN(153, "RGMII_TXCLK", 0,
485 153, UNIPHIER_PIN_DRV_4_8,
486 153, UNIPHIER_PIN_PULL_DOWN),
487 UNIPHIER_PINCTRL_PIN(154, "RGMII_TXD0", 0,
488 154, UNIPHIER_PIN_DRV_4_8,
489 154, UNIPHIER_PIN_PULL_DOWN),
490 UNIPHIER_PINCTRL_PIN(155, "RGMII_TXD1", 0,
491 155, UNIPHIER_PIN_DRV_4_8,
492 155, UNIPHIER_PIN_PULL_DOWN),
493 UNIPHIER_PINCTRL_PIN(156, "RGMII_TXD2", 0,
494 156, UNIPHIER_PIN_DRV_4_8,
495 156, UNIPHIER_PIN_PULL_DOWN),
496 UNIPHIER_PINCTRL_PIN(157, "RGMII_TXD3", 0,
497 157, UNIPHIER_PIN_DRV_4_8,
498 157, UNIPHIER_PIN_PULL_DOWN),
499 UNIPHIER_PINCTRL_PIN(158, "RGMII_TXCTL", 0,
500 158, UNIPHIER_PIN_DRV_4_8,
501 158, UNIPHIER_PIN_PULL_DOWN),
502 UNIPHIER_PINCTRL_PIN(159, "SDA3", UNIPHIER_PIN_IECTRL_NONE,
503 -1, UNIPHIER_PIN_DRV_FIXED_8,
504 159, UNIPHIER_PIN_PULL_DOWN),
505 UNIPHIER_PINCTRL_PIN(160, "SCL3", UNIPHIER_PIN_IECTRL_NONE,
506 -1, UNIPHIER_PIN_DRV_FIXED_8,
507 160, UNIPHIER_PIN_PULL_DOWN),
508 UNIPHIER_PINCTRL_PIN(161, "AI1ADCCK", UNIPHIER_PIN_IECTRL_NONE,
509 -1, UNIPHIER_PIN_DRV_FIXED_8,
510 161, UNIPHIER_PIN_PULL_DOWN),
511 UNIPHIER_PINCTRL_PIN(162, "AI1BCK", UNIPHIER_PIN_IECTRL_NONE,
512 -1, UNIPHIER_PIN_DRV_FIXED_8,
513 162, UNIPHIER_PIN_PULL_DOWN),
514 UNIPHIER_PINCTRL_PIN(163, "CH2CLK", UNIPHIER_PIN_IECTRL_NONE,
515 -1, UNIPHIER_PIN_DRV_FIXED_8,
516 163, UNIPHIER_PIN_PULL_DOWN),
517 UNIPHIER_PINCTRL_PIN(164, "CH2PSYNC", UNIPHIER_PIN_IECTRL_NONE,
518 -1, UNIPHIER_PIN_DRV_FIXED_8,
519 164, UNIPHIER_PIN_PULL_DOWN),
520 UNIPHIER_PINCTRL_PIN(165, "CH2VAL", UNIPHIER_PIN_IECTRL_NONE,
521 -1, UNIPHIER_PIN_DRV_FIXED_8,
522 165, UNIPHIER_PIN_PULL_DOWN),
523 UNIPHIER_PINCTRL_PIN(166, "CH2DATA", UNIPHIER_PIN_IECTRL_NONE,
524 -1, UNIPHIER_PIN_DRV_FIXED_8,
525 166, UNIPHIER_PIN_PULL_DOWN),
526 UNIPHIER_PINCTRL_PIN(167, "CH3CLK", UNIPHIER_PIN_IECTRL_NONE,
527 -1, UNIPHIER_PIN_DRV_FIXED_8,
528 167, UNIPHIER_PIN_PULL_DOWN),
529 UNIPHIER_PINCTRL_PIN(168, "CH3PSYNC", UNIPHIER_PIN_IECTRL_NONE,
530 -1, UNIPHIER_PIN_DRV_FIXED_8,
531 168, UNIPHIER_PIN_PULL_DOWN),
532 UNIPHIER_PINCTRL_PIN(169, "CH3VAL", UNIPHIER_PIN_IECTRL_NONE,
533 -1, UNIPHIER_PIN_DRV_FIXED_8,
534 169, UNIPHIER_PIN_PULL_DOWN),
535 UNIPHIER_PINCTRL_PIN(170, "CH3DATA", UNIPHIER_PIN_IECTRL_NONE,
536 -1, UNIPHIER_PIN_DRV_FIXED_8,
537 170, UNIPHIER_PIN_PULL_DOWN),
538 UNIPHIER_PINCTRL_PIN(171, "SDA2", UNIPHIER_PIN_IECTRL_NONE,
539 -1, UNIPHIER_PIN_DRV_FIXED_8,
540 171, UNIPHIER_PIN_PULL_DOWN),
541 UNIPHIER_PINCTRL_PIN(172, "SCL2", UNIPHIER_PIN_IECTRL_NONE,
542 -1, UNIPHIER_PIN_DRV_FIXED_8,
543 172, UNIPHIER_PIN_PULL_DOWN),
544 UNIPHIER_PINCTRL_PIN(173, "AI1LRCK", UNIPHIER_PIN_IECTRL_NONE,
545 -1, UNIPHIER_PIN_DRV_FIXED_8,
546 173, UNIPHIER_PIN_PULL_DOWN),
547 UNIPHIER_PINCTRL_PIN(174, "AI1D0", UNIPHIER_PIN_IECTRL_NONE,
548 -1, UNIPHIER_PIN_DRV_FIXED_8,
549 174, UNIPHIER_PIN_PULL_DOWN),
550 UNIPHIER_PINCTRL_PIN(175, "AO2LRCK", UNIPHIER_PIN_IECTRL_NONE,
551 -1, UNIPHIER_PIN_DRV_FIXED_8,
552 175, UNIPHIER_PIN_PULL_DOWN),
553 UNIPHIER_PINCTRL_PIN(176, "AO2D0", UNIPHIER_PIN_IECTRL_NONE,
554 -1, UNIPHIER_PIN_DRV_FIXED_8,
555 176, UNIPHIER_PIN_PULL_DOWN),
556 UNIPHIER_PINCTRL_PIN(177, "AO2DACCK", UNIPHIER_PIN_IECTRL_NONE,
557 -1, UNIPHIER_PIN_DRV_FIXED_8,
558 177, UNIPHIER_PIN_PULL_DOWN),
559 UNIPHIER_PINCTRL_PIN(178, "AO2BCK", UNIPHIER_PIN_IECTRL_NONE,
560 -1, UNIPHIER_PIN_DRV_FIXED_8,
561 178, UNIPHIER_PIN_PULL_DOWN),
562 UNIPHIER_PINCTRL_PIN(179, "PORT222", UNIPHIER_PIN_IECTRL_NONE,
563 -1, UNIPHIER_PIN_DRV_FIXED_8,
564 179, UNIPHIER_PIN_PULL_DOWN),
565 UNIPHIER_PINCTRL_PIN(180, "PORT223", UNIPHIER_PIN_IECTRL_NONE,
566 -1, UNIPHIER_PIN_DRV_FIXED_8,
567 180, UNIPHIER_PIN_PULL_DOWN),
568 UNIPHIER_PINCTRL_PIN(181, "PORT224", UNIPHIER_PIN_IECTRL_NONE,
569 -1, UNIPHIER_PIN_DRV_FIXED_8,
570 181, UNIPHIER_PIN_PULL_DOWN),
571 UNIPHIER_PINCTRL_PIN(182, "PORT225", UNIPHIER_PIN_IECTRL_NONE,
572 -1, UNIPHIER_PIN_DRV_FIXED_8,
573 182, UNIPHIER_PIN_PULL_DOWN),
574 UNIPHIER_PINCTRL_PIN(183, "PORT226", UNIPHIER_PIN_IECTRL_NONE,
575 -1, UNIPHIER_PIN_DRV_FIXED_8,
576 183, UNIPHIER_PIN_PULL_DOWN),
577 UNIPHIER_PINCTRL_PIN(184, "PORT227", UNIPHIER_PIN_IECTRL_NONE,
578 -1, UNIPHIER_PIN_DRV_FIXED_8,
579 184, UNIPHIER_PIN_PULL_DOWN),
580 UNIPHIER_PINCTRL_PIN(185, "PORT230", UNIPHIER_PIN_IECTRL_NONE,
581 -1, UNIPHIER_PIN_DRV_FIXED_8,
582 185, UNIPHIER_PIN_PULL_DOWN),
583 UNIPHIER_PINCTRL_PIN(186, "FANPWM", UNIPHIER_PIN_IECTRL_NONE,
584 -1, UNIPHIER_PIN_DRV_FIXED_8,
585 186, UNIPHIER_PIN_PULL_DOWN),
586 UNIPHIER_PINCTRL_PIN(187, "HRDDCSDA0", 0,
587 187, UNIPHIER_PIN_DRV_4_8,
588 187, UNIPHIER_PIN_PULL_DOWN),
589 UNIPHIER_PINCTRL_PIN(188, "HRDDCSCL0", 0,
590 188, UNIPHIER_PIN_DRV_4_8,
591 188, UNIPHIER_PIN_PULL_DOWN),
592 UNIPHIER_PINCTRL_PIN(189, "HRDDCSDA1", 0,
593 189, UNIPHIER_PIN_DRV_4_8,
594 189, UNIPHIER_PIN_PULL_DOWN),
595 UNIPHIER_PINCTRL_PIN(190, "HRDDCSCL1", 0,
596 190, UNIPHIER_PIN_DRV_4_8,
597 190, UNIPHIER_PIN_PULL_DOWN),
598 UNIPHIER_PINCTRL_PIN(191, "HTDDCSDA0", 0,
599 191, UNIPHIER_PIN_DRV_4_8,
600 191, UNIPHIER_PIN_PULL_DOWN),
601 UNIPHIER_PINCTRL_PIN(192, "HTDDCSCL0", 0,
602 192, UNIPHIER_PIN_DRV_4_8,
603 192, UNIPHIER_PIN_PULL_DOWN),
604 UNIPHIER_PINCTRL_PIN(193, "HTDDCSDA1", 0,
605 193, UNIPHIER_PIN_DRV_4_8,
606 193, UNIPHIER_PIN_PULL_DOWN),
607 UNIPHIER_PINCTRL_PIN(194, "HTDDCSCL1", 0,
608 194, UNIPHIER_PIN_DRV_4_8,
609 194, UNIPHIER_PIN_PULL_DOWN),
610 UNIPHIER_PINCTRL_PIN(195, "PORT241", 0,
611 195, UNIPHIER_PIN_DRV_4_8,
612 195, UNIPHIER_PIN_PULL_DOWN),
613 UNIPHIER_PINCTRL_PIN(196, "PORT242", 0,
614 196, UNIPHIER_PIN_DRV_4_8,
615 196, UNIPHIER_PIN_PULL_DOWN),
616 UNIPHIER_PINCTRL_PIN(197, "PORT243", 0,
617 197, UNIPHIER_PIN_DRV_4_8,
618 197, UNIPHIER_PIN_PULL_DOWN),
619 UNIPHIER_PINCTRL_PIN(198, "MVSYNC", 0,
620 198, UNIPHIER_PIN_DRV_4_8,
621 198, UNIPHIER_PIN_PULL_DOWN),
622 UNIPHIER_PINCTRL_PIN(199, "SPISYNC0", UNIPHIER_PIN_IECTRL_NONE,
623 199, UNIPHIER_PIN_DRV_4_8,
624 199, UNIPHIER_PIN_PULL_DOWN),
625 UNIPHIER_PINCTRL_PIN(200, "SPISCLK0", UNIPHIER_PIN_IECTRL_NONE,
626 200, UNIPHIER_PIN_DRV_4_8,
627 200, UNIPHIER_PIN_PULL_DOWN),
628 UNIPHIER_PINCTRL_PIN(201, "SPITXD0", UNIPHIER_PIN_IECTRL_NONE,
629 201, UNIPHIER_PIN_DRV_4_8,
630 201, UNIPHIER_PIN_PULL_DOWN),
631 UNIPHIER_PINCTRL_PIN(202, "SPIRXD0", UNIPHIER_PIN_IECTRL_NONE,
632 202, UNIPHIER_PIN_DRV_4_8,
633 202, UNIPHIER_PIN_PULL_DOWN),
634 UNIPHIER_PINCTRL_PIN(203, "CK54EXI", UNIPHIER_PIN_IECTRL_NONE,
635 -1, UNIPHIER_PIN_DRV_FIXED_8,
636 203, UNIPHIER_PIN_PULL_DOWN),
637 UNIPHIER_PINCTRL_PIN(204, "AEXCKA1", UNIPHIER_PIN_IECTRL_NONE,
638 -1, UNIPHIER_PIN_DRV_FIXED_8,
639 204, UNIPHIER_PIN_PULL_DOWN),
640 UNIPHIER_PINCTRL_PIN(205, "AEXCKA2", UNIPHIER_PIN_IECTRL_NONE,
641 -1, UNIPHIER_PIN_DRV_FIXED_8,
642 205, UNIPHIER_PIN_PULL_DOWN),
643 UNIPHIER_PINCTRL_PIN(206, "CK27EXI", UNIPHIER_PIN_IECTRL_NONE,
644 -1, UNIPHIER_PIN_DRV_FIXED_8,
645 206, UNIPHIER_PIN_PULL_DOWN),
646 UNIPHIER_PINCTRL_PIN(207, "STCDIN", 0,
647 207, UNIPHIER_PIN_DRV_4_8,
648 207, UNIPHIER_PIN_PULL_DOWN),
649 UNIPHIER_PINCTRL_PIN(208, "PHSYNI", 0,
650 208, UNIPHIER_PIN_DRV_4_8,
651 208, UNIPHIER_PIN_PULL_DOWN),
652 UNIPHIER_PINCTRL_PIN(209, "PVSYNI", 0,
653 209, UNIPHIER_PIN_DRV_4_8,
654 209, UNIPHIER_PIN_PULL_DOWN),
655 UNIPHIER_PINCTRL_PIN(210, "MVSYN", UNIPHIER_PIN_IECTRL_NONE,
656 210, UNIPHIER_PIN_DRV_4_8,
657 210, UNIPHIER_PIN_PULL_DOWN),
658 UNIPHIER_PINCTRL_PIN(211, "STCV", UNIPHIER_PIN_IECTRL_NONE,
659 211, UNIPHIER_PIN_DRV_4_8,
660 211, UNIPHIER_PIN_PULL_DOWN),
661 UNIPHIER_PINCTRL_PIN(212, "PORT262", UNIPHIER_PIN_IECTRL_NONE,
662 212, UNIPHIER_PIN_DRV_4_8,
663 212, UNIPHIER_PIN_PULL_DOWN),
664 UNIPHIER_PINCTRL_PIN(213, "USB0VBUS_IRQ", UNIPHIER_PIN_IECTRL_NONE,
665 -1, UNIPHIER_PIN_DRV_FIXED_4,
666 213, UNIPHIER_PIN_PULL_DOWN),
667 UNIPHIER_PINCTRL_PIN(214, "USB1VBUS_IRQ", UNIPHIER_PIN_IECTRL_NONE,
668 -1, UNIPHIER_PIN_DRV_FIXED_4,
669 214, UNIPHIER_PIN_PULL_DOWN),
670 UNIPHIER_PINCTRL_PIN(215, "PORT265", UNIPHIER_PIN_IECTRL_NONE,
671 215, UNIPHIER_PIN_DRV_4_8,
672 215, UNIPHIER_PIN_PULL_DOWN),
673 UNIPHIER_PINCTRL_PIN(216, "CK25O", 0,
674 216, UNIPHIER_PIN_DRV_4_8,
675 216, UNIPHIER_PIN_PULL_DOWN),
676 UNIPHIER_PINCTRL_PIN(217, "TXD0", 0,
677 217, UNIPHIER_PIN_DRV_4_8,
678 217, UNIPHIER_PIN_PULL_DOWN),
679 UNIPHIER_PINCTRL_PIN(218, "RXD0", 0,
680 218, UNIPHIER_PIN_DRV_4_8,
681 218, UNIPHIER_PIN_PULL_DOWN),
682 UNIPHIER_PINCTRL_PIN(219, "TXD3", 0,
683 219, UNIPHIER_PIN_DRV_4_8,
684 219, UNIPHIER_PIN_PULL_DOWN),
685 UNIPHIER_PINCTRL_PIN(220, "RXD3", 0,
686 220, UNIPHIER_PIN_DRV_4_8,
687 220, UNIPHIER_PIN_PULL_DOWN),
688 UNIPHIER_PINCTRL_PIN(221, "PORT273", 0,
689 221, UNIPHIER_PIN_DRV_4_8,
690 221, UNIPHIER_PIN_PULL_DOWN),
691 UNIPHIER_PINCTRL_PIN(222, "STCDOUTC", 0,
692 222, UNIPHIER_PIN_DRV_4_8,
693 222, UNIPHIER_PIN_PULL_DOWN),
694 UNIPHIER_PINCTRL_PIN(223, "PORT274", 0,
695 223, UNIPHIER_PIN_DRV_4_8,
696 223, UNIPHIER_PIN_PULL_DOWN),
697 UNIPHIER_PINCTRL_PIN(224, "PORT275", 0,
698 224, UNIPHIER_PIN_DRV_4_8,
699 224, UNIPHIER_PIN_PULL_DOWN),
700 UNIPHIER_PINCTRL_PIN(225, "PORT276", 0,
701 225, UNIPHIER_PIN_DRV_4_8,
702 225, UNIPHIER_PIN_PULL_DOWN),
703 UNIPHIER_PINCTRL_PIN(226, "PORT277", 0,
704 226, UNIPHIER_PIN_DRV_4_8,
705 226, UNIPHIER_PIN_PULL_DOWN),
706 UNIPHIER_PINCTRL_PIN(227, "PORT280", 0,
707 227, UNIPHIER_PIN_DRV_4_8,
708 227, UNIPHIER_PIN_PULL_DOWN),
709 UNIPHIER_PINCTRL_PIN(228, "PORT281", 0,
710 228, UNIPHIER_PIN_DRV_4_8,
711 228, UNIPHIER_PIN_PULL_DOWN),
712 UNIPHIER_PINCTRL_PIN(229, "PORT282", 0,
713 229, UNIPHIER_PIN_DRV_4_8,
714 229, UNIPHIER_PIN_PULL_DOWN),
715 UNIPHIER_PINCTRL_PIN(230, "PORT283", 0,
716 230, UNIPHIER_PIN_DRV_4_8,
717 230, UNIPHIER_PIN_PULL_DOWN),
718 UNIPHIER_PINCTRL_PIN(231, "PORT284", 0,
719 231, UNIPHIER_PIN_DRV_4_8,
720 231, UNIPHIER_PIN_PULL_DOWN),
721 UNIPHIER_PINCTRL_PIN(232, "PORT285", 0,
722 232, UNIPHIER_PIN_DRV_4_8,
723 232, UNIPHIER_PIN_PULL_DOWN),
724 UNIPHIER_PINCTRL_PIN(233, "T0HPD", 0,
725 233, UNIPHIER_PIN_DRV_4_8,
726 233, UNIPHIER_PIN_PULL_DOWN),
727 UNIPHIER_PINCTRL_PIN(234, "T1HPD", 0,
728 234, UNIPHIER_PIN_DRV_4_8,
729 234, UNIPHIER_PIN_PULL_DOWN),
730};
731
732static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
733static const unsigned emmc_muxvals[] = {9, 9, 9, 9, 9, 9, 9};
734static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
735static const unsigned emmc_dat8_muxvals[] = {9, 9, 9, 9};
736static const unsigned i2c0_pins[] = {109, 110};
737static const unsigned i2c0_muxvals[] = {8, 8};
738static const unsigned i2c1_pins[] = {111, 112};
739static const unsigned i2c1_muxvals[] = {8, 8};
740static const unsigned i2c2_pins[] = {171, 172};
741static const unsigned i2c2_muxvals[] = {8, 8};
742static const unsigned i2c3_pins[] = {159, 160};
743static const unsigned i2c3_muxvals[] = {8, 8};
744static const unsigned i2c5_pins[] = {183, 184};
745static const unsigned i2c5_muxvals[] = {11, 11};
746static const unsigned i2c6_pins[] = {185, 186};
747static const unsigned i2c6_muxvals[] = {11, 11};
748static const unsigned nand_pins[] = {30, 31, 32, 33, 34, 35, 36, 39, 40, 41,
749 42, 43, 44, 45, 46};
750static const unsigned nand_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
751 8, 8};
752static const unsigned nand_cs1_pins[] = {37, 38};
753static const unsigned nand_cs1_muxvals[] = {8, 8};
754static const unsigned uart0_pins[] = {217, 218};
755static const unsigned uart0_muxvals[] = {8, 8};
756static const unsigned uart0b_pins[] = {179, 180};
757static const unsigned uart0b_muxvals[] = {10, 10};
758static const unsigned uart1_pins[] = {115, 116};
759static const unsigned uart1_muxvals[] = {8, 8};
760static const unsigned uart2_pins[] = {113, 114};
761static const unsigned uart2_muxvals[] = {8, 8};
762static const unsigned uart3_pins[] = {219, 220};
763static const unsigned uart3_muxvals[] = {8, 8};
764static const unsigned uart3b_pins[] = {181, 182};
765static const unsigned uart3b_muxvals[] = {10, 10};
766static const unsigned usb0_pins[] = {56, 57};
767static const unsigned usb0_muxvals[] = {8, 8};
768static const unsigned usb1_pins[] = {58, 59};
769static const unsigned usb1_muxvals[] = {8, 8};
770static const unsigned usb2_pins[] = {60, 61};
771static const unsigned usb2_muxvals[] = {8, 8};
772static const unsigned usb3_pins[] = {62, 63};
773static const unsigned usb3_muxvals[] = {8, 8};
774static const unsigned port_range0_pins[] = {
775 127, 128, 129, 130, 131, 132, 133, 134, /* PORT0x */
776 135, 136, 137, 138, 139, 140, 141, 142, /* PORT1x */
777 0, 1, 2, 3, 4, 5, 6, 7, /* PORT2x */
778 8, 9, 10, 11, 12, 13, 14, 15, /* PORT3x */
779 16, 17, 18, 19, 21, 22, 23, 24, /* PORT4x */
780 25, 30, 31, 32, 33, 34, 35, 36, /* PORT5x */
781 37, 38, 39, 40, 41, 42, 43, 44, /* PORT6x */
782 45, 46, 47, 48, 49, 50, 51, 52, /* PORT7x */
783 53, 54, 55, 56, 57, 58, 59, 60, /* PORT8x */
784 61, 62, 63, 64, 65, 66, 67, 68, /* PORT9x */
785 69, 70, 71, 76, 77, 78, 79, 80, /* PORT10x */
786};
787static const unsigned port_range0_muxvals[] = {
788 15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */
789 15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */
790 15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */
791 15, 15, 15, 15, 15, 15, 15, 15, /* PORT3x */
792 15, 15, 15, 15, 15, 15, 15, 15, /* PORT4x */
793 15, 15, 15, 15, 15, 15, 15, 15, /* PORT5x */
794 15, 15, 15, 15, 15, 15, 15, 15, /* PORT6x */
795 15, 15, 15, 15, 15, 15, 15, 15, /* PORT7x */
796 15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */
797 15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */
798 15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */
799};
800static const unsigned port_range1_pins[] = {
801 81, 82, 83, 84, 85, 86, 87, 88, /* PORT12x */
802 89, 90, 95, 96, 97, 98, 99, 100, /* PORT13x */
803 101, 102, 103, 104, 105, 106, 107, 108, /* PORT14x */
804 118, 119, 120, 121, 122, 123, 124, 125, /* PORT15x */
805 126, 72, 73, 92, 177, 93, 94, 176, /* PORT16x */
806 74, 91, 27, 28, 29, 75, 20, 26, /* PORT17x */
807 109, 110, 111, 112, 113, 114, 115, 116, /* PORT18x */
808 117, 143, 144, 145, 146, 147, 148, 149, /* PORT19x */
809 150, 151, 152, 153, 154, 155, 156, 157, /* PORT20x */
810 158, 159, 160, 161, 162, 163, 164, 165, /* PORT21x */
811 166, 178, 179, 180, 181, 182, 183, 184, /* PORT22x */
812 185, 187, 188, 189, 190, 191, 192, 193, /* PORT23x */
813 194, 195, 196, 197, 198, 199, 200, 201, /* PORT24x */
814 202, 203, 204, 205, 206, 207, 208, 209, /* PORT25x */
815 210, 211, 212, 213, 214, 215, 216, 217, /* PORT26x */
816 218, 219, 220, 221, 223, 224, 225, 226, /* PORT27x */
817 227, 228, 229, 230, 231, 232, 233, 234, /* PORT28x */
818};
819static const unsigned port_range1_muxvals[] = {
820 15, 15, 15, 15, 15, 15, 15, 15, /* PORT12x */
821 15, 15, 15, 15, 15, 15, 15, 15, /* PORT13x */
822 15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */
823 15, 15, 15, 15, 15, 15, 15, 15, /* PORT15x */
824 15, 15, 15, 15, 15, 15, 15, 15, /* PORT16x */
825 15, 15, 15, 15, 15, 15, 15, 15, /* PORT17x */
826 15, 15, 15, 15, 15, 15, 15, 15, /* PORT18x */
827 15, 15, 15, 15, 15, 15, 15, 15, /* PORT19x */
828 15, 15, 15, 15, 15, 15, 15, 15, /* PORT20x */
829 15, 15, 15, 15, 15, 15, 15, 15, /* PORT21x */
830 15, 15, 15, 15, 15, 15, 15, 15, /* PORT22x */
831 15, 15, 15, 15, 15, 15, 15, 15, /* PORT23x */
832 15, 15, 15, 15, 15, 15, 15, 15, /* PORT24x */
833 15, 15, 15, 15, 15, 15, 15, 15, /* PORT25x */
834 15, 15, 15, 15, 15, 15, 15, 15, /* PORT26x */
835 15, 15, 15, 15, 15, 15, 15, 15, /* PORT27x */
836 15, 15, 15, 15, 15, 15, 15, 15, /* PORT28x */
837};
838static const unsigned xirq_pins[] = {
839 118, 119, 120, 121, 122, 123, 124, 125, /* XIRQ0-7 */
840 126, 72, 73, 92, 177, 93, 94, 176, /* XIRQ8-15 */
841 74, 91, 27, 28, 29, 75, 20, 26, /* XIRQ16-23 */
842};
843static const unsigned xirq_muxvals[] = {
844 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ0-7 */
845 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ8-15 */
846 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ16-23 */
847};
848
849static const struct uniphier_pinctrl_group proxstream2_groups[] = {
850 UNIPHIER_PINCTRL_GROUP(emmc),
851 UNIPHIER_PINCTRL_GROUP(emmc_dat8),
852 UNIPHIER_PINCTRL_GROUP(i2c0),
853 UNIPHIER_PINCTRL_GROUP(i2c1),
854 UNIPHIER_PINCTRL_GROUP(i2c2),
855 UNIPHIER_PINCTRL_GROUP(i2c3),
856 UNIPHIER_PINCTRL_GROUP(i2c5),
857 UNIPHIER_PINCTRL_GROUP(i2c6),
858 UNIPHIER_PINCTRL_GROUP(nand),
859 UNIPHIER_PINCTRL_GROUP(nand_cs1),
860 UNIPHIER_PINCTRL_GROUP(uart0),
861 UNIPHIER_PINCTRL_GROUP(uart0b),
862 UNIPHIER_PINCTRL_GROUP(uart1),
863 UNIPHIER_PINCTRL_GROUP(uart2),
864 UNIPHIER_PINCTRL_GROUP(uart3),
865 UNIPHIER_PINCTRL_GROUP(uart3b),
866 UNIPHIER_PINCTRL_GROUP(usb0),
867 UNIPHIER_PINCTRL_GROUP(usb1),
868 UNIPHIER_PINCTRL_GROUP(usb2),
869 UNIPHIER_PINCTRL_GROUP(usb3),
870 UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0),
871 UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1),
872 UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq),
873 UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0),
874 UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1),
875 UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2),
876 UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3),
877 UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4),
878 UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5),
879 UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6),
880 UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7),
881 UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8),
882 UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9),
883 UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10),
884 UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11),
885 UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12),
886 UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13),
887 UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14),
888 UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15),
889 UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16),
890 UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17),
891 UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18),
892 UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19),
893 UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20),
894 UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21),
895 UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22),
896 UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23),
897 UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24),
898 UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25),
899 UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26),
900 UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27),
901 UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28),
902 UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29),
903 UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30),
904 UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31),
905 UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32),
906 UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33),
907 UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34),
908 UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35),
909 UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36),
910 UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37),
911 UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38),
912 UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39),
913 UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40),
914 UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41),
915 UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42),
916 UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43),
917 UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44),
918 UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45),
919 UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46),
920 UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47),
921 UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48),
922 UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49),
923 UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50),
924 UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51),
925 UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52),
926 UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53),
927 UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54),
928 UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55),
929 UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56),
930 UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57),
931 UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58),
932 UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59),
933 UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60),
934 UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61),
935 UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62),
936 UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63),
937 UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64),
938 UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65),
939 UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66),
940 UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67),
941 UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68),
942 UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69),
943 UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70),
944 UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71),
945 UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72),
946 UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73),
947 UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74),
948 UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75),
949 UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76),
950 UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77),
951 UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78),
952 UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79),
953 UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80),
954 UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81),
955 UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82),
956 UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83),
957 UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84),
958 UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85),
959 UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86),
960 UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87),
961 UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range1, 0),
962 UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range1, 1),
963 UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range1, 2),
964 UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range1, 3),
965 UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range1, 4),
966 UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range1, 5),
967 UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range1, 6),
968 UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range1, 7),
969 UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range1, 8),
970 UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range1, 9),
971 UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range1, 10),
972 UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range1, 11),
973 UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range1, 12),
974 UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range1, 13),
975 UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range1, 14),
976 UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range1, 15),
977 UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range1, 16),
978 UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range1, 17),
979 UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range1, 18),
980 UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range1, 19),
981 UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range1, 20),
982 UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range1, 21),
983 UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range1, 22),
984 UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range1, 23),
985 UNIPHIER_PINCTRL_GROUP_SINGLE(port150, port_range1, 24),
986 UNIPHIER_PINCTRL_GROUP_SINGLE(port151, port_range1, 25),
987 UNIPHIER_PINCTRL_GROUP_SINGLE(port152, port_range1, 26),
988 UNIPHIER_PINCTRL_GROUP_SINGLE(port153, port_range1, 27),
989 UNIPHIER_PINCTRL_GROUP_SINGLE(port154, port_range1, 28),
990 UNIPHIER_PINCTRL_GROUP_SINGLE(port155, port_range1, 29),
991 UNIPHIER_PINCTRL_GROUP_SINGLE(port156, port_range1, 30),
992 UNIPHIER_PINCTRL_GROUP_SINGLE(port157, port_range1, 31),
993 UNIPHIER_PINCTRL_GROUP_SINGLE(port160, port_range1, 32),
994 UNIPHIER_PINCTRL_GROUP_SINGLE(port161, port_range1, 33),
995 UNIPHIER_PINCTRL_GROUP_SINGLE(port162, port_range1, 34),
996 UNIPHIER_PINCTRL_GROUP_SINGLE(port163, port_range1, 35),
997 UNIPHIER_PINCTRL_GROUP_SINGLE(port164, port_range1, 36),
998 UNIPHIER_PINCTRL_GROUP_SINGLE(port165, port_range1, 37),
999 UNIPHIER_PINCTRL_GROUP_SINGLE(port166, port_range1, 38),
1000 UNIPHIER_PINCTRL_GROUP_SINGLE(port167, port_range1, 39),
1001 UNIPHIER_PINCTRL_GROUP_SINGLE(port170, port_range1, 40),
1002 UNIPHIER_PINCTRL_GROUP_SINGLE(port171, port_range1, 41),
1003 UNIPHIER_PINCTRL_GROUP_SINGLE(port172, port_range1, 42),
1004 UNIPHIER_PINCTRL_GROUP_SINGLE(port173, port_range1, 43),
1005 UNIPHIER_PINCTRL_GROUP_SINGLE(port174, port_range1, 44),
1006 UNIPHIER_PINCTRL_GROUP_SINGLE(port175, port_range1, 45),
1007 UNIPHIER_PINCTRL_GROUP_SINGLE(port176, port_range1, 46),
1008 UNIPHIER_PINCTRL_GROUP_SINGLE(port177, port_range1, 47),
1009 UNIPHIER_PINCTRL_GROUP_SINGLE(port180, port_range1, 48),
1010 UNIPHIER_PINCTRL_GROUP_SINGLE(port181, port_range1, 49),
1011 UNIPHIER_PINCTRL_GROUP_SINGLE(port182, port_range1, 50),
1012 UNIPHIER_PINCTRL_GROUP_SINGLE(port183, port_range1, 51),
1013 UNIPHIER_PINCTRL_GROUP_SINGLE(port184, port_range1, 52),
1014 UNIPHIER_PINCTRL_GROUP_SINGLE(port185, port_range1, 53),
1015 UNIPHIER_PINCTRL_GROUP_SINGLE(port186, port_range1, 54),
1016 UNIPHIER_PINCTRL_GROUP_SINGLE(port187, port_range1, 55),
1017 UNIPHIER_PINCTRL_GROUP_SINGLE(port190, port_range1, 56),
1018 UNIPHIER_PINCTRL_GROUP_SINGLE(port191, port_range1, 57),
1019 UNIPHIER_PINCTRL_GROUP_SINGLE(port192, port_range1, 58),
1020 UNIPHIER_PINCTRL_GROUP_SINGLE(port193, port_range1, 59),
1021 UNIPHIER_PINCTRL_GROUP_SINGLE(port194, port_range1, 60),
1022 UNIPHIER_PINCTRL_GROUP_SINGLE(port195, port_range1, 61),
1023 UNIPHIER_PINCTRL_GROUP_SINGLE(port196, port_range1, 62),
1024 UNIPHIER_PINCTRL_GROUP_SINGLE(port197, port_range1, 63),
1025 UNIPHIER_PINCTRL_GROUP_SINGLE(port200, port_range1, 64),
1026 UNIPHIER_PINCTRL_GROUP_SINGLE(port201, port_range1, 65),
1027 UNIPHIER_PINCTRL_GROUP_SINGLE(port202, port_range1, 66),
1028 UNIPHIER_PINCTRL_GROUP_SINGLE(port203, port_range1, 67),
1029 UNIPHIER_PINCTRL_GROUP_SINGLE(port204, port_range1, 68),
1030 UNIPHIER_PINCTRL_GROUP_SINGLE(port205, port_range1, 69),
1031 UNIPHIER_PINCTRL_GROUP_SINGLE(port206, port_range1, 70),
1032 UNIPHIER_PINCTRL_GROUP_SINGLE(port207, port_range1, 71),
1033 UNIPHIER_PINCTRL_GROUP_SINGLE(port210, port_range1, 72),
1034 UNIPHIER_PINCTRL_GROUP_SINGLE(port211, port_range1, 73),
1035 UNIPHIER_PINCTRL_GROUP_SINGLE(port212, port_range1, 74),
1036 UNIPHIER_PINCTRL_GROUP_SINGLE(port213, port_range1, 75),
1037 UNIPHIER_PINCTRL_GROUP_SINGLE(port214, port_range1, 76),
1038 UNIPHIER_PINCTRL_GROUP_SINGLE(port215, port_range1, 77),
1039 UNIPHIER_PINCTRL_GROUP_SINGLE(port216, port_range1, 78),
1040 UNIPHIER_PINCTRL_GROUP_SINGLE(port217, port_range1, 79),
1041 UNIPHIER_PINCTRL_GROUP_SINGLE(port220, port_range1, 80),
1042 UNIPHIER_PINCTRL_GROUP_SINGLE(port221, port_range1, 81),
1043 UNIPHIER_PINCTRL_GROUP_SINGLE(port222, port_range1, 82),
1044 UNIPHIER_PINCTRL_GROUP_SINGLE(port223, port_range1, 83),
1045 UNIPHIER_PINCTRL_GROUP_SINGLE(port224, port_range1, 84),
1046 UNIPHIER_PINCTRL_GROUP_SINGLE(port225, port_range1, 85),
1047 UNIPHIER_PINCTRL_GROUP_SINGLE(port226, port_range1, 86),
1048 UNIPHIER_PINCTRL_GROUP_SINGLE(port227, port_range1, 87),
1049 UNIPHIER_PINCTRL_GROUP_SINGLE(port230, port_range1, 88),
1050 UNIPHIER_PINCTRL_GROUP_SINGLE(port231, port_range1, 89),
1051 UNIPHIER_PINCTRL_GROUP_SINGLE(port232, port_range1, 90),
1052 UNIPHIER_PINCTRL_GROUP_SINGLE(port233, port_range1, 91),
1053 UNIPHIER_PINCTRL_GROUP_SINGLE(port234, port_range1, 92),
1054 UNIPHIER_PINCTRL_GROUP_SINGLE(port235, port_range1, 93),
1055 UNIPHIER_PINCTRL_GROUP_SINGLE(port236, port_range1, 94),
1056 UNIPHIER_PINCTRL_GROUP_SINGLE(port237, port_range1, 95),
1057 UNIPHIER_PINCTRL_GROUP_SINGLE(port240, port_range1, 96),
1058 UNIPHIER_PINCTRL_GROUP_SINGLE(port241, port_range1, 97),
1059 UNIPHIER_PINCTRL_GROUP_SINGLE(port242, port_range1, 98),
1060 UNIPHIER_PINCTRL_GROUP_SINGLE(port243, port_range1, 99),
1061 UNIPHIER_PINCTRL_GROUP_SINGLE(port244, port_range1, 100),
1062 UNIPHIER_PINCTRL_GROUP_SINGLE(port245, port_range1, 101),
1063 UNIPHIER_PINCTRL_GROUP_SINGLE(port246, port_range1, 102),
1064 UNIPHIER_PINCTRL_GROUP_SINGLE(port247, port_range1, 103),
1065 UNIPHIER_PINCTRL_GROUP_SINGLE(port250, port_range1, 104),
1066 UNIPHIER_PINCTRL_GROUP_SINGLE(port251, port_range1, 105),
1067 UNIPHIER_PINCTRL_GROUP_SINGLE(port252, port_range1, 106),
1068 UNIPHIER_PINCTRL_GROUP_SINGLE(port253, port_range1, 107),
1069 UNIPHIER_PINCTRL_GROUP_SINGLE(port254, port_range1, 108),
1070 UNIPHIER_PINCTRL_GROUP_SINGLE(port255, port_range1, 109),
1071 UNIPHIER_PINCTRL_GROUP_SINGLE(port256, port_range1, 110),
1072 UNIPHIER_PINCTRL_GROUP_SINGLE(port257, port_range1, 111),
1073 UNIPHIER_PINCTRL_GROUP_SINGLE(port260, port_range1, 112),
1074 UNIPHIER_PINCTRL_GROUP_SINGLE(port261, port_range1, 113),
1075 UNIPHIER_PINCTRL_GROUP_SINGLE(port262, port_range1, 114),
1076 UNIPHIER_PINCTRL_GROUP_SINGLE(port263, port_range1, 115),
1077 UNIPHIER_PINCTRL_GROUP_SINGLE(port264, port_range1, 116),
1078 UNIPHIER_PINCTRL_GROUP_SINGLE(port265, port_range1, 117),
1079 UNIPHIER_PINCTRL_GROUP_SINGLE(port266, port_range1, 118),
1080 UNIPHIER_PINCTRL_GROUP_SINGLE(port267, port_range1, 119),
1081 UNIPHIER_PINCTRL_GROUP_SINGLE(port270, port_range1, 120),
1082 UNIPHIER_PINCTRL_GROUP_SINGLE(port271, port_range1, 121),
1083 UNIPHIER_PINCTRL_GROUP_SINGLE(port272, port_range1, 122),
1084 UNIPHIER_PINCTRL_GROUP_SINGLE(port273, port_range1, 123),
1085 UNIPHIER_PINCTRL_GROUP_SINGLE(port274, port_range1, 124),
1086 UNIPHIER_PINCTRL_GROUP_SINGLE(port275, port_range1, 125),
1087 UNIPHIER_PINCTRL_GROUP_SINGLE(port276, port_range1, 126),
1088 UNIPHIER_PINCTRL_GROUP_SINGLE(port277, port_range1, 127),
1089 UNIPHIER_PINCTRL_GROUP_SINGLE(port280, port_range1, 128),
1090 UNIPHIER_PINCTRL_GROUP_SINGLE(port281, port_range1, 129),
1091 UNIPHIER_PINCTRL_GROUP_SINGLE(port282, port_range1, 130),
1092 UNIPHIER_PINCTRL_GROUP_SINGLE(port283, port_range1, 131),
1093 UNIPHIER_PINCTRL_GROUP_SINGLE(port284, port_range1, 132),
1094 UNIPHIER_PINCTRL_GROUP_SINGLE(port285, port_range1, 133),
1095 UNIPHIER_PINCTRL_GROUP_SINGLE(port286, port_range1, 134),
1096 UNIPHIER_PINCTRL_GROUP_SINGLE(port287, port_range1, 135),
1097 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq, 0),
1098 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq, 1),
1099 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq, 2),
1100 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq, 3),
1101 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq, 4),
1102 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq, 5),
1103 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq, 6),
1104 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq, 7),
1105 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq, 8),
1106 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq, 9),
1107 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq, 10),
1108 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq, 11),
1109 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq, 12),
1110 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq13, xirq, 13),
1111 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq, 14),
1112 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq, 15),
1113 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16, xirq, 16),
1114 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17, xirq, 17),
1115 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18, xirq, 18),
1116 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19, xirq, 19),
1117 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20, xirq, 20),
1118 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq21, xirq, 21),
1119 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq22, xirq, 22),
1120 UNIPHIER_PINCTRL_GROUP_SINGLE(xirq23, xirq, 23),
1121};
1122
1123static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
1124static const char * const i2c0_groups[] = {"i2c0"};
1125static const char * const i2c1_groups[] = {"i2c1"};
1126static const char * const i2c2_groups[] = {"i2c2"};
1127static const char * const i2c3_groups[] = {"i2c3"};
1128static const char * const i2c5_groups[] = {"i2c5"};
1129static const char * const i2c6_groups[] = {"i2c6"};
1130static const char * const nand_groups[] = {"nand", "nand_cs1"};
1131static const char * const uart0_groups[] = {"uart0", "uart0b"};
1132static const char * const uart1_groups[] = {"uart1"};
1133static const char * const uart2_groups[] = {"uart2"};
1134static const char * const uart3_groups[] = {"uart3", "uart3b"};
1135static const char * const usb0_groups[] = {"usb0"};
1136static const char * const usb1_groups[] = {"usb1"};
1137static const char * const usb2_groups[] = {"usb2"};
1138static const char * const usb3_groups[] = {"usb3"};
1139static const char * const port_groups[] = {
1140 "port00", "port01", "port02", "port03",
1141 "port04", "port05", "port06", "port07",
1142 "port10", "port11", "port12", "port13",
1143 "port14", "port15", "port16", "port17",
1144 "port20", "port21", "port22", "port23",
1145 "port24", "port25", "port26", "port27",
1146 "port30", "port31", "port32", "port33",
1147 "port34", "port35", "port36", "port37",
1148 "port40", "port41", "port42", "port43",
1149 "port44", "port45", "port46", "port47",
1150 "port50", "port51", "port52", "port53",
1151 "port54", "port55", "port56", "port57",
1152 "port60", "port61", "port62", "port63",
1153 "port64", "port65", "port66", "port67",
1154 "port70", "port71", "port72", "port73",
1155 "port74", "port75", "port76", "port77",
1156 "port80", "port81", "port82", "port83",
1157 "port84", "port85", "port86", "port87",
1158 "port90", "port91", "port92", "port93",
1159 "port94", "port95", "port96", "port97",
1160 "port100", "port101", "port102", "port103",
1161 "port104", "port105", "port106", "port107",
1162 /* port110-117 missing */
1163 "port120", "port121", "port122", "port123",
1164 "port124", "port125", "port126", "port127",
1165 "port130", "port131", "port132", "port133",
1166 "port134", "port135", "port136", "port137",
1167 "port140", "port141", "port142", "port143",
1168 "port144", "port145", "port146", "port147",
1169 "port150", "port151", "port152", "port153",
1170 "port154", "port155", "port156", "port157",
1171 "port160", "port161", "port162", "port163",
1172 "port164", "port165", "port166", "port167",
1173 "port170", "port171", "port172", "port173",
1174 "port174", "port175", "port176", "port177",
1175 "port180", "port181", "port182", "port183",
1176 "port184", "port185", "port186", "port187",
1177 "port190", "port191", "port192", "port193",
1178 "port194", "port195", "port196", "port197",
1179 "port200", "port201", "port202", "port203",
1180 "port204", "port205", "port206", "port207",
1181 "port210", "port211", "port212", "port213",
1182 "port214", "port215", "port216", "port217",
1183 "port220", "port221", "port222", "port223",
1184 "port224", "port225", "port226", "port227",
1185 "port230", "port231", "port232", "port233",
1186 "port234", "port235", "port236", "port237",
1187 "port240", "port241", "port242", "port243",
1188 "port244", "port245", "port246", "port247",
1189 "port250", "port251", "port252", "port253",
1190 "port254", "port255", "port256", "port257",
1191 "port260", "port261", "port262", "port263",
1192 "port264", "port265", "port266", "port267",
1193 "port270", "port271", "port272", "port273",
1194 "port274", "port275", "port276", "port277",
1195 "port280", "port281", "port282", "port283",
1196 "port284", "port285", "port286", "port287",
1197};
1198static const char * const xirq_groups[] = {
1199 "xirq0", "xirq1", "xirq2", "xirq3",
1200 "xirq4", "xirq5", "xirq6", "xirq7",
1201 "xirq8", "xirq9", "xirq10", "xirq11",
1202 "xirq12", "xirq13", "xirq14", "xirq15",
1203 "xirq16", "xirq17", "xirq18", "xirq19",
1204 "xirq20", "xirq21", "xirq22", "xirq23",
1205};
1206
1207static const struct uniphier_pinmux_function proxstream2_functions[] = {
1208 UNIPHIER_PINMUX_FUNCTION(emmc),
1209 UNIPHIER_PINMUX_FUNCTION(i2c0),
1210 UNIPHIER_PINMUX_FUNCTION(i2c1),
1211 UNIPHIER_PINMUX_FUNCTION(i2c2),
1212 UNIPHIER_PINMUX_FUNCTION(i2c3),
1213 UNIPHIER_PINMUX_FUNCTION(i2c5),
1214 UNIPHIER_PINMUX_FUNCTION(i2c6),
1215 UNIPHIER_PINMUX_FUNCTION(nand),
1216 UNIPHIER_PINMUX_FUNCTION(uart0),
1217 UNIPHIER_PINMUX_FUNCTION(uart1),
1218 UNIPHIER_PINMUX_FUNCTION(uart2),
1219 UNIPHIER_PINMUX_FUNCTION(uart3),
1220 UNIPHIER_PINMUX_FUNCTION(usb0),
1221 UNIPHIER_PINMUX_FUNCTION(usb1),
1222 UNIPHIER_PINMUX_FUNCTION(usb2),
1223 UNIPHIER_PINMUX_FUNCTION(usb3),
1224 UNIPHIER_PINMUX_FUNCTION(port),
1225 UNIPHIER_PINMUX_FUNCTION(xirq),
1226};
1227
1228static struct uniphier_pinctrl_socdata proxstream2_pindata = {
1229 .groups = proxstream2_groups,
1230 .groups_count = ARRAY_SIZE(proxstream2_groups),
1231 .functions = proxstream2_functions,
1232 .functions_count = ARRAY_SIZE(proxstream2_functions),
1233 .mux_bits = 8,
1234 .reg_stride = 4,
1235 .load_pinctrl = false,
1236};
1237
1238static struct pinctrl_desc proxstream2_pinctrl_desc = {
1239 .name = DRIVER_NAME,
1240 .pins = proxstream2_pins,
1241 .npins = ARRAY_SIZE(proxstream2_pins),
1242 .owner = THIS_MODULE,
1243};
1244
1245static int proxstream2_pinctrl_probe(struct platform_device *pdev)
1246{
1247 return uniphier_pinctrl_probe(pdev, &proxstream2_pinctrl_desc,
1248 &proxstream2_pindata);
1249}
1250
1251static const struct of_device_id proxstream2_pinctrl_match[] = {
1252 { .compatible = "socionext,proxstream2-pinctrl" },
1253 { /* sentinel */ }
1254};
1255MODULE_DEVICE_TABLE(of, proxstream2_pinctrl_match);
1256
1257static struct platform_driver proxstream2_pinctrl_driver = {
1258 .probe = proxstream2_pinctrl_probe,
1259 .remove = uniphier_pinctrl_remove,
1260 .driver = {
1261 .name = DRIVER_NAME,
1262 .of_match_table = proxstream2_pinctrl_match,
1263 },
1264};
1265module_platform_driver(proxstream2_pinctrl_driver);
1266
1267MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
1268MODULE_DESCRIPTION("UniPhier ProXstream2 pinctrl driver");
1269MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
new file mode 100644
index 000000000000..918f3b643f1b
--- /dev/null
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
@@ -0,0 +1,684 @@
1/*
2 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/export.h>
16#include <linux/mfd/syscon.h>
17#include <linux/pinctrl/pinconf.h>
18#include <linux/pinctrl/pinconf-generic.h>
19#include <linux/pinctrl/pinctrl.h>
20#include <linux/pinctrl/pinmux.h>
21#include <linux/platform_device.h>
22#include <linux/regmap.h>
23
24#include "../core.h"
25#include "../pinctrl-utils.h"
26#include "pinctrl-uniphier.h"
27
28struct uniphier_pinctrl_priv {
29 struct pinctrl_dev *pctldev;
30 struct regmap *regmap;
31 struct uniphier_pinctrl_socdata *socdata;
32};
33
34static int uniphier_pctl_get_groups_count(struct pinctrl_dev *pctldev)
35{
36 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
37
38 return priv->socdata->groups_count;
39}
40
41static const char *uniphier_pctl_get_group_name(struct pinctrl_dev *pctldev,
42 unsigned selector)
43{
44 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
45
46 return priv->socdata->groups[selector].name;
47}
48
49static int uniphier_pctl_get_group_pins(struct pinctrl_dev *pctldev,
50 unsigned selector,
51 const unsigned **pins,
52 unsigned *num_pins)
53{
54 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
55
56 *pins = priv->socdata->groups[selector].pins;
57 *num_pins = priv->socdata->groups[selector].num_pins;
58
59 return 0;
60}
61
62#ifdef CONFIG_DEBUG_FS
63static void uniphier_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
64 struct seq_file *s, unsigned offset)
65{
66 const struct pinctrl_pin_desc *pin = &pctldev->desc->pins[offset];
67 const char *pull_dir, *drv_str;
68
69 switch (uniphier_pin_get_pull_dir(pin->drv_data)) {
70 case UNIPHIER_PIN_PULL_UP:
71 pull_dir = "UP";
72 break;
73 case UNIPHIER_PIN_PULL_DOWN:
74 pull_dir = "DOWN";
75 break;
76 case UNIPHIER_PIN_PULL_NONE:
77 pull_dir = "NONE";
78 break;
79 default:
80 BUG();
81 }
82
83 switch (uniphier_pin_get_drv_str(pin->drv_data)) {
84 case UNIPHIER_PIN_DRV_4_8:
85 drv_str = "4/8(mA)";
86 break;
87 case UNIPHIER_PIN_DRV_8_12_16_20:
88 drv_str = "8/12/16/20(mA)";
89 break;
90 case UNIPHIER_PIN_DRV_FIXED_4:
91 drv_str = "4(mA)";
92 break;
93 case UNIPHIER_PIN_DRV_FIXED_5:
94 drv_str = "5(mA)";
95 break;
96 case UNIPHIER_PIN_DRV_FIXED_8:
97 drv_str = "8(mA)";
98 break;
99 case UNIPHIER_PIN_DRV_NONE:
100 drv_str = "NONE";
101 break;
102 default:
103 BUG();
104 }
105
106 seq_printf(s, " PULL_DIR=%s DRV_STR=%s", pull_dir, drv_str);
107}
108#endif
109
110static const struct pinctrl_ops uniphier_pctlops = {
111 .get_groups_count = uniphier_pctl_get_groups_count,
112 .get_group_name = uniphier_pctl_get_group_name,
113 .get_group_pins = uniphier_pctl_get_group_pins,
114#ifdef CONFIG_DEBUG_FS
115 .pin_dbg_show = uniphier_pctl_pin_dbg_show,
116#endif
117 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
118 .dt_free_map = pinctrl_utils_dt_free_map,
119};
120
121static int uniphier_conf_pin_bias_get(struct pinctrl_dev *pctldev,
122 const struct pinctrl_pin_desc *pin,
123 enum pin_config_param param)
124{
125 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
126 enum uniphier_pin_pull_dir pull_dir =
127 uniphier_pin_get_pull_dir(pin->drv_data);
128 unsigned int pupdctrl, reg, shift, val;
129 unsigned int expected = 1;
130 int ret;
131
132 switch (param) {
133 case PIN_CONFIG_BIAS_DISABLE:
134 if (pull_dir == UNIPHIER_PIN_PULL_NONE)
135 return 0;
136 if (pull_dir == UNIPHIER_PIN_PULL_UP_FIXED ||
137 pull_dir == UNIPHIER_PIN_PULL_DOWN_FIXED)
138 return -EINVAL;
139 expected = 0;
140 break;
141 case PIN_CONFIG_BIAS_PULL_UP:
142 if (pull_dir == UNIPHIER_PIN_PULL_UP_FIXED)
143 return 0;
144 if (pull_dir != UNIPHIER_PIN_PULL_UP)
145 return -EINVAL;
146 break;
147 case PIN_CONFIG_BIAS_PULL_DOWN:
148 if (pull_dir == UNIPHIER_PIN_PULL_DOWN_FIXED)
149 return 0;
150 if (pull_dir != UNIPHIER_PIN_PULL_DOWN)
151 return -EINVAL;
152 break;
153 default:
154 BUG();
155 }
156
157 pupdctrl = uniphier_pin_get_pupdctrl(pin->drv_data);
158
159 reg = UNIPHIER_PINCTRL_PUPDCTRL_BASE + pupdctrl / 32 * 4;
160 shift = pupdctrl % 32;
161
162 ret = regmap_read(priv->regmap, reg, &val);
163 if (ret)
164 return ret;
165
166 val = (val >> shift) & 1;
167
168 return (val == expected) ? 0 : -EINVAL;
169}
170
171static int uniphier_conf_pin_drive_get(struct pinctrl_dev *pctldev,
172 const struct pinctrl_pin_desc *pin,
173 u16 *strength)
174{
175 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
176 enum uniphier_pin_drv_str drv_str =
177 uniphier_pin_get_drv_str(pin->drv_data);
178 const unsigned int strength_4_8[] = {4, 8};
179 const unsigned int strength_8_12_16_20[] = {8, 12, 16, 20};
180 const unsigned int *supported_strength;
181 unsigned int drvctrl, reg, shift, mask, width, val;
182 int ret;
183
184 switch (drv_str) {
185 case UNIPHIER_PIN_DRV_4_8:
186 supported_strength = strength_4_8;
187 width = 1;
188 break;
189 case UNIPHIER_PIN_DRV_8_12_16_20:
190 supported_strength = strength_8_12_16_20;
191 width = 2;
192 break;
193 case UNIPHIER_PIN_DRV_FIXED_4:
194 *strength = 4;
195 return 0;
196 case UNIPHIER_PIN_DRV_FIXED_5:
197 *strength = 5;
198 return 0;
199 case UNIPHIER_PIN_DRV_FIXED_8:
200 *strength = 8;
201 return 0;
202 default:
203 /* drive strength control is not supported for this pin */
204 return -EINVAL;
205 }
206
207 drvctrl = uniphier_pin_get_drvctrl(pin->drv_data);
208 drvctrl *= width;
209
210 reg = (width == 2) ? UNIPHIER_PINCTRL_DRV2CTRL_BASE :
211 UNIPHIER_PINCTRL_DRVCTRL_BASE;
212
213 reg += drvctrl / 32 * 4;
214 shift = drvctrl % 32;
215 mask = (1U << width) - 1;
216
217 ret = regmap_read(priv->regmap, reg, &val);
218 if (ret)
219 return ret;
220
221 *strength = supported_strength[(val >> shift) & mask];
222
223 return 0;
224}
225
226static int uniphier_conf_pin_input_enable_get(struct pinctrl_dev *pctldev,
227 const struct pinctrl_pin_desc *pin)
228{
229 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
230 unsigned int iectrl = uniphier_pin_get_iectrl(pin->drv_data);
231 unsigned int val;
232 int ret;
233
234 if (iectrl == UNIPHIER_PIN_IECTRL_NONE)
235 /* This pin is always input-enabled. */
236 return 0;
237
238 ret = regmap_read(priv->regmap, UNIPHIER_PINCTRL_IECTRL, &val);
239 if (ret)
240 return ret;
241
242 return val & BIT(iectrl) ? 0 : -EINVAL;
243}
244
245static int uniphier_conf_pin_config_get(struct pinctrl_dev *pctldev,
246 unsigned pin,
247 unsigned long *configs)
248{
249 const struct pinctrl_pin_desc *pin_desc = &pctldev->desc->pins[pin];
250 enum pin_config_param param = pinconf_to_config_param(*configs);
251 bool has_arg = false;
252 u16 arg;
253 int ret;
254
255 switch (param) {
256 case PIN_CONFIG_BIAS_DISABLE:
257 case PIN_CONFIG_BIAS_PULL_UP:
258 case PIN_CONFIG_BIAS_PULL_DOWN:
259 ret = uniphier_conf_pin_bias_get(pctldev, pin_desc, param);
260 break;
261 case PIN_CONFIG_DRIVE_STRENGTH:
262 ret = uniphier_conf_pin_drive_get(pctldev, pin_desc, &arg);
263 has_arg = true;
264 break;
265 case PIN_CONFIG_INPUT_ENABLE:
266 ret = uniphier_conf_pin_input_enable_get(pctldev, pin_desc);
267 break;
268 default:
269 /* unsupported parameter */
270 ret = -EINVAL;
271 break;
272 }
273
274 if (ret == 0 && has_arg)
275 *configs = pinconf_to_config_packed(param, arg);
276
277 return ret;
278}
279
280static int uniphier_conf_pin_bias_set(struct pinctrl_dev *pctldev,
281 const struct pinctrl_pin_desc *pin,
282 enum pin_config_param param,
283 u16 arg)
284{
285 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
286 enum uniphier_pin_pull_dir pull_dir =
287 uniphier_pin_get_pull_dir(pin->drv_data);
288 unsigned int pupdctrl, reg, shift;
289 unsigned int val = 1;
290
291 switch (param) {
292 case PIN_CONFIG_BIAS_DISABLE:
293 if (pull_dir == UNIPHIER_PIN_PULL_NONE)
294 return 0;
295 if (pull_dir == UNIPHIER_PIN_PULL_UP_FIXED ||
296 pull_dir == UNIPHIER_PIN_PULL_DOWN_FIXED) {
297 dev_err(pctldev->dev,
298 "can not disable pull register for pin %u (%s)\n",
299 pin->number, pin->name);
300 return -EINVAL;
301 }
302 val = 0;
303 break;
304 case PIN_CONFIG_BIAS_PULL_UP:
305 if (pull_dir == UNIPHIER_PIN_PULL_UP_FIXED && arg != 0)
306 return 0;
307 if (pull_dir != UNIPHIER_PIN_PULL_UP) {
308 dev_err(pctldev->dev,
309 "pull-up is unsupported for pin %u (%s)\n",
310 pin->number, pin->name);
311 return -EINVAL;
312 }
313 if (arg == 0) {
314 dev_err(pctldev->dev, "pull-up can not be total\n");
315 return -EINVAL;
316 }
317 break;
318 case PIN_CONFIG_BIAS_PULL_DOWN:
319 if (pull_dir == UNIPHIER_PIN_PULL_DOWN_FIXED && arg != 0)
320 return 0;
321 if (pull_dir != UNIPHIER_PIN_PULL_DOWN) {
322 dev_err(pctldev->dev,
323 "pull-down is unsupported for pin %u (%s)\n",
324 pin->number, pin->name);
325 return -EINVAL;
326 }
327 if (arg == 0) {
328 dev_err(pctldev->dev, "pull-down can not be total\n");
329 return -EINVAL;
330 }
331 break;
332 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
333 if (pull_dir == UNIPHIER_PIN_PULL_NONE) {
334 dev_err(pctldev->dev,
335 "pull-up/down is unsupported for pin %u (%s)\n",
336 pin->number, pin->name);
337 return -EINVAL;
338 }
339
340 if (arg == 0)
341 return 0; /* configuration ingored */
342 break;
343 default:
344 BUG();
345 }
346
347 pupdctrl = uniphier_pin_get_pupdctrl(pin->drv_data);
348
349 reg = UNIPHIER_PINCTRL_PUPDCTRL_BASE + pupdctrl / 32 * 4;
350 shift = pupdctrl % 32;
351
352 return regmap_update_bits(priv->regmap, reg, 1 << shift, val << shift);
353}
354
355static int uniphier_conf_pin_drive_set(struct pinctrl_dev *pctldev,
356 const struct pinctrl_pin_desc *pin,
357 u16 strength)
358{
359 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
360 enum uniphier_pin_drv_str drv_str =
361 uniphier_pin_get_drv_str(pin->drv_data);
362 const unsigned int strength_4_8[] = {4, 8, -1};
363 const unsigned int strength_8_12_16_20[] = {8, 12, 16, 20, -1};
364 const unsigned int *supported_strength;
365 unsigned int drvctrl, reg, shift, mask, width, val;
366
367 switch (drv_str) {
368 case UNIPHIER_PIN_DRV_4_8:
369 supported_strength = strength_4_8;
370 width = 1;
371 break;
372 case UNIPHIER_PIN_DRV_8_12_16_20:
373 supported_strength = strength_8_12_16_20;
374 width = 2;
375 break;
376 default:
377 dev_err(pctldev->dev,
378 "cannot change drive strength for pin %u (%s)\n",
379 pin->number, pin->name);
380 return -EINVAL;
381 }
382
383 for (val = 0; supported_strength[val] > 0; val++) {
384 if (supported_strength[val] > strength)
385 break;
386 }
387
388 if (val == 0) {
389 dev_err(pctldev->dev,
390 "unsupported drive strength %u mA for pin %u (%s)\n",
391 strength, pin->number, pin->name);
392 return -EINVAL;
393 }
394
395 val--;
396
397 drvctrl = uniphier_pin_get_drvctrl(pin->drv_data);
398 drvctrl *= width;
399
400 reg = (width == 2) ? UNIPHIER_PINCTRL_DRV2CTRL_BASE :
401 UNIPHIER_PINCTRL_DRVCTRL_BASE;
402
403 reg += drvctrl / 32 * 4;
404 shift = drvctrl % 32;
405 mask = (1U << width) - 1;
406
407 return regmap_update_bits(priv->regmap, reg,
408 mask << shift, val << shift);
409}
410
411static int uniphier_conf_pin_input_enable(struct pinctrl_dev *pctldev,
412 const struct pinctrl_pin_desc *pin,
413 u16 enable)
414{
415 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
416 unsigned int iectrl = uniphier_pin_get_iectrl(pin->drv_data);
417
418 if (enable == 0) {
419 /*
420 * Multiple pins share one input enable, so per-pin disabling
421 * is impossible.
422 */
423 dev_err(pctldev->dev, "unable to disable input\n");
424 return -EINVAL;
425 }
426
427 if (iectrl == UNIPHIER_PIN_IECTRL_NONE)
428 /* This pin is always input-enabled. nothing to do. */
429 return 0;
430
431 return regmap_update_bits(priv->regmap, UNIPHIER_PINCTRL_IECTRL,
432 BIT(iectrl), BIT(iectrl));
433}
434
435static int uniphier_conf_pin_config_set(struct pinctrl_dev *pctldev,
436 unsigned pin,
437 unsigned long *configs,
438 unsigned num_configs)
439{
440 const struct pinctrl_pin_desc *pin_desc = &pctldev->desc->pins[pin];
441 int i, ret;
442
443 for (i = 0; i < num_configs; i++) {
444 enum pin_config_param param =
445 pinconf_to_config_param(configs[i]);
446 u16 arg = pinconf_to_config_argument(configs[i]);
447
448 switch (param) {
449 case PIN_CONFIG_BIAS_DISABLE:
450 case PIN_CONFIG_BIAS_PULL_UP:
451 case PIN_CONFIG_BIAS_PULL_DOWN:
452 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
453 ret = uniphier_conf_pin_bias_set(pctldev, pin_desc,
454 param, arg);
455 break;
456 case PIN_CONFIG_DRIVE_STRENGTH:
457 ret = uniphier_conf_pin_drive_set(pctldev, pin_desc,
458 arg);
459 break;
460 case PIN_CONFIG_INPUT_ENABLE:
461 ret = uniphier_conf_pin_input_enable(pctldev,
462 pin_desc, arg);
463 break;
464 default:
465 dev_err(pctldev->dev,
466 "unsupported configuration parameter %u\n",
467 param);
468 return -EINVAL;
469 }
470
471 if (ret)
472 return ret;
473 }
474
475 return 0;
476}
477
478static int uniphier_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
479 unsigned selector,
480 unsigned long *configs,
481 unsigned num_configs)
482{
483 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
484 const unsigned *pins = priv->socdata->groups[selector].pins;
485 unsigned num_pins = priv->socdata->groups[selector].num_pins;
486 int i, ret;
487
488 for (i = 0; i < num_pins; i++) {
489 ret = uniphier_conf_pin_config_set(pctldev, pins[i],
490 configs, num_configs);
491 if (ret)
492 return ret;
493 }
494
495 return 0;
496}
497
498static const struct pinconf_ops uniphier_confops = {
499 .is_generic = true,
500 .pin_config_get = uniphier_conf_pin_config_get,
501 .pin_config_set = uniphier_conf_pin_config_set,
502 .pin_config_group_set = uniphier_conf_pin_config_group_set,
503};
504
505static int uniphier_pmx_get_functions_count(struct pinctrl_dev *pctldev)
506{
507 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
508
509 return priv->socdata->functions_count;
510}
511
512static const char *uniphier_pmx_get_function_name(struct pinctrl_dev *pctldev,
513 unsigned selector)
514{
515 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
516
517 return priv->socdata->functions[selector].name;
518}
519
520static int uniphier_pmx_get_function_groups(struct pinctrl_dev *pctldev,
521 unsigned selector,
522 const char * const **groups,
523 unsigned *num_groups)
524{
525 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
526
527 *groups = priv->socdata->functions[selector].groups;
528 *num_groups = priv->socdata->functions[selector].num_groups;
529
530 return 0;
531}
532
533static int uniphier_pmx_set_one_mux(struct pinctrl_dev *pctldev, unsigned pin,
534 unsigned muxval)
535{
536 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
537 unsigned mux_bits = priv->socdata->mux_bits;
538 unsigned reg_stride = priv->socdata->reg_stride;
539 unsigned reg, reg_end, shift, mask;
540 int ret;
541
542 reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride;
543 reg_end = reg + reg_stride;
544 shift = pin * mux_bits % 32;
545 mask = (1U << mux_bits) - 1;
546
547 /*
548 * If reg_stride is greater than 4, the MSB of each pinsel shall be
549 * stored in the offset+4.
550 */
551 for (; reg < reg_end; reg += 4) {
552 ret = regmap_update_bits(priv->regmap, reg,
553 mask << shift, muxval << shift);
554 if (ret)
555 return ret;
556 muxval >>= mux_bits;
557 }
558
559 if (priv->socdata->load_pinctrl) {
560 ret = regmap_write(priv->regmap,
561 UNIPHIER_PINCTRL_LOAD_PINMUX, 1);
562 if (ret)
563 return ret;
564 }
565
566 /* some pins need input-enabling */
567 return uniphier_conf_pin_input_enable(pctldev,
568 &pctldev->desc->pins[pin], 1);
569}
570
571static int uniphier_pmx_set_mux(struct pinctrl_dev *pctldev,
572 unsigned func_selector,
573 unsigned group_selector)
574{
575 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
576 const struct uniphier_pinctrl_group *grp =
577 &priv->socdata->groups[group_selector];
578 int i;
579 int ret;
580
581 for (i = 0; i < grp->num_pins; i++) {
582 ret = uniphier_pmx_set_one_mux(pctldev, grp->pins[i],
583 grp->muxvals[i]);
584 if (ret)
585 return ret;
586 }
587
588 return 0;
589}
590
591static int uniphier_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
592 struct pinctrl_gpio_range *range,
593 unsigned offset)
594{
595 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
596 const struct uniphier_pinctrl_group *groups = priv->socdata->groups;
597 int groups_count = priv->socdata->groups_count;
598 enum uniphier_pinmux_gpio_range_type range_type;
599 int i, j;
600
601 if (strstr(range->name, "irq"))
602 range_type = UNIPHIER_PINMUX_GPIO_RANGE_IRQ;
603 else
604 range_type = UNIPHIER_PINMUX_GPIO_RANGE_PORT;
605
606 for (i = 0; i < groups_count; i++) {
607 if (groups[i].range_type != range_type)
608 continue;
609
610 for (j = 0; j < groups[i].num_pins; j++)
611 if (groups[i].pins[j] == offset)
612 goto found;
613 }
614
615 dev_err(pctldev->dev, "pin %u does not support GPIO\n", offset);
616 return -EINVAL;
617
618found:
619 return uniphier_pmx_set_one_mux(pctldev, offset, groups[i].muxvals[j]);
620}
621
622static const struct pinmux_ops uniphier_pmxops = {
623 .get_functions_count = uniphier_pmx_get_functions_count,
624 .get_function_name = uniphier_pmx_get_function_name,
625 .get_function_groups = uniphier_pmx_get_function_groups,
626 .set_mux = uniphier_pmx_set_mux,
627 .gpio_request_enable = uniphier_pmx_gpio_request_enable,
628 .strict = true,
629};
630
631int uniphier_pinctrl_probe(struct platform_device *pdev,
632 struct pinctrl_desc *desc,
633 struct uniphier_pinctrl_socdata *socdata)
634{
635 struct device *dev = &pdev->dev;
636 struct uniphier_pinctrl_priv *priv;
637
638 if (!socdata ||
639 !socdata->groups ||
640 !socdata->groups_count ||
641 !socdata->functions ||
642 !socdata->functions_count ||
643 !socdata->mux_bits ||
644 !socdata->reg_stride) {
645 dev_err(dev, "pinctrl socdata lacks necessary members\n");
646 return -EINVAL;
647 }
648
649 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
650 if (!priv)
651 return -ENOMEM;
652
653 priv->regmap = syscon_node_to_regmap(dev->of_node);
654 if (IS_ERR(priv->regmap)) {
655 dev_err(dev, "failed to get regmap\n");
656 return PTR_ERR(priv->regmap);
657 }
658
659 priv->socdata = socdata;
660 desc->pctlops = &uniphier_pctlops;
661 desc->pmxops = &uniphier_pmxops;
662 desc->confops = &uniphier_confops;
663
664 priv->pctldev = pinctrl_register(desc, dev, priv);
665 if (IS_ERR(priv->pctldev)) {
666 dev_err(dev, "failed to register UniPhier pinctrl driver\n");
667 return PTR_ERR(priv->pctldev);
668 }
669
670 platform_set_drvdata(pdev, priv);
671
672 return 0;
673}
674EXPORT_SYMBOL_GPL(uniphier_pinctrl_probe);
675
676int uniphier_pinctrl_remove(struct platform_device *pdev)
677{
678 struct uniphier_pinctrl_priv *priv = platform_get_drvdata(pdev);
679
680 pinctrl_unregister(priv->pctldev);
681
682 return 0;
683}
684EXPORT_SYMBOL_GPL(uniphier_pinctrl_remove);
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier.h b/drivers/pinctrl/uniphier/pinctrl-uniphier.h
new file mode 100644
index 000000000000..e1e98b868be5
--- /dev/null
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier.h
@@ -0,0 +1,217 @@
1/*
2 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef __PINCTRL_UNIPHIER_H__
16#define __PINCTRL_UNIPHIER_H__
17
18#include <linux/bug.h>
19#include <linux/kernel.h>
20#include <linux/types.h>
21
22#define UNIPHIER_PINCTRL_PINMUX_BASE 0x0
23#define UNIPHIER_PINCTRL_LOAD_PINMUX 0x700
24#define UNIPHIER_PINCTRL_DRVCTRL_BASE 0x800
25#define UNIPHIER_PINCTRL_DRV2CTRL_BASE 0x900
26#define UNIPHIER_PINCTRL_PUPDCTRL_BASE 0xa00
27#define UNIPHIER_PINCTRL_IECTRL 0xd00
28
29/* input enable control register bit */
30#define UNIPHIER_PIN_IECTRL_SHIFT 0
31#define UNIPHIER_PIN_IECTRL_BITS 8
32#define UNIPHIER_PIN_IECTRL_MASK ((1UL << (UNIPHIER_PIN_IECTRL_BITS)) \
33 - 1)
34
35/* drive strength control register number */
36#define UNIPHIER_PIN_DRVCTRL_SHIFT ((UNIPHIER_PIN_IECTRL_SHIFT) + \
37 (UNIPHIER_PIN_IECTRL_BITS))
38#define UNIPHIER_PIN_DRVCTRL_BITS 9
39#define UNIPHIER_PIN_DRVCTRL_MASK ((1UL << (UNIPHIER_PIN_DRVCTRL_BITS)) \
40 - 1)
41
42/* supported drive strength (mA) */
43#define UNIPHIER_PIN_DRV_STR_SHIFT ((UNIPHIER_PIN_DRVCTRL_SHIFT) + \
44 (UNIPHIER_PIN_DRVCTRL_BITS))
45#define UNIPHIER_PIN_DRV_STR_BITS 3
46#define UNIPHIER_PIN_DRV_STR_MASK ((1UL << (UNIPHIER_PIN_DRV_STR_BITS)) \
47 - 1)
48
49/* pull-up / pull-down register number */
50#define UNIPHIER_PIN_PUPDCTRL_SHIFT ((UNIPHIER_PIN_DRV_STR_SHIFT) + \
51 (UNIPHIER_PIN_DRV_STR_BITS))
52#define UNIPHIER_PIN_PUPDCTRL_BITS 9
53#define UNIPHIER_PIN_PUPDCTRL_MASK ((1UL << (UNIPHIER_PIN_PUPDCTRL_BITS))\
54 - 1)
55
56/* direction of pull register */
57#define UNIPHIER_PIN_PULL_DIR_SHIFT ((UNIPHIER_PIN_PUPDCTRL_SHIFT) + \
58 (UNIPHIER_PIN_PUPDCTRL_BITS))
59#define UNIPHIER_PIN_PULL_DIR_BITS 3
60#define UNIPHIER_PIN_PULL_DIR_MASK ((1UL << (UNIPHIER_PIN_PULL_DIR_BITS))\
61 - 1)
62
63#if UNIPHIER_PIN_PULL_DIR_SHIFT + UNIPHIER_PIN_PULL_DIR_BITS > BITS_PER_LONG
64#error "unable to pack pin attributes."
65#endif
66
67#define UNIPHIER_PIN_IECTRL_NONE (UNIPHIER_PIN_IECTRL_MASK)
68
69/* selectable drive strength */
70enum uniphier_pin_drv_str {
71 UNIPHIER_PIN_DRV_4_8, /* 2 level control: 4/8 mA */
72 UNIPHIER_PIN_DRV_8_12_16_20, /* 4 level control: 8/12/16/20 mA */
73 UNIPHIER_PIN_DRV_FIXED_4, /* fixed to 4mA */
74 UNIPHIER_PIN_DRV_FIXED_5, /* fixed to 5mA */
75 UNIPHIER_PIN_DRV_FIXED_8, /* fixed to 8mA */
76 UNIPHIER_PIN_DRV_NONE, /* no support (input only pin) */
77};
78
79/* direction of pull register (no pin supports bi-directional pull biasing) */
80enum uniphier_pin_pull_dir {
81 UNIPHIER_PIN_PULL_UP, /* pull-up or disabled */
82 UNIPHIER_PIN_PULL_DOWN, /* pull-down or disabled */
83 UNIPHIER_PIN_PULL_UP_FIXED, /* always pull-up */
84 UNIPHIER_PIN_PULL_DOWN_FIXED, /* always pull-down */
85 UNIPHIER_PIN_PULL_NONE, /* no pull register */
86};
87
88#define UNIPHIER_PIN_IECTRL(x) \
89 (((x) & (UNIPHIER_PIN_IECTRL_MASK)) << (UNIPHIER_PIN_IECTRL_SHIFT))
90#define UNIPHIER_PIN_DRVCTRL(x) \
91 (((x) & (UNIPHIER_PIN_DRVCTRL_MASK)) << (UNIPHIER_PIN_DRVCTRL_SHIFT))
92#define UNIPHIER_PIN_DRV_STR(x) \
93 (((x) & (UNIPHIER_PIN_DRV_STR_MASK)) << (UNIPHIER_PIN_DRV_STR_SHIFT))
94#define UNIPHIER_PIN_PUPDCTRL(x) \
95 (((x) & (UNIPHIER_PIN_PUPDCTRL_MASK)) << (UNIPHIER_PIN_PUPDCTRL_SHIFT))
96#define UNIPHIER_PIN_PULL_DIR(x) \
97 (((x) & (UNIPHIER_PIN_PULL_DIR_MASK)) << (UNIPHIER_PIN_PULL_DIR_SHIFT))
98
99#define UNIPHIER_PIN_ATTR_PACKED(iectrl, drvctrl, drv_str, pupdctrl, pull_dir)\
100 (UNIPHIER_PIN_IECTRL(iectrl) | \
101 UNIPHIER_PIN_DRVCTRL(drvctrl) | \
102 UNIPHIER_PIN_DRV_STR(drv_str) | \
103 UNIPHIER_PIN_PUPDCTRL(pupdctrl) | \
104 UNIPHIER_PIN_PULL_DIR(pull_dir))
105
106static inline unsigned int uniphier_pin_get_iectrl(void *drv_data)
107{
108 return ((unsigned long)drv_data >> UNIPHIER_PIN_IECTRL_SHIFT) &
109 UNIPHIER_PIN_IECTRL_MASK;
110}
111
112static inline unsigned int uniphier_pin_get_drvctrl(void *drv_data)
113{
114 return ((unsigned long)drv_data >> UNIPHIER_PIN_DRVCTRL_SHIFT) &
115 UNIPHIER_PIN_DRVCTRL_MASK;
116}
117
118static inline unsigned int uniphier_pin_get_drv_str(void *drv_data)
119{
120 return ((unsigned long)drv_data >> UNIPHIER_PIN_DRV_STR_SHIFT) &
121 UNIPHIER_PIN_DRV_STR_MASK;
122}
123
124static inline unsigned int uniphier_pin_get_pupdctrl(void *drv_data)
125{
126 return ((unsigned long)drv_data >> UNIPHIER_PIN_PUPDCTRL_SHIFT) &
127 UNIPHIER_PIN_PUPDCTRL_MASK;
128}
129
130static inline unsigned int uniphier_pin_get_pull_dir(void *drv_data)
131{
132 return ((unsigned long)drv_data >> UNIPHIER_PIN_PULL_DIR_SHIFT) &
133 UNIPHIER_PIN_PULL_DIR_MASK;
134}
135
136enum uniphier_pinmux_gpio_range_type {
137 UNIPHIER_PINMUX_GPIO_RANGE_PORT,
138 UNIPHIER_PINMUX_GPIO_RANGE_IRQ,
139 UNIPHIER_PINMUX_GPIO_RANGE_NONE,
140};
141
142struct uniphier_pinctrl_group {
143 const char *name;
144 const unsigned *pins;
145 unsigned num_pins;
146 const unsigned *muxvals;
147 enum uniphier_pinmux_gpio_range_type range_type;
148};
149
150struct uniphier_pinmux_function {
151 const char *name;
152 const char * const *groups;
153 unsigned num_groups;
154};
155
156struct uniphier_pinctrl_socdata {
157 const struct uniphier_pinctrl_group *groups;
158 int groups_count;
159 const struct uniphier_pinmux_function *functions;
160 int functions_count;
161 unsigned mux_bits;
162 unsigned reg_stride;
163 bool load_pinctrl;
164};
165
166#define UNIPHIER_PINCTRL_PIN(a, b, c, d, e, f, g) \
167{ \
168 .number = a, \
169 .name = b, \
170 .drv_data = (void *)UNIPHIER_PIN_ATTR_PACKED(c, d, e, f, g), \
171}
172
173#define __UNIPHIER_PINCTRL_GROUP(grp, type) \
174 { \
175 .name = #grp, \
176 .pins = grp##_pins, \
177 .num_pins = ARRAY_SIZE(grp##_pins), \
178 .muxvals = grp##_muxvals + \
179 BUILD_BUG_ON_ZERO(ARRAY_SIZE(grp##_pins) != \
180 ARRAY_SIZE(grp##_muxvals)), \
181 .range_type = type, \
182 }
183
184#define UNIPHIER_PINCTRL_GROUP(grp) \
185 __UNIPHIER_PINCTRL_GROUP(grp, UNIPHIER_PINMUX_GPIO_RANGE_NONE)
186
187#define UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(grp) \
188 __UNIPHIER_PINCTRL_GROUP(grp, UNIPHIER_PINMUX_GPIO_RANGE_PORT)
189
190#define UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(grp) \
191 __UNIPHIER_PINCTRL_GROUP(grp, UNIPHIER_PINMUX_GPIO_RANGE_IRQ)
192
193#define UNIPHIER_PINCTRL_GROUP_SINGLE(grp, array, ofst) \
194 { \
195 .name = #grp, \
196 .pins = array##_pins + ofst, \
197 .num_pins = 1, \
198 .muxvals = array##_muxvals + ofst, \
199 }
200
201#define UNIPHIER_PINMUX_FUNCTION(func) \
202 { \
203 .name = #func, \
204 .groups = func##_groups, \
205 .num_groups = ARRAY_SIZE(func##_groups), \
206 }
207
208struct platform_device;
209struct pinctrl_desc;
210
211int uniphier_pinctrl_probe(struct platform_device *pdev,
212 struct pinctrl_desc *desc,
213 struct uniphier_pinctrl_socdata *socdata);
214
215int uniphier_pinctrl_remove(struct platform_device *pdev);
216
217#endif /* __PINCTRL_UNIPHIER_H__ */
diff --git a/include/dt-bindings/pinctrl/qcom,pmic-mpp.h b/include/dt-bindings/pinctrl/qcom,pmic-mpp.h
index c10205491f8d..a15c1704d0ec 100644
--- a/include/dt-bindings/pinctrl/qcom,pmic-mpp.h
+++ b/include/dt-bindings/pinctrl/qcom,pmic-mpp.h
@@ -7,6 +7,47 @@
7#define _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H 7#define _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H
8 8
9/* power-source */ 9/* power-source */
10
11/* Digital Input/Output: level [PM8058] */
12#define PM8058_MPP_VPH 0
13#define PM8058_MPP_S3 1
14#define PM8058_MPP_L2 2
15#define PM8058_MPP_L3 3
16
17/* Digital Input/Output: level [PM8901] */
18#define PM8901_MPP_MSMIO 0
19#define PM8901_MPP_DIG 1
20#define PM8901_MPP_L5 2
21#define PM8901_MPP_S4 3
22#define PM8901_MPP_VPH 4
23
24/* Digital Input/Output: level [PM8921] */
25#define PM8921_MPP_S4 1
26#define PM8921_MPP_L15 3
27#define PM8921_MPP_L17 4
28#define PM8921_MPP_VPH 7
29
30/* Digital Input/Output: level [PM8821] */
31#define PM8821_MPP_1P8 0
32#define PM8821_MPP_VPH 7
33
34/* Digital Input/Output: level [PM8018] */
35#define PM8018_MPP_L4 0
36#define PM8018_MPP_L14 1
37#define PM8018_MPP_S3 2
38#define PM8018_MPP_L6 3
39#define PM8018_MPP_L2 4
40#define PM8018_MPP_L5 5
41#define PM8018_MPP_VPH 7
42
43/* Digital Input/Output: level [PM8038] */
44#define PM8038_MPP_L20 0
45#define PM8038_MPP_L11 1
46#define PM8038_MPP_L5 2
47#define PM8038_MPP_L15 3
48#define PM8038_MPP_L17 4
49#define PM8038_MPP_VPH 7
50
10#define PM8841_MPP_VPH 0 51#define PM8841_MPP_VPH 0
11#define PM8841_MPP_S3 2 52#define PM8841_MPP_S3 2
12 53
@@ -37,6 +78,16 @@
37#define PMIC_MPP_AMUX_ROUTE_ABUS3 6 78#define PMIC_MPP_AMUX_ROUTE_ABUS3 6
38#define PMIC_MPP_AMUX_ROUTE_ABUS4 7 79#define PMIC_MPP_AMUX_ROUTE_ABUS4 7
39 80
81/* Analog Output: level */
82#define PMIC_MPP_AOUT_LVL_1V25 0
83#define PMIC_MPP_AOUT_LVL_1V25_2 1
84#define PMIC_MPP_AOUT_LVL_0V625 2
85#define PMIC_MPP_AOUT_LVL_0V3125 3
86#define PMIC_MPP_AOUT_LVL_MPP 4
87#define PMIC_MPP_AOUT_LVL_ABUS1 5
88#define PMIC_MPP_AOUT_LVL_ABUS2 6
89#define PMIC_MPP_AOUT_LVL_ABUS3 7
90
40/* To be used with "function" */ 91/* To be used with "function" */
41#define PMIC_MPP_FUNC_NORMAL "normal" 92#define PMIC_MPP_FUNC_NORMAL "normal"
42#define PMIC_MPP_FUNC_PAIRED "paired" 93#define PMIC_MPP_FUNC_PAIRED "paired"
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-19 12:11:22 -0500