Merge tag 'imx-drm-next-2015-10-30' of git://git.pengutronix.de/git/pza/linux into drm-next

imx-drm fixes and color format updates

- Some correctness fixes found by coccinelle
- Add drivers/gpu/ipu-v3 directory to MAINTAINERS
- Add support for more color formats
- Fix a regression, making displays larger than FullHD work again

* tag 'imx-drm-next-2015-10-30' of git://git.pengutronix.de/git/pza/linux:
  drm/imx: hdmi: fix HDMI setup to allow modes larger than FullHD
  gpu: ipu-v3: fix div_ratio type
  gpu: ipu-v3: csi: add support for 8 bpp grayscale sensors.
  drm/imx: enable ARGB4444 16-bit color format
  gpu: ipu-v3: add support for ARGB4444 16-bit color format
  drm/imx: ipuv3-plane: enable support for RGBX8888 and RGBA8888 pixel formats
  gpu: ipu-v3: add support for RGBX8888 and RGBA8888 pixel formats
  drm/imx: enable 15-bit RGB with 1-bit alpha formats
  gpu: ipu-v3: add support for 15-bit RGB with 1-bit alpha formats
  MAINTAINERS: Add IPUv3 core driver to the i.MX DRM driver section
  gpu: ipu-v3: ipu-csi: bool test doesn't need a comparison to false

3 files changed, 91 insertions, 6 deletions

diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
index e5a38d202a21..ba47b30d28fa 100644
--- a/drivers/gpu/ipu-v3/ipu-common.c
+++ b/drivers/gpu/ipu-v3/ipu-common.c
@@ -57,10 +57,15 @@ EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update);
 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc)
 {
         switch (drm_fourcc) {
+        case DRM_FORMAT_ARGB1555:
+        case DRM_FORMAT_ABGR1555:
+        case DRM_FORMAT_RGBA5551:
+        case DRM_FORMAT_BGRA5551:
         case DRM_FORMAT_RGB565:
         case DRM_FORMAT_BGR565:
         case DRM_FORMAT_RGB888:
         case DRM_FORMAT_BGR888:
+        case DRM_FORMAT_ARGB4444:
         case DRM_FORMAT_XRGB8888:
         case DRM_FORMAT_XBGR8888:
         case DRM_FORMAT_RGBX8888:
diff --git a/drivers/gpu/ipu-v3/ipu-cpmem.c b/drivers/gpu/ipu-v3/ipu-cpmem.c
index 3bf05bc4ab67..63eb16bf2cf0 100644
--- a/drivers/gpu/ipu-v3/ipu-cpmem.c
+++ b/drivers/gpu/ipu-v3/ipu-cpmem.c
@@ -452,7 +452,7 @@ void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch,
 }
 EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar);
 
-static const struct ipu_rgb def_rgb_32 = {
+static const struct ipu_rgb def_xrgb_32 = {
         .red    = { .offset = 16, .length = 8, },
         .green  = { .offset =  8, .length = 8, },
         .blue   = { .offset =  0, .length = 8, },
@@ -460,7 +460,7 @@ static const struct ipu_rgb def_rgb_32 = {
         .bits_per_pixel = 32,
 };
 
-static const struct ipu_rgb def_bgr_32 = {
+static const struct ipu_rgb def_xbgr_32 = {
         .red    = { .offset =  0, .length = 8, },
         .green  = { .offset =  8, .length = 8, },
         .blue   = { .offset = 16, .length = 8, },
@@ -468,6 +468,22 @@ static const struct ipu_rgb def_bgr_32 = {
         .bits_per_pixel = 32,
 };
 
+static const struct ipu_rgb def_rgbx_32 = {
+        .red    = { .offset = 24, .length = 8, },
+        .green  = { .offset = 16, .length = 8, },
+        .blue   = { .offset =  8, .length = 8, },
+        .transp = { .offset =  0, .length = 8, },
+        .bits_per_pixel = 32,
+};
+
+static const struct ipu_rgb def_bgrx_32 = {
+        .red    = { .offset =  8, .length = 8, },
+        .green  = { .offset = 16, .length = 8, },
+        .blue   = { .offset = 24, .length = 8, },
+        .transp = { .offset =  0, .length = 8, },
+        .bits_per_pixel = 32,
+};
+
 static const struct ipu_rgb def_rgb_24 = {
         .red    = { .offset = 16, .length = 8, },
         .green  = { .offset =  8, .length = 8, },
@@ -500,6 +516,46 @@ static const struct ipu_rgb def_bgr_16 = {
         .bits_per_pixel = 16,
 };
 
+static const struct ipu_rgb def_argb_16 = {
+        .red    = { .offset = 10, .length = 5, },
+        .green  = { .offset =  5, .length = 5, },
+        .blue   = { .offset =  0, .length = 5, },
+        .transp = { .offset = 15, .length = 1, },
+        .bits_per_pixel = 16,
+};
+
+static const struct ipu_rgb def_argb_16_4444 = {
+        .red    = { .offset =  8, .length = 4, },
+        .green  = { .offset =  4, .length = 4, },
+        .blue   = { .offset =  0, .length = 4, },
+        .transp = { .offset = 12, .length = 4, },
+        .bits_per_pixel = 16,
+};
+
+static const struct ipu_rgb def_abgr_16 = {
+        .red    = { .offset =  0, .length = 5, },
+        .green  = { .offset =  5, .length = 5, },
+        .blue   = { .offset = 10, .length = 5, },
+        .transp = { .offset = 15, .length = 1, },
+        .bits_per_pixel = 16,
+};
+
+static const struct ipu_rgb def_rgba_16 = {
+        .red    = { .offset = 11, .length = 5, },
+        .green  = { .offset =  6, .length = 5, },
+        .blue   = { .offset =  1, .length = 5, },
+        .transp = { .offset =  0, .length = 1, },
+        .bits_per_pixel = 16,
+};
+
+static const struct ipu_rgb def_bgra_16 = {
+        .red    = { .offset =  1, .length = 5, },
+        .green  = { .offset =  6, .length = 5, },
+        .blue   = { .offset = 11, .length = 5, },
+        .transp = { .offset =  0, .length = 1, },
+        .bits_per_pixel = 16,
+};
+
 #define Y_OFFSET(pix, x, y)     ((x) + pix->width * (y))
 #define U_OFFSET(pix, x, y)     ((pix->width * pix->height) +           \
                                  (pix->width * (y) / 4) + (x) / 2)
@@ -563,11 +619,19 @@ int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc)
                 break;
         case DRM_FORMAT_ABGR8888:
         case DRM_FORMAT_XBGR8888:
-                ipu_cpmem_set_format_rgb(ch, &def_bgr_32);
+                ipu_cpmem_set_format_rgb(ch, &def_xbgr_32);
                 break;
         case DRM_FORMAT_ARGB8888:
         case DRM_FORMAT_XRGB8888:
-                ipu_cpmem_set_format_rgb(ch, &def_rgb_32);
+                ipu_cpmem_set_format_rgb(ch, &def_xrgb_32);
+                break;
+        case DRM_FORMAT_RGBA8888:
+        case DRM_FORMAT_RGBX8888:
+                ipu_cpmem_set_format_rgb(ch, &def_rgbx_32);
+                break;
+        case DRM_FORMAT_BGRA8888:
+        case DRM_FORMAT_BGRX8888:
+                ipu_cpmem_set_format_rgb(ch, &def_bgrx_32);
                 break;
         case DRM_FORMAT_BGR888:
                 ipu_cpmem_set_format_rgb(ch, &def_bgr_24);
@@ -581,6 +645,21 @@ int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc)
         case DRM_FORMAT_BGR565:
                 ipu_cpmem_set_format_rgb(ch, &def_bgr_16);
                 break;
+        case DRM_FORMAT_ARGB1555:
+                ipu_cpmem_set_format_rgb(ch, &def_argb_16);
+                break;
+        case DRM_FORMAT_ABGR1555:
+                ipu_cpmem_set_format_rgb(ch, &def_abgr_16);
+                break;
+        case DRM_FORMAT_RGBA5551:
+                ipu_cpmem_set_format_rgb(ch, &def_rgba_16);
+                break;
+        case DRM_FORMAT_BGRA5551:
+                ipu_cpmem_set_format_rgb(ch, &def_bgra_16);
+                break;
+        case DRM_FORMAT_ARGB4444:
+                ipu_cpmem_set_format_rgb(ch, &def_argb_16_4444);
+                break;
         default:
                 return -EINVAL;
         }
diff --git a/drivers/gpu/ipu-v3/ipu-csi.c b/drivers/gpu/ipu-v3/ipu-csi.c
index 752cdd2da89a..06631ac61b04 100644
--- a/drivers/gpu/ipu-v3/ipu-csi.c
+++ b/drivers/gpu/ipu-v3/ipu-csi.c
@@ -202,7 +202,7 @@ static int ipu_csi_set_testgen_mclk(struct ipu_csi *csi, u32 pixel_clk,
                                         u32 ipu_clk)
 {
         u32 temp;
-        u32 div_ratio;
+        int div_ratio;
 
         div_ratio = (ipu_clk / pixel_clk) - 1;
 
@@ -271,6 +271,7 @@ static int mbus_code_to_bus_cfg(struct ipu_csi_bus_config *cfg, u32 mbus_code)
         case MEDIA_BUS_FMT_SGBRG8_1X8:
         case MEDIA_BUS_FMT_SGRBG8_1X8:
         case MEDIA_BUS_FMT_SRGGB8_1X8:
+        case MEDIA_BUS_FMT_Y8_1X8:
                 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
                 cfg->mipi_dt = MIPI_DT_RAW8;
                 cfg->data_width = IPU_CSI_DATA_WIDTH_8;