Merge tag 'clk-for-linus-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Michael Turquette:
 "The bulk of the changes are updates and fixes to existing clk provider
  drivers, along with a pretty standard number of new drivers.  The core
  recieved a small number of updates as well.

  Core changes of note:
   - removed CLK_IS_ROOT flag

  New clk provider drivers:
   - Renesas r8a7796 clock pulse generator / module standby and
     software reset
   - Allwinner sun8i H3 clock controller unit
   - AmLogic meson8b clock controller (rewritten)
   - AmLogic gxbb clock controller
   - support for some new ICs was added by simple changes to static
     data tables for chips sharing the same family

  Driver updates of note:
   - the Allwinner sunxi clock driver infrastucture was rewritten to
     comform to the state of the art at drivers/clk/sunxi-ng.  The old
     implementation is still supported for backwards compatibility with
     the DT ABI"

* tag 'clk-for-linus-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (162 commits)
  clk: Makefile: re-sort and clean up
  Revert "clk: gxbb: expose CLKID_MMC_PCLK"
  clk: samsung: Allow modular build of the Audio Subsystem CLKCON driver
  clk: samsung: make clk-s5pv210-audss explicitly non-modular
  clk: exynos5433: remove CLK_IGNORE_UNUSED flag from SPI clocks
  clk: oxnas: Add hardware dependencies
  clk: imx7d: do not set parent of ethernet time/ref clocks
  ARM: dt: sun8i: switch the H3 to the new CCU driver
  clk: sunxi-ng: h3: Fix Kconfig symbol typo
  clk: sunxi-ng: h3: Fix audio clock divider offset
  clk: sunxi-ng: Add H3 clocks
  clk: sunxi-ng: Add N-K-M-P factor clock
  clk: sunxi-ng: Add N-K-M Factor clock
  clk: sunxi-ng: Add N-M-factor clock support
  clk: sunxi-ng: Add N-K-factor clock support
  clk: sunxi-ng: Add M-P factor clock support
  clk: sunxi-ng: Add divider
  clk: sunxi-ng: Add phase clock support
  clk: sunxi-ng: Add mux clock support
  clk: sunxi-ng: Add gate clock support
  ...

1 files changed, 126 insertions, 0 deletions

diff --git a/drivers/clk/sunxi-ng/ccu_phase.c b/drivers/clk/sunxi-ng/ccu_phase.c
new file mode 100644
index 000000000000..400c58ad72fd
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu_phase.c
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2016 Maxime Ripard
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/spinlock.h>
+
+#include "ccu_phase.h"
+
+static int ccu_phase_get_phase(struct clk_hw *hw)
+{
+        struct ccu_phase *phase = hw_to_ccu_phase(hw);
+        struct clk_hw *parent, *grandparent;
+        unsigned int parent_rate, grandparent_rate;
+        u16 step, parent_div;
+        u32 reg;
+        u8 delay;
+
+        reg = readl(phase->common.base + phase->common.reg);
+        delay = (reg >> phase->shift);
+        delay &= (1 << phase->width) - 1;
+
+        if (!delay)
+                return 180;
+
+        /* Get our parent clock, it's the one that can adjust its rate */
+        parent = clk_hw_get_parent(hw);
+        if (!parent)
+                return -EINVAL;
+
+        /* And its rate */
+        parent_rate = clk_hw_get_rate(parent);
+        if (!parent_rate)
+                return -EINVAL;
+
+        /* Now, get our parent's parent (most likely some PLL) */
+        grandparent = clk_hw_get_parent(parent);
+        if (!grandparent)
+                return -EINVAL;
+
+        /* And its rate */
+        grandparent_rate = clk_hw_get_rate(grandparent);
+        if (!grandparent_rate)
+                return -EINVAL;
+
+        /* Get our parent clock divider */
+        parent_div = grandparent_rate / parent_rate;
+
+        step = DIV_ROUND_CLOSEST(360, parent_div);
+        return delay * step;
+}
+
+static int ccu_phase_set_phase(struct clk_hw *hw, int degrees)
+{
+        struct ccu_phase *phase = hw_to_ccu_phase(hw);
+        struct clk_hw *parent, *grandparent;
+        unsigned int parent_rate, grandparent_rate;
+        unsigned long flags;
+        u32 reg;
+        u8 delay;
+
+        /* Get our parent clock, it's the one that can adjust its rate */
+        parent = clk_hw_get_parent(hw);
+        if (!parent)
+                return -EINVAL;
+
+        /* And its rate */
+        parent_rate = clk_hw_get_rate(parent);
+        if (!parent_rate)
+                return -EINVAL;
+
+        /* Now, get our parent's parent (most likely some PLL) */
+        grandparent = clk_hw_get_parent(parent);
+        if (!grandparent)
+                return -EINVAL;
+
+        /* And its rate */
+        grandparent_rate = clk_hw_get_rate(grandparent);
+        if (!grandparent_rate)
+                return -EINVAL;
+
+        if (degrees != 180) {
+                u16 step, parent_div;
+
+                /* Get our parent divider */
+                parent_div = grandparent_rate / parent_rate;
+
+                /*
+                 * We can only outphase the clocks by multiple of the
+                 * PLL's period.
+                 *
+                 * Since our parent clock is only a divider, and the
+                 * formula to get the outphasing in degrees is deg =
+                 * 360 * delta / period
+                 *
+                 * If we simplify this formula, we can see that the
+                 * only thing that we're concerned about is the number
+                 * of period we want to outphase our clock from, and
+                 * the divider set by our parent clock.
+                 */
+                step = DIV_ROUND_CLOSEST(360, parent_div);
+                delay = DIV_ROUND_CLOSEST(degrees, step);
+        } else {
+                delay = 0;
+        }
+
+        spin_lock_irqsave(phase->common.lock, flags);
+        reg = readl(phase->common.base + phase->common.reg);
+        reg &= ~GENMASK(phase->width + phase->shift - 1, phase->shift);
+        writel(reg | (delay << phase->shift),
+               phase->common.base + phase->common.reg);
+        spin_unlock_irqrestore(phase->common.lock, flags);
+
+        return 0;
+}
+
+const struct clk_ops ccu_phase_ops = {
+        .get_phase      = ccu_phase_get_phase,
+        .set_phase      = ccu_phase_set_phase,
+};