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authorAlessio Igor Bogani <alessio.bogani@elettra.eu>2016-03-04 05:09:11 -0500
committerScott Wood <oss@buserror.net>2016-03-11 20:19:13 -0500
commit334479d1ccc2dd8f3b4a66a8aa8ff72ef93e4b67 (patch)
tree6c34a99aebd454604f5eb4a31363e55214a42483 /arch/powerpc/boot/dts/fsl
parent595207b93fe43e651548dcb3e6f0ec64e21205fd (diff)
powerpc/86xx: Introduce and use common dtsi
Signed-off-by: Alessio Igor Bogani <alessio.bogani@elettra.eu> Signed-off-by: Scott Wood <oss@buserror.net>
Diffstat (limited to 'arch/powerpc/boot/dts/fsl')
-rw-r--r--arch/powerpc/boot/dts/fsl/gef_ppc9a.dts258
-rw-r--r--arch/powerpc/boot/dts/fsl/gef_sbc310.dts246
-rw-r--r--arch/powerpc/boot/dts/fsl/gef_sbc610.dts258
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8641_hpcn.dts300
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8641_hpcn_36b.dts298
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8641si-post.dtsi120
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8641si-pre.dtsi58
-rw-r--r--arch/powerpc/boot/dts/fsl/sbc8641d.dts299
8 files changed, 394 insertions, 1443 deletions
diff --git a/arch/powerpc/boot/dts/fsl/gef_ppc9a.dts b/arch/powerpc/boot/dts/fsl/gef_ppc9a.dts
index 7e4487bae31c..0424fc2bd0e0 100644
--- a/arch/powerpc/boot/dts/fsl/gef_ppc9a.dts
+++ b/arch/powerpc/boot/dts/fsl/gef_ppc9a.dts
@@ -18,62 +18,19 @@
18 * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts 18 * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
19 */ 19 */
20 20
21/dts-v1/; 21/include/ "mpc8641si-pre.dtsi"
22 22
23/ { 23/ {
24 model = "GEF_PPC9A"; 24 model = "GEF_PPC9A";
25 compatible = "gef,ppc9a"; 25 compatible = "gef,ppc9a";
26 #address-cells = <1>;
27 #size-cells = <1>;
28 interrupt-parent = <&mpic>;
29
30 aliases {
31 ethernet0 = &enet0;
32 ethernet1 = &enet1;
33 serial0 = &serial0;
34 serial1 = &serial1;
35 pci0 = &pci0;
36 };
37
38 cpus {
39 #address-cells = <1>;
40 #size-cells = <0>;
41
42 PowerPC,8641@0 {
43 device_type = "cpu";
44 reg = <0>;
45 d-cache-line-size = <32>; // 32 bytes
46 i-cache-line-size = <32>; // 32 bytes
47 d-cache-size = <32768>; // L1, 32K
48 i-cache-size = <32768>; // L1, 32K
49 timebase-frequency = <0>; // From uboot
50 bus-frequency = <0>; // From uboot
51 clock-frequency = <0>; // From uboot
52 };
53 PowerPC,8641@1 {
54 device_type = "cpu";
55 reg = <1>;
56 d-cache-line-size = <32>; // 32 bytes
57 i-cache-line-size = <32>; // 32 bytes
58 d-cache-size = <32768>; // L1, 32K
59 i-cache-size = <32768>; // L1, 32K
60 timebase-frequency = <0>; // From uboot
61 bus-frequency = <0>; // From uboot
62 clock-frequency = <0>; // From uboot
63 };
64 };
65 26
66 memory { 27 memory {
67 device_type = "memory"; 28 device_type = "memory";
68 reg = <0x0 0x40000000>; // set by uboot 29 reg = <0x0 0x40000000>; // set by uboot
69 }; 30 };
70 31
71 localbus@fef05000 { 32 lbc: localbus@fef05000 {
72 #address-cells = <2>;
73 #size-cells = <1>;
74 compatible = "fsl,mpc8641-localbus", "simple-bus";
75 reg = <0xfef05000 0x1000>; 33 reg = <0xfef05000 0x1000>;
76 interrupts = <19 2 0 0>;
77 34
78 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash 35 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
79 1 0 0xe8000000 0x08000000 // Paged Flash 0 36 1 0 0xe8000000 0x08000000 // Paged Flash 0
@@ -161,34 +118,10 @@
161 }; 118 };
162 }; 119 };
163 120
164 soc@fef00000 { 121 soc: soc@fef00000 {
165 #address-cells = <1>;
166 #size-cells = <1>;
167 device_type = "soc";
168 compatible = "fsl,mpc8641-soc", "simple-bus";
169 ranges = <0x0 0xfef00000 0x00100000>; 122 ranges = <0x0 0xfef00000 0x00100000>;
170 bus-frequency = <33333333>;
171
172 mcm-law@0 {
173 compatible = "fsl,mcm-law";
174 reg = <0x0 0x1000>;
175 fsl,num-laws = <10>;
176 };
177
178 mcm@1000 {
179 compatible = "fsl,mpc8641-mcm", "fsl,mcm";
180 reg = <0x1000 0x1000>;
181 interrupts = <17 2 0 0>;
182 };
183 123
184 i2c@3000 { 124 i2c@3000 {
185 #address-cells = <1>;
186 #size-cells = <0>;
187 compatible = "fsl-i2c";
188 reg = <0x3000 0x100>;
189 interrupts = <0x2b 0x2 0 0>;
190 dfsrr;
191
192 hwmon@48 { 125 hwmon@48 {
193 compatible = "national,lm92"; 126 compatible = "national,lm92";
194 reg = <0x48>; 127 reg = <0x48>;
@@ -210,192 +143,65 @@
210 }; 143 };
211 }; 144 };
212 145
213 i2c@3100 {
214 #address-cells = <1>;
215 #size-cells = <0>;
216 compatible = "fsl-i2c";
217 reg = <0x3100 0x100>;
218 interrupts = <0x2b 0x2 0 0>;
219 dfsrr;
220 };
221
222 dma@21300 {
223 #address-cells = <1>;
224 #size-cells = <1>;
225 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
226 reg = <0x21300 0x4>;
227 ranges = <0x0 0x21100 0x200>;
228 cell-index = <0>;
229 dma-channel@0 {
230 compatible = "fsl,mpc8641-dma-channel",
231 "fsl,eloplus-dma-channel";
232 reg = <0x0 0x80>;
233 cell-index = <0>;
234 interrupts = <20 2 0 0>;
235 };
236 dma-channel@80 {
237 compatible = "fsl,mpc8641-dma-channel",
238 "fsl,eloplus-dma-channel";
239 reg = <0x80 0x80>;
240 cell-index = <1>;
241 interrupts = <21 2 0 0>;
242 };
243 dma-channel@100 {
244 compatible = "fsl,mpc8641-dma-channel",
245 "fsl,eloplus-dma-channel";
246 reg = <0x100 0x80>;
247 cell-index = <2>;
248 interrupts = <22 2 0 0>;
249 };
250 dma-channel@180 {
251 compatible = "fsl,mpc8641-dma-channel",
252 "fsl,eloplus-dma-channel";
253 reg = <0x180 0x80>;
254 cell-index = <3>;
255 interrupts = <23 2 0 0>;
256 };
257 };
258
259 enet0: ethernet@24000 { 146 enet0: ethernet@24000 {
260 #address-cells = <1>;
261 #size-cells = <1>;
262 cell-index = <0>;
263 device_type = "network";
264 model = "TSEC";
265 compatible = "gianfar";
266 reg = <0x24000 0x1000>;
267 ranges = <0x0 0x24000 0x1000>;
268 local-mac-address = [ 00 00 00 00 00 00 ];
269 interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
270 tbi-handle = <&tbi0>; 147 tbi-handle = <&tbi0>;
271 phy-handle = <&phy0>; 148 phy-handle = <&phy0>;
272 phy-connection-type = "gmii"; 149 phy-connection-type = "gmii";
150 };
273 151
274 mdio@520 { 152 mdio@24520 {
275 #address-cells = <1>; 153 phy0: ethernet-phy@0 {
276 #size-cells = <0>; 154 interrupt-parent = <&gef_pic>;
277 compatible = "fsl,gianfar-mdio"; 155 interrupts = <0x9 0x4>;
278 reg = <0x520 0x20>; 156 reg = <1>;
279 157 };
280 phy0: ethernet-phy@0 { 158 phy2: ethernet-phy@2 {
281 interrupt-parent = <&gef_pic>; 159 interrupt-parent = <&gef_pic>;
282 interrupts = <0x9 0x4>; 160 interrupts = <0x8 0x4>;
283 reg = <1>; 161 reg = <3>;
284 }; 162 };
285 phy2: ethernet-phy@2 { 163 tbi0: tbi-phy@11 {
286 interrupt-parent = <&gef_pic>; 164 reg = <0x11>;
287 interrupts = <0x8 0x4>; 165 device_type = "tbi-phy";
288 reg = <3>;
289 };
290 tbi0: tbi-phy@11 {
291 reg = <0x11>;
292 device_type = "tbi-phy";
293 };
294 }; 166 };
295 }; 167 };
296 168
297 enet1: ethernet@26000 { 169 enet1: ethernet@26000 {
298 #address-cells = <1>;
299 #size-cells = <1>;
300 cell-index = <2>;
301 device_type = "network";
302 model = "TSEC";
303 compatible = "gianfar";
304 reg = <0x26000 0x1000>;
305 ranges = <0x0 0x26000 0x1000>;
306 local-mac-address = [ 00 00 00 00 00 00 ];
307 interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
308 tbi-handle = <&tbi2>; 170 tbi-handle = <&tbi2>;
309 phy-handle = <&phy2>; 171 phy-handle = <&phy2>;
310 phy-connection-type = "gmii"; 172 phy-connection-type = "gmii";
311
312 mdio@520 {
313 #address-cells = <1>;
314 #size-cells = <0>;
315 compatible = "fsl,gianfar-tbi";
316 reg = <0x520 0x20>;
317
318 tbi2: tbi-phy@11 {
319 reg = <0x11>;
320 device_type = "tbi-phy";
321 };
322 };
323 }; 173 };
324 174
325 serial0: serial@4500 { 175 mdio@26520 {
326 cell-index = <0>; 176 tbi2: tbi-phy@11 {
327 device_type = "serial"; 177 reg = <0x11>;
328 compatible = "fsl,ns16550", "ns16550"; 178 device_type = "tbi-phy";
329 reg = <0x4500 0x100>; 179 };
330 clock-frequency = <0>;
331 interrupts = <0x2a 0x2 0 0>;
332 }; 180 };
333 181
334 serial1: serial@4600 { 182 enet2: ethernet@25000 {
335 cell-index = <1>; 183 status = "disabled";
336 device_type = "serial";
337 compatible = "fsl,ns16550", "ns16550";
338 reg = <0x4600 0x100>;
339 clock-frequency = <0>;
340 interrupts = <0x1c 0x2 0 0>;
341 }; 184 };
342 185
343 mpic: pic@40000 { 186 mdio@25520 {
344 clock-frequency = <0>; 187 status = "disabled";
345 interrupt-controller;
346 #address-cells = <0>;
347 #interrupt-cells = <4>;
348 reg = <0x40000 0x40000>;
349 compatible = "fsl,mpic", "chrp,open-pic";
350 device_type = "open-pic";
351 }; 188 };
352 189
353 msi@41600 { 190 enet3: ethernet@27000 {
354 compatible = "fsl,mpc8641-msi", "fsl,mpic-msi"; 191 status = "disabled";
355 reg = <0x41600 0x80>;
356 msi-available-ranges = <0 0x100>;
357 interrupts = <
358 0xe0 0 0 0
359 0xe1 0 0 0
360 0xe2 0 0 0
361 0xe3 0 0 0
362 0xe4 0 0 0
363 0xe5 0 0 0
364 0xe6 0 0 0
365 0xe7 0 0 0>;
366 }; 192 };
367 193
368 global-utilities@e0000 { 194 mdio@27520 {
369 compatible = "fsl,mpc8641-guts"; 195 status = "disabled";
370 reg = <0xe0000 0x1000>;
371 fsl,has-rstcr;
372 }; 196 };
373 }; 197 };
374 198
375 pci0: pcie@fef08000 { 199 pci0: pcie@fef08000 {
376 compatible = "fsl,mpc8641-pcie";
377 device_type = "pci";
378 #size-cells = <2>;
379 #address-cells = <3>;
380 reg = <0xfef08000 0x1000>; 200 reg = <0xfef08000 0x1000>;
381 bus-range = <0x0 0xff>;
382 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000 201 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
383 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>; 202 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
384 clock-frequency = <100000000>;
385 interrupts = <0x18 0x2 0 0>;
386 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
387 interrupt-map = <
388 0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
389 0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
390 0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
391 0x0000 0x0 0x0 0x4 &mpic 0x3 0x1
392 >;
393 203
394 pcie@0 { 204 pcie@0 {
395 reg = <0 0 0 0 0>;
396 #size-cells = <2>;
397 #address-cells = <3>;
398 device_type = "pci";
399 ranges = <0x02000000 0x0 0x80000000 205 ranges = <0x02000000 0x0 0x80000000
400 0x02000000 0x0 0x80000000 206 0x02000000 0x0 0x80000000
401 0x0 0x40000000 207 0x0 0x40000000
@@ -406,3 +212,5 @@
406 }; 212 };
407 }; 213 };
408}; 214};
215
216/include/ "mpc8641si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/gef_sbc310.dts b/arch/powerpc/boot/dts/fsl/gef_sbc310.dts
index 1299011c308b..84b3d38f880e 100644
--- a/arch/powerpc/boot/dts/fsl/gef_sbc310.dts
+++ b/arch/powerpc/boot/dts/fsl/gef_sbc310.dts
@@ -18,63 +18,23 @@
18 * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts 18 * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
19 */ 19 */
20 20
21/dts-v1/; 21/include/ "mpc8641si-pre.dtsi"
22 22
23/ { 23/ {
24 model = "GEF_SBC310"; 24 model = "GEF_SBC310";
25 compatible = "gef,sbc310"; 25 compatible = "gef,sbc310";
26 #address-cells = <1>;
27 #size-cells = <1>;
28 interrupt-parent = <&mpic>;
29 26
30 aliases { 27 aliases {
31 ethernet0 = &enet0;
32 ethernet1 = &enet1;
33 serial0 = &serial0;
34 serial1 = &serial1;
35 pci0 = &pci0;
36 pci1 = &pci1; 28 pci1 = &pci1;
37 }; 29 };
38 30
39 cpus {
40 #address-cells = <1>;
41 #size-cells = <0>;
42
43 PowerPC,8641@0 {
44 device_type = "cpu";
45 reg = <0>;
46 d-cache-line-size = <32>; // 32 bytes
47 i-cache-line-size = <32>; // 32 bytes
48 d-cache-size = <32768>; // L1, 32K
49 i-cache-size = <32768>; // L1, 32K
50 timebase-frequency = <0>; // From uboot
51 bus-frequency = <0>; // From uboot
52 clock-frequency = <0>; // From uboot
53 };
54 PowerPC,8641@1 {
55 device_type = "cpu";
56 reg = <1>;
57 d-cache-line-size = <32>; // 32 bytes
58 i-cache-line-size = <32>; // 32 bytes
59 d-cache-size = <32768>; // L1, 32K
60 i-cache-size = <32768>; // L1, 32K
61 timebase-frequency = <0>; // From uboot
62 bus-frequency = <0>; // From uboot
63 clock-frequency = <0>; // From uboot
64 };
65 };
66
67 memory { 31 memory {
68 device_type = "memory"; 32 device_type = "memory";
69 reg = <0x0 0x40000000>; // set by uboot 33 reg = <0x0 0x40000000>; // set by uboot
70 }; 34 };
71 35
72 localbus@fef05000 { 36 lbc: localbus@fef05000 {
73 #address-cells = <2>;
74 #size-cells = <1>;
75 compatible = "fsl,mpc8641-localbus", "simple-bus";
76 reg = <0xfef05000 0x1000>; 37 reg = <0xfef05000 0x1000>;
77 interrupts = <19 2 0 0>;
78 38
79 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash 39 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
80 1 0 0xe0000000 0x08000000 // Paged Flash 0 40 1 0 0xe0000000 0x08000000 // Paged Flash 0
@@ -159,34 +119,10 @@
159 }; 119 };
160 }; 120 };
161 121
162 soc@fef00000 { 122 soc: soc@fef00000 {
163 #address-cells = <1>;
164 #size-cells = <1>;
165 device_type = "soc";
166 compatible = "fsl,mpc8641-soc", "simple-bus";
167 ranges = <0x0 0xfef00000 0x00100000>; 123 ranges = <0x0 0xfef00000 0x00100000>;
168 bus-frequency = <33333333>;
169
170 mcm-law@0 {
171 compatible = "fsl,mcm-law";
172 reg = <0x0 0x1000>;
173 fsl,num-laws = <10>;
174 };
175
176 mcm@1000 {
177 compatible = "fsl,mpc8641-mcm", "fsl,mcm";
178 reg = <0x1000 0x1000>;
179 interrupts = <17 2 0 0>;
180 };
181 124
182 i2c@3000 { 125 i2c@3000 {
183 #address-cells = <1>;
184 #size-cells = <0>;
185 compatible = "fsl-i2c";
186 reg = <0x3000 0x100>;
187 interrupts = <0x2b 0x2 0 0>;
188 dfsrr;
189
190 rtc@51 { 126 rtc@51 {
191 compatible = "epson,rx8581"; 127 compatible = "epson,rx8581";
192 reg = <0x00000051>; 128 reg = <0x00000051>;
@@ -194,13 +130,6 @@
194 }; 130 };
195 131
196 i2c@3100 { 132 i2c@3100 {
197 #address-cells = <1>;
198 #size-cells = <0>;
199 compatible = "fsl-i2c";
200 reg = <0x3100 0x100>;
201 interrupts = <0x2b 0x2 0 0>;
202 dfsrr;
203
204 hwmon@48 { 133 hwmon@48 {
205 compatible = "national,lm92"; 134 compatible = "national,lm92";
206 reg = <0x48>; 135 reg = <0x48>;
@@ -217,170 +146,63 @@
217 }; 146 };
218 }; 147 };
219 148
220 dma@21300 {
221 #address-cells = <1>;
222 #size-cells = <1>;
223 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
224 reg = <0x21300 0x4>;
225 ranges = <0x0 0x21100 0x200>;
226 cell-index = <0>;
227 dma-channel@0 {
228 compatible = "fsl,mpc8641-dma-channel",
229 "fsl,eloplus-dma-channel";
230 reg = <0x0 0x80>;
231 cell-index = <0>;
232 interrupts = <20 2 0 0>;
233 };
234 dma-channel@80 {
235 compatible = "fsl,mpc8641-dma-channel",
236 "fsl,eloplus-dma-channel";
237 reg = <0x80 0x80>;
238 cell-index = <1>;
239 interrupts = <21 2 0 0>;
240 };
241 dma-channel@100 {
242 compatible = "fsl,mpc8641-dma-channel",
243 "fsl,eloplus-dma-channel";
244 reg = <0x100 0x80>;
245 cell-index = <2>;
246 interrupts = <22 2 0 0>;
247 };
248 dma-channel@180 {
249 compatible = "fsl,mpc8641-dma-channel",
250 "fsl,eloplus-dma-channel";
251 reg = <0x180 0x80>;
252 cell-index = <3>;
253 interrupts = <23 2 0 0>;
254 };
255 };
256
257 enet0: ethernet@24000 { 149 enet0: ethernet@24000 {
258 #address-cells = <1>;
259 #size-cells = <1>;
260 cell-index = <0>;
261 device_type = "network";
262 model = "TSEC";
263 compatible = "gianfar";
264 reg = <0x24000 0x1000>;
265 ranges = <0x0 0x24000 0x1000>;
266 local-mac-address = [ 00 00 00 00 00 00 ];
267 interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
268 tbi-handle = <&tbi0>; 150 tbi-handle = <&tbi0>;
269 phy-handle = <&phy0>; 151 phy-handle = <&phy0>;
270 phy-connection-type = "gmii"; 152 phy-connection-type = "gmii";
153 };
271 154
272 mdio@520 { 155 mdio@24520 {
273 #address-cells = <1>; 156 phy0: ethernet-phy@0 {
274 #size-cells = <0>; 157 interrupt-parent = <&gef_pic>;
275 compatible = "fsl,gianfar-mdio"; 158 interrupts = <0x9 0x4>;
276 reg = <0x520 0x20>; 159 reg = <1>;
277 160 };
278 phy0: ethernet-phy@0 { 161 phy2: ethernet-phy@2 {
279 interrupt-parent = <&gef_pic>; 162 interrupt-parent = <&gef_pic>;
280 interrupts = <0x9 0x4>; 163 interrupts = <0x8 0x4>;
281 reg = <1>; 164 reg = <3>;
282 }; 165 };
283 phy2: ethernet-phy@2 { 166 tbi0: tbi-phy@11 {
284 interrupt-parent = <&gef_pic>; 167 reg = <0x11>;
285 interrupts = <0x8 0x4>; 168 device_type = "tbi-phy";
286 reg = <3>;
287 };
288 tbi0: tbi-phy@11 {
289 reg = <0x11>;
290 device_type = "tbi-phy";
291 };
292 }; 169 };
293 }; 170 };
294 171
295 enet1: ethernet@26000 { 172 enet1: ethernet@26000 {
296 #address-cells = <1>;
297 #size-cells = <1>;
298 cell-index = <2>;
299 device_type = "network";
300 model = "TSEC";
301 compatible = "gianfar";
302 reg = <0x26000 0x1000>;
303 ranges = <0x0 0x26000 0x1000>;
304 local-mac-address = [ 00 00 00 00 00 00 ];
305 interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
306 tbi-handle = <&tbi2>; 173 tbi-handle = <&tbi2>;
307 phy-handle = <&phy2>; 174 phy-handle = <&phy2>;
308 phy-connection-type = "gmii"; 175 phy-connection-type = "gmii";
176 };
309 177
310 mdio@520 { 178 mdio@26520 {
311 #address-cells = <1>; 179 tbi2: tbi-phy@11 {
312 #size-cells = <0>; 180 reg = <0x11>;
313 compatible = "fsl,gianfar-tbi"; 181 device_type = "tbi-phy";
314 reg = <0x520 0x20>;
315
316 tbi2: tbi-phy@11 {
317 reg = <0x11>;
318 device_type = "tbi-phy";
319 };
320 }; 182 };
321 }; 183 };
322 184
323 serial0: serial@4500 { 185 enet2: ethernet@25000 {
324 cell-index = <0>; 186 status = "disabled";
325 device_type = "serial";
326 compatible = "fsl,ns16550", "ns16550";
327 reg = <0x4500 0x100>;
328 clock-frequency = <0>;
329 interrupts = <0x2a 0x2 0 0>;
330 }; 187 };
331 188
332 serial1: serial@4600 { 189 mdio@25520 {
333 cell-index = <1>; 190 status = "disabled";
334 device_type = "serial";
335 compatible = "fsl,ns16550", "ns16550";
336 reg = <0x4600 0x100>;
337 clock-frequency = <0>;
338 interrupts = <0x1c 0x2 0 0>;
339 }; 191 };
340 192
341 mpic: pic@40000 { 193 enet3: ethernet@27000 {
342 clock-frequency = <0>; 194 status = "disabled";
343 interrupt-controller;
344 #address-cells = <0>;
345 #interrupt-cells = <4>;
346 reg = <0x40000 0x40000>;
347 compatible = "fsl,mpic", "chrp,open-pic";
348 device_type = "open-pic";
349 }; 195 };
350 196
351 msi@41600 { 197 mdio@27520 {
352 compatible = "fsl,mpc8641-msi", "fsl,mpic-msi"; 198 status = "disabled";
353 reg = <0x41600 0x80>;
354 msi-available-ranges = <0 0x100>;
355 interrupts = <
356 0xe0 0 0 0
357 0xe1 0 0 0
358 0xe2 0 0 0
359 0xe3 0 0 0
360 0xe4 0 0 0
361 0xe5 0 0 0
362 0xe6 0 0 0
363 0xe7 0 0 0>;
364 };
365
366 global-utilities@e0000 {
367 compatible = "fsl,mpc8641-guts";
368 reg = <0xe0000 0x1000>;
369 fsl,has-rstcr;
370 }; 199 };
371 }; 200 };
372 201
373 pci0: pcie@fef08000 { 202 pci0: pcie@fef08000 {
374 compatible = "fsl,mpc8641-pcie";
375 device_type = "pci";
376 #size-cells = <2>;
377 #address-cells = <3>;
378 reg = <0xfef08000 0x1000>; 203 reg = <0xfef08000 0x1000>;
379 bus-range = <0x0 0xff>;
380 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000 204 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
381 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>; 205 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
382 clock-frequency = <100000000>;
383 interrupts = <0x18 0x2 0 0>;
384 interrupt-map-mask = <0xff00 0x0 0x0 0x7>; 206 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
385 interrupt-map = < 207 interrupt-map = <
386 0x0000 0x0 0x0 0x1 &mpic 0x0 0x2 208 0x0000 0x0 0x0 0x1 &mpic 0x0 0x2
@@ -390,10 +212,6 @@
390 >; 212 >;
391 213
392 pcie@0 { 214 pcie@0 {
393 reg = <0 0 0 0 0>;
394 #size-cells = <2>;
395 #address-cells = <3>;
396 device_type = "pci";
397 ranges = <0x02000000 0x0 0x80000000 215 ranges = <0x02000000 0x0 0x80000000
398 0x02000000 0x0 0x80000000 216 0x02000000 0x0 0x80000000
399 0x0 0x40000000 217 0x0 0x40000000
@@ -438,3 +256,5 @@
438 }; 256 };
439 }; 257 };
440}; 258};
259
260/include/ "mpc8641si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/gef_sbc610.dts b/arch/powerpc/boot/dts/fsl/gef_sbc610.dts
index 3a1f438f7e4d..974446acce23 100644
--- a/arch/powerpc/boot/dts/fsl/gef_sbc610.dts
+++ b/arch/powerpc/boot/dts/fsl/gef_sbc610.dts
@@ -18,62 +18,19 @@
18 * Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts 18 * Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts
19 */ 19 */
20 20
21/dts-v1/; 21/include/ "mpc8641si-pre.dtsi"
22 22
23/ { 23/ {
24 model = "GEF_SBC610"; 24 model = "GEF_SBC610";
25 compatible = "gef,sbc610"; 25 compatible = "gef,sbc610";
26 #address-cells = <1>;
27 #size-cells = <1>;
28 interrupt-parent = <&mpic>;
29
30 aliases {
31 ethernet0 = &enet0;
32 ethernet1 = &enet1;
33 serial0 = &serial0;
34 serial1 = &serial1;
35 pci0 = &pci0;
36 };
37
38 cpus {
39 #address-cells = <1>;
40 #size-cells = <0>;
41
42 PowerPC,8641@0 {
43 device_type = "cpu";
44 reg = <0>;
45 d-cache-line-size = <32>; // 32 bytes
46 i-cache-line-size = <32>; // 32 bytes
47 d-cache-size = <32768>; // L1, 32K
48 i-cache-size = <32768>; // L1, 32K
49 timebase-frequency = <0>; // From uboot
50 bus-frequency = <0>; // From uboot
51 clock-frequency = <0>; // From uboot
52 };
53 PowerPC,8641@1 {
54 device_type = "cpu";
55 reg = <1>;
56 d-cache-line-size = <32>; // 32 bytes
57 i-cache-line-size = <32>; // 32 bytes
58 d-cache-size = <32768>; // L1, 32K
59 i-cache-size = <32768>; // L1, 32K
60 timebase-frequency = <0>; // From uboot
61 bus-frequency = <0>; // From uboot
62 clock-frequency = <0>; // From uboot
63 };
64 };
65 26
66 memory { 27 memory {
67 device_type = "memory"; 28 device_type = "memory";
68 reg = <0x0 0x40000000>; // set by uboot 29 reg = <0x0 0x40000000>; // set by uboot
69 }; 30 };
70 31
71 localbus@fef05000 { 32 lbc: localbus@fef05000 {
72 #address-cells = <2>;
73 #size-cells = <1>;
74 compatible = "fsl,mpc8641-localbus", "simple-bus";
75 reg = <0xfef05000 0x1000>; 33 reg = <0xfef05000 0x1000>;
76 interrupts = <19 2 0 0>;
77 34
78 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash 35 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
79 1 0 0xe8000000 0x08000000 // Paged Flash 0 36 1 0 0xe8000000 0x08000000 // Paged Flash 0
@@ -159,34 +116,10 @@
159 }; 116 };
160 }; 117 };
161 118
162 soc@fef00000 { 119 soc: soc@fef00000 {
163 #address-cells = <1>;
164 #size-cells = <1>;
165 device_type = "soc";
166 compatible = "simple-bus";
167 ranges = <0x0 0xfef00000 0x00100000>; 120 ranges = <0x0 0xfef00000 0x00100000>;
168 bus-frequency = <33333333>;
169
170 mcm-law@0 {
171 compatible = "fsl,mcm-law";
172 reg = <0x0 0x1000>;
173 fsl,num-laws = <10>;
174 };
175
176 mcm@1000 {
177 compatible = "fsl,mpc8641-mcm", "fsl,mcm";
178 reg = <0x1000 0x1000>;
179 interrupts = <17 2 0 0>;
180 };
181 121
182 i2c@3000 { 122 i2c@3000 {
183 #address-cells = <1>;
184 #size-cells = <0>;
185 compatible = "fsl-i2c";
186 reg = <0x3000 0x100>;
187 interrupts = <0x2b 0x2 0 0>;
188 dfsrr;
189
190 hwmon@48 { 123 hwmon@48 {
191 compatible = "national,lm92"; 124 compatible = "national,lm92";
192 reg = <0x48>; 125 reg = <0x48>;
@@ -208,192 +141,65 @@
208 }; 141 };
209 }; 142 };
210 143
211 i2c@3100 {
212 #address-cells = <1>;
213 #size-cells = <0>;
214 compatible = "fsl-i2c";
215 reg = <0x3100 0x100>;
216 interrupts = <0x2b 0x2 0 0>;
217 dfsrr;
218 };
219
220 dma@21300 {
221 #address-cells = <1>;
222 #size-cells = <1>;
223 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
224 reg = <0x21300 0x4>;
225 ranges = <0x0 0x21100 0x200>;
226 cell-index = <0>;
227 dma-channel@0 {
228 compatible = "fsl,mpc8641-dma-channel",
229 "fsl,eloplus-dma-channel";
230 reg = <0x0 0x80>;
231 cell-index = <0>;
232 interrupts = <20 2 0 0>;
233 };
234 dma-channel@80 {
235 compatible = "fsl,mpc8641-dma-channel",
236 "fsl,eloplus-dma-channel";
237 reg = <0x80 0x80>;
238 cell-index = <1>;
239 interrupts = <21 2 0 0>;
240 };
241 dma-channel@100 {
242 compatible = "fsl,mpc8641-dma-channel",
243 "fsl,eloplus-dma-channel";
244 reg = <0x100 0x80>;
245 cell-index = <2>;
246 interrupts = <22 2 0 0>;
247 };
248 dma-channel@180 {
249 compatible = "fsl,mpc8641-dma-channel",
250 "fsl,eloplus-dma-channel";
251 reg = <0x180 0x80>;
252 cell-index = <3>;
253 interrupts = <23 2 0 0>;
254 };
255 };
256
257 enet0: ethernet@24000 { 144 enet0: ethernet@24000 {
258 #address-cells = <1>;
259 #size-cells = <1>;
260 cell-index = <0>;
261 device_type = "network";
262 model = "TSEC";
263 compatible = "gianfar";
264 reg = <0x24000 0x1000>;
265 ranges = <0x0 0x24000 0x1000>;
266 local-mac-address = [ 00 00 00 00 00 00 ];
267 interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
268 tbi-handle = <&tbi0>; 145 tbi-handle = <&tbi0>;
269 phy-handle = <&phy0>; 146 phy-handle = <&phy0>;
270 phy-connection-type = "gmii"; 147 phy-connection-type = "gmii";
148 };
271 149
272 mdio@520 { 150 mdio@24520 {
273 #address-cells = <1>; 151 phy0: ethernet-phy@0 {
274 #size-cells = <0>; 152 interrupt-parent = <&gef_pic>;
275 compatible = "fsl,gianfar-mdio"; 153 interrupts = <0x9 0x4>;
276 reg = <0x520 0x20>; 154 reg = <1>;
277 155 };
278 phy0: ethernet-phy@0 { 156 phy2: ethernet-phy@2 {
279 interrupt-parent = <&gef_pic>; 157 interrupt-parent = <&gef_pic>;
280 interrupts = <0x9 0x4>; 158 interrupts = <0x8 0x4>;
281 reg = <1>; 159 reg = <3>;
282 }; 160 };
283 phy2: ethernet-phy@2 { 161 tbi0: tbi-phy@11 {
284 interrupt-parent = <&gef_pic>; 162 reg = <0x11>;
285 interrupts = <0x8 0x4>; 163 device_type = "tbi-phy";
286 reg = <3>;
287 };
288 tbi0: tbi-phy@11 {
289 reg = <0x11>;
290 device_type = "tbi-phy";
291 };
292 }; 164 };
293 }; 165 };
294 166
295 enet1: ethernet@26000 { 167 enet1: ethernet@26000 {
296 #address-cells = <1>;
297 #size-cells = <1>;
298 cell-index = <2>;
299 device_type = "network";
300 model = "TSEC";
301 compatible = "gianfar";
302 reg = <0x26000 0x1000>;
303 ranges = <0x0 0x26000 0x1000>;
304 local-mac-address = [ 00 00 00 00 00 00 ];
305 interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
306 tbi-handle = <&tbi2>; 168 tbi-handle = <&tbi2>;
307 phy-handle = <&phy2>; 169 phy-handle = <&phy2>;
308 phy-connection-type = "gmii"; 170 phy-connection-type = "gmii";
309
310 mdio@520 {
311 #address-cells = <1>;
312 #size-cells = <0>;
313 compatible = "fsl,gianfar-tbi";
314 reg = <0x520 0x20>;
315
316 tbi2: tbi-phy@11 {
317 reg = <0x11>;
318 device_type = "tbi-phy";
319 };
320 };
321 }; 171 };
322 172
323 serial0: serial@4500 { 173 mdio@26520 {
324 cell-index = <0>; 174 tbi2: tbi-phy@11 {
325 device_type = "serial"; 175 reg = <0x11>;
326 compatible = "fsl,ns16550", "ns16550"; 176 device_type = "tbi-phy";
327 reg = <0x4500 0x100>; 177 };
328 clock-frequency = <0>;
329 interrupts = <0x2a 0x2 0 0>;
330 }; 178 };
331 179
332 serial1: serial@4600 { 180 enet2: ethernet@25000 {
333 cell-index = <1>; 181 status = "disabled";
334 device_type = "serial";
335 compatible = "fsl,ns16550", "ns16550";
336 reg = <0x4600 0x100>;
337 clock-frequency = <0>;
338 interrupts = <0x1c 0x2 0 0>;
339 }; 182 };
340 183
341 mpic: pic@40000 { 184 mdio@25520 {
342 clock-frequency = <0>; 185 status = "disabled";
343 interrupt-controller;
344 #address-cells = <0>;
345 #interrupt-cells = <4>;
346 reg = <0x40000 0x40000>;
347 compatible = "fsl,mpic", "chrp,open-pic";
348 device_type = "open-pic";
349 }; 186 };
350 187
351 msi@41600 { 188 enet3: ethernet@27000 {
352 compatible = "fsl,mpc8641-msi", "fsl,mpic-msi"; 189 status = "disabled";
353 reg = <0x41600 0x80>;
354 msi-available-ranges = <0 0x100>;
355 interrupts = <
356 0xe0 0 0 0
357 0xe1 0 0 0
358 0xe2 0 0 0
359 0xe3 0 0 0
360 0xe4 0 0 0
361 0xe5 0 0 0
362 0xe6 0 0 0
363 0xe7 0 0 0>;
364 }; 190 };
365 191
366 global-utilities@e0000 { 192 mdio@27520 {
367 compatible = "fsl,mpc8641-guts"; 193 status = "disabled";
368 reg = <0xe0000 0x1000>;
369 fsl,has-rstcr;
370 }; 194 };
371 }; 195 };
372 196
373 pci0: pcie@fef08000 { 197 pci0: pcie@fef08000 {
374 compatible = "fsl,mpc8641-pcie";
375 device_type = "pci";
376 #size-cells = <2>;
377 #address-cells = <3>;
378 reg = <0xfef08000 0x1000>; 198 reg = <0xfef08000 0x1000>;
379 bus-range = <0x0 0xff>;
380 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000 199 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
381 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>; 200 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
382 clock-frequency = <100000000>;
383 interrupts = <0x18 0x2 0 0>;
384 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
385 interrupt-map = <
386 0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
387 0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
388 0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
389 0x0000 0x0 0x0 0x4 &mpic 0x3 0x1
390 >;
391 201
392 pcie@0 { 202 pcie@0 {
393 reg = <0 0 0 0 0>;
394 #size-cells = <2>;
395 #address-cells = <3>;
396 device_type = "pci";
397 ranges = <0x02000000 0x0 0x80000000 203 ranges = <0x02000000 0x0 0x80000000
398 0x02000000 0x0 0x80000000 204 0x02000000 0x0 0x80000000
399 0x0 0x40000000 205 0x0 0x40000000
@@ -404,3 +210,5 @@
404 }; 210 };
405 }; 211 };
406}; 212};
213
214/include/ "mpc8641si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/fsl/mpc8641_hpcn.dts
index 03ef3f72e100..554001f2e96a 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8641_hpcn.dts
+++ b/arch/powerpc/boot/dts/fsl/mpc8641_hpcn.dts
@@ -9,65 +9,23 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "mpc8641si-pre.dtsi"
13 13
14/ { 14/ {
15 model = "MPC8641HPCN"; 15 model = "MPC8641HPCN";
16 compatible = "fsl,mpc8641hpcn"; 16 compatible = "fsl,mpc8641hpcn";
17 #address-cells = <1>;
18 #size-cells = <1>;
19 interrupt-parent = <&mpic>;
20 17
21 aliases { 18 aliases {
22 ethernet0 = &enet0;
23 ethernet1 = &enet1;
24 ethernet2 = &enet2;
25 ethernet3 = &enet3;
26 serial0 = &serial0;
27 serial1 = &serial1;
28 pci0 = &pci0;
29 pci1 = &pci1; 19 pci1 = &pci1;
30 }; 20 };
31 21
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 PowerPC,8641@0 {
37 device_type = "cpu";
38 reg = <0>;
39 d-cache-line-size = <32>;
40 i-cache-line-size = <32>;
41 d-cache-size = <32768>; // L1
42 i-cache-size = <32768>; // L1
43 timebase-frequency = <0>; // From uboot
44 bus-frequency = <0>; // From uboot
45 clock-frequency = <0>; // From uboot
46 };
47 PowerPC,8641@1 {
48 device_type = "cpu";
49 reg = <1>;
50 d-cache-line-size = <32>;
51 i-cache-line-size = <32>;
52 d-cache-size = <32768>;
53 i-cache-size = <32768>;
54 timebase-frequency = <0>; // From uboot
55 bus-frequency = <0>; // From uboot
56 clock-frequency = <0>; // From uboot
57 };
58 };
59
60 memory { 22 memory {
61 device_type = "memory"; 23 device_type = "memory";
62 reg = <0x00000000 0x40000000>; // 1G at 0x0 24 reg = <0x00000000 0x40000000>; // 1G at 0x0
63 }; 25 };
64 26
65 localbus@ffe05000 { 27 lbc: localbus@ffe05000 {
66 #address-cells = <2>;
67 #size-cells = <1>;
68 compatible = "fsl,mpc8641-localbus", "simple-bus";
69 reg = <0xffe05000 0x1000>; 28 reg = <0xffe05000 0x1000>;
70 interrupts = <19 2 0 0>;
71 29
72 ranges = <0 0 0xef800000 0x00800000 30 ranges = <0 0 0xef800000 0x00800000
73 2 0 0xffdf8000 0x00008000 31 2 0 0xffdf8000 0x00008000
@@ -101,236 +59,75 @@
101 }; 59 };
102 }; 60 };
103 61
104 soc8641@ffe00000 { 62 soc: soc8641@ffe00000 {
105 #address-cells = <1>;
106 #size-cells = <1>;
107 device_type = "soc";
108 compatible = "simple-bus";
109 ranges = <0x00000000 0xffe00000 0x00100000>; 63 ranges = <0x00000000 0xffe00000 0x00100000>;
110 bus-frequency = <0>;
111
112 mcm-law@0 {
113 compatible = "fsl,mcm-law";
114 reg = <0x0 0x1000>;
115 fsl,num-laws = <10>;
116 };
117
118 mcm@1000 {
119 compatible = "fsl,mpc8641-mcm", "fsl,mcm";
120 reg = <0x1000 0x1000>;
121 interrupts = <17 2 0 0>;
122 };
123 64
124 i2c@3000 { 65 enet0: ethernet@24000 {
125 #address-cells = <1>; 66 tbi-handle = <&tbi0>;
126 #size-cells = <0>; 67 phy-handle = <&phy0>;
127 cell-index = <0>; 68 phy-connection-type = "rgmii-id";
128 compatible = "fsl-i2c";
129 reg = <0x3000 0x100>;
130 interrupts = <43 2 0 0>;
131 dfsrr;
132 };
133
134 i2c@3100 {
135 #address-cells = <1>;
136 #size-cells = <0>;
137 cell-index = <1>;
138 compatible = "fsl-i2c";
139 reg = <0x3100 0x100>;
140 interrupts = <43 2 0 0>;
141 dfsrr;
142 }; 69 };
143 70
144 dma@21300 { 71 mdio@24520 {
145 #address-cells = <1>; 72 phy0: ethernet-phy@0 {
146 #size-cells = <1>; 73 interrupts = <10 1 0 0>;
147 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma"; 74 reg = <0>;
148 reg = <0x21300 0x4>;
149 ranges = <0x0 0x21100 0x200>;
150 cell-index = <0>;
151 dma-channel@0 {
152 compatible = "fsl,mpc8641-dma-channel",
153 "fsl,eloplus-dma-channel";
154 reg = <0x0 0x80>;
155 cell-index = <0>;
156 interrupts = <20 2 0 0>;
157 }; 75 };
158 dma-channel@80 { 76 phy1: ethernet-phy@1 {
159 compatible = "fsl,mpc8641-dma-channel", 77 interrupts = <10 1 0 0>;
160 "fsl,eloplus-dma-channel"; 78 reg = <1>;
161 reg = <0x80 0x80>;
162 cell-index = <1>;
163 interrupts = <21 2 0 0>;
164 }; 79 };
165 dma-channel@100 { 80 phy2: ethernet-phy@2 {
166 compatible = "fsl,mpc8641-dma-channel", 81 interrupts = <10 1 0 0>;
167 "fsl,eloplus-dma-channel"; 82 reg = <2>;
168 reg = <0x100 0x80>;
169 cell-index = <2>;
170 interrupts = <22 2 0 0>;
171 }; 83 };
172 dma-channel@180 { 84 phy3: ethernet-phy@3 {
173 compatible = "fsl,mpc8641-dma-channel", 85 interrupts = <10 1 0 0>;
174 "fsl,eloplus-dma-channel"; 86 reg = <3>;
175 reg = <0x180 0x80>;
176 cell-index = <3>;
177 interrupts = <23 2 0 0>;
178 }; 87 };
179 }; 88 tbi0: tbi-phy@11 {
180 89 reg = <0x11>;
181 enet0: ethernet@24000 { 90 device_type = "tbi-phy";
182 #address-cells = <1>;
183 #size-cells = <1>;
184 cell-index = <0>;
185 device_type = "network";
186 model = "TSEC";
187 compatible = "gianfar";
188 reg = <0x24000 0x1000>;
189 ranges = <0x0 0x24000 0x1000>;
190 local-mac-address = [ 00 00 00 00 00 00 ];
191 interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
192 tbi-handle = <&tbi0>;
193 phy-handle = <&phy0>;
194 phy-connection-type = "rgmii-id";
195
196 mdio@520 {
197 #address-cells = <1>;
198 #size-cells = <0>;
199 compatible = "fsl,gianfar-mdio";
200 reg = <0x520 0x20>;
201
202 phy0: ethernet-phy@0 {
203 interrupts = <10 1 0 0>;
204 reg = <0>;
205 };
206 phy1: ethernet-phy@1 {
207 interrupts = <10 1 0 0>;
208 reg = <1>;
209 };
210 phy2: ethernet-phy@2 {
211 interrupts = <10 1 0 0>;
212 reg = <2>;
213 };
214 phy3: ethernet-phy@3 {
215 interrupts = <10 1 0 0>;
216 reg = <3>;
217 };
218 tbi0: tbi-phy@11 {
219 reg = <0x11>;
220 device_type = "tbi-phy";
221 };
222 }; 91 };
223 }; 92 };
224 93
225 enet1: ethernet@25000 { 94 enet1: ethernet@25000 {
226 #address-cells = <1>;
227 #size-cells = <1>;
228 cell-index = <1>;
229 device_type = "network";
230 model = "TSEC";
231 compatible = "gianfar";
232 reg = <0x25000 0x1000>;
233 ranges = <0x0 0x25000 0x1000>;
234 local-mac-address = [ 00 00 00 00 00 00 ];
235 interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
236 tbi-handle = <&tbi1>; 95 tbi-handle = <&tbi1>;
237 phy-handle = <&phy1>; 96 phy-handle = <&phy1>;
238 phy-connection-type = "rgmii-id"; 97 phy-connection-type = "rgmii-id";
98 };
239 99
240 mdio@520 { 100 mdio@25520 {
241 #address-cells = <1>; 101 tbi1: tbi-phy@11 {
242 #size-cells = <0>; 102 reg = <0x11>;
243 compatible = "fsl,gianfar-tbi"; 103 device_type = "tbi-phy";
244 reg = <0x520 0x20>;
245
246 tbi1: tbi-phy@11 {
247 reg = <0x11>;
248 device_type = "tbi-phy";
249 };
250 }; 104 };
251 }; 105 };
252 106
253 enet2: ethernet@26000 { 107 enet2: ethernet@26000 {
254 #address-cells = <1>;
255 #size-cells = <1>;
256 cell-index = <2>;
257 device_type = "network";
258 model = "TSEC";
259 compatible = "gianfar";
260 reg = <0x26000 0x1000>;
261 ranges = <0x0 0x26000 0x1000>;
262 local-mac-address = [ 00 00 00 00 00 00 ];
263 interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
264 tbi-handle = <&tbi2>; 108 tbi-handle = <&tbi2>;
265 phy-handle = <&phy2>; 109 phy-handle = <&phy2>;
266 phy-connection-type = "rgmii-id"; 110 phy-connection-type = "rgmii-id";
111 };
267 112
268 mdio@520 { 113 mdio@26520 {
269 #address-cells = <1>; 114 tbi2: tbi-phy@11 {
270 #size-cells = <0>; 115 reg = <0x11>;
271 compatible = "fsl,gianfar-tbi"; 116 device_type = "tbi-phy";
272 reg = <0x520 0x20>;
273
274 tbi2: tbi-phy@11 {
275 reg = <0x11>;
276 device_type = "tbi-phy";
277 };
278 }; 117 };
279 }; 118 };
280 119
281 enet3: ethernet@27000 { 120 enet3: ethernet@27000 {
282 #address-cells = <1>;
283 #size-cells = <1>;
284 cell-index = <3>;
285 device_type = "network";
286 model = "TSEC";
287 compatible = "gianfar";
288 reg = <0x27000 0x1000>;
289 ranges = <0x0 0x27000 0x1000>;
290 local-mac-address = [ 00 00 00 00 00 00 ];
291 interrupts = <37 2 0 0 38 2 0 0 39 2 0 0>;
292 tbi-handle = <&tbi3>; 121 tbi-handle = <&tbi3>;
293 phy-handle = <&phy3>; 122 phy-handle = <&phy3>;
294 phy-connection-type = "rgmii-id"; 123 phy-connection-type = "rgmii-id";
295
296 mdio@520 {
297 #address-cells = <1>;
298 #size-cells = <0>;
299 compatible = "fsl,gianfar-tbi";
300 reg = <0x520 0x20>;
301
302 tbi3: tbi-phy@11 {
303 reg = <0x11>;
304 device_type = "tbi-phy";
305 };
306 };
307 }; 124 };
308 125
309 serial0: serial@4500 { 126 mdio@27520 {
310 cell-index = <0>; 127 tbi3: tbi-phy@11 {
311 device_type = "serial"; 128 reg = <0x11>;
312 compatible = "fsl,ns16550", "ns16550"; 129 device_type = "tbi-phy";
313 reg = <0x4500 0x100>; 130 };
314 clock-frequency = <0>;
315 interrupts = <42 2 0 0>;
316 };
317
318 serial1: serial@4600 {
319 cell-index = <1>;
320 device_type = "serial";
321 compatible = "fsl,ns16550", "ns16550";
322 reg = <0x4600 0x100>;
323 clock-frequency = <0>;
324 interrupts = <28 2 0 0>;
325 };
326
327 mpic: pic@40000 {
328 interrupt-controller;
329 #address-cells = <0>;
330 #interrupt-cells = <4>;
331 reg = <0x40000 0x40000>;
332 compatible = "fsl,mpic", "chrp,open-pic";
333 device_type = "open-pic";
334 }; 131 };
335 132
336 rmu: rmu@d3000 { 133 rmu: rmu@d3000 {
@@ -358,7 +155,7 @@
358 compatible = "fsl,srio-dbell-unit"; 155 compatible = "fsl,srio-dbell-unit";
359 reg = <0x400 0x80>; 156 reg = <0x400 0x80>;
360 interrupts = < 157 interrupts = <
361 49 2 0 0 /* bell_outb_irq */ 158 49 2 0 0 /* bell_outb_irq */
362 50 2 0 0>;/* bell_inb_irq */ 159 50 2 0 0>;/* bell_inb_irq */
363 }; 160 };
364 port-write-unit@4e0 { 161 port-write-unit@4e0 {
@@ -367,25 +164,12 @@
367 interrupts = <48 2 0 0>; 164 interrupts = <48 2 0 0>;
368 }; 165 };
369 }; 166 };
370
371 global-utilities@e0000 {
372 compatible = "fsl,mpc8641-guts";
373 reg = <0xe0000 0x1000>;
374 fsl,has-rstcr;
375 };
376 }; 167 };
377 168
378 pci0: pcie@ffe08000 { 169 pci0: pcie@ffe08000 {
379 compatible = "fsl,mpc8641-pcie";
380 device_type = "pci";
381 #size-cells = <2>;
382 #address-cells = <3>;
383 reg = <0xffe08000 0x1000>; 170 reg = <0xffe08000 0x1000>;
384 bus-range = <0x0 0xff>;
385 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000 171 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
386 0x01000000 0x0 0x00000000 0xffc00000 0x0 0x00010000>; 172 0x01000000 0x0 0x00000000 0xffc00000 0x0 0x00010000>;
387 clock-frequency = <100000000>;
388 interrupts = <24 2 0 0>;
389 interrupt-map-mask = <0xff00 0 0 7>; 173 interrupt-map-mask = <0xff00 0 0 7>;
390 interrupt-map = < 174 interrupt-map = <
391 /* IDSEL 0x11 func 0 - PCI slot 1 */ 175 /* IDSEL 0x11 func 0 - PCI slot 1 */
@@ -503,10 +287,6 @@
503 >; 287 >;
504 288
505 pcie@0 { 289 pcie@0 {
506 reg = <0 0 0 0 0>;
507 #size-cells = <2>;
508 #address-cells = <3>;
509 device_type = "pci";
510 ranges = <0x02000000 0x0 0x80000000 290 ranges = <0x02000000 0x0 0x80000000
511 0x02000000 0x0 0x80000000 291 0x02000000 0x0 0x80000000
512 0x0 0x20000000 292 0x0 0x20000000
@@ -636,3 +416,5 @@
636*/ 416*/
637 417
638}; 418};
419
420/include/ "mpc8641si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/mpc8641_hpcn_36b.dts b/arch/powerpc/boot/dts/fsl/mpc8641_hpcn_36b.dts
index 0a2c21f4af67..fec58671a6d6 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8641_hpcn_36b.dts
+++ b/arch/powerpc/boot/dts/fsl/mpc8641_hpcn_36b.dts
@@ -9,65 +9,25 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "mpc8641si-pre.dtsi"
13 13
14/ { 14/ {
15 model = "MPC8641HPCN"; 15 model = "MPC8641HPCN";
16 compatible = "fsl,mpc8641hpcn"; 16 compatible = "fsl,mpc8641hpcn";
17 #address-cells = <2>; 17 #address-cells = <2>;
18 #size-cells = <2>; 18 #size-cells = <2>;
19 interrupt-parent = <&mpic>;
20 19
21 aliases { 20 aliases {
22 ethernet0 = &enet0;
23 ethernet1 = &enet1;
24 ethernet2 = &enet2;
25 ethernet3 = &enet3;
26 serial0 = &serial0;
27 serial1 = &serial1;
28 pci0 = &pci0;
29 pci1 = &pci1; 21 pci1 = &pci1;
30 }; 22 };
31 23
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 PowerPC,8641@0 {
37 device_type = "cpu";
38 reg = <0>;
39 d-cache-line-size = <32>; // 32 bytes
40 i-cache-line-size = <32>; // 32 bytes
41 d-cache-size = <32768>; // L1, 32K
42 i-cache-size = <32768>; // L1, 32K
43 timebase-frequency = <0>; // 33 MHz, from uboot
44 bus-frequency = <0>; // From uboot
45 clock-frequency = <0>; // From uboot
46 };
47 PowerPC,8641@1 {
48 device_type = "cpu";
49 reg = <1>;
50 d-cache-line-size = <32>; // 32 bytes
51 i-cache-line-size = <32>; // 32 bytes
52 d-cache-size = <32768>; // L1, 32K
53 i-cache-size = <32768>; // L1, 32K
54 timebase-frequency = <0>; // 33 MHz, from uboot
55 bus-frequency = <0>; // From uboot
56 clock-frequency = <0>; // From uboot
57 };
58 };
59
60 memory { 24 memory {
61 device_type = "memory"; 25 device_type = "memory";
62 reg = <0x0 0x00000000 0x0 0x40000000>; // 1G at 0x0 26 reg = <0x0 0x00000000 0x0 0x40000000>; // 1G at 0x0
63 }; 27 };
64 28
65 localbus@fffe05000 { 29 lbc: localbus@fffe05000 {
66 #address-cells = <2>;
67 #size-cells = <1>;
68 compatible = "fsl,mpc8641-localbus", "simple-bus";
69 reg = <0x0f 0xffe05000 0x0 0x1000>; 30 reg = <0x0f 0xffe05000 0x0 0x1000>;
70 interrupts = <19 2 0 0>;
71 31
72 ranges = <0 0 0xf 0xef800000 0x00800000 32 ranges = <0 0 0xf 0xef800000 0x00800000
73 2 0 0xf 0xffdf8000 0x00008000 33 2 0 0xf 0xffdf8000 0x00008000
@@ -101,257 +61,82 @@
101 }; 61 };
102 }; 62 };
103 63
104 soc8641@fffe00000 { 64 soc: soc8641@fffe00000 {
105 #address-cells = <1>;
106 #size-cells = <1>;
107 device_type = "soc";
108 compatible = "simple-bus";
109 ranges = <0x00000000 0x0f 0xffe00000 0x00100000>; 65 ranges = <0x00000000 0x0f 0xffe00000 0x00100000>;
110 bus-frequency = <0>;
111 66
112 mcm-law@0 { 67 enet0: ethernet@24000 {
113 compatible = "fsl,mcm-law"; 68 tbi-handle = <&tbi0>;
114 reg = <0x0 0x1000>; 69 phy-handle = <&phy0>;
115 fsl,num-laws = <10>; 70 phy-connection-type = "rgmii-id";
116 };
117
118 mcm@1000 {
119 compatible = "fsl,mpc8641-mcm", "fsl,mcm";
120 reg = <0x1000 0x1000>;
121 interrupts = <17 2 0 0>;
122 };
123
124 i2c@3000 {
125 #address-cells = <1>;
126 #size-cells = <0>;
127 cell-index = <0>;
128 compatible = "fsl-i2c";
129 reg = <0x3000 0x100>;
130 interrupts = <43 2 0 0>;
131 dfsrr;
132 };
133
134 i2c@3100 {
135 #address-cells = <1>;
136 #size-cells = <0>;
137 cell-index = <1>;
138 compatible = "fsl-i2c";
139 reg = <0x3100 0x100>;
140 interrupts = <43 2 0 0>;
141 dfsrr;
142 }; 71 };
143 72
144 dma@21300 { 73 mdio@24520 {
145 #address-cells = <1>; 74 phy0: ethernet-phy@0 {
146 #size-cells = <1>; 75 interrupts = <10 1 0 0>;
147 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma"; 76 reg = <0>;
148 reg = <0x21300 0x4>;
149 ranges = <0x0 0x21100 0x200>;
150 cell-index = <0>;
151 dma-channel@0 {
152 compatible = "fsl,mpc8641-dma-channel",
153 "fsl,eloplus-dma-channel";
154 reg = <0x0 0x80>;
155 cell-index = <0>;
156 interrupts = <20 2 0 0>;
157 }; 77 };
158 dma-channel@80 { 78 phy1: ethernet-phy@1 {
159 compatible = "fsl,mpc8641-dma-channel", 79 interrupts = <10 1 0 0>;
160 "fsl,eloplus-dma-channel"; 80 reg = <1>;
161 reg = <0x80 0x80>;
162 cell-index = <1>;
163 interrupts = <21 2 0 0>;
164 }; 81 };
165 dma-channel@100 { 82 phy2: ethernet-phy@2 {
166 compatible = "fsl,mpc8641-dma-channel", 83 interrupts = <10 1 0 0>;
167 "fsl,eloplus-dma-channel"; 84 reg = <2>;
168 reg = <0x100 0x80>;
169 cell-index = <2>;
170 interrupts = <22 2 0 0>;
171 }; 85 };
172 dma-channel@180 { 86 phy3: ethernet-phy@3 {
173 compatible = "fsl,mpc8641-dma-channel", 87 interrupts = <10 1 0 0>;
174 "fsl,eloplus-dma-channel"; 88 reg = <3>;
175 reg = <0x180 0x80>;
176 cell-index = <3>;
177 interrupts = <23 2 0 0>;
178 }; 89 };
179 }; 90 tbi0: tbi-phy@11 {
180 91 reg = <0x11>;
181 enet0: ethernet@24000 { 92 device_type = "tbi-phy";
182 #address-cells = <1>;
183 #size-cells = <1>;
184 cell-index = <0>;
185 device_type = "network";
186 model = "TSEC";
187 compatible = "gianfar";
188 reg = <0x24000 0x1000>;
189 ranges = <0x0 0x24000 0x1000>;
190 local-mac-address = [ 00 00 00 00 00 00 ];
191 interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
192 tbi-handle = <&tbi0>;
193 phy-handle = <&phy0>;
194 phy-connection-type = "rgmii-id";
195
196 mdio@520 {
197 #address-cells = <1>;
198 #size-cells = <0>;
199 compatible = "fsl,gianfar-mdio";
200 reg = <0x520 0x20>;
201
202 phy0: ethernet-phy@0 {
203 interrupts = <10 1 0 0>;
204 reg = <0>;
205 };
206 phy1: ethernet-phy@1 {
207 interrupts = <10 1 0 0>;
208 reg = <1>;
209 };
210 phy2: ethernet-phy@2 {
211 interrupts = <10 1 0 0>;
212 reg = <2>;
213 };
214 phy3: ethernet-phy@3 {
215 interrupts = <10 1 0 0>;
216 reg = <3>;
217 };
218 tbi0: tbi-phy@11 {
219 reg = <0x11>;
220 device_type = "tbi-phy";
221 };
222 }; 93 };
223 }; 94 };
224 95
225 enet1: ethernet@25000 { 96 enet1: ethernet@25000 {
226 #address-cells = <1>;
227 #size-cells = <1>;
228 cell-index = <1>;
229 device_type = "network";
230 model = "TSEC";
231 compatible = "gianfar";
232 reg = <0x25000 0x1000>;
233 ranges = <0x0 0x25000 0x1000>;
234 local-mac-address = [ 00 00 00 00 00 00 ];
235 interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
236 tbi-handle = <&tbi1>; 97 tbi-handle = <&tbi1>;
237 phy-handle = <&phy1>; 98 phy-handle = <&phy1>;
238 phy-connection-type = "rgmii-id"; 99 phy-connection-type = "rgmii-id";
100 };
239 101
240 mdio@520 { 102 mdio@25520 {
241 #address-cells = <1>; 103 tbi1: tbi-phy@11 {
242 #size-cells = <0>; 104 reg = <0x11>;
243 compatible = "fsl,gianfar-tbi"; 105 device_type = "tbi-phy";
244 reg = <0x520 0x20>;
245
246 tbi1: tbi-phy@11 {
247 reg = <0x11>;
248 device_type = "tbi-phy";
249 };
250 }; 106 };
251 }; 107 };
252 108
253 enet2: ethernet@26000 { 109 enet2: ethernet@26000 {
254 #address-cells = <1>;
255 #size-cells = <1>;
256 cell-index = <2>;
257 device_type = "network";
258 model = "TSEC";
259 compatible = "gianfar";
260 reg = <0x26000 0x1000>;
261 ranges = <0x0 0x26000 0x1000>;
262 local-mac-address = [ 00 00 00 00 00 00 ];
263 interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
264 tbi-handle = <&tbi2>; 110 tbi-handle = <&tbi2>;
265 phy-handle = <&phy2>; 111 phy-handle = <&phy2>;
266 phy-connection-type = "rgmii-id"; 112 phy-connection-type = "rgmii-id";
113 };
267 114
268 mdio@520 { 115 mdio@26520 {
269 #address-cells = <1>; 116 tbi2: tbi-phy@11 {
270 #size-cells = <0>; 117 reg = <0x11>;
271 compatible = "fsl,gianfar-tbi"; 118 device_type = "tbi-phy";
272 reg = <0x520 0x20>;
273
274 tbi2: tbi-phy@11 {
275 reg = <0x11>;
276 device_type = "tbi-phy";
277 };
278 }; 119 };
279 }; 120 };
280 121
281 enet3: ethernet@27000 { 122 enet3: ethernet@27000 {
282 #address-cells = <1>;
283 #size-cells = <1>;
284 cell-index = <3>;
285 device_type = "network";
286 model = "TSEC";
287 compatible = "gianfar";
288 reg = <0x27000 0x1000>;
289 ranges = <0x0 0x27000 0x1000>;
290 local-mac-address = [ 00 00 00 00 00 00 ];
291 interrupts = <37 2 0 0 38 2 0 0 39 2 0 0>;
292 tbi-handle = <&tbi3>; 123 tbi-handle = <&tbi3>;
293 phy-handle = <&phy3>; 124 phy-handle = <&phy3>;
294 phy-connection-type = "rgmii-id"; 125 phy-connection-type = "rgmii-id";
295
296 mdio@520 {
297 #address-cells = <1>;
298 #size-cells = <0>;
299 compatible = "fsl,gianfar-tbi";
300 reg = <0x520 0x20>;
301
302 tbi3: tbi-phy@11 {
303 reg = <0x11>;
304 device_type = "tbi-phy";
305 };
306 };
307 };
308
309 serial0: serial@4500 {
310 cell-index = <0>;
311 device_type = "serial";
312 compatible = "fsl,ns16550", "ns16550";
313 reg = <0x4500 0x100>;
314 clock-frequency = <0>;
315 interrupts = <42 2 0 0>;
316 }; 126 };
317 127
318 serial1: serial@4600 { 128 mdio@27520 {
319 cell-index = <1>; 129 tbi3: tbi-phy@11 {
320 device_type = "serial"; 130 reg = <0x11>;
321 compatible = "fsl,ns16550", "ns16550"; 131 device_type = "tbi-phy";
322 reg = <0x4600 0x100>; 132 };
323 clock-frequency = <0>;
324 interrupts = <28 2 0 0>;
325 };
326
327 mpic: pic@40000 {
328 interrupt-controller;
329 #address-cells = <0>;
330 #interrupt-cells = <4>;
331 reg = <0x40000 0x40000>;
332 compatible = "fsl,mpic", "chrp,open-pic";
333 device_type = "open-pic";
334 };
335
336 global-utilities@e0000 {
337 compatible = "fsl,mpc8641-guts";
338 reg = <0xe0000 0x1000>;
339 fsl,has-rstcr;
340 }; 133 };
341 }; 134 };
342 135
343 pci0: pcie@fffe08000 { 136 pci0: pcie@fffe08000 {
344 cell-index = <0>;
345 compatible = "fsl,mpc8641-pcie";
346 device_type = "pci";
347 #size-cells = <2>;
348 #address-cells = <3>;
349 reg = <0x0f 0xffe08000 0x0 0x1000>; 137 reg = <0x0f 0xffe08000 0x0 0x1000>;
350 bus-range = <0x0 0xff>;
351 ranges = <0x02000000 0x0 0xe0000000 0x0c 0x00000000 0x0 0x20000000 138 ranges = <0x02000000 0x0 0xe0000000 0x0c 0x00000000 0x0 0x20000000
352 0x01000000 0x0 0x00000000 0x0f 0xffc00000 0x0 0x00010000>; 139 0x01000000 0x0 0x00000000 0x0f 0xffc00000 0x0 0x00010000>;
353 clock-frequency = <100000000>;
354 interrupts = <24 2 0 0>;
355 interrupt-map-mask = <0xff00 0 0 7>; 140 interrupt-map-mask = <0xff00 0 0 7>;
356 interrupt-map = < 141 interrupt-map = <
357 /* IDSEL 0x11 func 0 - PCI slot 1 */ 142 /* IDSEL 0x11 func 0 - PCI slot 1 */
@@ -469,10 +254,6 @@
469 >; 254 >;
470 255
471 pcie@0 { 256 pcie@0 {
472 reg = <0 0 0 0 0>;
473 #size-cells = <2>;
474 #address-cells = <3>;
475 device_type = "pci";
476 ranges = <0x02000000 0x0 0xe0000000 257 ranges = <0x02000000 0x0 0xe0000000
477 0x02000000 0x0 0xe0000000 258 0x02000000 0x0 0xe0000000
478 0x0 0x20000000 259 0x0 0x20000000
@@ -545,7 +326,6 @@
545 }; 326 };
546 327
547 pci1: pcie@fffe09000 { 328 pci1: pcie@fffe09000 {
548 cell-index = <1>;
549 compatible = "fsl,mpc8641-pcie"; 329 compatible = "fsl,mpc8641-pcie";
550 device_type = "pci"; 330 device_type = "pci";
551 #size-cells = <2>; 331 #size-cells = <2>;
@@ -579,3 +359,5 @@
579 }; 359 };
580 }; 360 };
581}; 361};
362
363/include/ "mpc8641si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/mpc8641si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8641si-post.dtsi
new file mode 100644
index 000000000000..70889d8e8850
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8641si-post.dtsi
@@ -0,0 +1,120 @@
1/*
2 * MPC8641 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 */
12
13&lbc {
14 #address-cells = <2>;
15 #size-cells = <1>;
16 compatible = "fsl,mpc8641-localbus", "simple-bus";
17 interrupts = <19 2 0 0>;
18};
19
20&soc {
21 #address-cells = <1>;
22 #size-cells = <1>;
23 device_type = "soc";
24 compatible = "fsl,mpc8641-soc", "simple-bus";
25 bus-frequency = <0>;
26
27 mcm-law@0 {
28 compatible = "fsl,mcm-law";
29 reg = <0x0 0x1000>;
30 fsl,num-laws = <10>;
31 };
32
33 mcm@1000 {
34 compatible = "fsl,mpc8641-mcm", "fsl,mcm";
35 reg = <0x1000 0x1000>;
36 interrupts = <17 2 0 0>;
37 };
38
39/include/ "pq3-i2c-0.dtsi"
40/include/ "pq3-i2c-1.dtsi"
41/include/ "pq3-duart-0.dtsi"
42 serial@4600 {
43 interrupts = <28 2 0 0>;
44 };
45/include/ "pq3-dma-0.dtsi"
46 dma@21300 {
47 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
48 };
49 dma-channel@0 {
50 compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel";
51 };
52 dma-channel@80 {
53 compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel";
54 };
55 dma-channel@100 {
56 compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel";
57 };
58 dma-channel@180 {
59 compatible = "fsl,mpc8641-dma-channel", "fsl,eloplus-dma-channel";
60 };
61
62/include/ "pq3-etsec1-0.dtsi"
63 ethernet@24000 {
64 model = "TSEC";
65 };
66/include/ "pq3-etsec1-1.dtsi"
67 ethernet@25000 {
68 model = "TSEC";
69 };
70/include/ "pq3-etsec1-2.dtsi"
71 ethernet@26000 {
72 model = "TSEC";
73 };
74/include/ "pq3-etsec1-3.dtsi"
75 ethernet@27000 {
76 model = "TSEC";
77 };
78
79/include/ "qoriq-mpic.dtsi"
80 msi@41600 {
81 compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
82 };
83 msi@41800 {
84 compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
85 };
86 msi@41a00 {
87 compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
88 };
89
90 global-utilities@e0000 {
91 compatible = "fsl,mpc8641-guts";
92 reg = <0xe0000 0x1000>;
93 fsl,has-rstcr;
94 };
95};
96
97&pci0 {
98 compatible = "fsl,mpc8641-pcie";
99 device_type = "pci";
100 #size-cells = <2>;
101 #address-cells = <3>;
102 bus-range = <0x0 0xff>;
103 clock-frequency = <100000000>;
104 interrupts = <24 2 0 0>;
105 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
106
107 interrupt-map = <
108 0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
109 0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
110 0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
111 0x0000 0x0 0x0 0x4 &mpic 0x3 0x1
112 >;
113
114 pcie@0 {
115 reg = <0 0 0 0 0>;
116 #size-cells = <2>;
117 #address-cells = <3>;
118 device_type = "pci";
119 };
120};
diff --git a/arch/powerpc/boot/dts/fsl/mpc8641si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8641si-pre.dtsi
new file mode 100644
index 000000000000..9e03328561d3
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/mpc8641si-pre.dtsi
@@ -0,0 +1,58 @@
1/*
2 * MPC8641 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 */
12
13/dts-v1/;
14
15/ {
16 #address-cells = <1>;
17 #size-cells = <1>;
18 interrupt-parent = <&mpic>;
19
20 aliases {
21 ethernet0 = &enet0;
22 ethernet1 = &enet1;
23 ethernet2 = &enet2;
24 ethernet3 = &enet3;
25 serial0 = &serial0;
26 serial1 = &serial1;
27 pci0 = &pci0;
28 };
29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 PowerPC,8641@0 {
35 device_type = "cpu";
36 reg = <0>;
37 d-cache-line-size = <32>;
38 i-cache-line-size = <32>;
39 d-cache-size = <32768>;
40 i-cache-size = <32768>;
41 timebase-frequency = <0>;
42 bus-frequency = <0>;
43 clock-frequency = <0>;
44 };
45
46 PowerPC,8641@1 {
47 device_type = "cpu";
48 reg = <1>;
49 d-cache-line-size = <32>;
50 i-cache-line-size = <32>;
51 d-cache-size = <32768>;
52 i-cache-size = <32768>;
53 timebase-frequency = <0>;
54 bus-frequency = <0>;
55 clock-frequency = <0>;
56 };
57 };
58};
diff --git a/arch/powerpc/boot/dts/fsl/sbc8641d.dts b/arch/powerpc/boot/dts/fsl/sbc8641d.dts
index 47c83a0713fb..0a9733cd418d 100644
--- a/arch/powerpc/boot/dts/fsl/sbc8641d.dts
+++ b/arch/powerpc/boot/dts/fsl/sbc8641d.dts
@@ -13,65 +13,23 @@
13 * option) any later version. 13 * option) any later version.
14 */ 14 */
15 15
16/dts-v1/; 16/include/ "mpc8641si-pre.dtsi"
17 17
18/ { 18/ {
19 model = "SBC8641D"; 19 model = "SBC8641D";
20 compatible = "wind,sbc8641"; 20 compatible = "wind,sbc8641";
21 #address-cells = <1>;
22 #size-cells = <1>;
23 interrupt-parent = <&mpic>;
24 21
25 aliases { 22 aliases {
26 ethernet0 = &enet0;
27 ethernet1 = &enet1;
28 ethernet2 = &enet2;
29 ethernet3 = &enet3;
30 serial0 = &serial0;
31 serial1 = &serial1;
32 pci0 = &pci0;
33 pci1 = &pci1; 23 pci1 = &pci1;
34 }; 24 };
35 25
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 PowerPC,8641@0 {
41 device_type = "cpu";
42 reg = <0>;
43 d-cache-line-size = <32>;
44 i-cache-line-size = <32>;
45 d-cache-size = <32768>; // L1
46 i-cache-size = <32768>; // L1
47 timebase-frequency = <0>; // From uboot
48 bus-frequency = <0>; // From uboot
49 clock-frequency = <0>; // From uboot
50 };
51 PowerPC,8641@1 {
52 device_type = "cpu";
53 reg = <1>;
54 d-cache-line-size = <32>;
55 i-cache-line-size = <32>;
56 d-cache-size = <32768>;
57 i-cache-size = <32768>;
58 timebase-frequency = <0>; // From uboot
59 bus-frequency = <0>; // From uboot
60 clock-frequency = <0>; // From uboot
61 };
62 };
63
64 memory { 26 memory {
65 device_type = "memory"; 27 device_type = "memory";
66 reg = <0x00000000 0x20000000>; // 512M at 0x0 28 reg = <0x00000000 0x20000000>; // 512M at 0x0
67 }; 29 };
68 30
69 localbus@f8005000 { 31 lbc: localbus@f8005000 {
70 #address-cells = <2>;
71 #size-cells = <1>;
72 compatible = "fsl,mpc8641-localbus", "simple-bus";
73 reg = <0xf8005000 0x1000>; 32 reg = <0xf8005000 0x1000>;
74 interrupts = <19 2 0 0>;
75 33
76 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash 34 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
77 1 0 0xf0000000 0x00010000 // 64KB EEPROM 35 1 0 0xf0000000 0x00010000 // 64KB EEPROM
@@ -120,268 +78,81 @@
120 }; 78 };
121 }; 79 };
122 80
123 soc@f8000000 { 81 soc: soc@f8000000 {
124 #address-cells = <1>;
125 #size-cells = <1>;
126 device_type = "soc";
127 compatible = "simple-bus";
128 ranges = <0x00000000 0xf8000000 0x00100000>; 82 ranges = <0x00000000 0xf8000000 0x00100000>;
129 bus-frequency = <0>;
130
131 mcm-law@0 {
132 compatible = "fsl,mcm-law";
133 reg = <0x0 0x1000>;
134 fsl,num-laws = <10>;
135 };
136
137 mcm@1000 {
138 compatible = "fsl,mpc8641-mcm", "fsl,mcm";
139 reg = <0x1000 0x1000>;
140 interrupts = <17 2 0 0>;
141 };
142
143 i2c@3000 {
144 #address-cells = <1>;
145 #size-cells = <0>;
146 cell-index = <0>;
147 compatible = "fsl-i2c";
148 reg = <0x3000 0x100>;
149 interrupts = <43 2 0 0>;
150 dfsrr;
151 };
152 83
153 i2c@3100 { 84 enet0: ethernet@24000 {
154 #address-cells = <1>; 85 tbi-handle = <&tbi0>;
155 #size-cells = <0>; 86 phy-handle = <&phy0>;
156 cell-index = <1>; 87 phy-connection-type = "rgmii-id";
157 compatible = "fsl-i2c";
158 reg = <0x3100 0x100>;
159 interrupts = <43 2 0 0>;
160 dfsrr;
161 }; 88 };
162 89
163 dma@21300 { 90 mdio@24520 {
164 #address-cells = <1>; 91 phy0: ethernet-phy@1f {
165 #size-cells = <1>; 92 reg = <0x1f>;
166 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
167 reg = <0x21300 0x4>;
168 ranges = <0x0 0x21100 0x200>;
169 cell-index = <0>;
170 dma-channel@0 {
171 compatible = "fsl,mpc8641-dma-channel",
172 "fsl,eloplus-dma-channel";
173 reg = <0x0 0x80>;
174 cell-index = <0>;
175 interrupts = <20 2 0 0>;
176 }; 93 };
177 dma-channel@80 { 94 phy1: ethernet-phy@0 {
178 compatible = "fsl,mpc8641-dma-channel", 95 reg = <0>;
179 "fsl,eloplus-dma-channel";
180 reg = <0x80 0x80>;
181 cell-index = <1>;
182 interrupts = <21 2 0 0>;
183 }; 96 };
184 dma-channel@100 { 97 phy2: ethernet-phy@1 {
185 compatible = "fsl,mpc8641-dma-channel", 98 reg = <1>;
186 "fsl,eloplus-dma-channel";
187 reg = <0x100 0x80>;
188 cell-index = <2>;
189 interrupts = <22 2 0 0>;
190 }; 99 };
191 dma-channel@180 { 100 phy3: ethernet-phy@2 {
192 compatible = "fsl,mpc8641-dma-channel", 101 reg = <2>;
193 "fsl,eloplus-dma-channel";
194 reg = <0x180 0x80>;
195 cell-index = <3>;
196 interrupts = <23 2 0 0>;
197 }; 102 };
198 }; 103 tbi0: tbi-phy@11 {
199 104 reg = <0x11>;
200 enet0: ethernet@24000 { 105 device_type = "tbi-phy";
201 #address-cells = <1>;
202 #size-cells = <1>;
203 cell-index = <0>;
204 device_type = "network";
205 model = "TSEC";
206 compatible = "gianfar";
207 reg = <0x24000 0x1000>;
208 ranges = <0x0 0x24000 0x1000>;
209 local-mac-address = [ 00 00 00 00 00 00 ];
210 interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
211 tbi-handle = <&tbi0>;
212 phy-handle = <&phy0>;
213 phy-connection-type = "rgmii-id";
214
215 mdio@520 {
216 #address-cells = <1>;
217 #size-cells = <0>;
218 compatible = "fsl,gianfar-mdio";
219 reg = <0x520 0x20>;
220
221 phy0: ethernet-phy@1f {
222 reg = <0x1f>;
223 };
224 phy1: ethernet-phy@0 {
225 reg = <0>;
226 };
227 phy2: ethernet-phy@1 {
228 reg = <1>;
229 };
230 phy3: ethernet-phy@2 {
231 reg = <2>;
232 };
233 tbi0: tbi-phy@11 {
234 reg = <0x11>;
235 device_type = "tbi-phy";
236 };
237 }; 106 };
238 }; 107 };
239 108
240 enet1: ethernet@25000 { 109 enet1: ethernet@25000 {
241 #address-cells = <1>;
242 #size-cells = <1>;
243 cell-index = <1>;
244 device_type = "network";
245 model = "TSEC";
246 compatible = "gianfar";
247 reg = <0x25000 0x1000>;
248 ranges = <0x0 0x25000 0x1000>;
249 local-mac-address = [ 00 00 00 00 00 00 ];
250 interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
251 tbi-handle = <&tbi1>; 110 tbi-handle = <&tbi1>;
252 phy-handle = <&phy1>; 111 phy-handle = <&phy1>;
253 phy-connection-type = "rgmii-id"; 112 phy-connection-type = "rgmii-id";
113 };
254 114
255 mdio@520 { 115 mdio@25520 {
256 #address-cells = <1>; 116 tbi1: tbi-phy@11 {
257 #size-cells = <0>; 117 reg = <0x11>;
258 compatible = "fsl,gianfar-tbi"; 118 device_type = "tbi-phy";
259 reg = <0x520 0x20>;
260
261 tbi1: tbi-phy@11 {
262 reg = <0x11>;
263 device_type = "tbi-phy";
264 };
265 }; 119 };
266 }; 120 };
267 121
268 enet2: ethernet@26000 { 122 enet2: ethernet@26000 {
269 #address-cells = <1>;
270 #size-cells = <1>;
271 cell-index = <2>;
272 device_type = "network";
273 model = "TSEC";
274 compatible = "gianfar";
275 reg = <0x26000 0x1000>;
276 ranges = <0x0 0x26000 0x1000>;
277 local-mac-address = [ 00 00 00 00 00 00 ];
278 interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
279 tbi-handle = <&tbi2>; 123 tbi-handle = <&tbi2>;
280 phy-handle = <&phy2>; 124 phy-handle = <&phy2>;
281 phy-connection-type = "rgmii-id"; 125 phy-connection-type = "rgmii-id";
126 };
282 127
283 mdio@520 { 128 mdio@26520 {
284 #address-cells = <1>; 129 tbi2: tbi-phy@11 {
285 #size-cells = <0>; 130 reg = <0x11>;
286 compatible = "fsl,gianfar-tbi"; 131 device_type = "tbi-phy";
287 reg = <0x520 0x20>;
288
289 tbi2: tbi-phy@11 {
290 reg = <0x11>;
291 device_type = "tbi-phy";
292 };
293 }; 132 };
294 }; 133 };
295 134
296 enet3: ethernet@27000 { 135 enet3: ethernet@27000 {
297 #address-cells = <1>;
298 #size-cells = <1>;
299 cell-index = <3>;
300 device_type = "network";
301 model = "TSEC";
302 compatible = "gianfar";
303 reg = <0x27000 0x1000>;
304 ranges = <0x0 0x27000 0x1000>;
305 local-mac-address = [ 00 00 00 00 00 00 ];
306 interrupts = <37 2 0 0 38 2 0 0 39 2 0 0>;
307 tbi-handle = <&tbi3>; 136 tbi-handle = <&tbi3>;
308 phy-handle = <&phy3>; 137 phy-handle = <&phy3>;
309 phy-connection-type = "rgmii-id"; 138 phy-connection-type = "rgmii-id";
310
311 mdio@520 {
312 #address-cells = <1>;
313 #size-cells = <0>;
314 compatible = "fsl,gianfar-tbi";
315 reg = <0x520 0x20>;
316
317 tbi3: tbi-phy@11 {
318 reg = <0x11>;
319 device_type = "tbi-phy";
320 };
321 };
322 };
323
324 serial0: serial@4500 {
325 cell-index = <0>;
326 device_type = "serial";
327 compatible = "fsl,ns16550", "ns16550";
328 reg = <0x4500 0x100>;
329 clock-frequency = <0>;
330 interrupts = <42 2 0 0>;
331 };
332
333 serial1: serial@4600 {
334 cell-index = <1>;
335 device_type = "serial";
336 compatible = "fsl,ns16550", "ns16550";
337 reg = <0x4600 0x100>;
338 clock-frequency = <0>;
339 interrupts = <28 2 0 0>;
340 }; 139 };
341 140
342 mpic: pic@40000 { 141 mdio@27520 {
343 clock-frequency = <0>; 142 tbi3: tbi-phy@11 {
344 interrupt-controller; 143 reg = <0x11>;
345 #address-cells = <0>; 144 device_type = "tbi-phy";
346 #interrupt-cells = <4>; 145 };
347 reg = <0x40000 0x40000>;
348 compatible = "fsl,mpic", "chrp,open-pic";
349 device_type = "open-pic";
350 big-endian;
351 };
352
353 global-utilities@e0000 {
354 compatible = "fsl,mpc8641-guts";
355 reg = <0xe0000 0x1000>;
356 fsl,has-rstcr;
357 }; 146 };
358 }; 147 };
359 148
360 pci0: pcie@f8008000 { 149 pci0: pcie@f8008000 {
361 compatible = "fsl,mpc8641-pcie";
362 device_type = "pci";
363 #size-cells = <2>;
364 #address-cells = <3>;
365 reg = <0xf8008000 0x1000>; 150 reg = <0xf8008000 0x1000>;
366 bus-range = <0x0 0xff>;
367 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000 151 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
368 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>; 152 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
369 clock-frequency = <100000000>;
370 interrupts = <24 2 0 0>;
371 interrupt-map-mask = <0xff00 0 0 7>; 153 interrupt-map-mask = <0xff00 0 0 7>;
372 interrupt-map = <
373 /* IDSEL 0x0 */
374 0x0000 0 0 1 &mpic 0 1
375 0x0000 0 0 2 &mpic 1 1
376 0x0000 0 0 3 &mpic 2 1
377 0x0000 0 0 4 &mpic 3 1
378 >;
379 154
380 pcie@0 { 155 pcie@0 {
381 reg = <0 0 0 0 0>;
382 #size-cells = <2>;
383 #address-cells = <3>;
384 device_type = "pci";
385 ranges = <0x02000000 0x0 0x80000000 156 ranges = <0x02000000 0x0 0x80000000
386 0x02000000 0x0 0x80000000 157 0x02000000 0x0 0x80000000
387 0x0 0x20000000 158 0x0 0x20000000
@@ -428,3 +199,5 @@
428 }; 199 };
429 }; 200 };
430}; 201};
202
203/include/ "mpc8641si-post.dtsi"
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-25 01:54:22 -0500