aboutsummaryrefslogtreecommitdiffstats
path: root/arch/powerpc/boot/dts/fsl/mpc8641_hpcn.dts
diff options
context:
space:
mode:
Diffstat (limited to 'arch/powerpc/boot/dts/fsl/mpc8641_hpcn.dts')
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8641_hpcn.dts300
1 files changed, 41 insertions, 259 deletions
diff --git a/arch/powerpc/boot/dts/fsl/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/fsl/mpc8641_hpcn.dts
index 03ef3f72e100..554001f2e96a 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8641_hpcn.dts
+++ b/arch/powerpc/boot/dts/fsl/mpc8641_hpcn.dts
@@ -9,65 +9,23 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "mpc8641si-pre.dtsi"
13 13
14/ { 14/ {
15 model = "MPC8641HPCN"; 15 model = "MPC8641HPCN";
16 compatible = "fsl,mpc8641hpcn"; 16 compatible = "fsl,mpc8641hpcn";
17 #address-cells = <1>;
18 #size-cells = <1>;
19 interrupt-parent = <&mpic>;
20 17
21 aliases { 18 aliases {
22 ethernet0 = &enet0;
23 ethernet1 = &enet1;
24 ethernet2 = &enet2;
25 ethernet3 = &enet3;
26 serial0 = &serial0;
27 serial1 = &serial1;
28 pci0 = &pci0;
29 pci1 = &pci1; 19 pci1 = &pci1;
30 }; 20 };
31 21
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 PowerPC,8641@0 {
37 device_type = "cpu";
38 reg = <0>;
39 d-cache-line-size = <32>;
40 i-cache-line-size = <32>;
41 d-cache-size = <32768>; // L1
42 i-cache-size = <32768>; // L1
43 timebase-frequency = <0>; // From uboot
44 bus-frequency = <0>; // From uboot
45 clock-frequency = <0>; // From uboot
46 };
47 PowerPC,8641@1 {
48 device_type = "cpu";
49 reg = <1>;
50 d-cache-line-size = <32>;
51 i-cache-line-size = <32>;
52 d-cache-size = <32768>;
53 i-cache-size = <32768>;
54 timebase-frequency = <0>; // From uboot
55 bus-frequency = <0>; // From uboot
56 clock-frequency = <0>; // From uboot
57 };
58 };
59
60 memory { 22 memory {
61 device_type = "memory"; 23 device_type = "memory";
62 reg = <0x00000000 0x40000000>; // 1G at 0x0 24 reg = <0x00000000 0x40000000>; // 1G at 0x0
63 }; 25 };
64 26
65 localbus@ffe05000 { 27 lbc: localbus@ffe05000 {
66 #address-cells = <2>;
67 #size-cells = <1>;
68 compatible = "fsl,mpc8641-localbus", "simple-bus";
69 reg = <0xffe05000 0x1000>; 28 reg = <0xffe05000 0x1000>;
70 interrupts = <19 2 0 0>;
71 29
72 ranges = <0 0 0xef800000 0x00800000 30 ranges = <0 0 0xef800000 0x00800000
73 2 0 0xffdf8000 0x00008000 31 2 0 0xffdf8000 0x00008000
@@ -101,236 +59,75 @@
101 }; 59 };
102 }; 60 };
103 61
104 soc8641@ffe00000 { 62 soc: soc8641@ffe00000 {
105 #address-cells = <1>;
106 #size-cells = <1>;
107 device_type = "soc";
108 compatible = "simple-bus";
109 ranges = <0x00000000 0xffe00000 0x00100000>; 63 ranges = <0x00000000 0xffe00000 0x00100000>;
110 bus-frequency = <0>;
111
112 mcm-law@0 {
113 compatible = "fsl,mcm-law";
114 reg = <0x0 0x1000>;
115 fsl,num-laws = <10>;
116 };
117
118 mcm@1000 {
119 compatible = "fsl,mpc8641-mcm", "fsl,mcm";
120 reg = <0x1000 0x1000>;
121 interrupts = <17 2 0 0>;
122 };
123 64
124 i2c@3000 { 65 enet0: ethernet@24000 {
125 #address-cells = <1>; 66 tbi-handle = <&tbi0>;
126 #size-cells = <0>; 67 phy-handle = <&phy0>;
127 cell-index = <0>; 68 phy-connection-type = "rgmii-id";
128 compatible = "fsl-i2c";
129 reg = <0x3000 0x100>;
130 interrupts = <43 2 0 0>;
131 dfsrr;
132 };
133
134 i2c@3100 {
135 #address-cells = <1>;
136 #size-cells = <0>;
137 cell-index = <1>;
138 compatible = "fsl-i2c";
139 reg = <0x3100 0x100>;
140 interrupts = <43 2 0 0>;
141 dfsrr;
142 }; 69 };
143 70
144 dma@21300 { 71 mdio@24520 {
145 #address-cells = <1>; 72 phy0: ethernet-phy@0 {
146 #size-cells = <1>; 73 interrupts = <10 1 0 0>;
147 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma"; 74 reg = <0>;
148 reg = <0x21300 0x4>;
149 ranges = <0x0 0x21100 0x200>;
150 cell-index = <0>;
151 dma-channel@0 {
152 compatible = "fsl,mpc8641-dma-channel",
153 "fsl,eloplus-dma-channel";
154 reg = <0x0 0x80>;
155 cell-index = <0>;
156 interrupts = <20 2 0 0>;
157 }; 75 };
158 dma-channel@80 { 76 phy1: ethernet-phy@1 {
159 compatible = "fsl,mpc8641-dma-channel", 77 interrupts = <10 1 0 0>;
160 "fsl,eloplus-dma-channel"; 78 reg = <1>;
161 reg = <0x80 0x80>;
162 cell-index = <1>;
163 interrupts = <21 2 0 0>;
164 }; 79 };
165 dma-channel@100 { 80 phy2: ethernet-phy@2 {
166 compatible = "fsl,mpc8641-dma-channel", 81 interrupts = <10 1 0 0>;
167 "fsl,eloplus-dma-channel"; 82 reg = <2>;
168 reg = <0x100 0x80>;
169 cell-index = <2>;
170 interrupts = <22 2 0 0>;
171 }; 83 };
172 dma-channel@180 { 84 phy3: ethernet-phy@3 {
173 compatible = "fsl,mpc8641-dma-channel", 85 interrupts = <10 1 0 0>;
174 "fsl,eloplus-dma-channel"; 86 reg = <3>;
175 reg = <0x180 0x80>;
176 cell-index = <3>;
177 interrupts = <23 2 0 0>;
178 }; 87 };
179 }; 88 tbi0: tbi-phy@11 {
180 89 reg = <0x11>;
181 enet0: ethernet@24000 { 90 device_type = "tbi-phy";
182 #address-cells = <1>;
183 #size-cells = <1>;
184 cell-index = <0>;
185 device_type = "network";
186 model = "TSEC";
187 compatible = "gianfar";
188 reg = <0x24000 0x1000>;
189 ranges = <0x0 0x24000 0x1000>;
190 local-mac-address = [ 00 00 00 00 00 00 ];
191 interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
192 tbi-handle = <&tbi0>;
193 phy-handle = <&phy0>;
194 phy-connection-type = "rgmii-id";
195
196 mdio@520 {
197 #address-cells = <1>;
198 #size-cells = <0>;
199 compatible = "fsl,gianfar-mdio";
200 reg = <0x520 0x20>;
201
202 phy0: ethernet-phy@0 {
203 interrupts = <10 1 0 0>;
204 reg = <0>;
205 };
206 phy1: ethernet-phy@1 {
207 interrupts = <10 1 0 0>;
208 reg = <1>;
209 };
210 phy2: ethernet-phy@2 {
211 interrupts = <10 1 0 0>;
212 reg = <2>;
213 };
214 phy3: ethernet-phy@3 {
215 interrupts = <10 1 0 0>;
216 reg = <3>;
217 };
218 tbi0: tbi-phy@11 {
219 reg = <0x11>;
220 device_type = "tbi-phy";
221 };
222 }; 91 };
223 }; 92 };
224 93
225 enet1: ethernet@25000 { 94 enet1: ethernet@25000 {
226 #address-cells = <1>;
227 #size-cells = <1>;
228 cell-index = <1>;
229 device_type = "network";
230 model = "TSEC";
231 compatible = "gianfar";
232 reg = <0x25000 0x1000>;
233 ranges = <0x0 0x25000 0x1000>;
234 local-mac-address = [ 00 00 00 00 00 00 ];
235 interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
236 tbi-handle = <&tbi1>; 95 tbi-handle = <&tbi1>;
237 phy-handle = <&phy1>; 96 phy-handle = <&phy1>;
238 phy-connection-type = "rgmii-id"; 97 phy-connection-type = "rgmii-id";
98 };
239 99
240 mdio@520 { 100 mdio@25520 {
241 #address-cells = <1>; 101 tbi1: tbi-phy@11 {
242 #size-cells = <0>; 102 reg = <0x11>;
243 compatible = "fsl,gianfar-tbi"; 103 device_type = "tbi-phy";
244 reg = <0x520 0x20>;
245
246 tbi1: tbi-phy@11 {
247 reg = <0x11>;
248 device_type = "tbi-phy";
249 };
250 }; 104 };
251 }; 105 };
252 106
253 enet2: ethernet@26000 { 107 enet2: ethernet@26000 {
254 #address-cells = <1>;
255 #size-cells = <1>;
256 cell-index = <2>;
257 device_type = "network";
258 model = "TSEC";
259 compatible = "gianfar";
260 reg = <0x26000 0x1000>;
261 ranges = <0x0 0x26000 0x1000>;
262 local-mac-address = [ 00 00 00 00 00 00 ];
263 interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
264 tbi-handle = <&tbi2>; 108 tbi-handle = <&tbi2>;
265 phy-handle = <&phy2>; 109 phy-handle = <&phy2>;
266 phy-connection-type = "rgmii-id"; 110 phy-connection-type = "rgmii-id";
111 };
267 112
268 mdio@520 { 113 mdio@26520 {
269 #address-cells = <1>; 114 tbi2: tbi-phy@11 {
270 #size-cells = <0>; 115 reg = <0x11>;
271 compatible = "fsl,gianfar-tbi"; 116 device_type = "tbi-phy";
272 reg = <0x520 0x20>;
273
274 tbi2: tbi-phy@11 {
275 reg = <0x11>;
276 device_type = "tbi-phy";
277 };
278 }; 117 };
279 }; 118 };
280 119
281 enet3: ethernet@27000 { 120 enet3: ethernet@27000 {
282 #address-cells = <1>;
283 #size-cells = <1>;
284 cell-index = <3>;
285 device_type = "network";
286 model = "TSEC";
287 compatible = "gianfar";
288 reg = <0x27000 0x1000>;
289 ranges = <0x0 0x27000 0x1000>;
290 local-mac-address = [ 00 00 00 00 00 00 ];
291 interrupts = <37 2 0 0 38 2 0 0 39 2 0 0>;
292 tbi-handle = <&tbi3>; 121 tbi-handle = <&tbi3>;
293 phy-handle = <&phy3>; 122 phy-handle = <&phy3>;
294 phy-connection-type = "rgmii-id"; 123 phy-connection-type = "rgmii-id";
295
296 mdio@520 {
297 #address-cells = <1>;
298 #size-cells = <0>;
299 compatible = "fsl,gianfar-tbi";
300 reg = <0x520 0x20>;
301
302 tbi3: tbi-phy@11 {
303 reg = <0x11>;
304 device_type = "tbi-phy";
305 };
306 };
307 }; 124 };
308 125
309 serial0: serial@4500 { 126 mdio@27520 {
310 cell-index = <0>; 127 tbi3: tbi-phy@11 {
311 device_type = "serial"; 128 reg = <0x11>;
312 compatible = "fsl,ns16550", "ns16550"; 129 device_type = "tbi-phy";
313 reg = <0x4500 0x100>; 130 };
314 clock-frequency = <0>;
315 interrupts = <42 2 0 0>;
316 };
317
318 serial1: serial@4600 {
319 cell-index = <1>;
320 device_type = "serial";
321 compatible = "fsl,ns16550", "ns16550";
322 reg = <0x4600 0x100>;
323 clock-frequency = <0>;
324 interrupts = <28 2 0 0>;
325 };
326
327 mpic: pic@40000 {
328 interrupt-controller;
329 #address-cells = <0>;
330 #interrupt-cells = <4>;
331 reg = <0x40000 0x40000>;
332 compatible = "fsl,mpic", "chrp,open-pic";
333 device_type = "open-pic";
334 }; 131 };
335 132
336 rmu: rmu@d3000 { 133 rmu: rmu@d3000 {
@@ -358,7 +155,7 @@
358 compatible = "fsl,srio-dbell-unit"; 155 compatible = "fsl,srio-dbell-unit";
359 reg = <0x400 0x80>; 156 reg = <0x400 0x80>;
360 interrupts = < 157 interrupts = <
361 49 2 0 0 /* bell_outb_irq */ 158 49 2 0 0 /* bell_outb_irq */
362 50 2 0 0>;/* bell_inb_irq */ 159 50 2 0 0>;/* bell_inb_irq */
363 }; 160 };
364 port-write-unit@4e0 { 161 port-write-unit@4e0 {
@@ -367,25 +164,12 @@
367 interrupts = <48 2 0 0>; 164 interrupts = <48 2 0 0>;
368 }; 165 };
369 }; 166 };
370
371 global-utilities@e0000 {
372 compatible = "fsl,mpc8641-guts";
373 reg = <0xe0000 0x1000>;
374 fsl,has-rstcr;
375 };
376 }; 167 };
377 168
378 pci0: pcie@ffe08000 { 169 pci0: pcie@ffe08000 {
379 compatible = "fsl,mpc8641-pcie";
380 device_type = "pci";
381 #size-cells = <2>;
382 #address-cells = <3>;
383 reg = <0xffe08000 0x1000>; 170 reg = <0xffe08000 0x1000>;
384 bus-range = <0x0 0xff>;
385 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000 171 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
386 0x01000000 0x0 0x00000000 0xffc00000 0x0 0x00010000>; 172 0x01000000 0x0 0x00000000 0xffc00000 0x0 0x00010000>;
387 clock-frequency = <100000000>;
388 interrupts = <24 2 0 0>;
389 interrupt-map-mask = <0xff00 0 0 7>; 173 interrupt-map-mask = <0xff00 0 0 7>;
390 interrupt-map = < 174 interrupt-map = <
391 /* IDSEL 0x11 func 0 - PCI slot 1 */ 175 /* IDSEL 0x11 func 0 - PCI slot 1 */
@@ -503,10 +287,6 @@
503 >; 287 >;
504 288
505 pcie@0 { 289 pcie@0 {
506 reg = <0 0 0 0 0>;
507 #size-cells = <2>;
508 #address-cells = <3>;
509 device_type = "pci";
510 ranges = <0x02000000 0x0 0x80000000 290 ranges = <0x02000000 0x0 0x80000000
511 0x02000000 0x0 0x80000000 291 0x02000000 0x0 0x80000000
512 0x0 0x20000000 292 0x0 0x20000000
@@ -636,3 +416,5 @@
636*/ 416*/
637 417
638}; 418};
419
420/include/ "mpc8641si-post.dtsi"
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-25 05:19:27 -0500