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authorDinh Nguyen <dinguyen@altera.com>2014-04-14 17:13:34 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2014-04-24 16:12:43 -0400
commit47a1685f139271de401212bd69d17374ca5a5270 (patch)
treea0e670780e9b428f054c4893af63cc97b813a65d
parent6ab53324496dbfd9e6110539f9aa0ab108bd664b (diff)
usb: dwc2/s3c-hsotg: move s3c-hsotg into dwc2 directory
Moves the s3c-hsotg driver into the dwc2 directory and uses the dwc2 defines in hw.h. Renames s3c-hsotg.c to gadget.c. NOTE: You can build both host and peripheral as a dynamically linked module, but be aware that if you insmod dwc2_gadget, then rmmod it, then insmod dwc2 and dwc2_platform for host mode, this will not work. As the step to rmmod dwc2_gadget.ko will turn off the clock to the USB IP. The dwc2 host driver currently does not look to turn on a clock yet. A patch to fix that will be coming soon. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> [ jh,rb - For gadget part only: ] Tested-by: Jingoo Han <jg1.han@samsung.com> Tested-by: Robert Baldyga <r.baldyga@samsung.com> [ pz: Folded Kconfig/Makefile changes, which were originally in a separate patch, into this one, to avoid a build breakage. Modified Kconfig/Makefile changes a bit. Tested host part only. ] Signed-off-by: Paul Zimmerman <paulz@synopsys.com> Acked-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat
-rw-r--r--drivers/usb/dwc2/Kconfig61
-rw-r--r--drivers/usb/dwc2/Makefile37
-rw-r--r--drivers/usb/dwc2/gadget.c (renamed from drivers/usb/gadget/s3c-hsotg.c)415
-rw-r--r--drivers/usb/gadget/Kconfig6
-rw-r--r--drivers/usb/gadget/Makefile1
-rw-r--r--drivers/usb/gadget/s3c-hsotg.h378
6 files changed, 273 insertions, 625 deletions
diff --git a/drivers/usb/dwc2/Kconfig b/drivers/usb/dwc2/Kconfig
index be947d673844..f93807b3631a 100644
--- a/drivers/usb/dwc2/Kconfig
+++ b/drivers/usb/dwc2/Kconfig
@@ -1,25 +1,58 @@
1config USB_DWC2 1config USB_DWC2
2 tristate "DesignWare USB2 DRD Core Support" 2 bool "DesignWare USB2 DRD Core Support"
3 depends on USB 3 depends on USB
4 help 4 help
5 Say Y or M here if your system has a Dual Role HighSpeed 5 Say Y here if your system has a Dual Role Hi-Speed USB
6 USB controller based on the DesignWare HSOTG IP Core. 6 controller based on the DesignWare HSOTG IP Core.
7 7
8 If you choose to build this driver as dynamically linked 8 For host mode, if you choose to build the driver as dynamically
9 modules, the core module will be called dwc2.ko, the 9 linked modules, the core module will be called dwc2.ko, the PCI
10 PCI bus interface module (if you have a PCI bus system) 10 bus interface module (if you have a PCI bus system) will be
11 will be called dwc2_pci.ko and the platform interface module 11 called dwc2_pci.ko, and the platform interface module (for
12 (for controllers directly connected to the CPU) will be called 12 controllers directly connected to the CPU) will be called
13 dwc2_platform.ko. 13 dwc2_platform.ko. For gadget mode, there will be a single
14 module called dwc2_gadget.ko.
14 15
15 NOTE: This driver at present only implements the Host mode 16 NOTE: The s3c-hsotg driver is now renamed to dwc2_gadget. The
16 of the controller. The existing s3c-hsotg driver supports 17 host and gadget drivers are still currently separate drivers.
17 Peripheral mode, but only for the Samsung S3C platforms. 18 There are plans to merge the dwc2_gadget driver with the dwc2
18 There are plans to merge the s3c-hsotg driver with this 19 host driver in the near future to create a dual-role driver.
19 driver in the near future to create a dual-role driver.
20 20
21if USB_DWC2 21if USB_DWC2
22 22
23config USB_DWC2_HOST
24 tristate "Host only mode"
25 depends on USB
26 help
27 The Designware USB2.0 high-speed host controller
28 integrated into many SoCs.
29
30config USB_DWC2_PLATFORM
31 bool "DWC2 Platform"
32 depends on USB_DWC2_HOST
33 default USB_DWC2_HOST
34 help
35 The Designware USB2.0 platform interface module for
36 controllers directly connected to the CPU. This is only
37 used for host mode.
38
39config USB_DWC2_PCI
40 bool "DWC2 PCI"
41 depends on USB_DWC2_HOST && PCI
42 default USB_DWC2_HOST
43 help
44 The Designware USB2.0 PCI interface module for controllers
45 connected to a PCI bus. This is only used for host mode.
46
47comment "Gadget mode requires USB Gadget support to be enabled"
48
49config USB_DWC2_PERIPHERAL
50 tristate "Gadget only mode"
51 depends on USB_GADGET
52 help
53 The Designware USB2.0 high-speed gadget controller
54 integrated into many SoCs.
55
23config USB_DWC2_DEBUG 56config USB_DWC2_DEBUG
24 bool "Enable Debugging Messages" 57 bool "Enable Debugging Messages"
25 help 58 help
diff --git a/drivers/usb/dwc2/Makefile b/drivers/usb/dwc2/Makefile
index 11529d3439b0..b73d2a527970 100644
--- a/drivers/usb/dwc2/Makefile
+++ b/drivers/usb/dwc2/Makefile
@@ -1,25 +1,28 @@
1ccflags-$(CONFIG_USB_DWC2_DEBUG) += -DDEBUG 1ccflags-$(CONFIG_USB_DWC2_DEBUG) += -DDEBUG
2ccflags-$(CONFIG_USB_DWC2_VERBOSE) += -DVERBOSE_DEBUG 2ccflags-$(CONFIG_USB_DWC2_VERBOSE) += -DVERBOSE_DEBUG
3 3
4obj-$(CONFIG_USB_DWC2) += dwc2.o 4obj-$(CONFIG_USB_DWC2_HOST) += dwc2.o
5 5dwc2-y := core.o core_intr.o
6dwc2-y += core.o core_intr.o
7
8# NOTE: This driver at present only implements the Host mode
9# of the controller. The existing s3c-hsotg driver supports
10# Peripheral mode, but only for the Samsung S3C platforms.
11# There are plans to merge the s3c-hsotg driver with this
12# driver in the near future to create a dual-role driver. Once
13# that is done, Host mode will become an optional feature that
14# is selected with a config option.
15
16dwc2-y += hcd.o hcd_intr.o 6dwc2-y += hcd.o hcd_intr.o
17dwc2-y += hcd_queue.o hcd_ddma.o 7dwc2-y += hcd_queue.o hcd_ddma.o
18 8
19ifneq ($(CONFIG_PCI),) 9# NOTE: The previous s3c-hsotg peripheral mode only driver has been moved to
20 obj-$(CONFIG_USB_DWC2) += dwc2_pci.o 10# this location and renamed gadget.c. When building for dynamically linked
11# modules, dwc2_gadget.ko will get built for peripheral mode. For host mode,
12# the core module will be dwc2.ko, the PCI bus interface module will called
13# dwc2_pci.ko and the platform interface module will be called dwc2_platform.ko.
14# At present the host and gadget driver will be separate drivers, but there
15# are plans in the near future to create a dual-role driver.
16
17ifneq ($(CONFIG_USB_DWC2_PCI),)
18 obj-$(CONFIG_USB_DWC2_HOST) += dwc2_pci.o
19 dwc2_pci-y := pci.o
20endif
21
22ifneq ($(CONFIG_USB_DWC2_PLATFORM),)
23 obj-$(CONFIG_USB_DWC2_HOST) += dwc2_platform.o
24 dwc2_platform-y := platform.o
21endif 25endif
22obj-$(CONFIG_USB_DWC2) += dwc2_platform.o
23 26
24dwc2_pci-y += pci.o 27obj-$(CONFIG_USB_DWC2_PERIPHERAL) += dwc2_gadget.o
25dwc2_platform-y += platform.o 28dwc2_gadget-y := gadget.o
diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/dwc2/gadget.c
index 2a9cb674926a..a8db29e54320 100644
--- a/drivers/usb/gadget/s3c-hsotg.c
+++ b/drivers/usb/dwc2/gadget.c
@@ -37,7 +37,7 @@
37#include <linux/usb/phy.h> 37#include <linux/usb/phy.h>
38#include <linux/platform_data/s3c-hsotg.h> 38#include <linux/platform_data/s3c-hsotg.h>
39 39
40#include "s3c-hsotg.h" 40#include "hw.h"
41 41
42static const char * const s3c_hsotg_supply_names[] = { 42static const char * const s3c_hsotg_supply_names[] = {
43 "vusb_d", /* digital USB supply, 1.2V */ 43 "vusb_d", /* digital USB supply, 1.2V */
@@ -340,9 +340,8 @@ static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg)
340 /* set FIFO sizes to 2048/1024 */ 340 /* set FIFO sizes to 2048/1024 */
341 341
342 writel(2048, hsotg->regs + GRXFSIZ); 342 writel(2048, hsotg->regs + GRXFSIZ);
343 writel(GNPTXFSIZ_NPTxFStAddr(2048) | 343 writel((2048 << FIFOSIZE_STARTADDR_SHIFT) |
344 GNPTXFSIZ_NPTxFDep(1024), 344 (1024 << FIFOSIZE_DEPTH_SHIFT), hsotg->regs + GNPTXFSIZ);
345 hsotg->regs + GNPTXFSIZ);
346 345
347 /* 346 /*
348 * arange all the rest of the TX FIFOs, as some versions of this 347 * arange all the rest of the TX FIFOs, as some versions of this
@@ -362,10 +361,10 @@ static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg)
362 361
363 for (ep = 1; ep <= 15; ep++) { 362 for (ep = 1; ep <= 15; ep++) {
364 val = addr; 363 val = addr;
365 val |= size << DPTXFSIZn_DPTxFSize_SHIFT; 364 val |= size << FIFOSIZE_DEPTH_SHIFT;
366 addr += size; 365 addr += size;
367 366
368 writel(val, hsotg->regs + DPTXFSIZn(ep)); 367 writel(val, hsotg->regs + DPTXFSIZN(ep));
369 } 368 }
370 369
371 /* 370 /*
@@ -373,15 +372,15 @@ static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg)
373 * all fifos are flushed before continuing 372 * all fifos are flushed before continuing
374 */ 373 */
375 374
376 writel(GRSTCTL_TxFNum(0x10) | GRSTCTL_TxFFlsh | 375 writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
377 GRSTCTL_RxFFlsh, hsotg->regs + GRSTCTL); 376 GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL);
378 377
379 /* wait until the fifos are both flushed */ 378 /* wait until the fifos are both flushed */
380 timeout = 100; 379 timeout = 100;
381 while (1) { 380 while (1) {
382 val = readl(hsotg->regs + GRSTCTL); 381 val = readl(hsotg->regs + GRSTCTL);
383 382
384 if ((val & (GRSTCTL_TxFFlsh | GRSTCTL_RxFFlsh)) == 0) 383 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
385 break; 384 break;
386 385
387 if (--timeout == 0) { 386 if (--timeout == 0) {
@@ -495,14 +494,14 @@ static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
495 * how much data is left in the fifo. 494 * how much data is left in the fifo.
496 */ 495 */
497 496
498 size_left = DxEPTSIZ_XferSize_GET(epsize); 497 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
499 498
500 /* 499 /*
501 * if shared fifo, we cannot write anything until the 500 * if shared fifo, we cannot write anything until the
502 * previous data has been completely sent. 501 * previous data has been completely sent.
503 */ 502 */
504 if (hs_ep->fifo_load != 0) { 503 if (hs_ep->fifo_load != 0) {
505 s3c_hsotg_en_gsint(hsotg, GINTSTS_PTxFEmp); 504 s3c_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
506 return -ENOSPC; 505 return -ENOSPC;
507 } 506 }
508 507
@@ -523,7 +522,7 @@ static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
523 __func__, can_write); 522 __func__, can_write);
524 523
525 if (can_write <= 0) { 524 if (can_write <= 0) {
526 s3c_hsotg_en_gsint(hsotg, GINTSTS_PTxFEmp); 525 s3c_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
527 return -ENOSPC; 526 return -ENOSPC;
528 } 527 }
529 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { 528 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
@@ -532,16 +531,16 @@ static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
532 can_write &= 0xffff; 531 can_write &= 0xffff;
533 can_write *= 4; 532 can_write *= 4;
534 } else { 533 } else {
535 if (GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts) == 0) { 534 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
536 dev_dbg(hsotg->dev, 535 dev_dbg(hsotg->dev,
537 "%s: no queue slots available (0x%08x)\n", 536 "%s: no queue slots available (0x%08x)\n",
538 __func__, gnptxsts); 537 __func__, gnptxsts);
539 538
540 s3c_hsotg_en_gsint(hsotg, GINTSTS_NPTxFEmp); 539 s3c_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
541 return -ENOSPC; 540 return -ENOSPC;
542 } 541 }
543 542
544 can_write = GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts); 543 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
545 can_write *= 4; /* fifo size is in 32bit quantities. */ 544 can_write *= 4; /* fifo size is in 32bit quantities. */
546 } 545 }
547 546
@@ -569,8 +568,8 @@ static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
569 /* it's needed only when we do not use dedicated fifos */ 568 /* it's needed only when we do not use dedicated fifos */
570 if (!hsotg->dedicated_fifos) 569 if (!hsotg->dedicated_fifos)
571 s3c_hsotg_en_gsint(hsotg, 570 s3c_hsotg_en_gsint(hsotg,
572 periodic ? GINTSTS_PTxFEmp : 571 periodic ? GINTSTS_PTXFEMP :
573 GINTSTS_NPTxFEmp); 572 GINTSTS_NPTXFEMP);
574 } 573 }
575 574
576 /* see if we can write data */ 575 /* see if we can write data */
@@ -598,8 +597,8 @@ static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
598 /* it's needed only when we do not use dedicated fifos */ 597 /* it's needed only when we do not use dedicated fifos */
599 if (!hsotg->dedicated_fifos) 598 if (!hsotg->dedicated_fifos)
600 s3c_hsotg_en_gsint(hsotg, 599 s3c_hsotg_en_gsint(hsotg,
601 periodic ? GINTSTS_PTxFEmp : 600 periodic ? GINTSTS_PTXFEMP :
602 GINTSTS_NPTxFEmp); 601 GINTSTS_NPTXFEMP);
603 } 602 }
604 603
605 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n", 604 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
@@ -636,12 +635,12 @@ static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep)
636 unsigned maxpkt; 635 unsigned maxpkt;
637 636
638 if (index != 0) { 637 if (index != 0) {
639 maxsize = DxEPTSIZ_XferSize_LIMIT + 1; 638 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
640 maxpkt = DxEPTSIZ_PktCnt_LIMIT + 1; 639 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
641 } else { 640 } else {
642 maxsize = 64+64; 641 maxsize = 64+64;
643 if (hs_ep->dir_in) 642 if (hs_ep->dir_in)
644 maxpkt = DIEPTSIZ0_PktCnt_LIMIT + 1; 643 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
645 else 644 else
646 maxpkt = 2; 645 maxpkt = 2;
647 } 646 }
@@ -710,7 +709,7 @@ static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
710 /* If endpoint is stalled, we will restart request later */ 709 /* If endpoint is stalled, we will restart request later */
711 ctrl = readl(hsotg->regs + epctrl_reg); 710 ctrl = readl(hsotg->regs + epctrl_reg);
712 711
713 if (ctrl & DxEPCTL_Stall) { 712 if (ctrl & DXEPCTL_STALL) {
714 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); 713 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
715 return; 714 return;
716 } 715 }
@@ -750,9 +749,9 @@ static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
750 749
751 if (dir_in && index != 0) 750 if (dir_in && index != 0)
752 if (hs_ep->isochronous) 751 if (hs_ep->isochronous)
753 epsize = DxEPTSIZ_MC(packets); 752 epsize = DXEPTSIZ_MC(packets);
754 else 753 else
755 epsize = DxEPTSIZ_MC(1); 754 epsize = DXEPTSIZ_MC(1);
756 else 755 else
757 epsize = 0; 756 epsize = 0;
758 757
@@ -766,8 +765,8 @@ static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
766 packets++; 765 packets++;
767 } 766 }
768 767
769 epsize |= DxEPTSIZ_PktCnt(packets); 768 epsize |= DXEPTSIZ_PKTCNT(packets);
770 epsize |= DxEPTSIZ_XferSize(length); 769 epsize |= DXEPTSIZ_XFERSIZE(length);
771 770
772 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n", 771 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
773 __func__, packets, length, ureq->length, epsize, epsize_reg); 772 __func__, packets, length, ureq->length, epsize, epsize_reg);
@@ -793,8 +792,8 @@ static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
793 __func__, &ureq->dma, dma_reg); 792 __func__, &ureq->dma, dma_reg);
794 } 793 }
795 794
796 ctrl |= DxEPCTL_EPEna; /* ensure ep enabled */ 795 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
797 ctrl |= DxEPCTL_USBActEp; 796 ctrl |= DXEPCTL_USBACTEP;
798 797
799 dev_dbg(hsotg->dev, "setup req:%d\n", hsotg->setup); 798 dev_dbg(hsotg->dev, "setup req:%d\n", hsotg->setup);
800 799
@@ -802,7 +801,7 @@ static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
802 if (hsotg->setup && index == 0) 801 if (hsotg->setup && index == 0)
803 hsotg->setup = 0; 802 hsotg->setup = 0;
804 else 803 else
805 ctrl |= DxEPCTL_CNAK; /* clear NAK set by core */ 804 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
806 805
807 806
808 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); 807 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
@@ -828,7 +827,7 @@ static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
828 * to debugging to see what is going on. 827 * to debugging to see what is going on.
829 */ 828 */
830 if (dir_in) 829 if (dir_in)
831 writel(DIEPMSK_INTknTXFEmpMsk, 830 writel(DIEPMSK_INTKNTXFEMPMSK,
832 hsotg->regs + DIEPINT(index)); 831 hsotg->regs + DIEPINT(index));
833 832
834 /* 833 /*
@@ -837,12 +836,12 @@ static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
837 */ 836 */
838 837
839 /* check ep is enabled */ 838 /* check ep is enabled */
840 if (!(readl(hsotg->regs + epctrl_reg) & DxEPCTL_EPEna)) 839 if (!(readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA))
841 dev_warn(hsotg->dev, 840 dev_warn(hsotg->dev,
842 "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n", 841 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
843 index, readl(hsotg->regs + epctrl_reg)); 842 index, readl(hsotg->regs + epctrl_reg));
844 843
845 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", 844 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
846 __func__, readl(hsotg->regs + epctrl_reg)); 845 __func__, readl(hsotg->regs + epctrl_reg));
847 846
848 /* enable ep interrupts */ 847 /* enable ep interrupts */
@@ -1205,12 +1204,12 @@ static void s3c_hsotg_stall_ep0(struct s3c_hsotg *hsotg) {
1205 */ 1204 */
1206 1205
1207 ctrl = readl(hsotg->regs + reg); 1206 ctrl = readl(hsotg->regs + reg);
1208 ctrl |= DxEPCTL_Stall; 1207 ctrl |= DXEPCTL_STALL;
1209 ctrl |= DxEPCTL_CNAK; 1208 ctrl |= DXEPCTL_CNAK;
1210 writel(ctrl, hsotg->regs + reg); 1209 writel(ctrl, hsotg->regs + reg);
1211 1210
1212 dev_dbg(hsotg->dev, 1211 dev_dbg(hsotg->dev,
1213 "written DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n", 1212 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1214 ctrl, reg, readl(hsotg->regs + reg)); 1213 ctrl, reg, readl(hsotg->regs + reg));
1215 1214
1216 /* 1215 /*
@@ -1262,8 +1261,8 @@ static void s3c_hsotg_process_control(struct s3c_hsotg *hsotg,
1262 case USB_REQ_SET_ADDRESS: 1261 case USB_REQ_SET_ADDRESS:
1263 s3c_hsotg_disconnect(hsotg); 1262 s3c_hsotg_disconnect(hsotg);
1264 dcfg = readl(hsotg->regs + DCFG); 1263 dcfg = readl(hsotg->regs + DCFG);
1265 dcfg &= ~DCFG_DevAddr_MASK; 1264 dcfg &= ~DCFG_DEVADDR_MASK;
1266 dcfg |= ctrl->wValue << DCFG_DevAddr_SHIFT; 1265 dcfg |= ctrl->wValue << DCFG_DEVADDR_SHIFT;
1267 writel(dcfg, hsotg->regs + DCFG); 1266 writel(dcfg, hsotg->regs + DCFG);
1268 1267
1269 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); 1268 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
@@ -1458,7 +1457,7 @@ static void s3c_hsotg_rx_data(struct s3c_hsotg *hsotg, int ep_idx, int size)
1458 int ptr; 1457 int ptr;
1459 1458
1460 dev_warn(hsotg->dev, 1459 dev_warn(hsotg->dev,
1461 "%s: FIFO %d bytes on ep%d but no req (DxEPCTl=0x%08x)\n", 1460 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
1462 __func__, size, ep_idx, epctl); 1461 __func__, size, ep_idx, epctl);
1463 1462
1464 /* dump the data from the FIFO, we've nothing we can do */ 1463 /* dump the data from the FIFO, we've nothing we can do */
@@ -1530,13 +1529,13 @@ static void s3c_hsotg_send_zlp(struct s3c_hsotg *hsotg,
1530 dev_dbg(hsotg->dev, "sending zero-length packet\n"); 1529 dev_dbg(hsotg->dev, "sending zero-length packet\n");
1531 1530
1532 /* issue a zero-sized packet to terminate this */ 1531 /* issue a zero-sized packet to terminate this */
1533 writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) | 1532 writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1534 DxEPTSIZ_XferSize(0), hsotg->regs + DIEPTSIZ(0)); 1533 DXEPTSIZ_XFERSIZE(0), hsotg->regs + DIEPTSIZ(0));
1535 1534
1536 ctrl = readl(hsotg->regs + DIEPCTL0); 1535 ctrl = readl(hsotg->regs + DIEPCTL0);
1537 ctrl |= DxEPCTL_CNAK; /* clear NAK set by core */ 1536 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1538 ctrl |= DxEPCTL_EPEna; /* ensure ep enabled */ 1537 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1539 ctrl |= DxEPCTL_USBActEp; 1538 ctrl |= DXEPCTL_USBACTEP;
1540 writel(ctrl, hsotg->regs + DIEPCTL0); 1539 writel(ctrl, hsotg->regs + DIEPCTL0);
1541} 1540}
1542 1541
@@ -1557,7 +1556,7 @@ static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
1557 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum]; 1556 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum];
1558 struct s3c_hsotg_req *hs_req = hs_ep->req; 1557 struct s3c_hsotg_req *hs_req = hs_ep->req;
1559 struct usb_request *req = &hs_req->req; 1558 struct usb_request *req = &hs_req->req;
1560 unsigned size_left = DxEPTSIZ_XferSize_GET(epsize); 1559 unsigned size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
1561 int result = 0; 1560 int result = 0;
1562 1561
1563 if (!hs_req) { 1562 if (!hs_req) {
@@ -1657,24 +1656,22 @@ static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg)
1657 1656
1658 WARN_ON(using_dma(hsotg)); 1657 WARN_ON(using_dma(hsotg));
1659 1658
1660 epnum = grxstsr & GRXSTS_EPNum_MASK; 1659 epnum = grxstsr & GRXSTS_EPNUM_MASK;
1661 status = grxstsr & GRXSTS_PktSts_MASK; 1660 status = grxstsr & GRXSTS_PKTSTS_MASK;
1662 1661
1663 size = grxstsr & GRXSTS_ByteCnt_MASK; 1662 size = grxstsr & GRXSTS_BYTECNT_MASK;
1664 size >>= GRXSTS_ByteCnt_SHIFT; 1663 size >>= GRXSTS_BYTECNT_SHIFT;
1665 1664
1666 if (1) 1665 if (1)
1667 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n", 1666 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1668 __func__, grxstsr, size, epnum); 1667 __func__, grxstsr, size, epnum);
1669 1668
1670#define __status(x) ((x) >> GRXSTS_PktSts_SHIFT) 1669 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
1671 1670 case GRXSTS_PKTSTS_GLOBALOUTNAK:
1672 switch (status >> GRXSTS_PktSts_SHIFT) { 1671 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
1673 case __status(GRXSTS_PktSts_GlobalOutNAK):
1674 dev_dbg(hsotg->dev, "GlobalOutNAK\n");
1675 break; 1672 break;
1676 1673
1677 case __status(GRXSTS_PktSts_OutDone): 1674 case GRXSTS_PKTSTS_OUTDONE:
1678 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n", 1675 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1679 s3c_hsotg_read_frameno(hsotg)); 1676 s3c_hsotg_read_frameno(hsotg));
1680 1677
@@ -1682,7 +1679,7 @@ static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg)
1682 s3c_hsotg_handle_outdone(hsotg, epnum, false); 1679 s3c_hsotg_handle_outdone(hsotg, epnum, false);
1683 break; 1680 break;
1684 1681
1685 case __status(GRXSTS_PktSts_SetupDone): 1682 case GRXSTS_PKTSTS_SETUPDONE:
1686 dev_dbg(hsotg->dev, 1683 dev_dbg(hsotg->dev,
1687 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", 1684 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1688 s3c_hsotg_read_frameno(hsotg), 1685 s3c_hsotg_read_frameno(hsotg),
@@ -1691,11 +1688,11 @@ static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg)
1691 s3c_hsotg_handle_outdone(hsotg, epnum, true); 1688 s3c_hsotg_handle_outdone(hsotg, epnum, true);
1692 break; 1689 break;
1693 1690
1694 case __status(GRXSTS_PktSts_OutRX): 1691 case GRXSTS_PKTSTS_OUTRX:
1695 s3c_hsotg_rx_data(hsotg, epnum, size); 1692 s3c_hsotg_rx_data(hsotg, epnum, size);
1696 break; 1693 break;
1697 1694
1698 case __status(GRXSTS_PktSts_SetupRX): 1695 case GRXSTS_PKTSTS_SETUPRX:
1699 dev_dbg(hsotg->dev, 1696 dev_dbg(hsotg->dev,
1700 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", 1697 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1701 s3c_hsotg_read_frameno(hsotg), 1698 s3c_hsotg_read_frameno(hsotg),
@@ -1761,7 +1758,7 @@ static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg *hsotg,
1761 hs_ep->ep.maxpacket = mps; 1758 hs_ep->ep.maxpacket = mps;
1762 hs_ep->mc = 1; 1759 hs_ep->mc = 1;
1763 } else { 1760 } else {
1764 mpsval = mps & DxEPCTL_MPS_MASK; 1761 mpsval = mps & DXEPCTL_MPS_MASK;
1765 if (mpsval > 1024) 1762 if (mpsval > 1024)
1766 goto bad_mps; 1763 goto bad_mps;
1767 mcval = ((mps >> 11) & 0x3) + 1; 1764 mcval = ((mps >> 11) & 0x3) + 1;
@@ -1777,13 +1774,13 @@ static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg *hsotg,
1777 */ 1774 */
1778 1775
1779 reg = readl(regs + DIEPCTL(ep)); 1776 reg = readl(regs + DIEPCTL(ep));
1780 reg &= ~DxEPCTL_MPS_MASK; 1777 reg &= ~DXEPCTL_MPS_MASK;
1781 reg |= mpsval; 1778 reg |= mpsval;
1782 writel(reg, regs + DIEPCTL(ep)); 1779 writel(reg, regs + DIEPCTL(ep));
1783 1780
1784 if (ep) { 1781 if (ep) {
1785 reg = readl(regs + DOEPCTL(ep)); 1782 reg = readl(regs + DOEPCTL(ep));
1786 reg &= ~DxEPCTL_MPS_MASK; 1783 reg &= ~DXEPCTL_MPS_MASK;
1787 reg |= mpsval; 1784 reg |= mpsval;
1788 writel(reg, regs + DOEPCTL(ep)); 1785 writel(reg, regs + DOEPCTL(ep));
1789 } 1786 }
@@ -1804,7 +1801,7 @@ static void s3c_hsotg_txfifo_flush(struct s3c_hsotg *hsotg, unsigned int idx)
1804 int timeout; 1801 int timeout;
1805 int val; 1802 int val;
1806 1803
1807 writel(GRSTCTL_TxFNum(idx) | GRSTCTL_TxFFlsh, 1804 writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
1808 hsotg->regs + GRSTCTL); 1805 hsotg->regs + GRSTCTL);
1809 1806
1810 /* wait until the fifo is flushed */ 1807 /* wait until the fifo is flushed */
@@ -1813,7 +1810,7 @@ static void s3c_hsotg_txfifo_flush(struct s3c_hsotg *hsotg, unsigned int idx)
1813 while (1) { 1810 while (1) {
1814 val = readl(hsotg->regs + GRSTCTL); 1811 val = readl(hsotg->regs + GRSTCTL);
1815 1812
1816 if ((val & (GRSTCTL_TxFFlsh)) == 0) 1813 if ((val & (GRSTCTL_TXFFLSH)) == 0)
1817 break; 1814 break;
1818 1815
1819 if (--timeout == 0) { 1816 if (--timeout == 0) {
@@ -1896,7 +1893,7 @@ static void s3c_hsotg_complete_in(struct s3c_hsotg *hsotg,
1896 * aligned). 1893 * aligned).
1897 */ 1894 */
1898 1895
1899 size_left = DxEPTSIZ_XferSize_GET(epsize); 1896 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
1900 1897
1901 size_done = hs_ep->size_loaded - size_left; 1898 size_done = hs_ep->size_loaded - size_left;
1902 size_done += hs_ep->last_load; 1899 size_done += hs_ep->last_load;
@@ -1963,17 +1960,17 @@ static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
1963 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n", 1960 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1964 __func__, idx, dir_in ? "in" : "out", ints); 1961 __func__, idx, dir_in ? "in" : "out", ints);
1965 1962
1966 if (ints & DxEPINT_XferCompl) { 1963 if (ints & DXEPINT_XFERCOMPL) {
1967 if (hs_ep->isochronous && hs_ep->interval == 1) { 1964 if (hs_ep->isochronous && hs_ep->interval == 1) {
1968 if (ctrl & DxEPCTL_EOFrNum) 1965 if (ctrl & DXEPCTL_EOFRNUM)
1969 ctrl |= DxEPCTL_SetEvenFr; 1966 ctrl |= DXEPCTL_SETEVENFR;
1970 else 1967 else
1971 ctrl |= DxEPCTL_SetOddFr; 1968 ctrl |= DXEPCTL_SETODDFR;
1972 writel(ctrl, hsotg->regs + epctl_reg); 1969 writel(ctrl, hsotg->regs + epctl_reg);
1973 } 1970 }
1974 1971
1975 dev_dbg(hsotg->dev, 1972 dev_dbg(hsotg->dev,
1976 "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n", 1973 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
1977 __func__, readl(hsotg->regs + epctl_reg), 1974 __func__, readl(hsotg->regs + epctl_reg),
1978 readl(hsotg->regs + epsiz_reg)); 1975 readl(hsotg->regs + epsiz_reg));
1979 1976
@@ -1996,7 +1993,7 @@ static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
1996 } 1993 }
1997 } 1994 }
1998 1995
1999 if (ints & DxEPINT_EPDisbld) { 1996 if (ints & DXEPINT_EPDISBLD) {
2000 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); 1997 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2001 1998
2002 if (dir_in) { 1999 if (dir_in) {
@@ -2004,20 +2001,20 @@ static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
2004 2001
2005 s3c_hsotg_txfifo_flush(hsotg, idx); 2002 s3c_hsotg_txfifo_flush(hsotg, idx);
2006 2003
2007 if ((epctl & DxEPCTL_Stall) && 2004 if ((epctl & DXEPCTL_STALL) &&
2008 (epctl & DxEPCTL_EPType_Bulk)) { 2005 (epctl & DXEPCTL_EPTYPE_BULK)) {
2009 int dctl = readl(hsotg->regs + DCTL); 2006 int dctl = readl(hsotg->regs + DCTL);
2010 2007
2011 dctl |= DCTL_CGNPInNAK; 2008 dctl |= DCTL_CGNPINNAK;
2012 writel(dctl, hsotg->regs + DCTL); 2009 writel(dctl, hsotg->regs + DCTL);
2013 } 2010 }
2014 } 2011 }
2015 } 2012 }
2016 2013
2017 if (ints & DxEPINT_AHBErr) 2014 if (ints & DXEPINT_AHBERR)
2018 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__); 2015 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
2019 2016
2020 if (ints & DxEPINT_Setup) { /* Setup or Timeout */ 2017 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
2021 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__); 2018 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
2022 2019
2023 if (using_dma(hsotg) && idx == 0) { 2020 if (using_dma(hsotg) && idx == 0) {
@@ -2035,25 +2032,25 @@ static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
2035 } 2032 }
2036 } 2033 }
2037 2034
2038 if (ints & DxEPINT_Back2BackSetup) 2035 if (ints & DXEPINT_BACK2BACKSETUP)
2039 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__); 2036 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
2040 2037
2041 if (dir_in && !hs_ep->isochronous) { 2038 if (dir_in && !hs_ep->isochronous) {
2042 /* not sure if this is important, but we'll clear it anyway */ 2039 /* not sure if this is important, but we'll clear it anyway */
2043 if (ints & DIEPMSK_INTknTXFEmpMsk) { 2040 if (ints & DIEPMSK_INTKNTXFEMPMSK) {
2044 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n", 2041 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
2045 __func__, idx); 2042 __func__, idx);
2046 } 2043 }
2047 2044
2048 /* this probably means something bad is happening */ 2045 /* this probably means something bad is happening */
2049 if (ints & DIEPMSK_INTknEPMisMsk) { 2046 if (ints & DIEPMSK_INTKNEPMISMSK) {
2050 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n", 2047 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
2051 __func__, idx); 2048 __func__, idx);
2052 } 2049 }
2053 2050
2054 /* FIFO has space or is empty (see GAHBCFG) */ 2051 /* FIFO has space or is empty (see GAHBCFG) */
2055 if (hsotg->dedicated_fifos && 2052 if (hsotg->dedicated_fifos &&
2056 ints & DIEPMSK_TxFIFOEmpty) { 2053 ints & DIEPMSK_TXFIFOEMPTY) {
2057 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n", 2054 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
2058 __func__, idx); 2055 __func__, idx);
2059 if (!using_dma(hsotg)) 2056 if (!using_dma(hsotg))
@@ -2089,21 +2086,21 @@ static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg)
2089 */ 2086 */
2090 2087
2091 /* catch both EnumSpd_FS and EnumSpd_FS48 */ 2088 /* catch both EnumSpd_FS and EnumSpd_FS48 */
2092 switch (dsts & DSTS_EnumSpd_MASK) { 2089 switch (dsts & DSTS_ENUMSPD_MASK) {
2093 case DSTS_EnumSpd_FS: 2090 case DSTS_ENUMSPD_FS:
2094 case DSTS_EnumSpd_FS48: 2091 case DSTS_ENUMSPD_FS48:
2095 hsotg->gadget.speed = USB_SPEED_FULL; 2092 hsotg->gadget.speed = USB_SPEED_FULL;
2096 ep0_mps = EP0_MPS_LIMIT; 2093 ep0_mps = EP0_MPS_LIMIT;
2097 ep_mps = 1023; 2094 ep_mps = 1023;
2098 break; 2095 break;
2099 2096
2100 case DSTS_EnumSpd_HS: 2097 case DSTS_ENUMSPD_HS:
2101 hsotg->gadget.speed = USB_SPEED_HIGH; 2098 hsotg->gadget.speed = USB_SPEED_HIGH;
2102 ep0_mps = EP0_MPS_LIMIT; 2099 ep0_mps = EP0_MPS_LIMIT;
2103 ep_mps = 1024; 2100 ep_mps = 1024;
2104 break; 2101 break;
2105 2102
2106 case DSTS_EnumSpd_LS: 2103 case DSTS_ENUMSPD_LS:
2107 hsotg->gadget.speed = USB_SPEED_LOW; 2104 hsotg->gadget.speed = USB_SPEED_LOW;
2108 /* 2105 /*
2109 * note, we don't actually support LS in this driver at the 2106 * note, we don't actually support LS in this driver at the
@@ -2226,9 +2223,9 @@ static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg *hsotg, bool periodic)
2226} 2223}
2227 2224
2228/* IRQ flags which will trigger a retry around the IRQ loop */ 2225/* IRQ flags which will trigger a retry around the IRQ loop */
2229#define IRQ_RETRY_MASK (GINTSTS_NPTxFEmp | \ 2226#define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
2230 GINTSTS_PTxFEmp | \ 2227 GINTSTS_PTXFEMP | \
2231 GINTSTS_RxFLvl) 2228 GINTSTS_RXFLVL)
2232 2229
2233/** 2230/**
2234 * s3c_hsotg_corereset - issue softreset to the core 2231 * s3c_hsotg_corereset - issue softreset to the core
@@ -2244,14 +2241,14 @@ static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
2244 dev_dbg(hsotg->dev, "resetting core\n"); 2241 dev_dbg(hsotg->dev, "resetting core\n");
2245 2242
2246 /* issue soft reset */ 2243 /* issue soft reset */
2247 writel(GRSTCTL_CSftRst, hsotg->regs + GRSTCTL); 2244 writel(GRSTCTL_CSFTRST, hsotg->regs + GRSTCTL);
2248 2245
2249 timeout = 10000; 2246 timeout = 10000;
2250 do { 2247 do {
2251 grstctl = readl(hsotg->regs + GRSTCTL); 2248 grstctl = readl(hsotg->regs + GRSTCTL);
2252 } while ((grstctl & GRSTCTL_CSftRst) && timeout-- > 0); 2249 } while ((grstctl & GRSTCTL_CSFTRST) && timeout-- > 0);
2253 2250
2254 if (grstctl & GRSTCTL_CSftRst) { 2251 if (grstctl & GRSTCTL_CSFTRST) {
2255 dev_err(hsotg->dev, "Failed to get CSftRst asserted\n"); 2252 dev_err(hsotg->dev, "Failed to get CSftRst asserted\n");
2256 return -EINVAL; 2253 return -EINVAL;
2257 } 2254 }
@@ -2268,7 +2265,7 @@ static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
2268 return -ETIMEDOUT; 2265 return -ETIMEDOUT;
2269 } 2266 }
2270 2267
2271 if (!(grstctl & GRSTCTL_AHBIdle)) 2268 if (!(grstctl & GRSTCTL_AHBIDLE))
2272 continue; 2269 continue;
2273 2270
2274 break; /* reset done */ 2271 break; /* reset done */
@@ -2294,14 +2291,14 @@ static void s3c_hsotg_core_init(struct s3c_hsotg *hsotg)
2294 */ 2291 */
2295 2292
2296 /* set the PLL on, remove the HNP/SRP and set the PHY */ 2293 /* set the PLL on, remove the HNP/SRP and set the PHY */
2297 writel(hsotg->phyif | GUSBCFG_TOutCal(7) | 2294 writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) |
2298 (0x5 << 10), hsotg->regs + GUSBCFG); 2295 (0x5 << 10), hsotg->regs + GUSBCFG);
2299 2296
2300 s3c_hsotg_init_fifo(hsotg); 2297 s3c_hsotg_init_fifo(hsotg);
2301 2298
2302 __orr32(hsotg->regs + DCTL, DCTL_SftDiscon); 2299 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2303 2300
2304 writel(1 << 18 | DCFG_DevSpd_HS, hsotg->regs + DCFG); 2301 writel(1 << 18 | DCFG_DEVSPD_HS, hsotg->regs + DCFG);
2305 2302
2306 /* Clear any pending OTG interrupts */ 2303 /* Clear any pending OTG interrupts */
2307 writel(0xffffffff, hsotg->regs + GOTGINT); 2304 writel(0xffffffff, hsotg->regs + GOTGINT);
@@ -2309,21 +2306,21 @@ static void s3c_hsotg_core_init(struct s3c_hsotg *hsotg)
2309 /* Clear any pending interrupts */ 2306 /* Clear any pending interrupts */
2310 writel(0xffffffff, hsotg->regs + GINTSTS); 2307 writel(0xffffffff, hsotg->regs + GINTSTS);
2311 2308
2312 writel(GINTSTS_ErlySusp | GINTSTS_SessReqInt | 2309 writel(GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
2313 GINTSTS_GOUTNakEff | GINTSTS_GINNakEff | 2310 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
2314 GINTSTS_ConIDStsChng | GINTSTS_USBRst | 2311 GINTSTS_CONIDSTSCHNG | GINTSTS_USBRST |
2315 GINTSTS_EnumDone | GINTSTS_OTGInt | 2312 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
2316 GINTSTS_USBSusp | GINTSTS_WkUpInt, 2313 GINTSTS_USBSUSP | GINTSTS_WKUPINT,
2317 hsotg->regs + GINTMSK); 2314 hsotg->regs + GINTMSK);
2318 2315
2319 if (using_dma(hsotg)) 2316 if (using_dma(hsotg))
2320 writel(GAHBCFG_GlblIntrEn | GAHBCFG_DMAEn | 2317 writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
2321 GAHBCFG_HBstLen_Incr4, 2318 GAHBCFG_HBSTLEN_INCR4,
2322 hsotg->regs + GAHBCFG); 2319 hsotg->regs + GAHBCFG);
2323 else 2320 else
2324 writel(((hsotg->dedicated_fifos) ? (GAHBCFG_NPTxFEmpLvl | 2321 writel(((hsotg->dedicated_fifos) ? (GAHBCFG_NP_TXF_EMP_LVL |
2325 GAHBCFG_PTxFEmpLvl) : 0) | 2322 GAHBCFG_P_TXF_EMP_LVL) : 0) |
2326 GAHBCFG_GlblIntrEn, 2323 GAHBCFG_GLBL_INTR_EN,
2327 hsotg->regs + GAHBCFG); 2324 hsotg->regs + GAHBCFG);
2328 2325
2329 /* 2326 /*
@@ -2332,22 +2329,22 @@ static void s3c_hsotg_core_init(struct s3c_hsotg *hsotg)
2332 * interrupts. 2329 * interrupts.
2333 */ 2330 */
2334 2331
2335 writel(((hsotg->dedicated_fifos) ? DIEPMSK_TxFIFOEmpty | 2332 writel(((hsotg->dedicated_fifos) ? DIEPMSK_TXFIFOEMPTY |
2336 DIEPMSK_INTknTXFEmpMsk : 0) | 2333 DIEPMSK_INTKNTXFEMPMSK : 0) |
2337 DIEPMSK_EPDisbldMsk | DIEPMSK_XferComplMsk | 2334 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
2338 DIEPMSK_TimeOUTMsk | DIEPMSK_AHBErrMsk | 2335 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
2339 DIEPMSK_INTknEPMisMsk, 2336 DIEPMSK_INTKNEPMISMSK,
2340 hsotg->regs + DIEPMSK); 2337 hsotg->regs + DIEPMSK);
2341 2338
2342 /* 2339 /*
2343 * don't need XferCompl, we get that from RXFIFO in slave mode. In 2340 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2344 * DMA mode we may need this. 2341 * DMA mode we may need this.
2345 */ 2342 */
2346 writel((using_dma(hsotg) ? (DIEPMSK_XferComplMsk | 2343 writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
2347 DIEPMSK_TimeOUTMsk) : 0) | 2344 DIEPMSK_TIMEOUTMSK) : 0) |
2348 DOEPMSK_EPDisbldMsk | DOEPMSK_AHBErrMsk | 2345 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
2349 DOEPMSK_SetupMsk, 2346 DOEPMSK_SETUPMSK,
2350 hsotg->regs + DOEPMSK); 2347 hsotg->regs + DOEPMSK);
2351 2348
2352 writel(0, hsotg->regs + DAINTMSK); 2349 writel(0, hsotg->regs + DAINTMSK);
2353 2350
@@ -2356,7 +2353,7 @@ static void s3c_hsotg_core_init(struct s3c_hsotg *hsotg)
2356 readl(hsotg->regs + DOEPCTL0)); 2353 readl(hsotg->regs + DOEPCTL0));
2357 2354
2358 /* enable in and out endpoint interrupts */ 2355 /* enable in and out endpoint interrupts */
2359 s3c_hsotg_en_gsint(hsotg, GINTSTS_OEPInt | GINTSTS_IEPInt); 2356 s3c_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
2360 2357
2361 /* 2358 /*
2362 * Enable the RXFIFO when in slave mode, as this is how we collect 2359 * Enable the RXFIFO when in slave mode, as this is how we collect
@@ -2364,15 +2361,15 @@ static void s3c_hsotg_core_init(struct s3c_hsotg *hsotg)
2364 * things we cannot process, so do not use it. 2361 * things we cannot process, so do not use it.
2365 */ 2362 */
2366 if (!using_dma(hsotg)) 2363 if (!using_dma(hsotg))
2367 s3c_hsotg_en_gsint(hsotg, GINTSTS_RxFLvl); 2364 s3c_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
2368 2365
2369 /* Enable interrupts for EP0 in and out */ 2366 /* Enable interrupts for EP0 in and out */
2370 s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1); 2367 s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2371 s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1); 2368 s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2372 2369
2373 __orr32(hsotg->regs + DCTL, DCTL_PWROnPrgDone); 2370 __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
2374 udelay(10); /* see openiboot */ 2371 udelay(10); /* see openiboot */
2375 __bic32(hsotg->regs + DCTL, DCTL_PWROnPrgDone); 2372 __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
2376 2373
2377 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + DCTL)); 2374 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + DCTL));
2378 2375
@@ -2382,17 +2379,17 @@ static void s3c_hsotg_core_init(struct s3c_hsotg *hsotg)
2382 */ 2379 */
2383 2380
2384 /* set to read 1 8byte packet */ 2381 /* set to read 1 8byte packet */
2385 writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) | 2382 writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2386 DxEPTSIZ_XferSize(8), hsotg->regs + DOEPTSIZ0); 2383 DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0);
2387 2384
2388 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) | 2385 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2389 DxEPCTL_CNAK | DxEPCTL_EPEna | 2386 DXEPCTL_CNAK | DXEPCTL_EPENA |
2390 DxEPCTL_USBActEp, 2387 DXEPCTL_USBACTEP,
2391 hsotg->regs + DOEPCTL0); 2388 hsotg->regs + DOEPCTL0);
2392 2389
2393 /* enable, but don't activate EP0in */ 2390 /* enable, but don't activate EP0in */
2394 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) | 2391 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2395 DxEPCTL_USBActEp, hsotg->regs + DIEPCTL0); 2392 DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0);
2396 2393
2397 s3c_hsotg_enqueue_setup(hsotg); 2394 s3c_hsotg_enqueue_setup(hsotg);
2398 2395
@@ -2401,14 +2398,14 @@ static void s3c_hsotg_core_init(struct s3c_hsotg *hsotg)
2401 readl(hsotg->regs + DOEPCTL0)); 2398 readl(hsotg->regs + DOEPCTL0));
2402 2399
2403 /* clear global NAKs */ 2400 /* clear global NAKs */
2404 writel(DCTL_CGOUTNak | DCTL_CGNPInNAK, 2401 writel(DCTL_CGOUTNAK | DCTL_CGNPINNAK,
2405 hsotg->regs + DCTL); 2402 hsotg->regs + DCTL);
2406 2403
2407 /* must be at-least 3ms to allow bus to see disconnect */ 2404 /* must be at-least 3ms to allow bus to see disconnect */
2408 mdelay(3); 2405 mdelay(3);
2409 2406
2410 /* remove the soft-disconnect and let's go */ 2407 /* remove the soft-disconnect and let's go */
2411 __bic32(hsotg->regs + DCTL, DCTL_SftDiscon); 2408 __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2412} 2409}
2413 2410
2414/** 2411/**
@@ -2433,7 +2430,7 @@ irq_retry:
2433 2430
2434 gintsts &= gintmsk; 2431 gintsts &= gintmsk;
2435 2432
2436 if (gintsts & GINTSTS_OTGInt) { 2433 if (gintsts & GINTSTS_OTGINT) {
2437 u32 otgint = readl(hsotg->regs + GOTGINT); 2434 u32 otgint = readl(hsotg->regs + GOTGINT);
2438 2435
2439 dev_info(hsotg->dev, "OTGInt: %08x\n", otgint); 2436 dev_info(hsotg->dev, "OTGInt: %08x\n", otgint);
@@ -2441,34 +2438,34 @@ irq_retry:
2441 writel(otgint, hsotg->regs + GOTGINT); 2438 writel(otgint, hsotg->regs + GOTGINT);
2442 } 2439 }
2443 2440
2444 if (gintsts & GINTSTS_SessReqInt) { 2441 if (gintsts & GINTSTS_SESSREQINT) {
2445 dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__); 2442 dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__);
2446 writel(GINTSTS_SessReqInt, hsotg->regs + GINTSTS); 2443 writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS);
2447 } 2444 }
2448 2445
2449 if (gintsts & GINTSTS_EnumDone) { 2446 if (gintsts & GINTSTS_ENUMDONE) {
2450 writel(GINTSTS_EnumDone, hsotg->regs + GINTSTS); 2447 writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS);
2451 2448
2452 s3c_hsotg_irq_enumdone(hsotg); 2449 s3c_hsotg_irq_enumdone(hsotg);
2453 } 2450 }
2454 2451
2455 if (gintsts & GINTSTS_ConIDStsChng) { 2452 if (gintsts & GINTSTS_CONIDSTSCHNG) {
2456 dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n", 2453 dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
2457 readl(hsotg->regs + DSTS), 2454 readl(hsotg->regs + DSTS),
2458 readl(hsotg->regs + GOTGCTL)); 2455 readl(hsotg->regs + GOTGCTL));
2459 2456
2460 writel(GINTSTS_ConIDStsChng, hsotg->regs + GINTSTS); 2457 writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS);
2461 } 2458 }
2462 2459
2463 if (gintsts & (GINTSTS_OEPInt | GINTSTS_IEPInt)) { 2460 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
2464 u32 daint = readl(hsotg->regs + DAINT); 2461 u32 daint = readl(hsotg->regs + DAINT);
2465 u32 daintmsk = readl(hsotg->regs + DAINTMSK); 2462 u32 daintmsk = readl(hsotg->regs + DAINTMSK);
2466 u32 daint_out, daint_in; 2463 u32 daint_out, daint_in;
2467 int ep; 2464 int ep;
2468 2465
2469 daint &= daintmsk; 2466 daint &= daintmsk;
2470 daint_out = daint >> DAINT_OutEP_SHIFT; 2467 daint_out = daint >> DAINT_OUTEP_SHIFT;
2471 daint_in = daint & ~(daint_out << DAINT_OutEP_SHIFT); 2468 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
2472 2469
2473 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint); 2470 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
2474 2471
@@ -2483,7 +2480,7 @@ irq_retry:
2483 } 2480 }
2484 } 2481 }
2485 2482
2486 if (gintsts & GINTSTS_USBRst) { 2483 if (gintsts & GINTSTS_USBRST) {
2487 2484
2488 u32 usb_status = readl(hsotg->regs + GOTGCTL); 2485 u32 usb_status = readl(hsotg->regs + GOTGCTL);
2489 2486
@@ -2491,7 +2488,7 @@ irq_retry:
2491 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", 2488 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2492 readl(hsotg->regs + GNPTXSTS)); 2489 readl(hsotg->regs + GNPTXSTS));
2493 2490
2494 writel(GINTSTS_USBRst, hsotg->regs + GINTSTS); 2491 writel(GINTSTS_USBRST, hsotg->regs + GINTSTS);
2495 2492
2496 if (usb_status & GOTGCTL_BSESVLD) { 2493 if (usb_status & GOTGCTL_BSESVLD) {
2497 if (time_after(jiffies, hsotg->last_rst + 2494 if (time_after(jiffies, hsotg->last_rst +
@@ -2508,7 +2505,7 @@ irq_retry:
2508 2505
2509 /* check both FIFOs */ 2506 /* check both FIFOs */
2510 2507
2511 if (gintsts & GINTSTS_NPTxFEmp) { 2508 if (gintsts & GINTSTS_NPTXFEMP) {
2512 dev_dbg(hsotg->dev, "NPTxFEmp\n"); 2509 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2513 2510
2514 /* 2511 /*
@@ -2517,20 +2514,20 @@ irq_retry:
2517 * it needs re-enabling 2514 * it needs re-enabling
2518 */ 2515 */
2519 2516
2520 s3c_hsotg_disable_gsint(hsotg, GINTSTS_NPTxFEmp); 2517 s3c_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
2521 s3c_hsotg_irq_fifoempty(hsotg, false); 2518 s3c_hsotg_irq_fifoempty(hsotg, false);
2522 } 2519 }
2523 2520
2524 if (gintsts & GINTSTS_PTxFEmp) { 2521 if (gintsts & GINTSTS_PTXFEMP) {
2525 dev_dbg(hsotg->dev, "PTxFEmp\n"); 2522 dev_dbg(hsotg->dev, "PTxFEmp\n");
2526 2523
2527 /* See note in GINTSTS_NPTxFEmp */ 2524 /* See note in GINTSTS_NPTxFEmp */
2528 2525
2529 s3c_hsotg_disable_gsint(hsotg, GINTSTS_PTxFEmp); 2526 s3c_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
2530 s3c_hsotg_irq_fifoempty(hsotg, true); 2527 s3c_hsotg_irq_fifoempty(hsotg, true);
2531 } 2528 }
2532 2529
2533 if (gintsts & GINTSTS_RxFLvl) { 2530 if (gintsts & GINTSTS_RXFLVL) {
2534 /* 2531 /*
2535 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty, 2532 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2536 * we need to retry s3c_hsotg_handle_rx if this is still 2533 * we need to retry s3c_hsotg_handle_rx if this is still
@@ -2540,28 +2537,28 @@ irq_retry:
2540 s3c_hsotg_handle_rx(hsotg); 2537 s3c_hsotg_handle_rx(hsotg);
2541 } 2538 }
2542 2539
2543 if (gintsts & GINTSTS_ModeMis) { 2540 if (gintsts & GINTSTS_MODEMIS) {
2544 dev_warn(hsotg->dev, "warning, mode mismatch triggered\n"); 2541 dev_warn(hsotg->dev, "warning, mode mismatch triggered\n");
2545 writel(GINTSTS_ModeMis, hsotg->regs + GINTSTS); 2542 writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS);
2546 } 2543 }
2547 2544
2548 if (gintsts & GINTSTS_USBSusp) { 2545 if (gintsts & GINTSTS_USBSUSP) {
2549 dev_info(hsotg->dev, "GINTSTS_USBSusp\n"); 2546 dev_info(hsotg->dev, "GINTSTS_USBSusp\n");
2550 writel(GINTSTS_USBSusp, hsotg->regs + GINTSTS); 2547 writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS);
2551 2548
2552 call_gadget(hsotg, suspend); 2549 call_gadget(hsotg, suspend);
2553 } 2550 }
2554 2551
2555 if (gintsts & GINTSTS_WkUpInt) { 2552 if (gintsts & GINTSTS_WKUPINT) {
2556 dev_info(hsotg->dev, "GINTSTS_WkUpIn\n"); 2553 dev_info(hsotg->dev, "GINTSTS_WkUpIn\n");
2557 writel(GINTSTS_WkUpInt, hsotg->regs + GINTSTS); 2554 writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
2558 2555
2559 call_gadget(hsotg, resume); 2556 call_gadget(hsotg, resume);
2560 } 2557 }
2561 2558
2562 if (gintsts & GINTSTS_ErlySusp) { 2559 if (gintsts & GINTSTS_ERLYSUSP) {
2563 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n"); 2560 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
2564 writel(GINTSTS_ErlySusp, hsotg->regs + GINTSTS); 2561 writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS);
2565 } 2562 }
2566 2563
2567 /* 2564 /*
@@ -2570,18 +2567,18 @@ irq_retry:
2570 * the occurrence. 2567 * the occurrence.
2571 */ 2568 */
2572 2569
2573 if (gintsts & GINTSTS_GOUTNakEff) { 2570 if (gintsts & GINTSTS_GOUTNAKEFF) {
2574 dev_info(hsotg->dev, "GOUTNakEff triggered\n"); 2571 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2575 2572
2576 writel(DCTL_CGOUTNak, hsotg->regs + DCTL); 2573 writel(DCTL_CGOUTNAK, hsotg->regs + DCTL);
2577 2574
2578 s3c_hsotg_dump(hsotg); 2575 s3c_hsotg_dump(hsotg);
2579 } 2576 }
2580 2577
2581 if (gintsts & GINTSTS_GINNakEff) { 2578 if (gintsts & GINTSTS_GINNAKEFF) {
2582 dev_info(hsotg->dev, "GINNakEff triggered\n"); 2579 dev_info(hsotg->dev, "GINNakEff triggered\n");
2583 2580
2584 writel(DCTL_CGNPInNAK, hsotg->regs + DCTL); 2581 writel(DCTL_CGNPINNAK, hsotg->regs + DCTL);
2585 2582
2586 s3c_hsotg_dump(hsotg); 2583 s3c_hsotg_dump(hsotg);
2587 } 2584 }
@@ -2645,14 +2642,14 @@ static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2645 2642
2646 spin_lock_irqsave(&hsotg->lock, flags); 2643 spin_lock_irqsave(&hsotg->lock, flags);
2647 2644
2648 epctrl &= ~(DxEPCTL_EPType_MASK | DxEPCTL_MPS_MASK); 2645 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
2649 epctrl |= DxEPCTL_MPS(mps); 2646 epctrl |= DXEPCTL_MPS(mps);
2650 2647
2651 /* 2648 /*
2652 * mark the endpoint as active, otherwise the core may ignore 2649 * mark the endpoint as active, otherwise the core may ignore
2653 * transactions entirely for this endpoint 2650 * transactions entirely for this endpoint
2654 */ 2651 */
2655 epctrl |= DxEPCTL_USBActEp; 2652 epctrl |= DXEPCTL_USBACTEP;
2656 2653
2657 /* 2654 /*
2658 * set the NAK status on the endpoint, otherwise we might try and 2655 * set the NAK status on the endpoint, otherwise we might try and
@@ -2661,7 +2658,7 @@ static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2661 * size register hasn't been set. 2658 * size register hasn't been set.
2662 */ 2659 */
2663 2660
2664 epctrl |= DxEPCTL_SNAK; 2661 epctrl |= DXEPCTL_SNAK;
2665 2662
2666 /* update the endpoint state */ 2663 /* update the endpoint state */
2667 s3c_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps); 2664 s3c_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps);
@@ -2677,15 +2674,15 @@ static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2677 2674
2678 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { 2675 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2679 case USB_ENDPOINT_XFER_ISOC: 2676 case USB_ENDPOINT_XFER_ISOC:
2680 epctrl |= DxEPCTL_EPType_Iso; 2677 epctrl |= DXEPCTL_EPTYPE_ISO;
2681 epctrl |= DxEPCTL_SetEvenFr; 2678 epctrl |= DXEPCTL_SETEVENFR;
2682 hs_ep->isochronous = 1; 2679 hs_ep->isochronous = 1;
2683 if (dir_in) 2680 if (dir_in)
2684 hs_ep->periodic = 1; 2681 hs_ep->periodic = 1;
2685 break; 2682 break;
2686 2683
2687 case USB_ENDPOINT_XFER_BULK: 2684 case USB_ENDPOINT_XFER_BULK:
2688 epctrl |= DxEPCTL_EPType_Bulk; 2685 epctrl |= DXEPCTL_EPTYPE_BULK;
2689 break; 2686 break;
2690 2687
2691 case USB_ENDPOINT_XFER_INT: 2688 case USB_ENDPOINT_XFER_INT:
@@ -2698,14 +2695,14 @@ static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2698 */ 2695 */
2699 2696
2700 hs_ep->periodic = 1; 2697 hs_ep->periodic = 1;
2701 epctrl |= DxEPCTL_TxFNum(index); 2698 epctrl |= DXEPCTL_TXFNUM(index);
2702 } 2699 }
2703 2700
2704 epctrl |= DxEPCTL_EPType_Intterupt; 2701 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
2705 break; 2702 break;
2706 2703
2707 case USB_ENDPOINT_XFER_CONTROL: 2704 case USB_ENDPOINT_XFER_CONTROL:
2708 epctrl |= DxEPCTL_EPType_Control; 2705 epctrl |= DXEPCTL_EPTYPE_CONTROL;
2709 break; 2706 break;
2710 } 2707 }
2711 2708
@@ -2714,11 +2711,11 @@ static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2714 * a unique tx-fifo even if it is non-periodic. 2711 * a unique tx-fifo even if it is non-periodic.
2715 */ 2712 */
2716 if (dir_in && hsotg->dedicated_fifos) 2713 if (dir_in && hsotg->dedicated_fifos)
2717 epctrl |= DxEPCTL_TxFNum(index); 2714 epctrl |= DXEPCTL_TXFNUM(index);
2718 2715
2719 /* for non control endpoints, set PID to D0 */ 2716 /* for non control endpoints, set PID to D0 */
2720 if (index) 2717 if (index)
2721 epctrl |= DxEPCTL_SetD0PID; 2718 epctrl |= DXEPCTL_SETD0PID;
2722 2719
2723 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", 2720 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2724 __func__, epctrl); 2721 __func__, epctrl);
@@ -2763,9 +2760,9 @@ static int s3c_hsotg_ep_disable(struct usb_ep *ep)
2763 2760
2764 2761
2765 ctrl = readl(hsotg->regs + epctrl_reg); 2762 ctrl = readl(hsotg->regs + epctrl_reg);
2766 ctrl &= ~DxEPCTL_EPEna; 2763 ctrl &= ~DXEPCTL_EPENA;
2767 ctrl &= ~DxEPCTL_USBActEp; 2764 ctrl &= ~DXEPCTL_USBACTEP;
2768 ctrl |= DxEPCTL_SNAK; 2765 ctrl |= DXEPCTL_SNAK;
2769 2766
2770 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); 2767 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2771 writel(ctrl, hsotg->regs + epctrl_reg); 2768 writel(ctrl, hsotg->regs + epctrl_reg);
@@ -2852,15 +2849,15 @@ static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2852 epctl = readl(hs->regs + epreg); 2849 epctl = readl(hs->regs + epreg);
2853 2850
2854 if (value) { 2851 if (value) {
2855 epctl |= DxEPCTL_Stall + DxEPCTL_SNAK; 2852 epctl |= DXEPCTL_STALL + DXEPCTL_SNAK;
2856 if (epctl & DxEPCTL_EPEna) 2853 if (epctl & DXEPCTL_EPENA)
2857 epctl |= DxEPCTL_EPDis; 2854 epctl |= DXEPCTL_EPDIS;
2858 } else { 2855 } else {
2859 epctl &= ~DxEPCTL_Stall; 2856 epctl &= ~DXEPCTL_STALL;
2860 xfertype = epctl & DxEPCTL_EPType_MASK; 2857 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
2861 if (xfertype == DxEPCTL_EPType_Bulk || 2858 if (xfertype == DXEPCTL_EPTYPE_BULK ||
2862 xfertype == DxEPCTL_EPType_Intterupt) 2859 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
2863 epctl |= DxEPCTL_SetD0PID; 2860 epctl |= DXEPCTL_SETD0PID;
2864 } 2861 }
2865 2862
2866 writel(epctl, hs->regs + epreg); 2863 writel(epctl, hs->regs + epreg);
@@ -2869,13 +2866,13 @@ static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2869 epctl = readl(hs->regs + epreg); 2866 epctl = readl(hs->regs + epreg);
2870 2867
2871 if (value) 2868 if (value)
2872 epctl |= DxEPCTL_Stall; 2869 epctl |= DXEPCTL_STALL;
2873 else { 2870 else {
2874 epctl &= ~DxEPCTL_Stall; 2871 epctl &= ~DXEPCTL_STALL;
2875 xfertype = epctl & DxEPCTL_EPType_MASK; 2872 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
2876 if (xfertype == DxEPCTL_EPType_Bulk || 2873 if (xfertype == DXEPCTL_EPTYPE_BULK ||
2877 xfertype == DxEPCTL_EPType_Intterupt) 2874 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
2878 epctl |= DxEPCTL_SetD0PID; 2875 epctl |= DXEPCTL_SETD0PID;
2879 } 2876 }
2880 2877
2881 writel(epctl, hs->regs + epreg); 2878 writel(epctl, hs->regs + epreg);
@@ -2965,22 +2962,22 @@ static void s3c_hsotg_init(struct s3c_hsotg *hsotg)
2965{ 2962{
2966 /* unmask subset of endpoint interrupts */ 2963 /* unmask subset of endpoint interrupts */
2967 2964
2968 writel(DIEPMSK_TimeOUTMsk | DIEPMSK_AHBErrMsk | 2965 writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
2969 DIEPMSK_EPDisbldMsk | DIEPMSK_XferComplMsk, 2966 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
2970 hsotg->regs + DIEPMSK); 2967 hsotg->regs + DIEPMSK);
2971 2968
2972 writel(DOEPMSK_SetupMsk | DOEPMSK_AHBErrMsk | 2969 writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
2973 DOEPMSK_EPDisbldMsk | DOEPMSK_XferComplMsk, 2970 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
2974 hsotg->regs + DOEPMSK); 2971 hsotg->regs + DOEPMSK);
2975 2972
2976 writel(0, hsotg->regs + DAINTMSK); 2973 writel(0, hsotg->regs + DAINTMSK);
2977 2974
2978 /* Be in disconnected state until gadget is registered */ 2975 /* Be in disconnected state until gadget is registered */
2979 __orr32(hsotg->regs + DCTL, DCTL_SftDiscon); 2976 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2980 2977
2981 if (0) { 2978 if (0) {
2982 /* post global nak until we're ready */ 2979 /* post global nak until we're ready */
2983 writel(DCTL_SGNPInNAK | DCTL_SGOUTNak, 2980 writel(DCTL_SGNPINNAK | DCTL_SGOUTNAK,
2984 hsotg->regs + DCTL); 2981 hsotg->regs + DCTL);
2985 } 2982 }
2986 2983
@@ -2993,10 +2990,10 @@ static void s3c_hsotg_init(struct s3c_hsotg *hsotg)
2993 s3c_hsotg_init_fifo(hsotg); 2990 s3c_hsotg_init_fifo(hsotg);
2994 2991
2995 /* set the PLL on, remove the HNP/SRP and set the PHY */ 2992 /* set the PLL on, remove the HNP/SRP and set the PHY */
2996 writel(GUSBCFG_PHYIf16 | GUSBCFG_TOutCal(7) | (0x5 << 10), 2993 writel(GUSBCFG_PHYIF16 | GUSBCFG_TOUTCAL(7) | (0x5 << 10),
2997 hsotg->regs + GUSBCFG); 2994 hsotg->regs + GUSBCFG);
2998 2995
2999 writel(using_dma(hsotg) ? GAHBCFG_DMAEn : 0x0, 2996 writel(using_dma(hsotg) ? GAHBCFG_DMA_EN : 0x0,
3000 hsotg->regs + GAHBCFG); 2997 hsotg->regs + GAHBCFG);
3001} 2998}
3002 2999
@@ -3187,8 +3184,8 @@ static void s3c_hsotg_initep(struct s3c_hsotg *hsotg,
3187 * code is changed to make each endpoint's direction changeable. 3184 * code is changed to make each endpoint's direction changeable.
3188 */ 3185 */
3189 3186
3190 ptxfifo = readl(hsotg->regs + DPTXFSIZn(epnum)); 3187 ptxfifo = readl(hsotg->regs + DPTXFSIZN(epnum));
3191 hs_ep->fifo_size = DPTXFSIZn_DPTxFSize_GET(ptxfifo) * 4; 3188 hs_ep->fifo_size = FIFOSIZE_DEPTH_GET(ptxfifo) * 4;
3192 3189
3193 /* 3190 /*
3194 * if we're using dma, we need to set the next-endpoint pointer 3191 * if we're using dma, we need to set the next-endpoint pointer
@@ -3196,7 +3193,7 @@ static void s3c_hsotg_initep(struct s3c_hsotg *hsotg,
3196 */ 3193 */
3197 3194
3198 if (using_dma(hsotg)) { 3195 if (using_dma(hsotg)) {
3199 u32 next = DxEPCTL_NextEp((epnum + 1) % 15); 3196 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
3200 writel(next, hsotg->regs + DIEPCTL(epnum)); 3197 writel(next, hsotg->regs + DIEPCTL(epnum));
3201 writel(next, hsotg->regs + DOEPCTL(epnum)); 3198 writel(next, hsotg->regs + DOEPCTL(epnum));
3202 } 3199 }
@@ -3250,10 +3247,10 @@ static void s3c_hsotg_dump(struct s3c_hsotg *hsotg)
3250 /* show periodic fifo settings */ 3247 /* show periodic fifo settings */
3251 3248
3252 for (idx = 1; idx <= 15; idx++) { 3249 for (idx = 1; idx <= 15; idx++) {
3253 val = readl(regs + DPTXFSIZn(idx)); 3250 val = readl(regs + DPTXFSIZN(idx));
3254 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, 3251 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
3255 val >> DPTXFSIZn_DPTxFSize_SHIFT, 3252 val >> FIFOSIZE_DEPTH_SHIFT,
3256 val & DPTXFSIZn_DPTxFStAddr_MASK); 3253 val & FIFOSIZE_STARTADDR_MASK);
3257 } 3254 }
3258 3255
3259 for (idx = 0; idx < 15; idx++) { 3256 for (idx = 0; idx < 15; idx++) {
@@ -3368,17 +3365,17 @@ static int fifo_show(struct seq_file *seq, void *v)
3368 3365
3369 val = readl(regs + GNPTXFSIZ); 3366 val = readl(regs + GNPTXFSIZ);
3370 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n", 3367 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
3371 val >> GNPTXFSIZ_NPTxFDep_SHIFT, 3368 val >> FIFOSIZE_DEPTH_SHIFT,
3372 val & GNPTXFSIZ_NPTxFStAddr_MASK); 3369 val & FIFOSIZE_DEPTH_MASK);
3373 3370
3374 seq_puts(seq, "\nPeriodic TXFIFOs:\n"); 3371 seq_puts(seq, "\nPeriodic TXFIFOs:\n");
3375 3372
3376 for (idx = 1; idx <= 15; idx++) { 3373 for (idx = 1; idx <= 15; idx++) {
3377 val = readl(regs + DPTXFSIZn(idx)); 3374 val = readl(regs + DPTXFSIZN(idx));
3378 3375
3379 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx, 3376 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
3380 val >> DPTXFSIZn_DPTxFSize_SHIFT, 3377 val >> FIFOSIZE_DEPTH_SHIFT,
3381 val & DPTXFSIZn_DPTxFStAddr_MASK); 3378 val & FIFOSIZE_STARTADDR_MASK);
3382 } 3379 }
3383 3380
3384 return 0; 3381 return 0;
@@ -3662,14 +3659,14 @@ static int s3c_hsotg_probe(struct platform_device *pdev)
3662 } 3659 }
3663 3660
3664 /* Set default UTMI width */ 3661 /* Set default UTMI width */
3665 hsotg->phyif = GUSBCFG_PHYIf16; 3662 hsotg->phyif = GUSBCFG_PHYIF16;
3666 3663
3667 /* 3664 /*
3668 * If using the generic PHY framework, check if the PHY bus 3665 * If using the generic PHY framework, check if the PHY bus
3669 * width is 8-bit and set the phyif appropriately. 3666 * width is 8-bit and set the phyif appropriately.
3670 */ 3667 */
3671 if (hsotg->phy && (phy_get_bus_width(phy) == 8)) 3668 if (hsotg->phy && (phy_get_bus_width(phy) == 8))
3672 hsotg->phyif = GUSBCFG_PHYIf8; 3669 hsotg->phyif = GUSBCFG_PHYIF8;
3673 3670
3674 if (hsotg->phy) 3671 if (hsotg->phy)
3675 phy_init(hsotg->phy); 3672 phy_init(hsotg->phy);
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 3557c7e5040d..7fca52bfe5b1 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -300,12 +300,6 @@ config USB_PXA27X
300 dynamically linked module called "pxa27x_udc" and force all 300 dynamically linked module called "pxa27x_udc" and force all
301 gadget drivers to also be dynamically linked. 301 gadget drivers to also be dynamically linked.
302 302
303config USB_S3C_HSOTG
304 tristate "Designware/S3C HS/OtG USB Device controller"
305 help
306 The Designware USB2.0 high-speed gadget controller
307 integrated into many SoCs.
308
309config USB_S3C2410 303config USB_S3C2410
310 tristate "S3C2410 USB Device Controller" 304 tristate "S3C2410 USB Device Controller"
311 depends on ARCH_S3C24XX 305 depends on ARCH_S3C24XX
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index 5f150bc1b4bc..49514ea60a98 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -26,7 +26,6 @@ fsl_usb2_udc-$(CONFIG_ARCH_MXC) += fsl_mxc_udc.o
26obj-$(CONFIG_USB_M66592) += m66592-udc.o 26obj-$(CONFIG_USB_M66592) += m66592-udc.o
27obj-$(CONFIG_USB_R8A66597) += r8a66597-udc.o 27obj-$(CONFIG_USB_R8A66597) += r8a66597-udc.o
28obj-$(CONFIG_USB_FSL_QE) += fsl_qe_udc.o 28obj-$(CONFIG_USB_FSL_QE) += fsl_qe_udc.o
29obj-$(CONFIG_USB_S3C_HSOTG) += s3c-hsotg.o
30obj-$(CONFIG_USB_S3C_HSUDC) += s3c-hsudc.o 29obj-$(CONFIG_USB_S3C_HSUDC) += s3c-hsudc.o
31obj-$(CONFIG_USB_LPC32XX) += lpc32xx_udc.o 30obj-$(CONFIG_USB_LPC32XX) += lpc32xx_udc.o
32obj-$(CONFIG_USB_EG20T) += pch_udc.o 31obj-$(CONFIG_USB_EG20T) += pch_udc.o
diff --git a/drivers/usb/gadget/s3c-hsotg.h b/drivers/usb/gadget/s3c-hsotg.h
deleted file mode 100644
index 85f549ff8c1f..000000000000
--- a/drivers/usb/gadget/s3c-hsotg.h
+++ /dev/null
@@ -1,378 +0,0 @@
1/* drivers/usb/gadget/s3c-hsotg.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * USB2.0 Highspeed/OtG Synopsis DWC2 device block registers
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __REGS_USB_HSOTG_H
16#define __REGS_USB_HSOTG_H __FILE__
17
18#define HSOTG_REG(x) (x)
19
20#define GOTGCTL HSOTG_REG(0x000)
21#define GOTGCTL_BSESVLD (1 << 19)
22#define GOTGCTL_ASESVLD (1 << 18)
23#define GOTGCTL_DBNC_SHORT (1 << 17)
24#define GOTGCTL_CONID_B (1 << 16)
25#define GOTGCTL_DEVHNPEN (1 << 11)
26#define GOTGCTL_HSSETHNPEN (1 << 10)
27#define GOTGCTL_HNPREQ (1 << 9)
28#define GOTGCTL_HSTNEGSCS (1 << 8)
29#define GOTGCTL_SESREQ (1 << 1)
30#define GOTGCTL_SESREQSCS (1 << 0)
31
32#define GOTGINT HSOTG_REG(0x004)
33#define GOTGINT_DbnceDone (1 << 19)
34#define GOTGINT_ADevTOUTChg (1 << 18)
35#define GOTGINT_HstNegDet (1 << 17)
36#define GOTGINT_HstnegSucStsChng (1 << 9)
37#define GOTGINT_SesReqSucStsChng (1 << 8)
38#define GOTGINT_SesEndDet (1 << 2)
39
40#define GAHBCFG HSOTG_REG(0x008)
41#define GAHBCFG_PTxFEmpLvl (1 << 8)
42#define GAHBCFG_NPTxFEmpLvl (1 << 7)
43#define GAHBCFG_DMAEn (1 << 5)
44#define GAHBCFG_HBstLen_MASK (0xf << 1)
45#define GAHBCFG_HBstLen_SHIFT (1)
46#define GAHBCFG_HBstLen_Single (0x0 << 1)
47#define GAHBCFG_HBstLen_Incr (0x1 << 1)
48#define GAHBCFG_HBstLen_Incr4 (0x3 << 1)
49#define GAHBCFG_HBstLen_Incr8 (0x5 << 1)
50#define GAHBCFG_HBstLen_Incr16 (0x7 << 1)
51#define GAHBCFG_GlblIntrEn (1 << 0)
52
53#define GUSBCFG HSOTG_REG(0x00C)
54#define GUSBCFG_PHYLPClkSel (1 << 15)
55#define GUSBCFG_HNPCap (1 << 9)
56#define GUSBCFG_SRPCap (1 << 8)
57#define GUSBCFG_PHYIf16 (1 << 3)
58#define GUSBCFG_PHYIf8 (0 << 3)
59#define GUSBCFG_TOutCal_MASK (0x7 << 0)
60#define GUSBCFG_TOutCal_SHIFT (0)
61#define GUSBCFG_TOutCal_LIMIT (0x7)
62#define GUSBCFG_TOutCal(_x) ((_x) << 0)
63
64#define GRSTCTL HSOTG_REG(0x010)
65
66#define GRSTCTL_AHBIdle (1 << 31)
67#define GRSTCTL_DMAReq (1 << 30)
68#define GRSTCTL_TxFNum_MASK (0x1f << 6)
69#define GRSTCTL_TxFNum_SHIFT (6)
70#define GRSTCTL_TxFNum_LIMIT (0x1f)
71#define GRSTCTL_TxFNum(_x) ((_x) << 6)
72#define GRSTCTL_TxFFlsh (1 << 5)
73#define GRSTCTL_RxFFlsh (1 << 4)
74#define GRSTCTL_INTknQFlsh (1 << 3)
75#define GRSTCTL_FrmCntrRst (1 << 2)
76#define GRSTCTL_HSftRst (1 << 1)
77#define GRSTCTL_CSftRst (1 << 0)
78
79#define GINTSTS HSOTG_REG(0x014)
80#define GINTMSK HSOTG_REG(0x018)
81
82#define GINTSTS_WkUpInt (1 << 31)
83#define GINTSTS_SessReqInt (1 << 30)
84#define GINTSTS_DisconnInt (1 << 29)
85#define GINTSTS_ConIDStsChng (1 << 28)
86#define GINTSTS_PTxFEmp (1 << 26)
87#define GINTSTS_HChInt (1 << 25)
88#define GINTSTS_PrtInt (1 << 24)
89#define GINTSTS_FetSusp (1 << 22)
90#define GINTSTS_incompIP (1 << 21)
91#define GINTSTS_IncomplSOIN (1 << 20)
92#define GINTSTS_OEPInt (1 << 19)
93#define GINTSTS_IEPInt (1 << 18)
94#define GINTSTS_EPMis (1 << 17)
95#define GINTSTS_EOPF (1 << 15)
96#define GINTSTS_ISOutDrop (1 << 14)
97#define GINTSTS_EnumDone (1 << 13)
98#define GINTSTS_USBRst (1 << 12)
99#define GINTSTS_USBSusp (1 << 11)
100#define GINTSTS_ErlySusp (1 << 10)
101#define GINTSTS_GOUTNakEff (1 << 7)
102#define GINTSTS_GINNakEff (1 << 6)
103#define GINTSTS_NPTxFEmp (1 << 5)
104#define GINTSTS_RxFLvl (1 << 4)
105#define GINTSTS_SOF (1 << 3)
106#define GINTSTS_OTGInt (1 << 2)
107#define GINTSTS_ModeMis (1 << 1)
108#define GINTSTS_CurMod_Host (1 << 0)
109
110#define GRXSTSR HSOTG_REG(0x01C)
111#define GRXSTSP HSOTG_REG(0x020)
112
113#define GRXSTS_FN_MASK (0x7f << 25)
114#define GRXSTS_FN_SHIFT (25)
115
116#define GRXSTS_PktSts_MASK (0xf << 17)
117#define GRXSTS_PktSts_SHIFT (17)
118#define GRXSTS_PktSts_GlobalOutNAK (0x1 << 17)
119#define GRXSTS_PktSts_OutRX (0x2 << 17)
120#define GRXSTS_PktSts_OutDone (0x3 << 17)
121#define GRXSTS_PktSts_SetupDone (0x4 << 17)
122#define GRXSTS_PktSts_SetupRX (0x6 << 17)
123
124#define GRXSTS_DPID_MASK (0x3 << 15)
125#define GRXSTS_DPID_SHIFT (15)
126#define GRXSTS_ByteCnt_MASK (0x7ff << 4)
127#define GRXSTS_ByteCnt_SHIFT (4)
128#define GRXSTS_EPNum_MASK (0xf << 0)
129#define GRXSTS_EPNum_SHIFT (0)
130
131#define GRXFSIZ HSOTG_REG(0x024)
132
133#define GNPTXFSIZ HSOTG_REG(0x028)
134
135#define GNPTXFSIZ_NPTxFDep_MASK (0xffff << 16)
136#define GNPTXFSIZ_NPTxFDep_SHIFT (16)
137#define GNPTXFSIZ_NPTxFDep_LIMIT (0xffff)
138#define GNPTXFSIZ_NPTxFDep(_x) ((_x) << 16)
139#define GNPTXFSIZ_NPTxFStAddr_MASK (0xffff << 0)
140#define GNPTXFSIZ_NPTxFStAddr_SHIFT (0)
141#define GNPTXFSIZ_NPTxFStAddr_LIMIT (0xffff)
142#define GNPTXFSIZ_NPTxFStAddr(_x) ((_x) << 0)
143
144#define GNPTXSTS HSOTG_REG(0x02C)
145
146#define GNPTXSTS_NPtxQTop_MASK (0x7f << 24)
147#define GNPTXSTS_NPtxQTop_SHIFT (24)
148
149#define GNPTXSTS_NPTxQSpcAvail_MASK (0xff << 16)
150#define GNPTXSTS_NPTxQSpcAvail_SHIFT (16)
151#define GNPTXSTS_NPTxQSpcAvail_GET(_v) (((_v) >> 16) & 0xff)
152
153#define GNPTXSTS_NPTxFSpcAvail_MASK (0xffff << 0)
154#define GNPTXSTS_NPTxFSpcAvail_SHIFT (0)
155#define GNPTXSTS_NPTxFSpcAvail_GET(_v) (((_v) >> 0) & 0xffff)
156
157
158#define HPTXFSIZ HSOTG_REG(0x100)
159
160#define DPTXFSIZn(_a) HSOTG_REG(0x104 + (((_a) - 1) * 4))
161
162#define DPTXFSIZn_DPTxFSize_MASK (0xffff << 16)
163#define DPTXFSIZn_DPTxFSize_SHIFT (16)
164#define DPTXFSIZn_DPTxFSize_GET(_v) (((_v) >> 16) & 0xffff)
165#define DPTXFSIZn_DPTxFSize_LIMIT (0xffff)
166#define DPTXFSIZn_DPTxFSize(_x) ((_x) << 16)
167
168#define DPTXFSIZn_DPTxFStAddr_MASK (0xffff << 0)
169#define DPTXFSIZn_DPTxFStAddr_SHIFT (0)
170
171/* Device mode registers */
172#define DCFG HSOTG_REG(0x800)
173
174#define DCFG_EPMisCnt_MASK (0x1f << 18)
175#define DCFG_EPMisCnt_SHIFT (18)
176#define DCFG_EPMisCnt_LIMIT (0x1f)
177#define DCFG_EPMisCnt(_x) ((_x) << 18)
178
179#define DCFG_PerFrInt_MASK (0x3 << 11)
180#define DCFG_PerFrInt_SHIFT (11)
181#define DCFG_PerFrInt_LIMIT (0x3)
182#define DCFG_PerFrInt(_x) ((_x) << 11)
183
184#define DCFG_DevAddr_MASK (0x7f << 4)
185#define DCFG_DevAddr_SHIFT (4)
186#define DCFG_DevAddr_LIMIT (0x7f)
187#define DCFG_DevAddr(_x) ((_x) << 4)
188
189#define DCFG_NZStsOUTHShk (1 << 2)
190
191#define DCFG_DevSpd_MASK (0x3 << 0)
192#define DCFG_DevSpd_SHIFT (0)
193#define DCFG_DevSpd_HS (0x0 << 0)
194#define DCFG_DevSpd_FS (0x1 << 0)
195#define DCFG_DevSpd_LS (0x2 << 0)
196#define DCFG_DevSpd_FS48 (0x3 << 0)
197
198#define DCTL HSOTG_REG(0x804)
199
200#define DCTL_PWROnPrgDone (1 << 11)
201#define DCTL_CGOUTNak (1 << 10)
202#define DCTL_SGOUTNak (1 << 9)
203#define DCTL_CGNPInNAK (1 << 8)
204#define DCTL_SGNPInNAK (1 << 7)
205#define DCTL_TstCtl_MASK (0x7 << 4)
206#define DCTL_TstCtl_SHIFT (4)
207#define DCTL_GOUTNakSts (1 << 3)
208#define DCTL_GNPINNakSts (1 << 2)
209#define DCTL_SftDiscon (1 << 1)
210#define DCTL_RmtWkUpSig (1 << 0)
211
212#define DSTS HSOTG_REG(0x808)
213
214#define DSTS_SOFFN_MASK (0x3fff << 8)
215#define DSTS_SOFFN_SHIFT (8)
216#define DSTS_SOFFN_LIMIT (0x3fff)
217#define DSTS_SOFFN(_x) ((_x) << 8)
218#define DSTS_ErraticErr (1 << 3)
219#define DSTS_EnumSpd_MASK (0x3 << 1)
220#define DSTS_EnumSpd_SHIFT (1)
221#define DSTS_EnumSpd_HS (0x0 << 1)
222#define DSTS_EnumSpd_FS (0x1 << 1)
223#define DSTS_EnumSpd_LS (0x2 << 1)
224#define DSTS_EnumSpd_FS48 (0x3 << 1)
225
226#define DSTS_SuspSts (1 << 0)
227
228#define DIEPMSK HSOTG_REG(0x810)
229
230#define DIEPMSK_TxFIFOEmpty (1 << 7)
231#define DIEPMSK_INEPNakEffMsk (1 << 6)
232#define DIEPMSK_INTknEPMisMsk (1 << 5)
233#define DIEPMSK_INTknTXFEmpMsk (1 << 4)
234#define DIEPMSK_TimeOUTMsk (1 << 3)
235#define DIEPMSK_AHBErrMsk (1 << 2)
236#define DIEPMSK_EPDisbldMsk (1 << 1)
237#define DIEPMSK_XferComplMsk (1 << 0)
238
239#define DOEPMSK HSOTG_REG(0x814)
240
241#define DOEPMSK_Back2BackSetup (1 << 6)
242#define DOEPMSK_OUTTknEPdisMsk (1 << 4)
243#define DOEPMSK_SetupMsk (1 << 3)
244#define DOEPMSK_AHBErrMsk (1 << 2)
245#define DOEPMSK_EPDisbldMsk (1 << 1)
246#define DOEPMSK_XferComplMsk (1 << 0)
247
248#define DAINT HSOTG_REG(0x818)
249#define DAINTMSK HSOTG_REG(0x81C)
250
251#define DAINT_OutEP_SHIFT (16)
252#define DAINT_OutEP(x) (1 << ((x) + 16))
253#define DAINT_InEP(x) (1 << (x))
254
255#define DTKNQR1 HSOTG_REG(0x820)
256#define DTKNQR2 HSOTG_REG(0x824)
257#define DTKNQR3 HSOTG_REG(0x830)
258#define DTKNQR4 HSOTG_REG(0x834)
259
260#define DVBUSDIS HSOTG_REG(0x828)
261#define DVBUSPULSE HSOTG_REG(0x82C)
262
263#define DIEPCTL0 HSOTG_REG(0x900)
264#define DOEPCTL0 HSOTG_REG(0xB00)
265#define DIEPCTL(_a) HSOTG_REG(0x900 + ((_a) * 0x20))
266#define DOEPCTL(_a) HSOTG_REG(0xB00 + ((_a) * 0x20))
267
268/* EP0 specialness:
269 * bits[29..28] - reserved (no SetD0PID, SetD1PID)
270 * bits[25..22] - should always be zero, this isn't a periodic endpoint
271 * bits[10..0] - MPS setting differenct for EP0
272 */
273#define D0EPCTL_MPS_MASK (0x3 << 0)
274#define D0EPCTL_MPS_SHIFT (0)
275#define D0EPCTL_MPS_64 (0x0 << 0)
276#define D0EPCTL_MPS_32 (0x1 << 0)
277#define D0EPCTL_MPS_16 (0x2 << 0)
278#define D0EPCTL_MPS_8 (0x3 << 0)
279
280#define DxEPCTL_EPEna (1 << 31)
281#define DxEPCTL_EPDis (1 << 30)
282#define DxEPCTL_SetD1PID (1 << 29)
283#define DxEPCTL_SetOddFr (1 << 29)
284#define DxEPCTL_SetD0PID (1 << 28)
285#define DxEPCTL_SetEvenFr (1 << 28)
286#define DxEPCTL_SNAK (1 << 27)
287#define DxEPCTL_CNAK (1 << 26)
288#define DxEPCTL_TxFNum_MASK (0xf << 22)
289#define DxEPCTL_TxFNum_SHIFT (22)
290#define DxEPCTL_TxFNum_LIMIT (0xf)
291#define DxEPCTL_TxFNum(_x) ((_x) << 22)
292
293#define DxEPCTL_Stall (1 << 21)
294#define DxEPCTL_Snp (1 << 20)
295#define DxEPCTL_EPType_MASK (0x3 << 18)
296#define DxEPCTL_EPType_SHIFT (18)
297#define DxEPCTL_EPType_Control (0x0 << 18)
298#define DxEPCTL_EPType_Iso (0x1 << 18)
299#define DxEPCTL_EPType_Bulk (0x2 << 18)
300#define DxEPCTL_EPType_Intterupt (0x3 << 18)
301
302#define DxEPCTL_NAKsts (1 << 17)
303#define DxEPCTL_DPID (1 << 16)
304#define DxEPCTL_EOFrNum (1 << 16)
305#define DxEPCTL_USBActEp (1 << 15)
306#define DxEPCTL_NextEp_MASK (0xf << 11)
307#define DxEPCTL_NextEp_SHIFT (11)
308#define DxEPCTL_NextEp_LIMIT (0xf)
309#define DxEPCTL_NextEp(_x) ((_x) << 11)
310
311#define DxEPCTL_MPS_MASK (0x7ff << 0)
312#define DxEPCTL_MPS_SHIFT (0)
313#define DxEPCTL_MPS_LIMIT (0x7ff)
314#define DxEPCTL_MPS(_x) ((_x) << 0)
315
316#define DIEPINT(_a) HSOTG_REG(0x908 + ((_a) * 0x20))
317#define DOEPINT(_a) HSOTG_REG(0xB08 + ((_a) * 0x20))
318
319#define DxEPINT_INEPNakEff (1 << 6)
320#define DxEPINT_Back2BackSetup (1 << 6)
321#define DxEPINT_INTknEPMis (1 << 5)
322#define DxEPINT_INTknTXFEmp (1 << 4)
323#define DxEPINT_OUTTknEPdis (1 << 4)
324#define DxEPINT_Timeout (1 << 3)
325#define DxEPINT_Setup (1 << 3)
326#define DxEPINT_AHBErr (1 << 2)
327#define DxEPINT_EPDisbld (1 << 1)
328#define DxEPINT_XferCompl (1 << 0)
329
330#define DIEPTSIZ0 HSOTG_REG(0x910)
331
332#define DIEPTSIZ0_PktCnt_MASK (0x3 << 19)
333#define DIEPTSIZ0_PktCnt_SHIFT (19)
334#define DIEPTSIZ0_PktCnt_LIMIT (0x3)
335#define DIEPTSIZ0_PktCnt(_x) ((_x) << 19)
336
337#define DIEPTSIZ0_XferSize_MASK (0x7f << 0)
338#define DIEPTSIZ0_XferSize_SHIFT (0)
339#define DIEPTSIZ0_XferSize_LIMIT (0x7f)
340#define DIEPTSIZ0_XferSize(_x) ((_x) << 0)
341
342#define DOEPTSIZ0 HSOTG_REG(0xB10)
343#define DOEPTSIZ0_SUPCnt_MASK (0x3 << 29)
344#define DOEPTSIZ0_SUPCnt_SHIFT (29)
345#define DOEPTSIZ0_SUPCnt_LIMIT (0x3)
346#define DOEPTSIZ0_SUPCnt(_x) ((_x) << 29)
347
348#define DOEPTSIZ0_PktCnt (1 << 19)
349#define DOEPTSIZ0_XferSize_MASK (0x7f << 0)
350#define DOEPTSIZ0_XferSize_SHIFT (0)
351
352#define DIEPTSIZ(_a) HSOTG_REG(0x910 + ((_a) * 0x20))
353#define DOEPTSIZ(_a) HSOTG_REG(0xB10 + ((_a) * 0x20))
354
355#define DxEPTSIZ_MC_MASK (0x3 << 29)
356#define DxEPTSIZ_MC_SHIFT (29)
357#define DxEPTSIZ_MC_LIMIT (0x3)
358#define DxEPTSIZ_MC(_x) ((_x) << 29)
359
360#define DxEPTSIZ_PktCnt_MASK (0x3ff << 19)
361#define DxEPTSIZ_PktCnt_SHIFT (19)
362#define DxEPTSIZ_PktCnt_GET(_v) (((_v) >> 19) & 0x3ff)
363#define DxEPTSIZ_PktCnt_LIMIT (0x3ff)
364#define DxEPTSIZ_PktCnt(_x) ((_x) << 19)
365
366#define DxEPTSIZ_XferSize_MASK (0x7ffff << 0)
367#define DxEPTSIZ_XferSize_SHIFT (0)
368#define DxEPTSIZ_XferSize_GET(_v) (((_v) >> 0) & 0x7ffff)
369#define DxEPTSIZ_XferSize_LIMIT (0x7ffff)
370#define DxEPTSIZ_XferSize(_x) ((_x) << 0)
371
372#define DIEPDMA(_a) HSOTG_REG(0x914 + ((_a) * 0x20))
373#define DOEPDMA(_a) HSOTG_REG(0xB14 + ((_a) * 0x20))
374#define DTXFSTS(_a) HSOTG_REG(0x918 + ((_a) * 0x20))
375
376#define EPFIFO(_a) HSOTG_REG(0x1000 + ((_a) * 0x1000))
377
378#endif /* __REGS_USB_HSOTG_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-11 11:18:54 -0400