diff options
| author | Dinh Nguyen <dinguyen@altera.com> | 2014-04-14 17:13:33 -0400 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2014-04-24 16:12:43 -0400 |
| commit | 6ab53324496dbfd9e6110539f9aa0ab108bd664b (patch) | |
| tree | 9983dc2fc10c941222016aae131b08eb8e81ad78 | |
| parent | 543cab6402794e9cb444779d73e8097b8f29f7ee (diff) | |
usb: dwc2: add defines to support s3c-hsotg driver
In preparation of combining the dwc2/s3c-hsotg driver in a single
DRD driver, the defines in dwc2/hw.h needs to get updated so that
the s3c-hsotg driver can use them.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
[ jh,rb - For gadget part only: ]
Tested-by: Jingoo Han <jg1.han@samsung.com>
Tested-by: Robert Baldyga <r.baldyga@samsung.com>
[ pz - Tested host part only. ]
Signed-off-by: Paul Zimmerman <paulz@synopsys.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| -rw-r--r-- | drivers/usb/dwc2/hw.h | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/drivers/usb/dwc2/hw.h b/drivers/usb/dwc2/hw.h index 9c92a3c7588a..51248b935493 100644 --- a/drivers/usb/dwc2/hw.h +++ b/drivers/usb/dwc2/hw.h | |||
| @@ -109,6 +109,7 @@ | |||
| 109 | #define GUSBCFG_FSINTF (1 << 5) | 109 | #define GUSBCFG_FSINTF (1 << 5) |
| 110 | #define GUSBCFG_ULPI_UTMI_SEL (1 << 4) | 110 | #define GUSBCFG_ULPI_UTMI_SEL (1 << 4) |
| 111 | #define GUSBCFG_PHYIF16 (1 << 3) | 111 | #define GUSBCFG_PHYIF16 (1 << 3) |
| 112 | #define GUSBCFG_PHYIF8 (0 << 3) | ||
| 112 | #define GUSBCFG_TOUTCAL_MASK (0x7 << 0) | 113 | #define GUSBCFG_TOUTCAL_MASK (0x7 << 0) |
| 113 | #define GUSBCFG_TOUTCAL_SHIFT 0 | 114 | #define GUSBCFG_TOUTCAL_SHIFT 0 |
| 114 | #define GUSBCFG_TOUTCAL_LIMIT 0x7 | 115 | #define GUSBCFG_TOUTCAL_LIMIT 0x7 |
| @@ -403,6 +404,7 @@ | |||
| 403 | #define FIFOSIZE_DEPTH_SHIFT 16 | 404 | #define FIFOSIZE_DEPTH_SHIFT 16 |
| 404 | #define FIFOSIZE_STARTADDR_MASK (0xffff << 0) | 405 | #define FIFOSIZE_STARTADDR_MASK (0xffff << 0) |
| 405 | #define FIFOSIZE_STARTADDR_SHIFT 0 | 406 | #define FIFOSIZE_STARTADDR_SHIFT 0 |
| 407 | #define FIFOSIZE_DEPTH_GET(_x) (((_x) >> 16) & 0xffff) | ||
| 406 | 408 | ||
| 407 | /* Device mode registers */ | 409 | /* Device mode registers */ |
| 408 | 410 | ||
| @@ -519,11 +521,11 @@ | |||
| 519 | #define DXEPCTL_STALL (1 << 21) | 521 | #define DXEPCTL_STALL (1 << 21) |
| 520 | #define DXEPCTL_SNP (1 << 20) | 522 | #define DXEPCTL_SNP (1 << 20) |
| 521 | #define DXEPCTL_EPTYPE_MASK (0x3 << 18) | 523 | #define DXEPCTL_EPTYPE_MASK (0x3 << 18) |
| 522 | #define DXEPCTL_EPTYPE_SHIFT 18 | 524 | #define DXEPCTL_EPTYPE_CONTROL (0x0 << 18) |
| 523 | #define DXEPCTL_EPTYPE_CONTROL 0 | 525 | #define DXEPCTL_EPTYPE_ISO (0x1 << 18) |
| 524 | #define DXEPCTL_EPTYPE_ISO 1 | 526 | #define DXEPCTL_EPTYPE_BULK (0x2 << 18) |
| 525 | #define DXEPCTL_EPTYPE_BULK 2 | 527 | #define DXEPCTL_EPTYPE_INTERRUPT (0x3 << 18) |
| 526 | #define DXEPCTL_EPTYPE_INTTERUPT 3 | 528 | |
| 527 | #define DXEPCTL_NAKSTS (1 << 17) | 529 | #define DXEPCTL_NAKSTS (1 << 17) |
| 528 | #define DXEPCTL_DPID (1 << 16) | 530 | #define DXEPCTL_DPID (1 << 16) |
| 529 | #define DXEPCTL_EOFRNUM (1 << 16) | 531 | #define DXEPCTL_EOFRNUM (1 << 16) |