/*
* Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include <asm/cpu.h>
#include <asm/cputype.h>
#include <asm/smp_plat.h>
#include <asm/traps.h>
#include <linux/debugfs.h>
#include <linux/cpu.h>
#include <linux/cpu_pm.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/tegra-mce.h>
#include <linux/t18x_ari.h>
#include <linux/platform/tegra/ari_mca.h>
#include <linux/platform/tegra/tegra18_cpu_map.h>
#include <linux/ioport.h>
#include <soc/tegra/chip-id.h>
#define ARI_BANK_PRINTF 0
#define ARI_MCA_SAVE_PREBOOT 0
#define ARI_MCA_CONTROL_ACCESS 0
#define ARI_MCA_VERBOSE_MODE 0
/* MCA bank handling functions */
static int read_bank_info(u64 *data)
{
u32 error;
int e;
mca_cmd_t mca_cmd = {.cmd = MCA_ARI_CMD_RD_SERR,
.idx = MCA_ARI_IDX_BANKINFO,
.subidx = 0};
e = tegra_mce_read_uncore_mca(mca_cmd, data, &error);
if (e != 0) {
pr_err("%s: ARI call failed\n", __func__);
return -EINVAL;
}
*data &= 0xff;
return 0;
}
static int read_bank_template(u64 bank, u64 *data)
{
u32 error;
int e;
mca_cmd_t mca_cmd = {.cmd = MCA_ARI_CMD_RD_SERR,
.idx = MCA_ARI_IDX_BANKTEMPLATE,
.subidx = 0};
e = tegra_mce_read_uncore_mca(mca_cmd, data, &error);
if (e != 0) {
pr_err("%s: ARI call failed\n", __func__);
return -EINVAL;
}
*data = (*data >> (8 * bank)) & 0xff;
return 0;
}
#if ARI_MCA_CONTROL_ACCESS
static int read_bank_control(struct ari_mca_bank *mca_bank, u64 *data,
int preboot)
{
u32 error;
int e;
mca_cmd_t mca_cmd = {.cmd = MCA_ARI_CMD_RD_SERR,
.idx = mca_bank->bank,
.subidx = MCA_ARI_RW_SUBIDX_CTRL};
#if ARI_BANK_PRINTF
pr_crit("%s: CPU%d mca_cmd = 0x%llx\n", __func__,
smp_processor_id(), mca_cmd.data);
#endif
e = tegra_mce_read_uncore_mca(mca_cmd, data, &error);
if (e != 0) {
pr_err("%s: ARI call failed\n", __func__);
return -EINVAL;
}
return 0;
}
static int write_bank_control(struct ari_mca_bank *mca_bank, u64 *data)
{
u32 error;
int e;
mca_cmd_t mca_cmd = {.cmd = MCA_ARI_CMD_WR_SERR,
.idx = mca_bank->bank,
.subidx = MCA_ARI_RW_SUBIDX_CTRL};
#if ARI_BANK_PRINTF
pr_crit("%s: CPU%d mca_cmd = 0x%llx\n", __func__,
smp_processor_id(), mca_cmd.data);
#endif
e = tegra_mce_read_uncore_mca(mca_cmd, data, &error);
if (e != 0) {
pr_err("%s: ARI call failed\n", __func__);
return -EINVAL;
}
return 0;
}
#endif
static int read_bank_status(struct ari_mca_bank *mca_bank, u64 *data,
int preboot)
{
u32 error;
int e;
mca_cmd_t mca_cmd = {.cmd = MCA_ARI_CMD_RD_SERR,
.idx = mca_bank->bank,
.subidx = MCA_ARI_RW_SUBIDX_STAT};
mca_cmd.cmd = preboot ? MCA_ARI_CMD_RD_PREBOOT_SERR :
MCA_ARI_CMD_RD_SERR;
#if ARI_BANK_PRINTF
pr_crit("%s: CPU%d mca_cmd = 0x%llx\n", __func__,
smp_processor_id(), mca_cmd.data);
#endif
e = tegra_mce_read_uncore_mca(mca_cmd, data, &error);
if (e != 0) {
pr_err("%s: ARI call failed\n", __func__);
return -EINVAL;
}
return 0;
}
static int read_bank_address(struct ari_mca_bank *mca_bank, u64 *data,
int preboot)
{
u32 error;
int e;
mca_cmd_t mca_cmd = {.cmd = MCA_ARI_CMD_RD_SERR,
.idx = mca_bank->bank,
.subidx = MCA_ARI_RW_SUBIDX_ADDR};
mca_cmd.cmd = preboot ? MCA_ARI_CMD_RD_PREBOOT_SERR :
MCA_ARI_CMD_RD_SERR;
#if ARI_BANK_PRINTF
pr_crit("%s: CPU%d mca_cmd = 0x%llx\n", __func__,
smp_processor_id(), mca_cmd.data);
#endif
e = tegra_mce_read_uncore_mca(mca_cmd, data, &error);
if (e != 0) {
pr_err("%s: ARI call failed\n", __func__);
return -EINVAL;
}
return 0;
}
static int
|