diff options
Diffstat (limited to 'drivers/gpu')
25 files changed, 238 insertions, 179 deletions
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index d7399c5d..d0dd252e 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile | |||
@@ -45,7 +45,12 @@ nvgpu-y += common/bus/bus_gk20a.o \ | |||
45 | common/fuse/fuse_gm20b.o \ | 45 | common/fuse/fuse_gm20b.o \ |
46 | common/fuse/fuse_gp10b.o \ | 46 | common/fuse/fuse_gp10b.o \ |
47 | common/fuse/fuse_gp106.o \ | 47 | common/fuse/fuse_gp106.o \ |
48 | common/top/top_gv100.o | 48 | common/top/top_gv100.o \ |
49 | common/mc/mc.o \ | ||
50 | common/mc/mc_gm20b.o \ | ||
51 | common/mc/mc_gp10b.o \ | ||
52 | common/mc/mc_gv11b.o \ | ||
53 | common/mc/mc_gv100.o | ||
49 | 54 | ||
50 | # Linux specific parts of nvgpu. | 55 | # Linux specific parts of nvgpu. |
51 | nvgpu-y += \ | 56 | nvgpu-y += \ |
@@ -236,7 +241,6 @@ nvgpu-y += \ | |||
236 | gk20a/hal.o \ | 241 | gk20a/hal.o \ |
237 | gk20a/tsg_gk20a.o \ | 242 | gk20a/tsg_gk20a.o \ |
238 | gk20a/fecs_trace_gk20a.o \ | 243 | gk20a/fecs_trace_gk20a.o \ |
239 | gk20a/mc_gk20a.o \ | ||
240 | gm20b/hal_gm20b.o \ | 244 | gm20b/hal_gm20b.o \ |
241 | gm20b/gr_gm20b.o \ | 245 | gm20b/gr_gm20b.o \ |
242 | gm20b/clk_gm20b.o \ | 246 | gm20b/clk_gm20b.o \ |
@@ -285,7 +289,6 @@ nvgpu-y += \ | |||
285 | gp10b/gr_gp10b.o \ | 289 | gp10b/gr_gp10b.o \ |
286 | gp10b/gr_ctx_gp10b.o \ | 290 | gp10b/gr_ctx_gp10b.o \ |
287 | gp10b/ce_gp10b.o \ | 291 | gp10b/ce_gp10b.o \ |
288 | gp10b/mc_gp10b.o \ | ||
289 | gp10b/fifo_gp10b.o \ | 292 | gp10b/fifo_gp10b.o \ |
290 | gp10b/mm_gp10b.o \ | 293 | gp10b/mm_gp10b.o \ |
291 | gp10b/pmu_gp10b.o \ | 294 | gp10b/pmu_gp10b.o \ |
@@ -308,7 +311,6 @@ nvgpu-y += \ | |||
308 | gv11b/gv11b.o \ | 311 | gv11b/gv11b.o \ |
309 | gv11b/css_gr_gv11b.o \ | 312 | gv11b/css_gr_gv11b.o \ |
310 | gv11b/dbg_gpu_gv11b.o \ | 313 | gv11b/dbg_gpu_gv11b.o \ |
311 | gv11b/mc_gv11b.o \ | ||
312 | gv11b/hal_gv11b.o \ | 314 | gv11b/hal_gv11b.o \ |
313 | gv11b/gr_gv11b.o \ | 315 | gv11b/gr_gv11b.o \ |
314 | gv11b/fifo_gv11b.o \ | 316 | gv11b/fifo_gv11b.o \ |
@@ -327,7 +329,6 @@ nvgpu-y += \ | |||
327 | gv100/gr_gv100.o \ | 329 | gv100/gr_gv100.o \ |
328 | gv100/regops_gv100.o \ | 330 | gv100/regops_gv100.o \ |
329 | gv100/flcn_gv100.o \ | 331 | gv100/flcn_gv100.o \ |
330 | gv100/mc_gv100.o \ | ||
331 | gv100/nvlink_gv100.o \ | 332 | gv100/nvlink_gv100.o \ |
332 | gv100/hal_gv100.o \ | 333 | gv100/hal_gv100.o \ |
333 | gv100/pmu_gv100.o \ | 334 | gv100/pmu_gv100.o \ |
diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index ceec9116..a53548f4 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources | |||
@@ -107,6 +107,11 @@ srcs := os/posix/nvgpu.c \ | |||
107 | common/clock_gating/gv100_gating_reglist.c \ | 107 | common/clock_gating/gv100_gating_reglist.c \ |
108 | common/fifo/channel.c \ | 108 | common/fifo/channel.c \ |
109 | common/fifo/submit.c \ | 109 | common/fifo/submit.c \ |
110 | common/mc/mc.c \ | ||
111 | common/mc/mc_gm20b.c \ | ||
112 | common/mc/mc_gp10b.c \ | ||
113 | common/mc/mc_gv11b.c \ | ||
114 | common/mc/mc_gv100.c \ | ||
110 | boardobj/boardobj.c \ | 115 | boardobj/boardobj.c \ |
111 | boardobj/boardobjgrp.c \ | 116 | boardobj/boardobjgrp.c \ |
112 | boardobj/boardobjgrpmask.c \ | 117 | boardobj/boardobjgrpmask.c \ |
@@ -154,7 +159,6 @@ srcs := os/posix/nvgpu.c \ | |||
154 | gk20a/gr_ctx_gk20a.c \ | 159 | gk20a/gr_ctx_gk20a.c \ |
155 | gk20a/hal.c \ | 160 | gk20a/hal.c \ |
156 | gk20a/tsg_gk20a.c \ | 161 | gk20a/tsg_gk20a.c \ |
157 | gk20a/mc_gk20a.c \ | ||
158 | gm20b/hal_gm20b.c \ | 162 | gm20b/hal_gm20b.c \ |
159 | gm20b/gr_gm20b.c \ | 163 | gm20b/gr_gm20b.c \ |
160 | gm20b/clk_gm20b.c \ | 164 | gm20b/clk_gm20b.c \ |
@@ -167,7 +171,6 @@ srcs := os/posix/nvgpu.c \ | |||
167 | gp10b/gr_gp10b.c \ | 171 | gp10b/gr_gp10b.c \ |
168 | gp10b/gr_ctx_gp10b.c \ | 172 | gp10b/gr_ctx_gp10b.c \ |
169 | gp10b/ce_gp10b.c \ | 173 | gp10b/ce_gp10b.c \ |
170 | gp10b/mc_gp10b.c \ | ||
171 | gp10b/fifo_gp10b.c \ | 174 | gp10b/fifo_gp10b.c \ |
172 | gp10b/mm_gp10b.c \ | 175 | gp10b/mm_gp10b.c \ |
173 | gp10b/pmu_gp10b.c \ | 176 | gp10b/pmu_gp10b.c \ |
@@ -178,7 +181,6 @@ srcs := os/posix/nvgpu.c \ | |||
178 | gp10b/ecc_gp10b.c \ | 181 | gp10b/ecc_gp10b.c \ |
179 | gv11b/gv11b.c \ | 182 | gv11b/gv11b.c \ |
180 | gv11b/dbg_gpu_gv11b.c \ | 183 | gv11b/dbg_gpu_gv11b.c \ |
181 | gv11b/mc_gv11b.c \ | ||
182 | gv11b/hal_gv11b.c \ | 184 | gv11b/hal_gv11b.c \ |
183 | gv11b/gr_gv11b.c \ | 185 | gv11b/gr_gv11b.c \ |
184 | gv11b/fifo_gv11b.c \ | 186 | gv11b/fifo_gv11b.c \ |
@@ -210,7 +212,6 @@ srcs := os/posix/nvgpu.c \ | |||
210 | gv100/gr_gv100.c \ | 212 | gv100/gr_gv100.c \ |
211 | gv100/regops_gv100.c \ | 213 | gv100/regops_gv100.c \ |
212 | gv100/flcn_gv100.c \ | 214 | gv100/flcn_gv100.c \ |
213 | gv100/mc_gv100.c \ | ||
214 | gv100/nvlink_gv100.c \ | 215 | gv100/nvlink_gv100.c \ |
215 | gv100/hal_gv100.c \ | 216 | gv100/hal_gv100.c \ |
216 | gv100/pmu_gv100.c | 217 | gv100/pmu_gv100.c |
diff --git a/drivers/gpu/nvgpu/common/mc/mc.c b/drivers/gpu/nvgpu/common/mc/mc.c new file mode 100644 index 00000000..77416ef9 --- /dev/null +++ b/drivers/gpu/nvgpu/common/mc/mc.c | |||
@@ -0,0 +1,54 @@ | |||
1 | /* | ||
2 | * GK20A Master Control | ||
3 | * | ||
4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include <nvgpu/io.h> | ||
26 | #include <nvgpu/mc.h> | ||
27 | |||
28 | #include "gk20a/gk20a.h" | ||
29 | |||
30 | #include <nvgpu/hw/gm20b/hw_mc_gm20b.h> | ||
31 | |||
32 | u32 nvgpu_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev) | ||
33 | { | ||
34 | u32 val = __nvgpu_readl(g, mc_boot_0_r()); | ||
35 | |||
36 | if (val != 0xffffffffU) { | ||
37 | |||
38 | if (arch != NULL) { | ||
39 | *arch = mc_boot_0_architecture_v(val) << | ||
40 | NVGPU_GPU_ARCHITECTURE_SHIFT; | ||
41 | } | ||
42 | |||
43 | if (impl != NULL) { | ||
44 | *impl = mc_boot_0_implementation_v(val); | ||
45 | } | ||
46 | |||
47 | if (rev != NULL) { | ||
48 | *rev = (mc_boot_0_major_revision_v(val) << 4) | | ||
49 | mc_boot_0_minor_revision_v(val); | ||
50 | } | ||
51 | } | ||
52 | |||
53 | return val; | ||
54 | } | ||
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/common/mc/mc_gm20b.c index f9996e71..88666b1d 100644 --- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c +++ b/drivers/gpu/nvgpu/common/mc/mc_gm20b.c | |||
@@ -22,17 +22,18 @@ | |||
22 | * DEALINGS IN THE SOFTWARE. | 22 | * DEALINGS IN THE SOFTWARE. |
23 | */ | 23 | */ |
24 | 24 | ||
25 | #include "gk20a.h" | ||
26 | #include "mc_gk20a.h" | ||
27 | |||
28 | #include <nvgpu/timers.h> | 25 | #include <nvgpu/timers.h> |
29 | #include <nvgpu/atomic.h> | 26 | #include <nvgpu/atomic.h> |
30 | #include <nvgpu/unit.h> | 27 | #include <nvgpu/unit.h> |
31 | #include <nvgpu/io.h> | 28 | #include <nvgpu/io.h> |
29 | #include <nvgpu/mc.h> | ||
30 | |||
31 | #include "gk20a/gk20a.h" | ||
32 | #include "mc_gm20b.h" | ||
32 | 33 | ||
33 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> | 34 | #include <nvgpu/hw/gm20b/hw_mc_gm20b.h> |
34 | 35 | ||
35 | void mc_gk20a_isr_stall(struct gk20a *g) | 36 | void gm20b_mc_isr_stall(struct gk20a *g) |
36 | { | 37 | { |
37 | u32 mc_intr_0; | 38 | u32 mc_intr_0; |
38 | u32 engine_id_idx; | 39 | u32 engine_id_idx; |
@@ -63,24 +64,24 @@ void mc_gk20a_isr_stall(struct gk20a *g) | |||
63 | } | 64 | } |
64 | } | 65 | } |
65 | } | 66 | } |
66 | if ((mc_intr_0 & mc_intr_0_pfifo_pending_f()) != 0U) { | 67 | if ((mc_intr_0 & mc_intr_pfifo_pending_f()) != 0U) { |
67 | gk20a_fifo_isr(g); | 68 | gk20a_fifo_isr(g); |
68 | } | 69 | } |
69 | if ((mc_intr_0 & mc_intr_0_pmu_pending_f()) != 0U) { | 70 | if ((mc_intr_0 & mc_intr_pmu_pending_f()) != 0U) { |
70 | g->ops.pmu.pmu_isr(g); | 71 | g->ops.pmu.pmu_isr(g); |
71 | } | 72 | } |
72 | if ((mc_intr_0 & mc_intr_0_priv_ring_pending_f()) != 0U) { | 73 | if ((mc_intr_0 & mc_intr_priv_ring_pending_f()) != 0U) { |
73 | g->ops.priv_ring.isr(g); | 74 | g->ops.priv_ring.isr(g); |
74 | } | 75 | } |
75 | if ((mc_intr_0 & mc_intr_0_ltc_pending_f()) != 0U) { | 76 | if ((mc_intr_0 & mc_intr_ltc_pending_f()) != 0U) { |
76 | g->ops.ltc.isr(g); | 77 | g->ops.ltc.isr(g); |
77 | } | 78 | } |
78 | if ((mc_intr_0 & mc_intr_0_pbus_pending_f()) != 0U) { | 79 | if ((mc_intr_0 & mc_intr_pbus_pending_f()) != 0U) { |
79 | g->ops.bus.isr(g); | 80 | g->ops.bus.isr(g); |
80 | } | 81 | } |
81 | } | 82 | } |
82 | 83 | ||
83 | u32 mc_gk20a_isr_nonstall(struct gk20a *g) | 84 | u32 gm20b_mc_isr_nonstall(struct gk20a *g) |
84 | { | 85 | { |
85 | u32 ops = 0; | 86 | u32 ops = 0; |
86 | u32 mc_intr_1; | 87 | u32 mc_intr_1; |
@@ -121,7 +122,7 @@ u32 mc_gk20a_isr_nonstall(struct gk20a *g) | |||
121 | return ops; | 122 | return ops; |
122 | } | 123 | } |
123 | 124 | ||
124 | void mc_gk20a_intr_mask(struct gk20a *g) | 125 | void gm20b_mc_intr_mask(struct gk20a *g) |
125 | { | 126 | { |
126 | nvgpu_writel(g, mc_intr_en_0_r(), | 127 | nvgpu_writel(g, mc_intr_en_0_r(), |
127 | mc_intr_en_0_inta_disabled_f()); | 128 | mc_intr_en_0_inta_disabled_f()); |
@@ -129,27 +130,27 @@ void mc_gk20a_intr_mask(struct gk20a *g) | |||
129 | mc_intr_en_1_inta_disabled_f()); | 130 | mc_intr_en_1_inta_disabled_f()); |
130 | } | 131 | } |
131 | 132 | ||
132 | void mc_gk20a_intr_enable(struct gk20a *g) | 133 | void gm20b_mc_intr_enable(struct gk20a *g) |
133 | { | 134 | { |
134 | u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); | 135 | u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); |
135 | 136 | ||
136 | gk20a_writel(g, mc_intr_mask_1_r(), | 137 | gk20a_writel(g, mc_intr_mask_1_r(), |
137 | mc_intr_0_pfifo_pending_f() | 138 | mc_intr_pfifo_pending_f() |
138 | | eng_intr_mask); | 139 | | eng_intr_mask); |
139 | gk20a_writel(g, mc_intr_en_1_r(), | 140 | gk20a_writel(g, mc_intr_en_1_r(), |
140 | mc_intr_en_1_inta_hardware_f()); | 141 | mc_intr_en_1_inta_hardware_f()); |
141 | 142 | ||
142 | gk20a_writel(g, mc_intr_mask_0_r(), | 143 | gk20a_writel(g, mc_intr_mask_0_r(), |
143 | mc_intr_0_pfifo_pending_f() | 144 | mc_intr_pfifo_pending_f() |
144 | | mc_intr_0_priv_ring_pending_f() | 145 | | mc_intr_priv_ring_pending_f() |
145 | | mc_intr_0_ltc_pending_f() | 146 | | mc_intr_ltc_pending_f() |
146 | | mc_intr_0_pbus_pending_f() | 147 | | mc_intr_pbus_pending_f() |
147 | | eng_intr_mask); | 148 | | eng_intr_mask); |
148 | gk20a_writel(g, mc_intr_en_0_r(), | 149 | gk20a_writel(g, mc_intr_en_0_r(), |
149 | mc_intr_en_0_inta_hardware_f()); | 150 | mc_intr_en_0_inta_hardware_f()); |
150 | } | 151 | } |
151 | 152 | ||
152 | void mc_gk20a_intr_unit_config(struct gk20a *g, bool enable, | 153 | void gm20b_mc_intr_unit_config(struct gk20a *g, bool enable, |
153 | bool is_stalling, u32 mask) | 154 | bool is_stalling, u32 mask) |
154 | { | 155 | { |
155 | u32 mask_reg = (is_stalling ? mc_intr_mask_0_r() : | 156 | u32 mask_reg = (is_stalling ? mc_intr_mask_0_r() : |
@@ -166,7 +167,7 @@ void mc_gk20a_intr_unit_config(struct gk20a *g, bool enable, | |||
166 | } | 167 | } |
167 | } | 168 | } |
168 | 169 | ||
169 | void mc_gk20a_intr_stall_pause(struct gk20a *g) | 170 | void gm20b_mc_intr_stall_pause(struct gk20a *g) |
170 | { | 171 | { |
171 | gk20a_writel(g, mc_intr_en_0_r(), | 172 | gk20a_writel(g, mc_intr_en_0_r(), |
172 | mc_intr_en_0_inta_disabled_f()); | 173 | mc_intr_en_0_inta_disabled_f()); |
@@ -175,7 +176,7 @@ void mc_gk20a_intr_stall_pause(struct gk20a *g) | |||
175 | (void) gk20a_readl(g, mc_intr_en_0_r()); | 176 | (void) gk20a_readl(g, mc_intr_en_0_r()); |
176 | } | 177 | } |
177 | 178 | ||
178 | void mc_gk20a_intr_stall_resume(struct gk20a *g) | 179 | void gm20b_mc_intr_stall_resume(struct gk20a *g) |
179 | { | 180 | { |
180 | gk20a_writel(g, mc_intr_en_0_r(), | 181 | gk20a_writel(g, mc_intr_en_0_r(), |
181 | mc_intr_en_0_inta_hardware_f()); | 182 | mc_intr_en_0_inta_hardware_f()); |
@@ -184,7 +185,7 @@ void mc_gk20a_intr_stall_resume(struct gk20a *g) | |||
184 | (void) gk20a_readl(g, mc_intr_en_0_r()); | 185 | (void) gk20a_readl(g, mc_intr_en_0_r()); |
185 | } | 186 | } |
186 | 187 | ||
187 | void mc_gk20a_intr_nonstall_pause(struct gk20a *g) | 188 | void gm20b_mc_intr_nonstall_pause(struct gk20a *g) |
188 | { | 189 | { |
189 | gk20a_writel(g, mc_intr_en_1_r(), | 190 | gk20a_writel(g, mc_intr_en_1_r(), |
190 | mc_intr_en_0_inta_disabled_f()); | 191 | mc_intr_en_0_inta_disabled_f()); |
@@ -193,7 +194,7 @@ void mc_gk20a_intr_nonstall_pause(struct gk20a *g) | |||
193 | (void) gk20a_readl(g, mc_intr_en_1_r()); | 194 | (void) gk20a_readl(g, mc_intr_en_1_r()); |
194 | } | 195 | } |
195 | 196 | ||
196 | void mc_gk20a_intr_nonstall_resume(struct gk20a *g) | 197 | void gm20b_mc_intr_nonstall_resume(struct gk20a *g) |
197 | { | 198 | { |
198 | gk20a_writel(g, mc_intr_en_1_r(), | 199 | gk20a_writel(g, mc_intr_en_1_r(), |
199 | mc_intr_en_0_inta_hardware_f()); | 200 | mc_intr_en_0_inta_hardware_f()); |
@@ -202,17 +203,17 @@ void mc_gk20a_intr_nonstall_resume(struct gk20a *g) | |||
202 | (void) gk20a_readl(g, mc_intr_en_1_r()); | 203 | (void) gk20a_readl(g, mc_intr_en_1_r()); |
203 | } | 204 | } |
204 | 205 | ||
205 | u32 mc_gk20a_intr_stall(struct gk20a *g) | 206 | u32 gm20b_mc_intr_stall(struct gk20a *g) |
206 | { | 207 | { |
207 | return gk20a_readl(g, mc_intr_0_r()); | 208 | return gk20a_readl(g, mc_intr_r(NVGPU_MC_INTR_STALLING)); |
208 | } | 209 | } |
209 | 210 | ||
210 | u32 mc_gk20a_intr_nonstall(struct gk20a *g) | 211 | u32 gm20b_mc_intr_nonstall(struct gk20a *g) |
211 | { | 212 | { |
212 | return gk20a_readl(g, mc_intr_1_r()); | 213 | return gk20a_readl(g, mc_intr_r(NVGPU_MC_INTR_NONSTALLING)); |
213 | } | 214 | } |
214 | 215 | ||
215 | void gk20a_mc_disable(struct gk20a *g, u32 units) | 216 | void gm20b_mc_disable(struct gk20a *g, u32 units) |
216 | { | 217 | { |
217 | u32 pmc; | 218 | u32 pmc; |
218 | 219 | ||
@@ -225,7 +226,7 @@ void gk20a_mc_disable(struct gk20a *g, u32 units) | |||
225 | nvgpu_spinlock_release(&g->mc_enable_lock); | 226 | nvgpu_spinlock_release(&g->mc_enable_lock); |
226 | } | 227 | } |
227 | 228 | ||
228 | void gk20a_mc_enable(struct gk20a *g, u32 units) | 229 | void gm20b_mc_enable(struct gk20a *g, u32 units) |
229 | { | 230 | { |
230 | u32 pmc; | 231 | u32 pmc; |
231 | 232 | ||
@@ -241,7 +242,7 @@ void gk20a_mc_enable(struct gk20a *g, u32 units) | |||
241 | nvgpu_udelay(20); | 242 | nvgpu_udelay(20); |
242 | } | 243 | } |
243 | 244 | ||
244 | void gk20a_mc_reset(struct gk20a *g, u32 units) | 245 | void gm20b_mc_reset(struct gk20a *g, u32 units) |
245 | { | 246 | { |
246 | g->ops.mc.disable(g, units); | 247 | g->ops.mc.disable(g, units); |
247 | if ((units & gk20a_fifo_get_all_ce_engine_reset_mask(g)) != 0U) { | 248 | if ((units & gk20a_fifo_get_all_ce_engine_reset_mask(g)) != 0U) { |
@@ -252,31 +253,7 @@ void gk20a_mc_reset(struct gk20a *g, u32 units) | |||
252 | g->ops.mc.enable(g, units); | 253 | g->ops.mc.enable(g, units); |
253 | } | 254 | } |
254 | 255 | ||
255 | u32 gk20a_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev) | 256 | bool gm20b_mc_is_intr1_pending(struct gk20a *g, |
256 | { | ||
257 | u32 val = __nvgpu_readl(g, mc_boot_0_r()); | ||
258 | |||
259 | if (val != 0xffffffffU) { | ||
260 | |||
261 | if (arch != NULL) { | ||
262 | *arch = mc_boot_0_architecture_v(val) << | ||
263 | NVGPU_GPU_ARCHITECTURE_SHIFT; | ||
264 | } | ||
265 | |||
266 | if (impl != NULL) { | ||
267 | *impl = mc_boot_0_implementation_v(val); | ||
268 | } | ||
269 | |||
270 | if (rev != NULL) { | ||
271 | *rev = (mc_boot_0_major_revision_v(val) << 4) | | ||
272 | mc_boot_0_minor_revision_v(val); | ||
273 | } | ||
274 | } | ||
275 | |||
276 | return val; | ||
277 | } | ||
278 | |||
279 | bool mc_gk20a_is_intr1_pending(struct gk20a *g, | ||
280 | enum nvgpu_unit unit, u32 mc_intr_1) | 257 | enum nvgpu_unit unit, u32 mc_intr_1) |
281 | { | 258 | { |
282 | u32 mask = 0U; | 259 | u32 mask = 0U; |
@@ -284,7 +261,7 @@ bool mc_gk20a_is_intr1_pending(struct gk20a *g, | |||
284 | 261 | ||
285 | switch (unit) { | 262 | switch (unit) { |
286 | case NVGPU_UNIT_FIFO: | 263 | case NVGPU_UNIT_FIFO: |
287 | mask = mc_intr_0_pfifo_pending_f(); | 264 | mask = mc_intr_pfifo_pending_f(); |
288 | break; | 265 | break; |
289 | default: | 266 | default: |
290 | break; | 267 | break; |
@@ -300,7 +277,7 @@ bool mc_gk20a_is_intr1_pending(struct gk20a *g, | |||
300 | return is_pending; | 277 | return is_pending; |
301 | } | 278 | } |
302 | 279 | ||
303 | void mc_gk20a_log_pending_intrs(struct gk20a *g) | 280 | void gm20b_mc_log_pending_intrs(struct gk20a *g) |
304 | { | 281 | { |
305 | u32 intr; | 282 | u32 intr; |
306 | 283 | ||
@@ -315,17 +292,3 @@ void mc_gk20a_log_pending_intrs(struct gk20a *g) | |||
315 | } | 292 | } |
316 | } | 293 | } |
317 | 294 | ||
318 | void mc_gk20a_handle_intr_nonstall(struct gk20a *g, u32 ops) | ||
319 | { | ||
320 | bool semaphore_wakeup, post_events; | ||
321 | |||
322 | semaphore_wakeup = | ||
323 | (((ops & GK20A_NONSTALL_OPS_WAKEUP_SEMAPHORE) != 0U) ? | ||
324 | true : false); | ||
325 | post_events = (((ops & GK20A_NONSTALL_OPS_POST_EVENTS) != 0U) ? | ||
326 | true: false); | ||
327 | |||
328 | if (semaphore_wakeup) { | ||
329 | g->ops.semaphore_wakeup(g, post_events); | ||
330 | } | ||
331 | } | ||
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.h b/drivers/gpu/nvgpu/common/mc/mc_gm20b.h index 0dfdf906..6700a48c 100644 --- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.h +++ b/drivers/gpu/nvgpu/common/mc/mc_gm20b.h | |||
@@ -20,29 +20,32 @@ | |||
20 | * DEALINGS IN THE SOFTWARE. | 20 | * DEALINGS IN THE SOFTWARE. |
21 | */ | 21 | */ |
22 | 22 | ||
23 | #ifndef MC_GK20A_H | 23 | #ifndef NVGPU_MC_GM20B_H |
24 | #define MC_GK20A_H | 24 | #define NVGPU_MC_GM20B_H |
25 | |||
26 | #include <nvgpu/types.h> | ||
27 | |||
25 | struct gk20a; | 28 | struct gk20a; |
29 | enum nvgpu_unit; | ||
26 | 30 | ||
27 | void mc_gk20a_intr_mask(struct gk20a *g); | 31 | void gm20b_mc_intr_mask(struct gk20a *g); |
28 | void mc_gk20a_intr_enable(struct gk20a *g); | 32 | void gm20b_mc_intr_enable(struct gk20a *g); |
29 | void mc_gk20a_intr_unit_config(struct gk20a *g, bool enable, | 33 | void gm20b_mc_intr_unit_config(struct gk20a *g, bool enable, |
30 | bool is_stalling, u32 mask); | 34 | bool is_stalling, u32 mask); |
31 | void mc_gk20a_isr_stall(struct gk20a *g); | 35 | void gm20b_mc_isr_stall(struct gk20a *g); |
32 | u32 mc_gk20a_intr_stall(struct gk20a *g); | 36 | u32 gm20b_mc_intr_stall(struct gk20a *g); |
33 | void mc_gk20a_intr_stall_pause(struct gk20a *g); | 37 | void gm20b_mc_intr_stall_pause(struct gk20a *g); |
34 | void mc_gk20a_intr_stall_resume(struct gk20a *g); | 38 | void gm20b_mc_intr_stall_resume(struct gk20a *g); |
35 | u32 mc_gk20a_intr_nonstall(struct gk20a *g); | 39 | u32 gm20b_mc_intr_nonstall(struct gk20a *g); |
36 | u32 mc_gk20a_isr_nonstall(struct gk20a *g); | 40 | u32 gm20b_mc_isr_nonstall(struct gk20a *g); |
37 | void mc_gk20a_intr_nonstall_pause(struct gk20a *g); | 41 | void gm20b_mc_intr_nonstall_pause(struct gk20a *g); |
38 | void mc_gk20a_intr_nonstall_resume(struct gk20a *g); | 42 | void gm20b_mc_intr_nonstall_resume(struct gk20a *g); |
39 | void gk20a_mc_enable(struct gk20a *g, u32 units); | 43 | void gm20b_mc_enable(struct gk20a *g, u32 units); |
40 | void gk20a_mc_disable(struct gk20a *g, u32 units); | 44 | void gm20b_mc_disable(struct gk20a *g, u32 units); |
41 | void gk20a_mc_reset(struct gk20a *g, u32 units); | 45 | void gm20b_mc_reset(struct gk20a *g, u32 units); |
42 | u32 gk20a_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev); | 46 | bool gm20b_mc_is_intr1_pending(struct gk20a *g, |
43 | bool mc_gk20a_is_intr1_pending(struct gk20a *g, | ||
44 | enum nvgpu_unit unit, u32 mc_intr_1); | 47 | enum nvgpu_unit unit, u32 mc_intr_1); |
45 | void mc_gk20a_log_pending_intrs(struct gk20a *g); | 48 | void gm20b_mc_log_pending_intrs(struct gk20a *g); |
46 | void mc_gk20a_handle_intr_nonstall(struct gk20a *g, u32 ops); | 49 | void gm20b_mc_handle_intr_nonstall(struct gk20a *g, u32 ops); |
47 | 50 | ||
48 | #endif /* MC_GK20A_H */ | 51 | #endif /* NVGPU_MC_GM20B_H */ |
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/common/mc/mc_gp10b.c index 033d02c5..a0f26dd3 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/common/mc/mc_gp10b.c | |||
@@ -24,6 +24,7 @@ | |||
24 | 24 | ||
25 | #include "gk20a/gk20a.h" | 25 | #include "gk20a/gk20a.h" |
26 | #include <nvgpu/io.h> | 26 | #include <nvgpu/io.h> |
27 | #include <nvgpu/mc.h> | ||
27 | 28 | ||
28 | #include "mc_gp10b.h" | 29 | #include "mc_gp10b.h" |
29 | 30 | ||
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.h b/drivers/gpu/nvgpu/common/mc/mc_gp10b.h index 8c22de62..ee3c0c3b 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.h +++ b/drivers/gpu/nvgpu/common/mc/mc_gp10b.h | |||
@@ -20,12 +20,13 @@ | |||
20 | * DEALINGS IN THE SOFTWARE. | 20 | * DEALINGS IN THE SOFTWARE. |
21 | */ | 21 | */ |
22 | 22 | ||
23 | #ifndef MC_GP20B_H | 23 | #ifndef MC_GP10B_H |
24 | #define MC_GP20B_H | 24 | #define MC_GP10B_H |
25 | struct gk20a; | 25 | |
26 | #include <nvgpu/types.h> | ||
26 | 27 | ||
27 | #define NVGPU_MC_INTR_STALLING 0U | 28 | struct gk20a; |
28 | #define NVGPU_MC_INTR_NONSTALLING 1U | 29 | enum nvgpu_unit; |
29 | 30 | ||
30 | void mc_gp10b_intr_mask(struct gk20a *g); | 31 | void mc_gp10b_intr_mask(struct gk20a *g); |
31 | void mc_gp10b_intr_enable(struct gk20a *g); | 32 | void mc_gp10b_intr_enable(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gv100/mc_gv100.c b/drivers/gpu/nvgpu/common/mc/mc_gv100.c index 069a012a..28c03434 100644 --- a/drivers/gpu/nvgpu/gv100/mc_gv100.c +++ b/drivers/gpu/nvgpu/common/mc/mc_gv100.c | |||
@@ -24,11 +24,11 @@ | |||
24 | 24 | ||
25 | #include <nvgpu/types.h> | 25 | #include <nvgpu/types.h> |
26 | #include <nvgpu/io.h> | 26 | #include <nvgpu/io.h> |
27 | #include <nvgpu/mc.h> | ||
27 | 28 | ||
28 | #include "gk20a/gk20a.h" | 29 | #include "gk20a/gk20a.h" |
29 | 30 | ||
30 | #include "gp10b/mc_gp10b.h" | 31 | #include "mc_gp10b.h" |
31 | |||
32 | #include "mc_gv100.h" | 32 | #include "mc_gv100.h" |
33 | 33 | ||
34 | #include <nvgpu/hw/gv100/hw_mc_gv100.h> | 34 | #include <nvgpu/hw/gv100/hw_mc_gv100.h> |
diff --git a/drivers/gpu/nvgpu/gv100/mc_gv100.h b/drivers/gpu/nvgpu/common/mc/mc_gv100.h index e9069258..c0a16ad9 100644 --- a/drivers/gpu/nvgpu/gv100/mc_gv100.h +++ b/drivers/gpu/nvgpu/common/mc/mc_gv100.h | |||
@@ -22,6 +22,9 @@ | |||
22 | 22 | ||
23 | #ifndef MC_GV100_H | 23 | #ifndef MC_GV100_H |
24 | #define MC_GV100_H | 24 | #define MC_GV100_H |
25 | |||
26 | #include <nvgpu/types.h> | ||
27 | |||
25 | struct gk20a; | 28 | struct gk20a; |
26 | 29 | ||
27 | void mc_gv100_intr_enable(struct gk20a *g); | 30 | void mc_gv100_intr_enable(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/common/mc/mc_gv11b.c index c8072d13..fa4d4bfb 100644 --- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c +++ b/drivers/gpu/nvgpu/common/mc/mc_gv11b.c | |||
@@ -24,11 +24,11 @@ | |||
24 | 24 | ||
25 | #include <nvgpu/types.h> | 25 | #include <nvgpu/types.h> |
26 | #include <nvgpu/io.h> | 26 | #include <nvgpu/io.h> |
27 | #include <nvgpu/mc.h> | ||
27 | 28 | ||
28 | #include "gk20a/gk20a.h" | 29 | #include "gk20a/gk20a.h" |
29 | 30 | ||
30 | #include "gp10b/mc_gp10b.h" | 31 | #include "mc_gp10b.h" |
31 | |||
32 | #include "mc_gv11b.h" | 32 | #include "mc_gv11b.h" |
33 | 33 | ||
34 | #include <nvgpu/hw/gv11b/hw_mc_gv11b.h> | 34 | #include <nvgpu/hw/gv11b/hw_mc_gv11b.h> |
diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.h b/drivers/gpu/nvgpu/common/mc/mc_gv11b.h index faa4d38d..48eba744 100644 --- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.h +++ b/drivers/gpu/nvgpu/common/mc/mc_gv11b.h | |||
@@ -22,6 +22,9 @@ | |||
22 | 22 | ||
23 | #ifndef MC_GV11B_H | 23 | #ifndef MC_GV11B_H |
24 | #define MC_GV11B_H | 24 | #define MC_GV11B_H |
25 | |||
26 | #include <nvgpu/types.h> | ||
27 | |||
25 | struct gk20a; | 28 | struct gk20a; |
26 | 29 | ||
27 | void mc_gv11b_intr_enable(struct gk20a *g); | 30 | void mc_gv11b_intr_enable(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index 1c34c152..df16af85 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c | |||
@@ -37,6 +37,7 @@ | |||
37 | #include <nvgpu/soc.h> | 37 | #include <nvgpu/soc.h> |
38 | #include <nvgpu/clk_arb.h> | 38 | #include <nvgpu/clk_arb.h> |
39 | #include <nvgpu/therm.h> | 39 | #include <nvgpu/therm.h> |
40 | #include <nvgpu/mc.h> | ||
40 | 41 | ||
41 | #include <trace/events/gk20a.h> | 42 | #include <trace/events/gk20a.h> |
42 | 43 | ||
@@ -44,7 +45,6 @@ | |||
44 | #include "channel_sync_gk20a.h" | 45 | #include "channel_sync_gk20a.h" |
45 | 46 | ||
46 | #include "dbg_gpu_gk20a.h" | 47 | #include "dbg_gpu_gk20a.h" |
47 | #include "mc_gk20a.h" | ||
48 | #include "hal.h" | 48 | #include "hal.h" |
49 | #include "pstate/pstate.h" | 49 | #include "pstate/pstate.h" |
50 | 50 | ||
@@ -52,12 +52,7 @@ void __nvgpu_check_gpu_state(struct gk20a *g) | |||
52 | { | 52 | { |
53 | u32 boot_0 = 0xffffffff; | 53 | u32 boot_0 = 0xffffffff; |
54 | 54 | ||
55 | if (!g->ops.mc.boot_0) { | 55 | boot_0 = nvgpu_mc_boot_0(g, NULL, NULL, NULL); |
56 | nvgpu_err(g, "Can't determine GPU state, mc.boot_0 unset"); | ||
57 | return; | ||
58 | } | ||
59 | |||
60 | boot_0 = g->ops.mc.boot_0(g, NULL, NULL, NULL); | ||
61 | if (boot_0 == 0xffffffff) { | 56 | if (boot_0 == 0xffffffff) { |
62 | nvgpu_err(g, "GPU has disappeared from bus!!"); | 57 | nvgpu_err(g, "GPU has disappeared from bus!!"); |
63 | nvgpu_err(g, "Rebooting system!!"); | 58 | nvgpu_err(g, "Rebooting system!!"); |
@@ -78,7 +73,7 @@ int gk20a_detect_chip(struct gk20a *g) | |||
78 | return 0; | 73 | return 0; |
79 | } | 74 | } |
80 | 75 | ||
81 | gk20a_mc_boot_0(g, &p->gpu_arch, &p->gpu_impl, &p->gpu_rev); | 76 | nvgpu_mc_boot_0(g, &p->gpu_arch, &p->gpu_impl, &p->gpu_rev); |
82 | 77 | ||
83 | if ((p->gpu_arch + p->gpu_impl) == NVGPU_GPUID_GV11B) { | 78 | if ((p->gpu_arch + p->gpu_impl) == NVGPU_GPUID_GV11B) { |
84 | 79 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 0df88edf..16a24531 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -30,4 +30,4 @@ | |||
30 | /* no new headers should be added here */ | 30 | /* no new headers should be added here */ |
31 | #include <nvgpu/gk20a.h> | 31 | #include <nvgpu/gk20a.h> |
32 | 32 | ||
33 | #endif \ No newline at end of file | 33 | #endif |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index ca7081cf..f863aa72 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -32,6 +32,7 @@ | |||
32 | #include "common/therm/therm_gm20b.h" | 32 | #include "common/therm/therm_gm20b.h" |
33 | #include "common/ltc/ltc_gm20b.h" | 33 | #include "common/ltc/ltc_gm20b.h" |
34 | #include "common/fuse/fuse_gm20b.h" | 34 | #include "common/fuse/fuse_gm20b.h" |
35 | #include "common/mc/mc_gm20b.h" | ||
35 | 36 | ||
36 | #include "gk20a/gk20a.h" | 37 | #include "gk20a/gk20a.h" |
37 | #include "gk20a/ce2_gk20a.h" | 38 | #include "gk20a/ce2_gk20a.h" |
@@ -39,7 +40,6 @@ | |||
39 | #include "gk20a/fifo_gk20a.h" | 40 | #include "gk20a/fifo_gk20a.h" |
40 | #include "gk20a/mm_gk20a.h" | 41 | #include "gk20a/mm_gk20a.h" |
41 | #include "gk20a/css_gr_gk20a.h" | 42 | #include "gk20a/css_gr_gk20a.h" |
42 | #include "gk20a/mc_gk20a.h" | ||
43 | #include "gk20a/flcn_gk20a.h" | 43 | #include "gk20a/flcn_gk20a.h" |
44 | #include "gk20a/regops_gk20a.h" | 44 | #include "gk20a/regops_gk20a.h" |
45 | #include "gk20a/pmu_gk20a.h" | 45 | #include "gk20a/pmu_gk20a.h" |
@@ -578,23 +578,22 @@ static const struct gpu_ops gm20b_ops = { | |||
578 | .get_qctl_whitelist_count = gm20b_get_qctl_whitelist_count, | 578 | .get_qctl_whitelist_count = gm20b_get_qctl_whitelist_count, |
579 | }, | 579 | }, |
580 | .mc = { | 580 | .mc = { |
581 | .intr_mask = mc_gk20a_intr_mask, | 581 | .intr_mask = gm20b_mc_intr_mask, |
582 | .intr_enable = mc_gk20a_intr_enable, | 582 | .intr_enable = gm20b_mc_intr_enable, |
583 | .intr_unit_config = mc_gk20a_intr_unit_config, | 583 | .intr_unit_config = gm20b_mc_intr_unit_config, |
584 | .isr_stall = mc_gk20a_isr_stall, | 584 | .isr_stall = gm20b_mc_isr_stall, |
585 | .intr_stall = mc_gk20a_intr_stall, | 585 | .intr_stall = gm20b_mc_intr_stall, |
586 | .intr_stall_pause = mc_gk20a_intr_stall_pause, | 586 | .intr_stall_pause = gm20b_mc_intr_stall_pause, |
587 | .intr_stall_resume = mc_gk20a_intr_stall_resume, | 587 | .intr_stall_resume = gm20b_mc_intr_stall_resume, |
588 | .intr_nonstall = mc_gk20a_intr_nonstall, | 588 | .intr_nonstall = gm20b_mc_intr_nonstall, |
589 | .intr_nonstall_pause = mc_gk20a_intr_nonstall_pause, | 589 | .intr_nonstall_pause = gm20b_mc_intr_nonstall_pause, |
590 | .intr_nonstall_resume = mc_gk20a_intr_nonstall_resume, | 590 | .intr_nonstall_resume = gm20b_mc_intr_nonstall_resume, |
591 | .isr_nonstall = mc_gk20a_isr_nonstall, | 591 | .isr_nonstall = gm20b_mc_isr_nonstall, |
592 | .enable = gk20a_mc_enable, | 592 | .enable = gm20b_mc_enable, |
593 | .disable = gk20a_mc_disable, | 593 | .disable = gm20b_mc_disable, |
594 | .reset = gk20a_mc_reset, | 594 | .reset = gm20b_mc_reset, |
595 | .boot_0 = gk20a_mc_boot_0, | 595 | .is_intr1_pending = gm20b_mc_is_intr1_pending, |
596 | .is_intr1_pending = mc_gk20a_is_intr1_pending, | 596 | .log_pending_intrs = gm20b_mc_log_pending_intrs, |
597 | .log_pending_intrs = mc_gk20a_log_pending_intrs, | ||
598 | }, | 597 | }, |
599 | .debug = { | 598 | .debug = { |
600 | .show_dump = gk20a_debug_show_dump, | 599 | .show_dump = gk20a_debug_show_dump, |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 69a797a6..a1682c79 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -40,6 +40,8 @@ | |||
40 | #include "common/fuse/fuse_gm20b.h" | 40 | #include "common/fuse/fuse_gm20b.h" |
41 | #include "common/fuse/fuse_gp10b.h" | 41 | #include "common/fuse/fuse_gp10b.h" |
42 | #include "common/fuse/fuse_gp106.h" | 42 | #include "common/fuse/fuse_gp106.h" |
43 | #include "common/mc/mc_gm20b.h" | ||
44 | #include "common/mc/mc_gp10b.h" | ||
43 | 45 | ||
44 | #include "gk20a/gk20a.h" | 46 | #include "gk20a/gk20a.h" |
45 | #include "gk20a/fifo_gk20a.h" | 47 | #include "gk20a/fifo_gk20a.h" |
@@ -49,13 +51,11 @@ | |||
49 | #include "gk20a/css_gr_gk20a.h" | 51 | #include "gk20a/css_gr_gk20a.h" |
50 | #include "gk20a/flcn_gk20a.h" | 52 | #include "gk20a/flcn_gk20a.h" |
51 | #include "gk20a/regops_gk20a.h" | 53 | #include "gk20a/regops_gk20a.h" |
52 | #include "gk20a/mc_gk20a.h" | ||
53 | #include "gk20a/pmu_gk20a.h" | 54 | #include "gk20a/pmu_gk20a.h" |
54 | #include "gk20a/gr_gk20a.h" | 55 | #include "gk20a/gr_gk20a.h" |
55 | 56 | ||
56 | #include "gp10b/gr_gp10b.h" | 57 | #include "gp10b/gr_gp10b.h" |
57 | #include "gp10b/fecs_trace_gp10b.h" | 58 | #include "gp10b/fecs_trace_gp10b.h" |
58 | #include "gp10b/mc_gp10b.h" | ||
59 | #include "gp10b/mm_gp10b.h" | 59 | #include "gp10b/mm_gp10b.h" |
60 | #include "gp10b/ce_gp10b.h" | 60 | #include "gp10b/ce_gp10b.h" |
61 | #include "gp10b/regops_gp10b.h" | 61 | #include "gp10b/regops_gp10b.h" |
@@ -714,11 +714,10 @@ static const struct gpu_ops gp106_ops = { | |||
714 | .intr_nonstall = mc_gp10b_intr_nonstall, | 714 | .intr_nonstall = mc_gp10b_intr_nonstall, |
715 | .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, | 715 | .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, |
716 | .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, | 716 | .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, |
717 | .isr_nonstall = mc_gk20a_isr_nonstall, | 717 | .isr_nonstall = gm20b_mc_isr_nonstall, |
718 | .enable = gk20a_mc_enable, | 718 | .enable = gm20b_mc_enable, |
719 | .disable = gk20a_mc_disable, | 719 | .disable = gm20b_mc_disable, |
720 | .reset = gk20a_mc_reset, | 720 | .reset = gm20b_mc_reset, |
721 | .boot_0 = gk20a_mc_boot_0, | ||
722 | .is_intr1_pending = mc_gp10b_is_intr1_pending, | 721 | .is_intr1_pending = mc_gp10b_is_intr1_pending, |
723 | .log_pending_intrs = mc_gp10b_log_pending_intrs, | 722 | .log_pending_intrs = mc_gp10b_log_pending_intrs, |
724 | }, | 723 | }, |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index af64d2a9..9430595b 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -37,6 +37,8 @@ | |||
37 | #include "common/ltc/ltc_gp10b.h" | 37 | #include "common/ltc/ltc_gp10b.h" |
38 | #include "common/fuse/fuse_gm20b.h" | 38 | #include "common/fuse/fuse_gm20b.h" |
39 | #include "common/fuse/fuse_gp10b.h" | 39 | #include "common/fuse/fuse_gp10b.h" |
40 | #include "common/mc/mc_gm20b.h" | ||
41 | #include "common/mc/mc_gp10b.h" | ||
40 | 42 | ||
41 | #include "gk20a/gk20a.h" | 43 | #include "gk20a/gk20a.h" |
42 | #include "gk20a/fifo_gk20a.h" | 44 | #include "gk20a/fifo_gk20a.h" |
@@ -46,14 +48,12 @@ | |||
46 | #include "gk20a/css_gr_gk20a.h" | 48 | #include "gk20a/css_gr_gk20a.h" |
47 | #include "gk20a/flcn_gk20a.h" | 49 | #include "gk20a/flcn_gk20a.h" |
48 | #include "gk20a/regops_gk20a.h" | 50 | #include "gk20a/regops_gk20a.h" |
49 | #include "gk20a/mc_gk20a.h" | ||
50 | #include "gk20a/pmu_gk20a.h" | 51 | #include "gk20a/pmu_gk20a.h" |
51 | #include "gk20a/gr_gk20a.h" | 52 | #include "gk20a/gr_gk20a.h" |
52 | #include "gk20a/tsg_gk20a.h" | 53 | #include "gk20a/tsg_gk20a.h" |
53 | 54 | ||
54 | #include "gp10b/gr_gp10b.h" | 55 | #include "gp10b/gr_gp10b.h" |
55 | #include "gp10b/fecs_trace_gp10b.h" | 56 | #include "gp10b/fecs_trace_gp10b.h" |
56 | #include "gp10b/mc_gp10b.h" | ||
57 | #include "gp10b/mm_gp10b.h" | 57 | #include "gp10b/mm_gp10b.h" |
58 | #include "gp10b/ce_gp10b.h" | 58 | #include "gp10b/ce_gp10b.h" |
59 | #include "gp10b/pmu_gp10b.h" | 59 | #include "gp10b/pmu_gp10b.h" |
@@ -640,11 +640,10 @@ static const struct gpu_ops gp10b_ops = { | |||
640 | .intr_nonstall = mc_gp10b_intr_nonstall, | 640 | .intr_nonstall = mc_gp10b_intr_nonstall, |
641 | .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, | 641 | .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, |
642 | .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, | 642 | .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, |
643 | .isr_nonstall = mc_gk20a_isr_nonstall, | 643 | .isr_nonstall = gm20b_mc_isr_nonstall, |
644 | .enable = gk20a_mc_enable, | 644 | .enable = gm20b_mc_enable, |
645 | .disable = gk20a_mc_disable, | 645 | .disable = gm20b_mc_disable, |
646 | .reset = gk20a_mc_reset, | 646 | .reset = gm20b_mc_reset, |
647 | .boot_0 = gk20a_mc_boot_0, | ||
648 | .is_intr1_pending = mc_gp10b_is_intr1_pending, | 647 | .is_intr1_pending = mc_gp10b_is_intr1_pending, |
649 | .log_pending_intrs = mc_gp10b_log_pending_intrs, | 648 | .log_pending_intrs = mc_gp10b_log_pending_intrs, |
650 | }, | 649 | }, |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 4af237b0..d6ee0139 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -45,12 +45,15 @@ | |||
45 | #include "common/fuse/fuse_gp10b.h" | 45 | #include "common/fuse/fuse_gp10b.h" |
46 | #include "common/fuse/fuse_gp106.h" | 46 | #include "common/fuse/fuse_gp106.h" |
47 | #include "common/top/top_gv100.h" | 47 | #include "common/top/top_gv100.h" |
48 | #include "common/mc/mc_gm20b.h" | ||
49 | #include "common/mc/mc_gp10b.h" | ||
50 | #include "common/mc/mc_gv11b.h" | ||
51 | #include "common/mc/mc_gv100.h" | ||
48 | 52 | ||
49 | #include "gk20a/gk20a.h" | 53 | #include "gk20a/gk20a.h" |
50 | #include "gk20a/fifo_gk20a.h" | 54 | #include "gk20a/fifo_gk20a.h" |
51 | #include "gk20a/fecs_trace_gk20a.h" | 55 | #include "gk20a/fecs_trace_gk20a.h" |
52 | #include "gk20a/css_gr_gk20a.h" | 56 | #include "gk20a/css_gr_gk20a.h" |
53 | #include "gk20a/mc_gk20a.h" | ||
54 | #include "gk20a/dbg_gpu_gk20a.h" | 57 | #include "gk20a/dbg_gpu_gk20a.h" |
55 | #include "gk20a/flcn_gk20a.h" | 58 | #include "gk20a/flcn_gk20a.h" |
56 | #include "gk20a/regops_gk20a.h" | 59 | #include "gk20a/regops_gk20a.h" |
@@ -74,7 +77,6 @@ | |||
74 | #include "gp106/flcn_gp106.h" | 77 | #include "gp106/flcn_gp106.h" |
75 | 78 | ||
76 | #include "gp10b/gr_gp10b.h" | 79 | #include "gp10b/gr_gp10b.h" |
77 | #include "gp10b/mc_gp10b.h" | ||
78 | #include "gp10b/ce_gp10b.h" | 80 | #include "gp10b/ce_gp10b.h" |
79 | #include "gp10b/fifo_gp10b.h" | 81 | #include "gp10b/fifo_gp10b.h" |
80 | #include "gp10b/fecs_trace_gp10b.h" | 82 | #include "gp10b/fecs_trace_gp10b.h" |
@@ -85,7 +87,6 @@ | |||
85 | #include "gv11b/dbg_gpu_gv11b.h" | 87 | #include "gv11b/dbg_gpu_gv11b.h" |
86 | #include "gv11b/hal_gv11b.h" | 88 | #include "gv11b/hal_gv11b.h" |
87 | #include "gv11b/gr_gv11b.h" | 89 | #include "gv11b/gr_gv11b.h" |
88 | #include "gv11b/mc_gv11b.h" | ||
89 | #include "gv11b/gv11b.h" | 90 | #include "gv11b/gv11b.h" |
90 | #include "gv11b/ce_gv11b.h" | 91 | #include "gv11b/ce_gv11b.h" |
91 | #include "gv11b/mm_gv11b.h" | 92 | #include "gv11b/mm_gv11b.h" |
@@ -102,7 +103,6 @@ | |||
102 | #include "gv100/flcn_gv100.h" | 103 | #include "gv100/flcn_gv100.h" |
103 | #include "gv100/gr_ctx_gv100.h" | 104 | #include "gv100/gr_ctx_gv100.h" |
104 | #include "gv100/gr_gv100.h" | 105 | #include "gv100/gr_gv100.h" |
105 | #include "gv100/mc_gv100.h" | ||
106 | #include "gv100/mm_gv100.h" | 106 | #include "gv100/mm_gv100.h" |
107 | #include "gv100/pmu_gv100.h" | 107 | #include "gv100/pmu_gv100.h" |
108 | #include "gv100/nvlink_gv100.h" | 108 | #include "gv100/nvlink_gv100.h" |
@@ -805,11 +805,10 @@ static const struct gpu_ops gv100_ops = { | |||
805 | .intr_nonstall = mc_gp10b_intr_nonstall, | 805 | .intr_nonstall = mc_gp10b_intr_nonstall, |
806 | .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, | 806 | .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, |
807 | .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, | 807 | .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, |
808 | .isr_nonstall = mc_gk20a_isr_nonstall, | 808 | .isr_nonstall = gm20b_mc_isr_nonstall, |
809 | .enable = gk20a_mc_enable, | 809 | .enable = gm20b_mc_enable, |
810 | .disable = gk20a_mc_disable, | 810 | .disable = gm20b_mc_disable, |
811 | .reset = gk20a_mc_reset, | 811 | .reset = gm20b_mc_reset, |
812 | .boot_0 = gk20a_mc_boot_0, | ||
813 | .log_pending_intrs = mc_gp10b_log_pending_intrs, | 812 | .log_pending_intrs = mc_gp10b_log_pending_intrs, |
814 | .is_intr1_pending = mc_gp10b_is_intr1_pending, | 813 | .is_intr1_pending = mc_gp10b_is_intr1_pending, |
815 | .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending, | 814 | .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending, |
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 64b8084e..4632d3f8 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |||
@@ -59,7 +59,6 @@ | |||
59 | #include "fifo_gv11b.h" | 59 | #include "fifo_gv11b.h" |
60 | #include "subctx_gv11b.h" | 60 | #include "subctx_gv11b.h" |
61 | #include "gr_gv11b.h" | 61 | #include "gr_gv11b.h" |
62 | #include "mc_gv11b.h" | ||
63 | 62 | ||
64 | void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist) | 63 | void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist) |
65 | { | 64 | { |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index a27d9ab5..91122fba 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -40,12 +40,14 @@ | |||
40 | #include "common/ltc/ltc_gv11b.h" | 40 | #include "common/ltc/ltc_gv11b.h" |
41 | #include "common/fuse/fuse_gm20b.h" | 41 | #include "common/fuse/fuse_gm20b.h" |
42 | #include "common/fuse/fuse_gp10b.h" | 42 | #include "common/fuse/fuse_gp10b.h" |
43 | #include "common/mc/mc_gm20b.h" | ||
44 | #include "common/mc/mc_gp10b.h" | ||
45 | #include "common/mc/mc_gv11b.h" | ||
43 | 46 | ||
44 | #include "gk20a/gk20a.h" | 47 | #include "gk20a/gk20a.h" |
45 | #include "gk20a/fifo_gk20a.h" | 48 | #include "gk20a/fifo_gk20a.h" |
46 | #include "gk20a/fecs_trace_gk20a.h" | 49 | #include "gk20a/fecs_trace_gk20a.h" |
47 | #include "gk20a/css_gr_gk20a.h" | 50 | #include "gk20a/css_gr_gk20a.h" |
48 | #include "gk20a/mc_gk20a.h" | ||
49 | #include "gk20a/mm_gk20a.h" | 51 | #include "gk20a/mm_gk20a.h" |
50 | #include "gk20a/dbg_gpu_gk20a.h" | 52 | #include "gk20a/dbg_gpu_gk20a.h" |
51 | #include "gk20a/flcn_gk20a.h" | 53 | #include "gk20a/flcn_gk20a.h" |
@@ -59,7 +61,6 @@ | |||
59 | #include "gm20b/acr_gm20b.h" | 61 | #include "gm20b/acr_gm20b.h" |
60 | #include "gm20b/pmu_gm20b.h" | 62 | #include "gm20b/pmu_gm20b.h" |
61 | 63 | ||
62 | #include "gp10b/mc_gp10b.h" | ||
63 | #include "gp10b/ce_gp10b.h" | 64 | #include "gp10b/ce_gp10b.h" |
64 | #include "gp10b/fifo_gp10b.h" | 65 | #include "gp10b/fifo_gp10b.h" |
65 | #include "gp10b/fecs_trace_gp10b.h" | 66 | #include "gp10b/fecs_trace_gp10b.h" |
@@ -76,7 +77,6 @@ | |||
76 | #include "hal_gv11b.h" | 77 | #include "hal_gv11b.h" |
77 | #include "css_gr_gv11b.h" | 78 | #include "css_gr_gv11b.h" |
78 | #include "gr_gv11b.h" | 79 | #include "gr_gv11b.h" |
79 | #include "mc_gv11b.h" | ||
80 | #include "gv11b.h" | 80 | #include "gv11b.h" |
81 | #include "ce_gv11b.h" | 81 | #include "ce_gv11b.h" |
82 | #include "gr_ctx_gv11b.h" | 82 | #include "gr_ctx_gv11b.h" |
@@ -736,11 +736,10 @@ static const struct gpu_ops gv11b_ops = { | |||
736 | .intr_nonstall = mc_gp10b_intr_nonstall, | 736 | .intr_nonstall = mc_gp10b_intr_nonstall, |
737 | .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, | 737 | .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, |
738 | .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, | 738 | .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, |
739 | .isr_nonstall = mc_gk20a_isr_nonstall, | 739 | .isr_nonstall = gm20b_mc_isr_nonstall, |
740 | .enable = gk20a_mc_enable, | 740 | .enable = gm20b_mc_enable, |
741 | .disable = gk20a_mc_disable, | 741 | .disable = gm20b_mc_disable, |
742 | .reset = gk20a_mc_reset, | 742 | .reset = gm20b_mc_reset, |
743 | .boot_0 = gk20a_mc_boot_0, | ||
744 | .is_intr1_pending = mc_gp10b_is_intr1_pending, | 743 | .is_intr1_pending = mc_gp10b_is_intr1_pending, |
745 | .log_pending_intrs = mc_gp10b_log_pending_intrs, | 744 | .log_pending_intrs = mc_gp10b_log_pending_intrs, |
746 | .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending, | 745 | .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending, |
diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index ceadc1c1..5d5aed94 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c | |||
@@ -32,7 +32,6 @@ | |||
32 | #include "gk20a/mm_gk20a.h" | 32 | #include "gk20a/mm_gk20a.h" |
33 | 33 | ||
34 | #include "gp10b/mm_gp10b.h" | 34 | #include "gp10b/mm_gp10b.h" |
35 | #include "gp10b/mc_gp10b.h" | ||
36 | 35 | ||
37 | #include "mm_gv11b.h" | 36 | #include "mm_gv11b.h" |
38 | #include "subctx_gv11b.h" | 37 | #include "subctx_gv11b.h" |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 31ca1b45..56b14245 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h | |||
@@ -1166,7 +1166,6 @@ struct gpu_ops { | |||
1166 | void (*enable)(struct gk20a *g, u32 units); | 1166 | void (*enable)(struct gk20a *g, u32 units); |
1167 | void (*disable)(struct gk20a *g, u32 units); | 1167 | void (*disable)(struct gk20a *g, u32 units); |
1168 | void (*reset)(struct gk20a *g, u32 units); | 1168 | void (*reset)(struct gk20a *g, u32 units); |
1169 | u32 (*boot_0)(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev); | ||
1170 | bool (*is_intr1_pending)(struct gk20a *g, enum nvgpu_unit unit, u32 mc_intr_1); | 1169 | bool (*is_intr1_pending)(struct gk20a *g, enum nvgpu_unit unit, u32 mc_intr_1); |
1171 | void (*log_pending_intrs)(struct gk20a *g); | 1170 | void (*log_pending_intrs)(struct gk20a *g); |
1172 | } mc; | 1171 | } mc; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/mc.h b/drivers/gpu/nvgpu/include/nvgpu/mc.h new file mode 100644 index 00000000..3c012f99 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/mc.h | |||
@@ -0,0 +1,35 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef NVGPU_MC_H | ||
24 | #define NVGPU_MC_H | ||
25 | |||
26 | #include <nvgpu/types.h> | ||
27 | |||
28 | struct gk20a; | ||
29 | |||
30 | #define NVGPU_MC_INTR_STALLING 0U | ||
31 | #define NVGPU_MC_INTR_NONSTALLING 1U | ||
32 | |||
33 | u32 nvgpu_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev); | ||
34 | |||
35 | #endif | ||
diff --git a/drivers/gpu/nvgpu/os/linux/intr.c b/drivers/gpu/nvgpu/os/linux/intr.c index 7ffc7e87..5ed6e35c 100644 --- a/drivers/gpu/nvgpu/os/linux/intr.c +++ b/drivers/gpu/nvgpu/os/linux/intr.c | |||
@@ -15,7 +15,6 @@ | |||
15 | #include <linux/irqreturn.h> | 15 | #include <linux/irqreturn.h> |
16 | 16 | ||
17 | #include "gk20a/gk20a.h" | 17 | #include "gk20a/gk20a.h" |
18 | #include "gk20a/mc_gk20a.h" | ||
19 | 18 | ||
20 | #include <nvgpu/atomic.h> | 19 | #include <nvgpu/atomic.h> |
21 | #include <nvgpu/unit.h> | 20 | #include <nvgpu/unit.h> |
@@ -107,6 +106,21 @@ irqreturn_t nvgpu_intr_nonstall(struct gk20a *g) | |||
107 | return IRQ_HANDLED; | 106 | return IRQ_HANDLED; |
108 | } | 107 | } |
109 | 108 | ||
109 | static void mc_gk20a_handle_intr_nonstall(struct gk20a *g, u32 ops) | ||
110 | { | ||
111 | bool semaphore_wakeup, post_events; | ||
112 | |||
113 | semaphore_wakeup = | ||
114 | (((ops & GK20A_NONSTALL_OPS_WAKEUP_SEMAPHORE) != 0U) ? | ||
115 | true : false); | ||
116 | post_events = (((ops & GK20A_NONSTALL_OPS_POST_EVENTS) != 0U) ? | ||
117 | true: false); | ||
118 | |||
119 | if (semaphore_wakeup) { | ||
120 | g->ops.semaphore_wakeup(g, post_events); | ||
121 | } | ||
122 | } | ||
123 | |||
110 | void nvgpu_intr_nonstall_cb(struct work_struct *work) | 124 | void nvgpu_intr_nonstall_cb(struct work_struct *work) |
111 | { | 125 | { |
112 | struct nvgpu_os_linux *l = | 126 | struct nvgpu_os_linux *l = |
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index 58f595f4..a90d2d94 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -49,11 +49,9 @@ | |||
49 | #include "vgpu_fuse_gp10b.h" | 49 | #include "vgpu_fuse_gp10b.h" |
50 | 50 | ||
51 | #include "gk20a/flcn_gk20a.h" | 51 | #include "gk20a/flcn_gk20a.h" |
52 | #include "gk20a/mc_gk20a.h" | ||
53 | #include "gk20a/dbg_gpu_gk20a.h" | 52 | #include "gk20a/dbg_gpu_gk20a.h" |
54 | #include "gk20a/pmu_gk20a.h" | 53 | #include "gk20a/pmu_gk20a.h" |
55 | 54 | ||
56 | #include "gp10b/mc_gp10b.h" | ||
57 | #include "gp10b/mm_gp10b.h" | 55 | #include "gp10b/mm_gp10b.h" |
58 | #include "gp10b/ce_gp10b.h" | 56 | #include "gp10b/ce_gp10b.h" |
59 | #include "gp10b/pmu_gp10b.h" | 57 | #include "gp10b/pmu_gp10b.h" |
@@ -484,7 +482,6 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
484 | .enable = NULL, | 482 | .enable = NULL, |
485 | .disable = NULL, | 483 | .disable = NULL, |
486 | .reset = NULL, | 484 | .reset = NULL, |
487 | .boot_0 = NULL, | ||
488 | .is_intr1_pending = NULL, | 485 | .is_intr1_pending = NULL, |
489 | .log_pending_intrs = NULL, | 486 | .log_pending_intrs = NULL, |
490 | }, | 487 | }, |
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 9832a714..3a917bf3 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | |||
@@ -54,7 +54,6 @@ | |||
54 | #include "vgpu/gp10b/vgpu_gr_gp10b.h" | 54 | #include "vgpu/gp10b/vgpu_gr_gp10b.h" |
55 | 55 | ||
56 | #include <gk20a/flcn_gk20a.h> | 56 | #include <gk20a/flcn_gk20a.h> |
57 | #include <gk20a/mc_gk20a.h> | ||
58 | #include "gk20a/dbg_gpu_gk20a.h" | 57 | #include "gk20a/dbg_gpu_gk20a.h" |
59 | #include <gk20a/pmu_gk20a.h> | 58 | #include <gk20a/pmu_gk20a.h> |
60 | 59 | ||
@@ -66,7 +65,6 @@ | |||
66 | 65 | ||
67 | #include <gp10b/pmu_gp10b.h> | 66 | #include <gp10b/pmu_gp10b.h> |
68 | #include <gp10b/mm_gp10b.h> | 67 | #include <gp10b/mm_gp10b.h> |
69 | #include <gp10b/mc_gp10b.h> | ||
70 | #include <gp10b/ce_gp10b.h> | 68 | #include <gp10b/ce_gp10b.h> |
71 | #include "gp10b/gr_gp10b.h" | 69 | #include "gp10b/gr_gp10b.h" |
72 | #include <gp10b/fifo_gp10b.h> | 70 | #include <gp10b/fifo_gp10b.h> |
@@ -77,7 +75,6 @@ | |||
77 | #include <gv11b/pmu_gv11b.h> | 75 | #include <gv11b/pmu_gv11b.h> |
78 | #include <gv11b/acr_gv11b.h> | 76 | #include <gv11b/acr_gv11b.h> |
79 | #include <gv11b/mm_gv11b.h> | 77 | #include <gv11b/mm_gv11b.h> |
80 | #include <gv11b/mc_gv11b.h> | ||
81 | #include <gv11b/ce_gv11b.h> | 78 | #include <gv11b/ce_gv11b.h> |
82 | #include <gv11b/fifo_gv11b.h> | 79 | #include <gv11b/fifo_gv11b.h> |
83 | #include <gv11b/regops_gv11b.h> | 80 | #include <gv11b/regops_gv11b.h> |
@@ -553,7 +550,6 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
553 | .enable = NULL, | 550 | .enable = NULL, |
554 | .disable = NULL, | 551 | .disable = NULL, |
555 | .reset = NULL, | 552 | .reset = NULL, |
556 | .boot_0 = NULL, | ||
557 | .is_intr1_pending = NULL, | 553 | .is_intr1_pending = NULL, |
558 | .is_intr_hub_pending = NULL, | 554 | .is_intr_hub_pending = NULL, |
559 | .log_pending_intrs = NULL , | 555 | .log_pending_intrs = NULL , |