diff options
Diffstat (limited to 'drivers/gpu/nvgpu/common/mc')
-rw-r--r-- | drivers/gpu/nvgpu/common/mc/mc.c | 54 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/mc/mc_gm20b.c | 294 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/mc/mc_gm20b.h | 51 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/mc/mc_gp10b.c | 224 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/mc/mc_gp10b.h | 47 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/mc/mc_gv100.c | 91 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/mc/mc_gv100.h | 34 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/mc/mc_gv11b.c | 90 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/mc/mc_gv11b.h | 34 |
9 files changed, 919 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/common/mc/mc.c b/drivers/gpu/nvgpu/common/mc/mc.c new file mode 100644 index 00000000..77416ef9 --- /dev/null +++ b/drivers/gpu/nvgpu/common/mc/mc.c | |||
@@ -0,0 +1,54 @@ | |||
1 | /* | ||
2 | * GK20A Master Control | ||
3 | * | ||
4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include <nvgpu/io.h> | ||
26 | #include <nvgpu/mc.h> | ||
27 | |||
28 | #include "gk20a/gk20a.h" | ||
29 | |||
30 | #include <nvgpu/hw/gm20b/hw_mc_gm20b.h> | ||
31 | |||
32 | u32 nvgpu_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev) | ||
33 | { | ||
34 | u32 val = __nvgpu_readl(g, mc_boot_0_r()); | ||
35 | |||
36 | if (val != 0xffffffffU) { | ||
37 | |||
38 | if (arch != NULL) { | ||
39 | *arch = mc_boot_0_architecture_v(val) << | ||
40 | NVGPU_GPU_ARCHITECTURE_SHIFT; | ||
41 | } | ||
42 | |||
43 | if (impl != NULL) { | ||
44 | *impl = mc_boot_0_implementation_v(val); | ||
45 | } | ||
46 | |||
47 | if (rev != NULL) { | ||
48 | *rev = (mc_boot_0_major_revision_v(val) << 4) | | ||
49 | mc_boot_0_minor_revision_v(val); | ||
50 | } | ||
51 | } | ||
52 | |||
53 | return val; | ||
54 | } | ||
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gm20b.c b/drivers/gpu/nvgpu/common/mc/mc_gm20b.c new file mode 100644 index 00000000..88666b1d --- /dev/null +++ b/drivers/gpu/nvgpu/common/mc/mc_gm20b.c | |||
@@ -0,0 +1,294 @@ | |||
1 | /* | ||
2 | * GK20A Master Control | ||
3 | * | ||
4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include <nvgpu/timers.h> | ||
26 | #include <nvgpu/atomic.h> | ||
27 | #include <nvgpu/unit.h> | ||
28 | #include <nvgpu/io.h> | ||
29 | #include <nvgpu/mc.h> | ||
30 | |||
31 | #include "gk20a/gk20a.h" | ||
32 | #include "mc_gm20b.h" | ||
33 | |||
34 | #include <nvgpu/hw/gm20b/hw_mc_gm20b.h> | ||
35 | |||
36 | void gm20b_mc_isr_stall(struct gk20a *g) | ||
37 | { | ||
38 | u32 mc_intr_0; | ||
39 | u32 engine_id_idx; | ||
40 | u32 active_engine_id = 0; | ||
41 | u32 engine_enum = ENGINE_INVAL_GK20A; | ||
42 | |||
43 | mc_intr_0 = g->ops.mc.intr_stall(g); | ||
44 | |||
45 | nvgpu_log(g, gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); | ||
46 | |||
47 | for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) { | ||
48 | active_engine_id = g->fifo.active_engines_list[engine_id_idx]; | ||
49 | |||
50 | if ((mc_intr_0 & g->fifo.engine_info[active_engine_id].intr_mask) != 0U) { | ||
51 | engine_enum = g->fifo.engine_info[active_engine_id].engine_enum; | ||
52 | /* GR Engine */ | ||
53 | if (engine_enum == ENGINE_GR_GK20A) { | ||
54 | gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); | ||
55 | } | ||
56 | |||
57 | /* CE Engine */ | ||
58 | if (((engine_enum == ENGINE_GRCE_GK20A) || | ||
59 | (engine_enum == ENGINE_ASYNC_CE_GK20A)) && | ||
60 | (g->ops.ce2.isr_stall != NULL)) { | ||
61 | g->ops.ce2.isr_stall(g, | ||
62 | g->fifo.engine_info[active_engine_id].inst_id, | ||
63 | g->fifo.engine_info[active_engine_id].pri_base); | ||
64 | } | ||
65 | } | ||
66 | } | ||
67 | if ((mc_intr_0 & mc_intr_pfifo_pending_f()) != 0U) { | ||
68 | gk20a_fifo_isr(g); | ||
69 | } | ||
70 | if ((mc_intr_0 & mc_intr_pmu_pending_f()) != 0U) { | ||
71 | g->ops.pmu.pmu_isr(g); | ||
72 | } | ||
73 | if ((mc_intr_0 & mc_intr_priv_ring_pending_f()) != 0U) { | ||
74 | g->ops.priv_ring.isr(g); | ||
75 | } | ||
76 | if ((mc_intr_0 & mc_intr_ltc_pending_f()) != 0U) { | ||
77 | g->ops.ltc.isr(g); | ||
78 | } | ||
79 | if ((mc_intr_0 & mc_intr_pbus_pending_f()) != 0U) { | ||
80 | g->ops.bus.isr(g); | ||
81 | } | ||
82 | } | ||
83 | |||
84 | u32 gm20b_mc_isr_nonstall(struct gk20a *g) | ||
85 | { | ||
86 | u32 ops = 0; | ||
87 | u32 mc_intr_1; | ||
88 | u32 engine_id_idx; | ||
89 | u32 active_engine_id = 0; | ||
90 | u32 engine_enum = ENGINE_INVAL_GK20A; | ||
91 | |||
92 | mc_intr_1 = g->ops.mc.intr_nonstall(g); | ||
93 | |||
94 | if (g->ops.mc.is_intr1_pending(g, NVGPU_UNIT_FIFO, mc_intr_1) != 0U) { | ||
95 | ops |= gk20a_fifo_nonstall_isr(g); | ||
96 | } | ||
97 | |||
98 | for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; | ||
99 | engine_id_idx++) { | ||
100 | struct fifo_engine_info_gk20a *engine_info; | ||
101 | |||
102 | active_engine_id = g->fifo.active_engines_list[engine_id_idx]; | ||
103 | engine_info = &g->fifo.engine_info[active_engine_id]; | ||
104 | |||
105 | if ((mc_intr_1 & engine_info->intr_mask) != 0U) { | ||
106 | engine_enum = engine_info->engine_enum; | ||
107 | /* GR Engine */ | ||
108 | if (engine_enum == ENGINE_GR_GK20A) { | ||
109 | ops |= gk20a_gr_nonstall_isr(g); | ||
110 | } | ||
111 | /* CE Engine */ | ||
112 | if (((engine_enum == ENGINE_GRCE_GK20A) || | ||
113 | (engine_enum == ENGINE_ASYNC_CE_GK20A)) && | ||
114 | (g->ops.ce2.isr_nonstall != NULL)) { | ||
115 | ops |= g->ops.ce2.isr_nonstall(g, | ||
116 | engine_info->inst_id, | ||
117 | engine_info->pri_base); | ||
118 | } | ||
119 | } | ||
120 | } | ||
121 | |||
122 | return ops; | ||
123 | } | ||
124 | |||
125 | void gm20b_mc_intr_mask(struct gk20a *g) | ||
126 | { | ||
127 | nvgpu_writel(g, mc_intr_en_0_r(), | ||
128 | mc_intr_en_0_inta_disabled_f()); | ||
129 | nvgpu_writel(g, mc_intr_en_1_r(), | ||
130 | mc_intr_en_1_inta_disabled_f()); | ||
131 | } | ||
132 | |||
133 | void gm20b_mc_intr_enable(struct gk20a *g) | ||
134 | { | ||
135 | u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); | ||
136 | |||
137 | gk20a_writel(g, mc_intr_mask_1_r(), | ||
138 | mc_intr_pfifo_pending_f() | ||
139 | | eng_intr_mask); | ||
140 | gk20a_writel(g, mc_intr_en_1_r(), | ||
141 | mc_intr_en_1_inta_hardware_f()); | ||
142 | |||
143 | gk20a_writel(g, mc_intr_mask_0_r(), | ||
144 | mc_intr_pfifo_pending_f() | ||
145 | | mc_intr_priv_ring_pending_f() | ||
146 | | mc_intr_ltc_pending_f() | ||
147 | | mc_intr_pbus_pending_f() | ||
148 | | eng_intr_mask); | ||
149 | gk20a_writel(g, mc_intr_en_0_r(), | ||
150 | mc_intr_en_0_inta_hardware_f()); | ||
151 | } | ||
152 | |||
153 | void gm20b_mc_intr_unit_config(struct gk20a *g, bool enable, | ||
154 | bool is_stalling, u32 mask) | ||
155 | { | ||
156 | u32 mask_reg = (is_stalling ? mc_intr_mask_0_r() : | ||
157 | mc_intr_mask_1_r()); | ||
158 | |||
159 | if (enable) { | ||
160 | gk20a_writel(g, mask_reg, | ||
161 | gk20a_readl(g, mask_reg) | | ||
162 | mask); | ||
163 | } else { | ||
164 | gk20a_writel(g, mask_reg, | ||
165 | gk20a_readl(g, mask_reg) & | ||
166 | ~mask); | ||
167 | } | ||
168 | } | ||
169 | |||
170 | void gm20b_mc_intr_stall_pause(struct gk20a *g) | ||
171 | { | ||
172 | gk20a_writel(g, mc_intr_en_0_r(), | ||
173 | mc_intr_en_0_inta_disabled_f()); | ||
174 | |||
175 | /* flush previous write */ | ||
176 | (void) gk20a_readl(g, mc_intr_en_0_r()); | ||
177 | } | ||
178 | |||
179 | void gm20b_mc_intr_stall_resume(struct gk20a *g) | ||
180 | { | ||
181 | gk20a_writel(g, mc_intr_en_0_r(), | ||
182 | mc_intr_en_0_inta_hardware_f()); | ||
183 | |||
184 | /* flush previous write */ | ||
185 | (void) gk20a_readl(g, mc_intr_en_0_r()); | ||
186 | } | ||
187 | |||
188 | void gm20b_mc_intr_nonstall_pause(struct gk20a *g) | ||
189 | { | ||
190 | gk20a_writel(g, mc_intr_en_1_r(), | ||
191 | mc_intr_en_0_inta_disabled_f()); | ||
192 | |||
193 | /* flush previous write */ | ||
194 | (void) gk20a_readl(g, mc_intr_en_1_r()); | ||
195 | } | ||
196 | |||
197 | void gm20b_mc_intr_nonstall_resume(struct gk20a *g) | ||
198 | { | ||
199 | gk20a_writel(g, mc_intr_en_1_r(), | ||
200 | mc_intr_en_0_inta_hardware_f()); | ||
201 | |||
202 | /* flush previous write */ | ||
203 | (void) gk20a_readl(g, mc_intr_en_1_r()); | ||
204 | } | ||
205 | |||
206 | u32 gm20b_mc_intr_stall(struct gk20a *g) | ||
207 | { | ||
208 | return gk20a_readl(g, mc_intr_r(NVGPU_MC_INTR_STALLING)); | ||
209 | } | ||
210 | |||
211 | u32 gm20b_mc_intr_nonstall(struct gk20a *g) | ||
212 | { | ||
213 | return gk20a_readl(g, mc_intr_r(NVGPU_MC_INTR_NONSTALLING)); | ||
214 | } | ||
215 | |||
216 | void gm20b_mc_disable(struct gk20a *g, u32 units) | ||
217 | { | ||
218 | u32 pmc; | ||
219 | |||
220 | nvgpu_log(g, gpu_dbg_info, "pmc disable: %08x\n", units); | ||
221 | |||
222 | nvgpu_spinlock_acquire(&g->mc_enable_lock); | ||
223 | pmc = gk20a_readl(g, mc_enable_r()); | ||
224 | pmc &= ~units; | ||
225 | gk20a_writel(g, mc_enable_r(), pmc); | ||
226 | nvgpu_spinlock_release(&g->mc_enable_lock); | ||
227 | } | ||
228 | |||
229 | void gm20b_mc_enable(struct gk20a *g, u32 units) | ||
230 | { | ||
231 | u32 pmc; | ||
232 | |||
233 | nvgpu_log(g, gpu_dbg_info, "pmc enable: %08x\n", units); | ||
234 | |||
235 | nvgpu_spinlock_acquire(&g->mc_enable_lock); | ||
236 | pmc = gk20a_readl(g, mc_enable_r()); | ||
237 | pmc |= units; | ||
238 | gk20a_writel(g, mc_enable_r(), pmc); | ||
239 | pmc = gk20a_readl(g, mc_enable_r()); | ||
240 | nvgpu_spinlock_release(&g->mc_enable_lock); | ||
241 | |||
242 | nvgpu_udelay(20); | ||
243 | } | ||
244 | |||
245 | void gm20b_mc_reset(struct gk20a *g, u32 units) | ||
246 | { | ||
247 | g->ops.mc.disable(g, units); | ||
248 | if ((units & gk20a_fifo_get_all_ce_engine_reset_mask(g)) != 0U) { | ||
249 | nvgpu_udelay(500); | ||
250 | } else { | ||
251 | nvgpu_udelay(20); | ||
252 | } | ||
253 | g->ops.mc.enable(g, units); | ||
254 | } | ||
255 | |||
256 | bool gm20b_mc_is_intr1_pending(struct gk20a *g, | ||
257 | enum nvgpu_unit unit, u32 mc_intr_1) | ||
258 | { | ||
259 | u32 mask = 0U; | ||
260 | bool is_pending; | ||
261 | |||
262 | switch (unit) { | ||
263 | case NVGPU_UNIT_FIFO: | ||
264 | mask = mc_intr_pfifo_pending_f(); | ||
265 | break; | ||
266 | default: | ||
267 | break; | ||
268 | } | ||
269 | |||
270 | if (mask == 0U) { | ||
271 | nvgpu_err(g, "unknown unit %d", unit); | ||
272 | is_pending = false; | ||
273 | } else { | ||
274 | is_pending = ((mc_intr_1 & mask) != 0U) ? true : false; | ||
275 | } | ||
276 | |||
277 | return is_pending; | ||
278 | } | ||
279 | |||
280 | void gm20b_mc_log_pending_intrs(struct gk20a *g) | ||
281 | { | ||
282 | u32 intr; | ||
283 | |||
284 | intr = g->ops.mc.intr_stall(g); | ||
285 | if (intr != 0U) { | ||
286 | nvgpu_info(g, "Pending stall intr0=0x%08x", intr); | ||
287 | } | ||
288 | |||
289 | intr = g->ops.mc.intr_nonstall(g); | ||
290 | if (intr != 0U) { | ||
291 | nvgpu_info(g, "Pending nonstall intr1=0x%08x", intr); | ||
292 | } | ||
293 | } | ||
294 | |||
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gm20b.h b/drivers/gpu/nvgpu/common/mc/mc_gm20b.h new file mode 100644 index 00000000..6700a48c --- /dev/null +++ b/drivers/gpu/nvgpu/common/mc/mc_gm20b.h | |||
@@ -0,0 +1,51 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef NVGPU_MC_GM20B_H | ||
24 | #define NVGPU_MC_GM20B_H | ||
25 | |||
26 | #include <nvgpu/types.h> | ||
27 | |||
28 | struct gk20a; | ||
29 | enum nvgpu_unit; | ||
30 | |||
31 | void gm20b_mc_intr_mask(struct gk20a *g); | ||
32 | void gm20b_mc_intr_enable(struct gk20a *g); | ||
33 | void gm20b_mc_intr_unit_config(struct gk20a *g, bool enable, | ||
34 | bool is_stalling, u32 mask); | ||
35 | void gm20b_mc_isr_stall(struct gk20a *g); | ||
36 | u32 gm20b_mc_intr_stall(struct gk20a *g); | ||
37 | void gm20b_mc_intr_stall_pause(struct gk20a *g); | ||
38 | void gm20b_mc_intr_stall_resume(struct gk20a *g); | ||
39 | u32 gm20b_mc_intr_nonstall(struct gk20a *g); | ||
40 | u32 gm20b_mc_isr_nonstall(struct gk20a *g); | ||
41 | void gm20b_mc_intr_nonstall_pause(struct gk20a *g); | ||
42 | void gm20b_mc_intr_nonstall_resume(struct gk20a *g); | ||
43 | void gm20b_mc_enable(struct gk20a *g, u32 units); | ||
44 | void gm20b_mc_disable(struct gk20a *g, u32 units); | ||
45 | void gm20b_mc_reset(struct gk20a *g, u32 units); | ||
46 | bool gm20b_mc_is_intr1_pending(struct gk20a *g, | ||
47 | enum nvgpu_unit unit, u32 mc_intr_1); | ||
48 | void gm20b_mc_log_pending_intrs(struct gk20a *g); | ||
49 | void gm20b_mc_handle_intr_nonstall(struct gk20a *g, u32 ops); | ||
50 | |||
51 | #endif /* NVGPU_MC_GM20B_H */ | ||
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gp10b.c b/drivers/gpu/nvgpu/common/mc/mc_gp10b.c new file mode 100644 index 00000000..a0f26dd3 --- /dev/null +++ b/drivers/gpu/nvgpu/common/mc/mc_gp10b.c | |||
@@ -0,0 +1,224 @@ | |||
1 | /* | ||
2 | * GP10B master | ||
3 | * | ||
4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include "gk20a/gk20a.h" | ||
26 | #include <nvgpu/io.h> | ||
27 | #include <nvgpu/mc.h> | ||
28 | |||
29 | #include "mc_gp10b.h" | ||
30 | |||
31 | #include <nvgpu/atomic.h> | ||
32 | #include <nvgpu/unit.h> | ||
33 | |||
34 | #include <nvgpu/hw/gp10b/hw_mc_gp10b.h> | ||
35 | |||
36 | #define MAX_MC_INTR_REGS 2U | ||
37 | |||
38 | void mc_gp10b_intr_mask(struct gk20a *g) | ||
39 | { | ||
40 | nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), | ||
41 | 0xffffffffU); | ||
42 | |||
43 | nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), | ||
44 | 0xffffffffU); | ||
45 | } | ||
46 | |||
47 | void mc_gp10b_intr_enable(struct gk20a *g) | ||
48 | { | ||
49 | u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); | ||
50 | |||
51 | gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), | ||
52 | 0xffffffffU); | ||
53 | g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] = | ||
54 | mc_intr_pfifo_pending_f() | | ||
55 | mc_intr_priv_ring_pending_f() | | ||
56 | mc_intr_pbus_pending_f() | | ||
57 | mc_intr_ltc_pending_f() | | ||
58 | mc_intr_replayable_fault_pending_f() | | ||
59 | eng_intr_mask; | ||
60 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), | ||
61 | g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]); | ||
62 | |||
63 | gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), | ||
64 | 0xffffffffU); | ||
65 | g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = | ||
66 | mc_intr_pfifo_pending_f() | | ||
67 | eng_intr_mask; | ||
68 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), | ||
69 | g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); | ||
70 | } | ||
71 | |||
72 | void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable, | ||
73 | bool is_stalling, u32 mask) | ||
74 | { | ||
75 | u32 intr_index = 0; | ||
76 | u32 reg = 0; | ||
77 | |||
78 | intr_index = (is_stalling ? NVGPU_MC_INTR_STALLING : | ||
79 | NVGPU_MC_INTR_NONSTALLING); | ||
80 | if (enable) { | ||
81 | reg = mc_intr_en_set_r(intr_index); | ||
82 | g->mc_intr_mask_restore[intr_index] |= mask; | ||
83 | |||
84 | } else { | ||
85 | reg = mc_intr_en_clear_r(intr_index); | ||
86 | g->mc_intr_mask_restore[intr_index] &= ~mask; | ||
87 | } | ||
88 | |||
89 | gk20a_writel(g, reg, mask); | ||
90 | } | ||
91 | |||
92 | void mc_gp10b_isr_stall(struct gk20a *g) | ||
93 | { | ||
94 | u32 mc_intr_0; | ||
95 | |||
96 | u32 engine_id_idx; | ||
97 | u32 active_engine_id = 0; | ||
98 | u32 engine_enum = ENGINE_INVAL_GK20A; | ||
99 | |||
100 | mc_intr_0 = gk20a_readl(g, mc_intr_r(0)); | ||
101 | |||
102 | nvgpu_log(g, gpu_dbg_intr, "stall intr 0x%08x\n", mc_intr_0); | ||
103 | |||
104 | for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) { | ||
105 | active_engine_id = g->fifo.active_engines_list[engine_id_idx]; | ||
106 | |||
107 | if ((mc_intr_0 & g->fifo.engine_info[active_engine_id].intr_mask) != 0U) { | ||
108 | engine_enum = g->fifo.engine_info[active_engine_id].engine_enum; | ||
109 | /* GR Engine */ | ||
110 | if (engine_enum == ENGINE_GR_GK20A) { | ||
111 | gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); | ||
112 | } | ||
113 | |||
114 | /* CE Engine */ | ||
115 | if (((engine_enum == ENGINE_GRCE_GK20A) || | ||
116 | (engine_enum == ENGINE_ASYNC_CE_GK20A)) && | ||
117 | (g->ops.ce2.isr_stall != NULL)) { | ||
118 | g->ops.ce2.isr_stall(g, | ||
119 | g->fifo.engine_info[active_engine_id].inst_id, | ||
120 | g->fifo.engine_info[active_engine_id].pri_base); | ||
121 | } | ||
122 | } | ||
123 | } | ||
124 | if ((g->ops.mc.is_intr_hub_pending != NULL) && | ||
125 | g->ops.mc.is_intr_hub_pending(g, mc_intr_0)) { | ||
126 | g->ops.fb.hub_isr(g); | ||
127 | } | ||
128 | if ((mc_intr_0 & mc_intr_pfifo_pending_f()) != 0U) { | ||
129 | gk20a_fifo_isr(g); | ||
130 | } | ||
131 | if ((mc_intr_0 & mc_intr_pmu_pending_f()) != 0U) { | ||
132 | g->ops.pmu.pmu_isr(g); | ||
133 | } | ||
134 | if ((mc_intr_0 & mc_intr_priv_ring_pending_f()) != 0U) { | ||
135 | g->ops.priv_ring.isr(g); | ||
136 | } | ||
137 | if ((mc_intr_0 & mc_intr_ltc_pending_f()) != 0U) { | ||
138 | g->ops.ltc.isr(g); | ||
139 | } | ||
140 | if ((mc_intr_0 & mc_intr_pbus_pending_f()) != 0U) { | ||
141 | g->ops.bus.isr(g); | ||
142 | } | ||
143 | if ((g->ops.mc.is_intr_nvlink_pending != NULL) && | ||
144 | g->ops.mc.is_intr_nvlink_pending(g, mc_intr_0)) { | ||
145 | g->ops.nvlink.isr(g); | ||
146 | } | ||
147 | if (mc_intr_0 & mc_intr_pfb_pending_f() && g->ops.fb.fbpa_isr) { | ||
148 | g->ops.fb.fbpa_isr(g); | ||
149 | } | ||
150 | |||
151 | nvgpu_log(g, gpu_dbg_intr, "stall intr done 0x%08x\n", mc_intr_0); | ||
152 | |||
153 | } | ||
154 | |||
155 | u32 mc_gp10b_intr_stall(struct gk20a *g) | ||
156 | { | ||
157 | return gk20a_readl(g, mc_intr_r(NVGPU_MC_INTR_STALLING)); | ||
158 | } | ||
159 | |||
160 | void mc_gp10b_intr_stall_pause(struct gk20a *g) | ||
161 | { | ||
162 | gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), 0xffffffffU); | ||
163 | } | ||
164 | |||
165 | void mc_gp10b_intr_stall_resume(struct gk20a *g) | ||
166 | { | ||
167 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), | ||
168 | g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]); | ||
169 | } | ||
170 | |||
171 | u32 mc_gp10b_intr_nonstall(struct gk20a *g) | ||
172 | { | ||
173 | return gk20a_readl(g, mc_intr_r(NVGPU_MC_INTR_NONSTALLING)); | ||
174 | } | ||
175 | |||
176 | void mc_gp10b_intr_nonstall_pause(struct gk20a *g) | ||
177 | { | ||
178 | gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), | ||
179 | 0xffffffffU); | ||
180 | } | ||
181 | |||
182 | void mc_gp10b_intr_nonstall_resume(struct gk20a *g) | ||
183 | { | ||
184 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), | ||
185 | g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); | ||
186 | } | ||
187 | |||
188 | bool mc_gp10b_is_intr1_pending(struct gk20a *g, | ||
189 | enum nvgpu_unit unit, u32 mc_intr_1) | ||
190 | { | ||
191 | u32 mask = 0; | ||
192 | bool is_pending; | ||
193 | |||
194 | switch (unit) { | ||
195 | case NVGPU_UNIT_FIFO: | ||
196 | mask = mc_intr_pfifo_pending_f(); | ||
197 | break; | ||
198 | default: | ||
199 | break; | ||
200 | } | ||
201 | |||
202 | if (mask == 0U) { | ||
203 | nvgpu_err(g, "unknown unit %d", unit); | ||
204 | is_pending = false; | ||
205 | } else { | ||
206 | is_pending = ((mc_intr_1 & mask) != 0U) ? true : false; | ||
207 | } | ||
208 | |||
209 | return is_pending; | ||
210 | } | ||
211 | |||
212 | void mc_gp10b_log_pending_intrs(struct gk20a *g) | ||
213 | { | ||
214 | u32 i, intr; | ||
215 | |||
216 | for (i = 0; i < MAX_MC_INTR_REGS; i++) { | ||
217 | intr = nvgpu_readl(g, mc_intr_r(i)); | ||
218 | if (intr == 0U) { | ||
219 | continue; | ||
220 | } | ||
221 | nvgpu_info(g, "Pending intr%d=0x%08x", i, intr); | ||
222 | } | ||
223 | |||
224 | } | ||
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gp10b.h b/drivers/gpu/nvgpu/common/mc/mc_gp10b.h new file mode 100644 index 00000000..ee3c0c3b --- /dev/null +++ b/drivers/gpu/nvgpu/common/mc/mc_gp10b.h | |||
@@ -0,0 +1,47 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef MC_GP10B_H | ||
24 | #define MC_GP10B_H | ||
25 | |||
26 | #include <nvgpu/types.h> | ||
27 | |||
28 | struct gk20a; | ||
29 | enum nvgpu_unit; | ||
30 | |||
31 | void mc_gp10b_intr_mask(struct gk20a *g); | ||
32 | void mc_gp10b_intr_enable(struct gk20a *g); | ||
33 | void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable, | ||
34 | bool is_stalling, u32 mask); | ||
35 | void mc_gp10b_isr_stall(struct gk20a *g); | ||
36 | bool mc_gp10b_is_intr1_pending(struct gk20a *g, | ||
37 | enum nvgpu_unit unit, u32 mc_intr_1); | ||
38 | |||
39 | void mc_gp10b_log_pending_intrs(struct gk20a *g); | ||
40 | u32 mc_gp10b_intr_stall(struct gk20a *g); | ||
41 | void mc_gp10b_intr_stall_pause(struct gk20a *g); | ||
42 | void mc_gp10b_intr_stall_resume(struct gk20a *g); | ||
43 | u32 mc_gp10b_intr_nonstall(struct gk20a *g); | ||
44 | void mc_gp10b_intr_nonstall_pause(struct gk20a *g); | ||
45 | void mc_gp10b_intr_nonstall_resume(struct gk20a *g); | ||
46 | |||
47 | #endif | ||
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gv100.c b/drivers/gpu/nvgpu/common/mc/mc_gv100.c new file mode 100644 index 00000000..28c03434 --- /dev/null +++ b/drivers/gpu/nvgpu/common/mc/mc_gv100.c | |||
@@ -0,0 +1,91 @@ | |||
1 | /* | ||
2 | * GV100 master | ||
3 | * | ||
4 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include <nvgpu/types.h> | ||
26 | #include <nvgpu/io.h> | ||
27 | #include <nvgpu/mc.h> | ||
28 | |||
29 | #include "gk20a/gk20a.h" | ||
30 | |||
31 | #include "mc_gp10b.h" | ||
32 | #include "mc_gv100.h" | ||
33 | |||
34 | #include <nvgpu/hw/gv100/hw_mc_gv100.h> | ||
35 | |||
36 | void mc_gv100_intr_enable(struct gk20a *g) | ||
37 | { | ||
38 | u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); | ||
39 | |||
40 | gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), | ||
41 | 0xffffffffU); | ||
42 | gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), | ||
43 | 0xffffffffU); | ||
44 | g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] = | ||
45 | mc_intr_pfifo_pending_f() | | ||
46 | mc_intr_hub_pending_f() | | ||
47 | mc_intr_priv_ring_pending_f() | | ||
48 | mc_intr_pbus_pending_f() | | ||
49 | mc_intr_ltc_pending_f() | | ||
50 | mc_intr_nvlink_pending_f() | | ||
51 | eng_intr_mask; | ||
52 | |||
53 | g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = | ||
54 | mc_intr_pfifo_pending_f() | ||
55 | | eng_intr_mask; | ||
56 | |||
57 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), | ||
58 | g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]); | ||
59 | |||
60 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), | ||
61 | g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); | ||
62 | |||
63 | } | ||
64 | |||
65 | bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0) | ||
66 | { | ||
67 | return (((mc_intr_0 & mc_intr_nvlink_pending_f()) != 0U) ? true : false); | ||
68 | } | ||
69 | |||
70 | bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id, | ||
71 | u32 *eng_intr_pending) | ||
72 | { | ||
73 | u32 mc_intr_0 = gk20a_readl(g, mc_intr_r(0)); | ||
74 | u32 stall_intr, eng_intr_mask; | ||
75 | |||
76 | eng_intr_mask = gk20a_fifo_act_eng_interrupt_mask(g, act_eng_id); | ||
77 | *eng_intr_pending = mc_intr_0 & eng_intr_mask; | ||
78 | |||
79 | stall_intr = mc_intr_pfifo_pending_f() | | ||
80 | mc_intr_hub_pending_f() | | ||
81 | mc_intr_priv_ring_pending_f() | | ||
82 | mc_intr_pbus_pending_f() | | ||
83 | mc_intr_ltc_pending_f() | | ||
84 | mc_intr_nvlink_pending_f(); | ||
85 | |||
86 | nvgpu_log(g, gpu_dbg_info | gpu_dbg_intr, | ||
87 | "mc_intr_0 = 0x%08x, eng_intr = 0x%08x", | ||
88 | mc_intr_0 & stall_intr, *eng_intr_pending); | ||
89 | |||
90 | return (mc_intr_0 & (eng_intr_mask | stall_intr)) != 0U; | ||
91 | } | ||
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gv100.h b/drivers/gpu/nvgpu/common/mc/mc_gv100.h new file mode 100644 index 00000000..c0a16ad9 --- /dev/null +++ b/drivers/gpu/nvgpu/common/mc/mc_gv100.h | |||
@@ -0,0 +1,34 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef MC_GV100_H | ||
24 | #define MC_GV100_H | ||
25 | |||
26 | #include <nvgpu/types.h> | ||
27 | |||
28 | struct gk20a; | ||
29 | |||
30 | void mc_gv100_intr_enable(struct gk20a *g); | ||
31 | bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0); | ||
32 | bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id, | ||
33 | u32 *eng_intr_pending); | ||
34 | #endif | ||
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gv11b.c b/drivers/gpu/nvgpu/common/mc/mc_gv11b.c new file mode 100644 index 00000000..fa4d4bfb --- /dev/null +++ b/drivers/gpu/nvgpu/common/mc/mc_gv11b.c | |||
@@ -0,0 +1,90 @@ | |||
1 | /* | ||
2 | * GV11B master | ||
3 | * | ||
4 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include <nvgpu/types.h> | ||
26 | #include <nvgpu/io.h> | ||
27 | #include <nvgpu/mc.h> | ||
28 | |||
29 | #include "gk20a/gk20a.h" | ||
30 | |||
31 | #include "mc_gp10b.h" | ||
32 | #include "mc_gv11b.h" | ||
33 | |||
34 | #include <nvgpu/hw/gv11b/hw_mc_gv11b.h> | ||
35 | |||
36 | void mc_gv11b_intr_enable(struct gk20a *g) | ||
37 | { | ||
38 | u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); | ||
39 | |||
40 | gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), | ||
41 | 0xffffffffU); | ||
42 | gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), | ||
43 | 0xffffffffU); | ||
44 | |||
45 | g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] = | ||
46 | mc_intr_pfifo_pending_f() | | ||
47 | mc_intr_hub_pending_f() | | ||
48 | mc_intr_priv_ring_pending_f() | | ||
49 | mc_intr_pbus_pending_f() | | ||
50 | mc_intr_ltc_pending_f() | | ||
51 | eng_intr_mask; | ||
52 | |||
53 | g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = | ||
54 | mc_intr_pfifo_pending_f() | ||
55 | | eng_intr_mask; | ||
56 | |||
57 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), | ||
58 | g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]); | ||
59 | |||
60 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), | ||
61 | g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); | ||
62 | |||
63 | } | ||
64 | |||
65 | bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0) | ||
66 | { | ||
67 | return (((mc_intr_0 & mc_intr_hub_pending_f()) != 0U) ? true : false); | ||
68 | } | ||
69 | |||
70 | bool gv11b_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id, | ||
71 | u32 *eng_intr_pending) | ||
72 | { | ||
73 | u32 mc_intr_0 = gk20a_readl(g, mc_intr_r(0)); | ||
74 | u32 stall_intr, eng_intr_mask; | ||
75 | |||
76 | eng_intr_mask = gk20a_fifo_act_eng_interrupt_mask(g, act_eng_id); | ||
77 | *eng_intr_pending = mc_intr_0 & eng_intr_mask; | ||
78 | |||
79 | stall_intr = mc_intr_pfifo_pending_f() | | ||
80 | mc_intr_hub_pending_f() | | ||
81 | mc_intr_priv_ring_pending_f() | | ||
82 | mc_intr_pbus_pending_f() | | ||
83 | mc_intr_ltc_pending_f(); | ||
84 | |||
85 | nvgpu_log(g, gpu_dbg_info | gpu_dbg_intr, | ||
86 | "mc_intr_0 = 0x%08x, eng_intr = 0x%08x", | ||
87 | mc_intr_0 & stall_intr, *eng_intr_pending); | ||
88 | |||
89 | return (mc_intr_0 & (eng_intr_mask | stall_intr)) != 0U; | ||
90 | } | ||
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gv11b.h b/drivers/gpu/nvgpu/common/mc/mc_gv11b.h new file mode 100644 index 00000000..48eba744 --- /dev/null +++ b/drivers/gpu/nvgpu/common/mc/mc_gv11b.h | |||
@@ -0,0 +1,34 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef MC_GV11B_H | ||
24 | #define MC_GV11B_H | ||
25 | |||
26 | #include <nvgpu/types.h> | ||
27 | |||
28 | struct gk20a; | ||
29 | |||
30 | void mc_gv11b_intr_enable(struct gk20a *g); | ||
31 | bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0); | ||
32 | bool gv11b_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id, | ||
33 | u32 *eng_intr_pending); | ||
34 | #endif | ||