diff options
Diffstat (limited to 'drivers/gpu/nvgpu/common/linux/vgpu')
44 files changed, 8022 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/ce2_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/ce2_vgpu.c new file mode 100644 index 00000000..ffb85f16 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/ce2_vgpu.c | |||
@@ -0,0 +1,45 @@ | |||
1 | /* | ||
2 | * Virtualized GPU CE2 | ||
3 | * | ||
4 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
17 | */ | ||
18 | |||
19 | #include "vgpu.h" | ||
20 | |||
21 | #include <nvgpu/bug.h> | ||
22 | |||
23 | int vgpu_ce2_nonstall_isr(struct gk20a *g, | ||
24 | struct tegra_vgpu_ce2_nonstall_intr_info *info) | ||
25 | { | ||
26 | gk20a_dbg_fn(""); | ||
27 | |||
28 | switch (info->type) { | ||
29 | case TEGRA_VGPU_CE2_NONSTALL_INTR_NONBLOCKPIPE: | ||
30 | gk20a_channel_semaphore_wakeup(g, true); | ||
31 | break; | ||
32 | default: | ||
33 | WARN_ON(1); | ||
34 | break; | ||
35 | } | ||
36 | |||
37 | return 0; | ||
38 | } | ||
39 | |||
40 | u32 vgpu_ce_get_num_pce(struct gk20a *g) | ||
41 | { | ||
42 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | ||
43 | |||
44 | return priv->constants.num_pce; | ||
45 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/clk_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/clk_vgpu.c new file mode 100644 index 00000000..bcdf8ee9 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/clk_vgpu.c | |||
@@ -0,0 +1,164 @@ | |||
1 | /* | ||
2 | * Virtualized GPU Clock Interface | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
17 | */ | ||
18 | |||
19 | #include "vgpu.h" | ||
20 | #include "clk_vgpu.h" | ||
21 | |||
22 | static unsigned long | ||
23 | vgpu_freq_table[TEGRA_VGPU_GPU_FREQ_TABLE_SIZE]; | ||
24 | |||
25 | static unsigned long vgpu_clk_get_rate(struct gk20a *g, u32 api_domain) | ||
26 | { | ||
27 | struct tegra_vgpu_cmd_msg msg = {}; | ||
28 | struct tegra_vgpu_gpu_clk_rate_params *p = &msg.params.gpu_clk_rate; | ||
29 | int err; | ||
30 | unsigned long ret = 0; | ||
31 | |||
32 | gk20a_dbg_fn(""); | ||
33 | |||
34 | switch (api_domain) { | ||
35 | case CTRL_CLK_DOMAIN_GPCCLK: | ||
36 | msg.cmd = TEGRA_VGPU_CMD_GET_GPU_CLK_RATE; | ||
37 | msg.handle = vgpu_get_handle(g); | ||
38 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
39 | err = err ? err : msg.ret; | ||
40 | if (err) | ||
41 | nvgpu_err(g, "%s failed - %d", __func__, err); | ||
42 | else | ||
43 | /* return frequency in Hz */ | ||
44 | ret = p->rate * 1000; | ||
45 | break; | ||
46 | case CTRL_CLK_DOMAIN_PWRCLK: | ||
47 | nvgpu_err(g, "unsupported clock: %u", api_domain); | ||
48 | break; | ||
49 | default: | ||
50 | nvgpu_err(g, "unknown clock: %u", api_domain); | ||
51 | break; | ||
52 | } | ||
53 | |||
54 | return ret; | ||
55 | } | ||
56 | |||
57 | static int vgpu_clk_set_rate(struct gk20a *g, | ||
58 | u32 api_domain, unsigned long rate) | ||
59 | { | ||
60 | struct tegra_vgpu_cmd_msg msg = {}; | ||
61 | struct tegra_vgpu_gpu_clk_rate_params *p = &msg.params.gpu_clk_rate; | ||
62 | int err = -EINVAL; | ||
63 | |||
64 | gk20a_dbg_fn(""); | ||
65 | |||
66 | switch (api_domain) { | ||
67 | case CTRL_CLK_DOMAIN_GPCCLK: | ||
68 | msg.cmd = TEGRA_VGPU_CMD_SET_GPU_CLK_RATE; | ||
69 | msg.handle = vgpu_get_handle(g); | ||
70 | |||
71 | /* server dvfs framework requires frequency in kHz */ | ||
72 | p->rate = (u32)(rate / 1000); | ||
73 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
74 | err = err ? err : msg.ret; | ||
75 | if (err) | ||
76 | nvgpu_err(g, "%s failed - %d", __func__, err); | ||
77 | break; | ||
78 | case CTRL_CLK_DOMAIN_PWRCLK: | ||
79 | nvgpu_err(g, "unsupported clock: %u", api_domain); | ||
80 | break; | ||
81 | default: | ||
82 | nvgpu_err(g, "unknown clock: %u", api_domain); | ||
83 | break; | ||
84 | } | ||
85 | |||
86 | return err; | ||
87 | } | ||
88 | |||
89 | static unsigned long vgpu_clk_get_maxrate(struct gk20a *g, u32 api_domain) | ||
90 | { | ||
91 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | ||
92 | |||
93 | return priv->constants.max_freq; | ||
94 | } | ||
95 | |||
96 | void vgpu_init_clk_support(struct gk20a *g) | ||
97 | { | ||
98 | g->ops.clk.get_rate = vgpu_clk_get_rate; | ||
99 | g->ops.clk.set_rate = vgpu_clk_set_rate; | ||
100 | g->ops.clk.get_maxrate = vgpu_clk_get_maxrate; | ||
101 | } | ||
102 | |||
103 | long vgpu_clk_round_rate(struct device *dev, unsigned long rate) | ||
104 | { | ||
105 | /* server will handle frequency rounding */ | ||
106 | return rate; | ||
107 | } | ||
108 | |||
109 | int vgpu_clk_get_freqs(struct device *dev, | ||
110 | unsigned long **freqs, int *num_freqs) | ||
111 | { | ||
112 | struct gk20a_platform *platform = gk20a_get_platform(dev); | ||
113 | struct gk20a *g = platform->g; | ||
114 | struct tegra_vgpu_cmd_msg msg = {}; | ||
115 | struct tegra_vgpu_get_gpu_freq_table_params *p = | ||
116 | &msg.params.get_gpu_freq_table; | ||
117 | unsigned int i; | ||
118 | int err; | ||
119 | |||
120 | gk20a_dbg_fn(""); | ||
121 | |||
122 | msg.cmd = TEGRA_VGPU_CMD_GET_GPU_FREQ_TABLE; | ||
123 | msg.handle = vgpu_get_handle(g); | ||
124 | |||
125 | p->num_freqs = TEGRA_VGPU_GPU_FREQ_TABLE_SIZE; | ||
126 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
127 | err = err ? err : msg.ret; | ||
128 | if (err) { | ||
129 | nvgpu_err(g, "%s failed - %d", __func__, err); | ||
130 | return err; | ||
131 | } | ||
132 | |||
133 | /* return frequency in Hz */ | ||
134 | for (i = 0; i < p->num_freqs; i++) | ||
135 | vgpu_freq_table[i] = p->freqs[i] * 1000; | ||
136 | |||
137 | *freqs = vgpu_freq_table; | ||
138 | *num_freqs = p->num_freqs; | ||
139 | |||
140 | return 0; | ||
141 | } | ||
142 | |||
143 | int vgpu_clk_cap_rate(struct device *dev, unsigned long rate) | ||
144 | { | ||
145 | struct gk20a_platform *platform = gk20a_get_platform(dev); | ||
146 | struct gk20a *g = platform->g; | ||
147 | struct tegra_vgpu_cmd_msg msg = {}; | ||
148 | struct tegra_vgpu_gpu_clk_rate_params *p = &msg.params.gpu_clk_rate; | ||
149 | int err = 0; | ||
150 | |||
151 | gk20a_dbg_fn(""); | ||
152 | |||
153 | msg.cmd = TEGRA_VGPU_CMD_CAP_GPU_CLK_RATE; | ||
154 | msg.handle = vgpu_get_handle(g); | ||
155 | p->rate = (u32)rate; | ||
156 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
157 | err = err ? err : msg.ret; | ||
158 | if (err) { | ||
159 | nvgpu_err(g, "%s failed - %d", __func__, err); | ||
160 | return err; | ||
161 | } | ||
162 | |||
163 | return 0; | ||
164 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/clk_vgpu.h b/drivers/gpu/nvgpu/common/linux/vgpu/clk_vgpu.h new file mode 100644 index 00000000..8d477643 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/clk_vgpu.h | |||
@@ -0,0 +1,27 @@ | |||
1 | /* | ||
2 | * Virtualized GPU Clock Interface | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
17 | */ | ||
18 | |||
19 | #ifndef _CLK_VIRT_H_ | ||
20 | #define _CLK_VIRT_H_ | ||
21 | |||
22 | void vgpu_init_clk_support(struct gk20a *g); | ||
23 | long vgpu_clk_round_rate(struct device *dev, unsigned long rate); | ||
24 | int vgpu_clk_get_freqs(struct device *dev, | ||
25 | unsigned long **freqs, int *num_freqs); | ||
26 | int vgpu_clk_cap_rate(struct device *dev, unsigned long rate); | ||
27 | #endif | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/css_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/css_vgpu.c new file mode 100644 index 00000000..fba3cc63 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/css_vgpu.c | |||
@@ -0,0 +1,234 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | #if defined(CONFIG_GK20A_CYCLE_STATS) | ||
17 | |||
18 | #include <linux/tegra-ivc.h> | ||
19 | #include <linux/tegra_vgpu.h> | ||
20 | #include <uapi/linux/nvgpu.h> | ||
21 | |||
22 | #include "gk20a/gk20a.h" | ||
23 | #include "gk20a/channel_gk20a.h" | ||
24 | #include "gk20a/css_gr_gk20a.h" | ||
25 | #include "common/linux/platform_gk20a.h" | ||
26 | #include "common/linux/vgpu/vgpu.h" | ||
27 | #include "common/linux/vgpu/css_vgpu.h" | ||
28 | |||
29 | static struct tegra_hv_ivm_cookie *css_cookie; | ||
30 | |||
31 | static struct tegra_hv_ivm_cookie *vgpu_css_reserve_mempool(struct gk20a *g) | ||
32 | { | ||
33 | struct device *dev = dev_from_gk20a(g); | ||
34 | struct device_node *np = dev->of_node; | ||
35 | struct of_phandle_args args; | ||
36 | struct device_node *hv_np; | ||
37 | struct tegra_hv_ivm_cookie *cookie; | ||
38 | u32 mempool; | ||
39 | int err; | ||
40 | |||
41 | err = of_parse_phandle_with_fixed_args(np, | ||
42 | "mempool-css", 1, 0, &args); | ||
43 | if (err) { | ||
44 | nvgpu_err(g, "dt missing mempool-css"); | ||
45 | return ERR_PTR(err); | ||
46 | } | ||
47 | |||
48 | hv_np = args.np; | ||
49 | mempool = args.args[0]; | ||
50 | cookie = tegra_hv_mempool_reserve(hv_np, mempool); | ||
51 | if (IS_ERR_OR_NULL(cookie)) { | ||
52 | nvgpu_err(g, "mempool %u reserve failed", mempool); | ||
53 | return ERR_PTR(-EINVAL); | ||
54 | } | ||
55 | return cookie; | ||
56 | } | ||
57 | |||
58 | u32 vgpu_css_get_buffer_size(struct gk20a *g) | ||
59 | { | ||
60 | struct tegra_hv_ivm_cookie *cookie; | ||
61 | u32 size; | ||
62 | |||
63 | nvgpu_log_fn(g, " "); | ||
64 | |||
65 | if (css_cookie) { | ||
66 | nvgpu_log_info(g, "buffer size = %llu", css_cookie->size); | ||
67 | return (u32)css_cookie->size; | ||
68 | } | ||
69 | |||
70 | cookie = vgpu_css_reserve_mempool(g); | ||
71 | if (IS_ERR(cookie)) | ||
72 | return 0; | ||
73 | |||
74 | size = cookie->size; | ||
75 | |||
76 | tegra_hv_mempool_unreserve(cookie); | ||
77 | nvgpu_log_info(g, "buffer size = %u", size); | ||
78 | return size; | ||
79 | } | ||
80 | |||
81 | static int vgpu_css_init_snapshot_buffer(struct gr_gk20a *gr) | ||
82 | { | ||
83 | struct gk20a *g = gr->g; | ||
84 | struct gk20a_cs_snapshot *data = gr->cs_data; | ||
85 | void *buf = NULL; | ||
86 | int err; | ||
87 | |||
88 | gk20a_dbg_fn(""); | ||
89 | |||
90 | if (data->hw_snapshot) | ||
91 | return 0; | ||
92 | |||
93 | css_cookie = vgpu_css_reserve_mempool(g); | ||
94 | if (IS_ERR(css_cookie)) | ||
95 | return PTR_ERR(css_cookie); | ||
96 | |||
97 | /* Make sure buffer size is large enough */ | ||
98 | if (css_cookie->size < CSS_MIN_HW_SNAPSHOT_SIZE) { | ||
99 | nvgpu_info(g, "mempool size %lld too small", | ||
100 | css_cookie->size); | ||
101 | err = -ENOMEM; | ||
102 | goto fail; | ||
103 | } | ||
104 | |||
105 | buf = ioremap_cache(css_cookie->ipa, css_cookie->size); | ||
106 | if (!buf) { | ||
107 | nvgpu_info(g, "ioremap_cache failed"); | ||
108 | err = -EINVAL; | ||
109 | goto fail; | ||
110 | } | ||
111 | |||
112 | data->hw_snapshot = buf; | ||
113 | data->hw_end = data->hw_snapshot + | ||
114 | css_cookie->size / sizeof(struct gk20a_cs_snapshot_fifo_entry); | ||
115 | data->hw_get = data->hw_snapshot; | ||
116 | memset(data->hw_snapshot, 0xff, css_cookie->size); | ||
117 | return 0; | ||
118 | fail: | ||
119 | tegra_hv_mempool_unreserve(css_cookie); | ||
120 | css_cookie = NULL; | ||
121 | return err; | ||
122 | } | ||
123 | |||
124 | void vgpu_css_release_snapshot_buffer(struct gr_gk20a *gr) | ||
125 | { | ||
126 | struct gk20a_cs_snapshot *data = gr->cs_data; | ||
127 | |||
128 | if (!data->hw_snapshot) | ||
129 | return; | ||
130 | |||
131 | iounmap(data->hw_snapshot); | ||
132 | data->hw_snapshot = NULL; | ||
133 | |||
134 | tegra_hv_mempool_unreserve(css_cookie); | ||
135 | css_cookie = NULL; | ||
136 | |||
137 | gk20a_dbg_info("cyclestats(vgpu): buffer for snapshots released\n"); | ||
138 | } | ||
139 | |||
140 | int vgpu_css_flush_snapshots(struct channel_gk20a *ch, | ||
141 | u32 *pending, bool *hw_overflow) | ||
142 | { | ||
143 | struct gk20a *g = ch->g; | ||
144 | struct tegra_vgpu_cmd_msg msg = {}; | ||
145 | struct tegra_vgpu_channel_cyclestats_snapshot_params *p; | ||
146 | struct gr_gk20a *gr = &g->gr; | ||
147 | struct gk20a_cs_snapshot *data = gr->cs_data; | ||
148 | int err; | ||
149 | |||
150 | gk20a_dbg_fn(""); | ||
151 | |||
152 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_CYCLESTATS_SNAPSHOT; | ||
153 | msg.handle = vgpu_get_handle(g); | ||
154 | p = &msg.params.cyclestats_snapshot; | ||
155 | p->handle = ch->virt_ctx; | ||
156 | p->subcmd = NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_FLUSH; | ||
157 | p->buf_info = (uintptr_t)data->hw_get - (uintptr_t)data->hw_snapshot; | ||
158 | |||
159 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
160 | |||
161 | err = (err || msg.ret) ? -1 : 0; | ||
162 | |||
163 | *pending = p->buf_info; | ||
164 | *hw_overflow = p->hw_overflow; | ||
165 | |||
166 | return err; | ||
167 | } | ||
168 | |||
169 | static int vgpu_css_attach(struct channel_gk20a *ch, | ||
170 | struct gk20a_cs_snapshot_client *cs_client) | ||
171 | { | ||
172 | struct gk20a *g = ch->g; | ||
173 | struct tegra_vgpu_cmd_msg msg = {}; | ||
174 | struct tegra_vgpu_channel_cyclestats_snapshot_params *p = | ||
175 | &msg.params.cyclestats_snapshot; | ||
176 | int err; | ||
177 | |||
178 | gk20a_dbg_fn(""); | ||
179 | |||
180 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_CYCLESTATS_SNAPSHOT; | ||
181 | msg.handle = vgpu_get_handle(g); | ||
182 | p->handle = ch->virt_ctx; | ||
183 | p->subcmd = NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_ATTACH; | ||
184 | p->perfmon_count = cs_client->perfmon_count; | ||
185 | |||
186 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
187 | err = err ? err : msg.ret; | ||
188 | if (err) | ||
189 | nvgpu_err(g, "failed"); | ||
190 | else | ||
191 | cs_client->perfmon_start = p->perfmon_start; | ||
192 | |||
193 | return err; | ||
194 | } | ||
195 | |||
196 | int vgpu_css_detach(struct channel_gk20a *ch, | ||
197 | struct gk20a_cs_snapshot_client *cs_client) | ||
198 | { | ||
199 | struct gk20a *g = ch->g; | ||
200 | struct tegra_vgpu_cmd_msg msg = {}; | ||
201 | struct tegra_vgpu_channel_cyclestats_snapshot_params *p = | ||
202 | &msg.params.cyclestats_snapshot; | ||
203 | int err; | ||
204 | |||
205 | gk20a_dbg_fn(""); | ||
206 | |||
207 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_CYCLESTATS_SNAPSHOT; | ||
208 | msg.handle = vgpu_get_handle(g); | ||
209 | p->handle = ch->virt_ctx; | ||
210 | p->subcmd = NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_DETACH; | ||
211 | p->perfmon_start = cs_client->perfmon_start; | ||
212 | p->perfmon_count = cs_client->perfmon_count; | ||
213 | |||
214 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
215 | err = err ? err : msg.ret; | ||
216 | if (err) | ||
217 | nvgpu_err(g, "failed"); | ||
218 | |||
219 | return err; | ||
220 | } | ||
221 | |||
222 | int vgpu_css_enable_snapshot_buffer(struct channel_gk20a *ch, | ||
223 | struct gk20a_cs_snapshot_client *cs_client) | ||
224 | { | ||
225 | int ret; | ||
226 | |||
227 | ret = vgpu_css_attach(ch, cs_client); | ||
228 | if (ret) | ||
229 | return ret; | ||
230 | |||
231 | ret = vgpu_css_init_snapshot_buffer(&ch->g->gr); | ||
232 | return ret; | ||
233 | } | ||
234 | #endif /* CONFIG_GK20A_CYCLE_STATS */ | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/css_vgpu.h b/drivers/gpu/nvgpu/common/linux/vgpu/css_vgpu.h new file mode 100644 index 00000000..df95e775 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/css_vgpu.h | |||
@@ -0,0 +1,34 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #ifndef _CSS_VGPU_H_ | ||
18 | #define _CSS_VGPU_H_ | ||
19 | |||
20 | #include <nvgpu/types.h> | ||
21 | |||
22 | struct gr_gk20a; | ||
23 | struct channel_gk20a; | ||
24 | struct gk20a_cs_snapshot_client; | ||
25 | |||
26 | void vgpu_css_release_snapshot_buffer(struct gr_gk20a *gr); | ||
27 | int vgpu_css_flush_snapshots(struct channel_gk20a *ch, | ||
28 | u32 *pending, bool *hw_overflow); | ||
29 | int vgpu_css_detach(struct channel_gk20a *ch, | ||
30 | struct gk20a_cs_snapshot_client *cs_client); | ||
31 | int vgpu_css_enable_snapshot_buffer(struct channel_gk20a *ch, | ||
32 | struct gk20a_cs_snapshot_client *cs_client); | ||
33 | u32 vgpu_css_get_buffer_size(struct gk20a *g); | ||
34 | #endif | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/dbg_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/dbg_vgpu.c new file mode 100644 index 00000000..06ef43b8 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/dbg_vgpu.c | |||
@@ -0,0 +1,210 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include <linux/tegra_gr_comm.h> | ||
18 | #include <linux/tegra_vgpu.h> | ||
19 | #include <uapi/linux/nvgpu.h> | ||
20 | |||
21 | #include "gk20a/gk20a.h" | ||
22 | #include "gk20a/channel_gk20a.h" | ||
23 | #include "gk20a/dbg_gpu_gk20a.h" | ||
24 | #include "vgpu.h" | ||
25 | #include "dbg_vgpu.h" | ||
26 | |||
27 | #include <nvgpu/bug.h> | ||
28 | |||
29 | int vgpu_exec_regops(struct dbg_session_gk20a *dbg_s, | ||
30 | struct nvgpu_dbg_gpu_reg_op *ops, | ||
31 | u64 num_ops) | ||
32 | { | ||
33 | struct channel_gk20a *ch; | ||
34 | struct tegra_vgpu_cmd_msg msg; | ||
35 | struct tegra_vgpu_reg_ops_params *p = &msg.params.reg_ops; | ||
36 | void *oob; | ||
37 | size_t oob_size, ops_size; | ||
38 | void *handle = NULL; | ||
39 | int err = 0; | ||
40 | |||
41 | gk20a_dbg_fn(""); | ||
42 | BUG_ON(sizeof(*ops) != sizeof(struct tegra_vgpu_reg_op)); | ||
43 | |||
44 | handle = tegra_gr_comm_oob_get_ptr(TEGRA_GR_COMM_CTX_CLIENT, | ||
45 | tegra_gr_comm_get_server_vmid(), | ||
46 | TEGRA_VGPU_QUEUE_CMD, | ||
47 | &oob, &oob_size); | ||
48 | if (!handle) | ||
49 | return -EINVAL; | ||
50 | |||
51 | ops_size = sizeof(*ops) * num_ops; | ||
52 | if (oob_size < ops_size) { | ||
53 | err = -ENOMEM; | ||
54 | goto fail; | ||
55 | } | ||
56 | |||
57 | memcpy(oob, ops, ops_size); | ||
58 | |||
59 | msg.cmd = TEGRA_VGPU_CMD_REG_OPS; | ||
60 | msg.handle = vgpu_get_handle(dbg_s->g); | ||
61 | ch = nvgpu_dbg_gpu_get_session_channel(dbg_s); | ||
62 | p->handle = ch ? ch->virt_ctx : 0; | ||
63 | p->num_ops = num_ops; | ||
64 | p->is_profiler = dbg_s->is_profiler; | ||
65 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
66 | err = err ? err : msg.ret; | ||
67 | if (!err) | ||
68 | memcpy(ops, oob, ops_size); | ||
69 | |||
70 | fail: | ||
71 | tegra_gr_comm_oob_put_ptr(handle); | ||
72 | return err; | ||
73 | } | ||
74 | |||
75 | int vgpu_dbg_set_powergate(struct dbg_session_gk20a *dbg_s, bool disable_powergate) | ||
76 | { | ||
77 | struct tegra_vgpu_cmd_msg msg; | ||
78 | struct tegra_vgpu_set_powergate_params *p = &msg.params.set_powergate; | ||
79 | int err = 0; | ||
80 | u32 mode; | ||
81 | |||
82 | gk20a_dbg_fn(""); | ||
83 | |||
84 | /* Just return if requested mode is the same as the session's mode */ | ||
85 | if (disable_powergate) { | ||
86 | if (dbg_s->is_pg_disabled) | ||
87 | return 0; | ||
88 | dbg_s->is_pg_disabled = true; | ||
89 | mode = NVGPU_DBG_GPU_POWERGATE_MODE_DISABLE; | ||
90 | } else { | ||
91 | if (!dbg_s->is_pg_disabled) | ||
92 | return 0; | ||
93 | dbg_s->is_pg_disabled = false; | ||
94 | mode = NVGPU_DBG_GPU_POWERGATE_MODE_ENABLE; | ||
95 | } | ||
96 | |||
97 | msg.cmd = TEGRA_VGPU_CMD_SET_POWERGATE; | ||
98 | msg.handle = vgpu_get_handle(dbg_s->g); | ||
99 | p->mode = mode; | ||
100 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
101 | err = err ? err : msg.ret; | ||
102 | return err; | ||
103 | } | ||
104 | |||
105 | static int vgpu_sendrecv_prof_cmd(struct dbg_session_gk20a *dbg_s, u32 mode) | ||
106 | { | ||
107 | struct tegra_vgpu_cmd_msg msg; | ||
108 | struct tegra_vgpu_prof_mgt_params *p = &msg.params.prof_management; | ||
109 | int err = 0; | ||
110 | |||
111 | msg.cmd = TEGRA_VGPU_CMD_PROF_MGT; | ||
112 | msg.handle = vgpu_get_handle(dbg_s->g); | ||
113 | |||
114 | p->mode = mode; | ||
115 | |||
116 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
117 | err = err ? err : msg.ret; | ||
118 | return err; | ||
119 | } | ||
120 | |||
121 | bool vgpu_check_and_set_global_reservation( | ||
122 | struct dbg_session_gk20a *dbg_s, | ||
123 | struct dbg_profiler_object_data *prof_obj) | ||
124 | { | ||
125 | struct gk20a *g = dbg_s->g; | ||
126 | |||
127 | if (g->profiler_reservation_count > 0) | ||
128 | return false; | ||
129 | |||
130 | /* Check that another guest OS doesn't already have a reservation */ | ||
131 | if (!vgpu_sendrecv_prof_cmd(dbg_s, TEGRA_VGPU_PROF_GET_GLOBAL)) { | ||
132 | g->global_profiler_reservation_held = true; | ||
133 | g->profiler_reservation_count = 1; | ||
134 | dbg_s->has_profiler_reservation = true; | ||
135 | prof_obj->has_reservation = true; | ||
136 | return true; | ||
137 | } | ||
138 | return false; | ||
139 | } | ||
140 | |||
141 | bool vgpu_check_and_set_context_reservation( | ||
142 | struct dbg_session_gk20a *dbg_s, | ||
143 | struct dbg_profiler_object_data *prof_obj) | ||
144 | { | ||
145 | struct gk20a *g = dbg_s->g; | ||
146 | |||
147 | /* Assumes that we've already checked that no global reservation | ||
148 | * is in effect for this guest. | ||
149 | * | ||
150 | * If our reservation count is non-zero, then no other guest has the | ||
151 | * global reservation; if it is zero, need to check with RM server. | ||
152 | * | ||
153 | */ | ||
154 | if ((g->profiler_reservation_count != 0) || | ||
155 | !vgpu_sendrecv_prof_cmd(dbg_s, TEGRA_VGPU_PROF_GET_CONTEXT)) { | ||
156 | g->profiler_reservation_count++; | ||
157 | dbg_s->has_profiler_reservation = true; | ||
158 | prof_obj->has_reservation = true; | ||
159 | return true; | ||
160 | } | ||
161 | return false; | ||
162 | } | ||
163 | |||
164 | void vgpu_release_profiler_reservation( | ||
165 | struct dbg_session_gk20a *dbg_s, | ||
166 | struct dbg_profiler_object_data *prof_obj) | ||
167 | { | ||
168 | struct gk20a *g = dbg_s->g; | ||
169 | |||
170 | dbg_s->has_profiler_reservation = false; | ||
171 | prof_obj->has_reservation = false; | ||
172 | if (prof_obj->ch == NULL) | ||
173 | g->global_profiler_reservation_held = false; | ||
174 | |||
175 | /* If new reservation count is zero, notify server */ | ||
176 | g->profiler_reservation_count--; | ||
177 | if (g->profiler_reservation_count == 0) | ||
178 | vgpu_sendrecv_prof_cmd(dbg_s, TEGRA_VGPU_PROF_RELEASE); | ||
179 | } | ||
180 | |||
181 | static int vgpu_sendrecv_perfbuf_cmd(struct gk20a *g, u64 offset, u32 size) | ||
182 | { | ||
183 | struct mm_gk20a *mm = &g->mm; | ||
184 | struct vm_gk20a *vm = mm->perfbuf.vm; | ||
185 | struct tegra_vgpu_cmd_msg msg; | ||
186 | struct tegra_vgpu_perfbuf_mgt_params *p = | ||
187 | &msg.params.perfbuf_management; | ||
188 | int err; | ||
189 | |||
190 | msg.cmd = TEGRA_VGPU_CMD_PERFBUF_MGT; | ||
191 | msg.handle = vgpu_get_handle(g); | ||
192 | |||
193 | p->vm_handle = vm->handle; | ||
194 | p->offset = offset; | ||
195 | p->size = size; | ||
196 | |||
197 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
198 | err = err ? err : msg.ret; | ||
199 | return err; | ||
200 | } | ||
201 | |||
202 | int vgpu_perfbuffer_enable(struct gk20a *g, u64 offset, u32 size) | ||
203 | { | ||
204 | return vgpu_sendrecv_perfbuf_cmd(g, offset, size); | ||
205 | } | ||
206 | |||
207 | int vgpu_perfbuffer_disable(struct gk20a *g) | ||
208 | { | ||
209 | return vgpu_sendrecv_perfbuf_cmd(g, 0, 0); | ||
210 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/dbg_vgpu.h b/drivers/gpu/nvgpu/common/linux/vgpu/dbg_vgpu.h new file mode 100644 index 00000000..8552a82e --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/dbg_vgpu.h | |||
@@ -0,0 +1,41 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #ifndef _DBG_VGPU_H_ | ||
18 | #define _DBG_VGPU_H_ | ||
19 | |||
20 | struct dbg_session_gk20a; | ||
21 | struct nvgpu_dbg_gpu_reg_op; | ||
22 | struct dbg_profiler_object_data; | ||
23 | struct gk20a; | ||
24 | |||
25 | int vgpu_exec_regops(struct dbg_session_gk20a *dbg_s, | ||
26 | struct nvgpu_dbg_gpu_reg_op *ops, | ||
27 | u64 num_ops); | ||
28 | int vgpu_dbg_set_powergate(struct dbg_session_gk20a *dbg_s, bool disable_powergate); | ||
29 | bool vgpu_check_and_set_global_reservation( | ||
30 | struct dbg_session_gk20a *dbg_s, | ||
31 | struct dbg_profiler_object_data *prof_obj); | ||
32 | bool vgpu_check_and_set_context_reservation( | ||
33 | struct dbg_session_gk20a *dbg_s, | ||
34 | struct dbg_profiler_object_data *prof_obj); | ||
35 | |||
36 | void vgpu_release_profiler_reservation( | ||
37 | struct dbg_session_gk20a *dbg_s, | ||
38 | struct dbg_profiler_object_data *prof_obj); | ||
39 | int vgpu_perfbuffer_enable(struct gk20a *g, u64 offset, u32 size); | ||
40 | int vgpu_perfbuffer_disable(struct gk20a *g); | ||
41 | #endif | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/fecs_trace_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/fecs_trace_vgpu.c new file mode 100644 index 00000000..5007de36 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/fecs_trace_vgpu.c | |||
@@ -0,0 +1,225 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include <linux/string.h> | ||
18 | #include <linux/tegra-ivc.h> | ||
19 | #include <linux/tegra_vgpu.h> | ||
20 | |||
21 | #include <uapi/linux/nvgpu.h> | ||
22 | |||
23 | #include <nvgpu/kmem.h> | ||
24 | #include <nvgpu/bug.h> | ||
25 | #include <nvgpu/enabled.h> | ||
26 | #include <nvgpu/ctxsw_trace.h> | ||
27 | |||
28 | #include "gk20a/gk20a.h" | ||
29 | #include "vgpu.h" | ||
30 | #include "fecs_trace_vgpu.h" | ||
31 | |||
32 | struct vgpu_fecs_trace { | ||
33 | struct tegra_hv_ivm_cookie *cookie; | ||
34 | struct nvgpu_ctxsw_ring_header *header; | ||
35 | struct nvgpu_ctxsw_trace_entry *entries; | ||
36 | int num_entries; | ||
37 | bool enabled; | ||
38 | void *buf; | ||
39 | }; | ||
40 | |||
41 | int vgpu_fecs_trace_init(struct gk20a *g) | ||
42 | { | ||
43 | struct device *dev = dev_from_gk20a(g); | ||
44 | struct device_node *np = dev->of_node; | ||
45 | struct of_phandle_args args; | ||
46 | struct device_node *hv_np; | ||
47 | struct vgpu_fecs_trace *vcst; | ||
48 | u32 mempool; | ||
49 | int err; | ||
50 | |||
51 | gk20a_dbg_fn(""); | ||
52 | |||
53 | vcst = nvgpu_kzalloc(g, sizeof(*vcst)); | ||
54 | if (!vcst) | ||
55 | return -ENOMEM; | ||
56 | |||
57 | err = of_parse_phandle_with_fixed_args(np, | ||
58 | "mempool-fecs-trace", 1, 0, &args); | ||
59 | if (err) { | ||
60 | dev_info(dev_from_gk20a(g), "does not support fecs trace\n"); | ||
61 | goto fail; | ||
62 | } | ||
63 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_FECS_CTXSW_TRACE, true); | ||
64 | |||
65 | hv_np = args.np; | ||
66 | mempool = args.args[0]; | ||
67 | vcst->cookie = tegra_hv_mempool_reserve(hv_np, mempool); | ||
68 | if (IS_ERR(vcst->cookie)) { | ||
69 | dev_info(dev_from_gk20a(g), | ||
70 | "mempool %u reserve failed\n", mempool); | ||
71 | vcst->cookie = NULL; | ||
72 | err = -EINVAL; | ||
73 | goto fail; | ||
74 | } | ||
75 | |||
76 | vcst->buf = ioremap_cache(vcst->cookie->ipa, vcst->cookie->size); | ||
77 | if (!vcst->buf) { | ||
78 | dev_info(dev_from_gk20a(g), "ioremap_cache failed\n"); | ||
79 | err = -EINVAL; | ||
80 | goto fail; | ||
81 | } | ||
82 | vcst->header = vcst->buf; | ||
83 | vcst->num_entries = vcst->header->num_ents; | ||
84 | if (unlikely(vcst->header->ent_size != sizeof(*vcst->entries))) { | ||
85 | dev_err(dev_from_gk20a(g), | ||
86 | "entry size mismatch\n"); | ||
87 | goto fail; | ||
88 | } | ||
89 | vcst->entries = vcst->buf + sizeof(*vcst->header); | ||
90 | g->fecs_trace = (struct gk20a_fecs_trace *)vcst; | ||
91 | |||
92 | return 0; | ||
93 | fail: | ||
94 | iounmap(vcst->buf); | ||
95 | if (vcst->cookie) | ||
96 | tegra_hv_mempool_unreserve(vcst->cookie); | ||
97 | nvgpu_kfree(g, vcst); | ||
98 | return err; | ||
99 | } | ||
100 | |||
101 | int vgpu_fecs_trace_deinit(struct gk20a *g) | ||
102 | { | ||
103 | struct vgpu_fecs_trace *vcst = (struct vgpu_fecs_trace *)g->fecs_trace; | ||
104 | |||
105 | iounmap(vcst->buf); | ||
106 | tegra_hv_mempool_unreserve(vcst->cookie); | ||
107 | nvgpu_kfree(g, vcst); | ||
108 | return 0; | ||
109 | } | ||
110 | |||
111 | int vgpu_fecs_trace_enable(struct gk20a *g) | ||
112 | { | ||
113 | struct vgpu_fecs_trace *vcst = (struct vgpu_fecs_trace *)g->fecs_trace; | ||
114 | struct tegra_vgpu_cmd_msg msg = { | ||
115 | .cmd = TEGRA_VGPU_CMD_FECS_TRACE_ENABLE, | ||
116 | .handle = vgpu_get_handle(g), | ||
117 | }; | ||
118 | int err; | ||
119 | |||
120 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
121 | err = err ? err : msg.ret; | ||
122 | WARN_ON(err); | ||
123 | vcst->enabled = !err; | ||
124 | return err; | ||
125 | } | ||
126 | |||
127 | int vgpu_fecs_trace_disable(struct gk20a *g) | ||
128 | { | ||
129 | struct vgpu_fecs_trace *vcst = (struct vgpu_fecs_trace *)g->fecs_trace; | ||
130 | struct tegra_vgpu_cmd_msg msg = { | ||
131 | .cmd = TEGRA_VGPU_CMD_FECS_TRACE_DISABLE, | ||
132 | .handle = vgpu_get_handle(g), | ||
133 | }; | ||
134 | int err; | ||
135 | |||
136 | vcst->enabled = false; | ||
137 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
138 | err = err ? err : msg.ret; | ||
139 | WARN_ON(err); | ||
140 | return err; | ||
141 | } | ||
142 | |||
143 | bool vgpu_fecs_trace_is_enabled(struct gk20a *g) | ||
144 | { | ||
145 | struct vgpu_fecs_trace *vcst = (struct vgpu_fecs_trace *)g->fecs_trace; | ||
146 | |||
147 | return (vcst && vcst->enabled); | ||
148 | } | ||
149 | |||
150 | int vgpu_fecs_trace_poll(struct gk20a *g) | ||
151 | { | ||
152 | struct tegra_vgpu_cmd_msg msg = { | ||
153 | .cmd = TEGRA_VGPU_CMD_FECS_TRACE_POLL, | ||
154 | .handle = vgpu_get_handle(g), | ||
155 | }; | ||
156 | int err; | ||
157 | |||
158 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
159 | err = err ? err : msg.ret; | ||
160 | WARN_ON(err); | ||
161 | return err; | ||
162 | } | ||
163 | |||
164 | int vgpu_alloc_user_buffer(struct gk20a *g, void **buf, size_t *size) | ||
165 | { | ||
166 | struct vgpu_fecs_trace *vcst = (struct vgpu_fecs_trace *)g->fecs_trace; | ||
167 | |||
168 | *buf = vcst->buf; | ||
169 | *size = vcst->cookie->size; | ||
170 | return 0; | ||
171 | } | ||
172 | |||
173 | int vgpu_free_user_buffer(struct gk20a *g) | ||
174 | { | ||
175 | return 0; | ||
176 | } | ||
177 | |||
178 | int vgpu_mmap_user_buffer(struct gk20a *g, struct vm_area_struct *vma) | ||
179 | { | ||
180 | struct vgpu_fecs_trace *vcst = (struct vgpu_fecs_trace *)g->fecs_trace; | ||
181 | unsigned long size = vcst->cookie->size; | ||
182 | unsigned long vsize = vma->vm_end - vma->vm_start; | ||
183 | |||
184 | size = min(size, vsize); | ||
185 | size = round_up(size, PAGE_SIZE); | ||
186 | |||
187 | return remap_pfn_range(vma, vma->vm_start, | ||
188 | vcst->cookie->ipa >> PAGE_SHIFT, | ||
189 | size, | ||
190 | vma->vm_page_prot); | ||
191 | } | ||
192 | |||
193 | int vgpu_fecs_trace_max_entries(struct gk20a *g, | ||
194 | struct nvgpu_ctxsw_trace_filter *filter) | ||
195 | { | ||
196 | struct vgpu_fecs_trace *vcst = (struct vgpu_fecs_trace *)g->fecs_trace; | ||
197 | |||
198 | return vcst->header->num_ents; | ||
199 | } | ||
200 | |||
201 | #if NVGPU_CTXSW_FILTER_SIZE != TEGRA_VGPU_FECS_TRACE_FILTER_SIZE | ||
202 | #error "FECS trace filter size mismatch!" | ||
203 | #endif | ||
204 | |||
205 | int vgpu_fecs_trace_set_filter(struct gk20a *g, | ||
206 | struct nvgpu_ctxsw_trace_filter *filter) | ||
207 | { | ||
208 | struct tegra_vgpu_cmd_msg msg = { | ||
209 | .cmd = TEGRA_VGPU_CMD_FECS_TRACE_SET_FILTER, | ||
210 | .handle = vgpu_get_handle(g), | ||
211 | }; | ||
212 | struct tegra_vgpu_fecs_trace_filter *p = &msg.params.fecs_trace_filter; | ||
213 | int err; | ||
214 | |||
215 | memcpy(&p->tag_bits, &filter->tag_bits, sizeof(p->tag_bits)); | ||
216 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
217 | err = err ? err : msg.ret; | ||
218 | WARN_ON(err); | ||
219 | return err; | ||
220 | } | ||
221 | |||
222 | void vgpu_fecs_trace_data_update(struct gk20a *g) | ||
223 | { | ||
224 | gk20a_ctxsw_trace_wake_up(g, 0); | ||
225 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/fecs_trace_vgpu.h b/drivers/gpu/nvgpu/common/linux/vgpu/fecs_trace_vgpu.h new file mode 100644 index 00000000..c375b841 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/fecs_trace_vgpu.h | |||
@@ -0,0 +1,41 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #ifndef __FECS_TRACE_VGPU_H | ||
18 | #define __FECS_TRACE_VGPU_H | ||
19 | |||
20 | #include <nvgpu/types.h> | ||
21 | |||
22 | struct gk20a; | ||
23 | struct vm_area_struct; | ||
24 | struct nvgpu_ctxsw_trace_filter; | ||
25 | |||
26 | void vgpu_fecs_trace_data_update(struct gk20a *g); | ||
27 | int vgpu_fecs_trace_init(struct gk20a *g); | ||
28 | int vgpu_fecs_trace_deinit(struct gk20a *g); | ||
29 | int vgpu_fecs_trace_enable(struct gk20a *g); | ||
30 | int vgpu_fecs_trace_disable(struct gk20a *g); | ||
31 | bool vgpu_fecs_trace_is_enabled(struct gk20a *g); | ||
32 | int vgpu_fecs_trace_poll(struct gk20a *g); | ||
33 | int vgpu_alloc_user_buffer(struct gk20a *g, void **buf, size_t *size); | ||
34 | int vgpu_free_user_buffer(struct gk20a *g); | ||
35 | int vgpu_mmap_user_buffer(struct gk20a *g, struct vm_area_struct *vma); | ||
36 | int vgpu_fecs_trace_max_entries(struct gk20a *g, | ||
37 | struct nvgpu_ctxsw_trace_filter *filter); | ||
38 | int vgpu_fecs_trace_set_filter(struct gk20a *g, | ||
39 | struct nvgpu_ctxsw_trace_filter *filter); | ||
40 | |||
41 | #endif /* __FECS_TRACE_VGPU_H */ | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c new file mode 100644 index 00000000..cdcecca5 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c | |||
@@ -0,0 +1,822 @@ | |||
1 | /* | ||
2 | * Virtualized GPU Fifo | ||
3 | * | ||
4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
17 | */ | ||
18 | |||
19 | #include <linux/dma-mapping.h> | ||
20 | #include <trace/events/gk20a.h> | ||
21 | #include <uapi/linux/nvgpu.h> | ||
22 | |||
23 | #include <nvgpu/kmem.h> | ||
24 | #include <nvgpu/dma.h> | ||
25 | #include <nvgpu/atomic.h> | ||
26 | #include <nvgpu/bug.h> | ||
27 | #include <nvgpu/barrier.h> | ||
28 | |||
29 | #include "vgpu.h" | ||
30 | #include "fifo_vgpu.h" | ||
31 | |||
32 | #include <nvgpu/hw/gk20a/hw_fifo_gk20a.h> | ||
33 | #include <nvgpu/hw/gk20a/hw_ram_gk20a.h> | ||
34 | |||
35 | void vgpu_channel_bind(struct channel_gk20a *ch) | ||
36 | { | ||
37 | struct tegra_vgpu_cmd_msg msg; | ||
38 | struct tegra_vgpu_channel_config_params *p = | ||
39 | &msg.params.channel_config; | ||
40 | int err; | ||
41 | |||
42 | gk20a_dbg_info("bind channel %d", ch->chid); | ||
43 | |||
44 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_BIND; | ||
45 | msg.handle = vgpu_get_handle(ch->g); | ||
46 | p->handle = ch->virt_ctx; | ||
47 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
48 | WARN_ON(err || msg.ret); | ||
49 | |||
50 | nvgpu_smp_wmb(); | ||
51 | nvgpu_atomic_set(&ch->bound, true); | ||
52 | } | ||
53 | |||
54 | void vgpu_channel_unbind(struct channel_gk20a *ch) | ||
55 | { | ||
56 | |||
57 | gk20a_dbg_fn(""); | ||
58 | |||
59 | if (nvgpu_atomic_cmpxchg(&ch->bound, true, false)) { | ||
60 | struct tegra_vgpu_cmd_msg msg; | ||
61 | struct tegra_vgpu_channel_config_params *p = | ||
62 | &msg.params.channel_config; | ||
63 | int err; | ||
64 | |||
65 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_UNBIND; | ||
66 | msg.handle = vgpu_get_handle(ch->g); | ||
67 | p->handle = ch->virt_ctx; | ||
68 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
69 | WARN_ON(err || msg.ret); | ||
70 | } | ||
71 | |||
72 | } | ||
73 | |||
74 | int vgpu_channel_alloc_inst(struct gk20a *g, struct channel_gk20a *ch) | ||
75 | { | ||
76 | struct tegra_vgpu_cmd_msg msg; | ||
77 | struct tegra_vgpu_channel_hwctx_params *p = &msg.params.channel_hwctx; | ||
78 | int err; | ||
79 | |||
80 | gk20a_dbg_fn(""); | ||
81 | |||
82 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_ALLOC_HWCTX; | ||
83 | msg.handle = vgpu_get_handle(g); | ||
84 | p->id = ch->chid; | ||
85 | p->pid = (u64)current->tgid; | ||
86 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
87 | if (err || msg.ret) { | ||
88 | nvgpu_err(g, "fail"); | ||
89 | return -ENOMEM; | ||
90 | } | ||
91 | |||
92 | ch->virt_ctx = p->handle; | ||
93 | gk20a_dbg_fn("done"); | ||
94 | return 0; | ||
95 | } | ||
96 | |||
97 | void vgpu_channel_free_inst(struct gk20a *g, struct channel_gk20a *ch) | ||
98 | { | ||
99 | struct tegra_vgpu_cmd_msg msg; | ||
100 | struct tegra_vgpu_channel_hwctx_params *p = &msg.params.channel_hwctx; | ||
101 | int err; | ||
102 | |||
103 | gk20a_dbg_fn(""); | ||
104 | |||
105 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_FREE_HWCTX; | ||
106 | msg.handle = vgpu_get_handle(g); | ||
107 | p->handle = ch->virt_ctx; | ||
108 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
109 | WARN_ON(err || msg.ret); | ||
110 | } | ||
111 | |||
112 | void vgpu_channel_enable(struct channel_gk20a *ch) | ||
113 | { | ||
114 | struct tegra_vgpu_cmd_msg msg; | ||
115 | struct tegra_vgpu_channel_config_params *p = | ||
116 | &msg.params.channel_config; | ||
117 | int err; | ||
118 | |||
119 | gk20a_dbg_fn(""); | ||
120 | |||
121 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_ENABLE; | ||
122 | msg.handle = vgpu_get_handle(ch->g); | ||
123 | p->handle = ch->virt_ctx; | ||
124 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
125 | WARN_ON(err || msg.ret); | ||
126 | } | ||
127 | |||
128 | void vgpu_channel_disable(struct channel_gk20a *ch) | ||
129 | { | ||
130 | struct tegra_vgpu_cmd_msg msg; | ||
131 | struct tegra_vgpu_channel_config_params *p = | ||
132 | &msg.params.channel_config; | ||
133 | int err; | ||
134 | |||
135 | gk20a_dbg_fn(""); | ||
136 | |||
137 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_DISABLE; | ||
138 | msg.handle = vgpu_get_handle(ch->g); | ||
139 | p->handle = ch->virt_ctx; | ||
140 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
141 | WARN_ON(err || msg.ret); | ||
142 | } | ||
143 | |||
144 | int vgpu_channel_setup_ramfc(struct channel_gk20a *ch, u64 gpfifo_base, | ||
145 | u32 gpfifo_entries, | ||
146 | unsigned long acquire_timeout, u32 flags) | ||
147 | { | ||
148 | struct device __maybe_unused *d = dev_from_gk20a(ch->g); | ||
149 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(d); | ||
150 | struct tegra_vgpu_cmd_msg msg; | ||
151 | struct tegra_vgpu_ramfc_params *p = &msg.params.ramfc; | ||
152 | int err; | ||
153 | |||
154 | gk20a_dbg_fn(""); | ||
155 | |||
156 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SETUP_RAMFC; | ||
157 | msg.handle = vgpu_get_handle(ch->g); | ||
158 | p->handle = ch->virt_ctx; | ||
159 | p->gpfifo_va = gpfifo_base; | ||
160 | p->num_entries = gpfifo_entries; | ||
161 | p->userd_addr = ch->userd_iova; | ||
162 | p->iova = mapping ? 1 : 0; | ||
163 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
164 | |||
165 | return (err || msg.ret) ? -ENOMEM : 0; | ||
166 | } | ||
167 | |||
168 | int vgpu_fifo_init_engine_info(struct fifo_gk20a *f) | ||
169 | { | ||
170 | struct vgpu_priv_data *priv = vgpu_get_priv_data(f->g); | ||
171 | struct tegra_vgpu_engines_info *engines = &priv->constants.engines_info; | ||
172 | u32 i; | ||
173 | |||
174 | gk20a_dbg_fn(""); | ||
175 | |||
176 | if (engines->num_engines > TEGRA_VGPU_MAX_ENGINES) { | ||
177 | nvgpu_err(f->g, "num_engines %d larger than max %d", | ||
178 | engines->num_engines, TEGRA_VGPU_MAX_ENGINES); | ||
179 | return -EINVAL; | ||
180 | } | ||
181 | |||
182 | f->num_engines = engines->num_engines; | ||
183 | for (i = 0; i < f->num_engines; i++) { | ||
184 | struct fifo_engine_info_gk20a *info = | ||
185 | &f->engine_info[engines->info[i].engine_id]; | ||
186 | |||
187 | if (engines->info[i].engine_id >= f->max_engines) { | ||
188 | nvgpu_err(f->g, "engine id %d larger than max %d", | ||
189 | engines->info[i].engine_id, | ||
190 | f->max_engines); | ||
191 | return -EINVAL; | ||
192 | } | ||
193 | |||
194 | info->intr_mask = engines->info[i].intr_mask; | ||
195 | info->reset_mask = engines->info[i].reset_mask; | ||
196 | info->runlist_id = engines->info[i].runlist_id; | ||
197 | info->pbdma_id = engines->info[i].pbdma_id; | ||
198 | info->inst_id = engines->info[i].inst_id; | ||
199 | info->pri_base = engines->info[i].pri_base; | ||
200 | info->engine_enum = engines->info[i].engine_enum; | ||
201 | info->fault_id = engines->info[i].fault_id; | ||
202 | f->active_engines_list[i] = engines->info[i].engine_id; | ||
203 | } | ||
204 | |||
205 | gk20a_dbg_fn("done"); | ||
206 | |||
207 | return 0; | ||
208 | } | ||
209 | |||
210 | static int init_runlist(struct gk20a *g, struct fifo_gk20a *f) | ||
211 | { | ||
212 | struct fifo_runlist_info_gk20a *runlist; | ||
213 | struct device *d = dev_from_gk20a(g); | ||
214 | unsigned int runlist_id = -1; | ||
215 | u32 i; | ||
216 | u64 runlist_size; | ||
217 | |||
218 | gk20a_dbg_fn(""); | ||
219 | |||
220 | f->max_runlists = g->ops.fifo.eng_runlist_base_size(); | ||
221 | f->runlist_info = nvgpu_kzalloc(g, | ||
222 | sizeof(struct fifo_runlist_info_gk20a) * | ||
223 | f->max_runlists); | ||
224 | if (!f->runlist_info) | ||
225 | goto clean_up_runlist; | ||
226 | |||
227 | memset(f->runlist_info, 0, (sizeof(struct fifo_runlist_info_gk20a) * | ||
228 | f->max_runlists)); | ||
229 | |||
230 | for (runlist_id = 0; runlist_id < f->max_runlists; runlist_id++) { | ||
231 | runlist = &f->runlist_info[runlist_id]; | ||
232 | |||
233 | runlist->active_channels = | ||
234 | nvgpu_kzalloc(g, DIV_ROUND_UP(f->num_channels, | ||
235 | BITS_PER_BYTE)); | ||
236 | if (!runlist->active_channels) | ||
237 | goto clean_up_runlist; | ||
238 | |||
239 | runlist_size = sizeof(u16) * f->num_channels; | ||
240 | for (i = 0; i < MAX_RUNLIST_BUFFERS; i++) { | ||
241 | int err = nvgpu_dma_alloc_sys(g, runlist_size, | ||
242 | &runlist->mem[i]); | ||
243 | if (err) { | ||
244 | dev_err(d, "memory allocation failed\n"); | ||
245 | goto clean_up_runlist; | ||
246 | } | ||
247 | } | ||
248 | nvgpu_mutex_init(&runlist->mutex); | ||
249 | |||
250 | /* None of buffers is pinned if this value doesn't change. | ||
251 | Otherwise, one of them (cur_buffer) must have been pinned. */ | ||
252 | runlist->cur_buffer = MAX_RUNLIST_BUFFERS; | ||
253 | } | ||
254 | |||
255 | gk20a_dbg_fn("done"); | ||
256 | return 0; | ||
257 | |||
258 | clean_up_runlist: | ||
259 | gk20a_fifo_delete_runlist(f); | ||
260 | gk20a_dbg_fn("fail"); | ||
261 | return -ENOMEM; | ||
262 | } | ||
263 | |||
264 | static int vgpu_init_fifo_setup_sw(struct gk20a *g) | ||
265 | { | ||
266 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | ||
267 | struct fifo_gk20a *f = &g->fifo; | ||
268 | struct device *d = dev_from_gk20a(g); | ||
269 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | ||
270 | unsigned int chid; | ||
271 | int err = 0; | ||
272 | |||
273 | gk20a_dbg_fn(""); | ||
274 | |||
275 | if (f->sw_ready) { | ||
276 | gk20a_dbg_fn("skip init"); | ||
277 | return 0; | ||
278 | } | ||
279 | |||
280 | f->g = g; | ||
281 | f->num_channels = priv->constants.num_channels; | ||
282 | f->max_engines = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_ENGINES); | ||
283 | |||
284 | f->userd_entry_size = 1 << ram_userd_base_shift_v(); | ||
285 | |||
286 | err = nvgpu_dma_alloc_sys(g, f->userd_entry_size * f->num_channels, | ||
287 | &f->userd); | ||
288 | if (err) { | ||
289 | dev_err(d, "memory allocation failed\n"); | ||
290 | goto clean_up; | ||
291 | } | ||
292 | |||
293 | /* bar1 va */ | ||
294 | if (g->ops.mm.is_bar1_supported(g)) { | ||
295 | f->userd.gpu_va = vgpu_bar1_map(g, &f->userd.priv.sgt, | ||
296 | f->userd.size); | ||
297 | if (!f->userd.gpu_va) { | ||
298 | dev_err(d, "gmmu mapping failed\n"); | ||
299 | goto clean_up; | ||
300 | } | ||
301 | /* if reduced BAR1 range is specified, use offset of 0 | ||
302 | * (server returns offset assuming full BAR1 range) | ||
303 | */ | ||
304 | if (resource_size(l->bar1_mem) == | ||
305 | (resource_size_t)f->userd.size) | ||
306 | f->userd.gpu_va = 0; | ||
307 | } | ||
308 | |||
309 | gk20a_dbg(gpu_dbg_map_v, "userd bar1 va = 0x%llx", f->userd.gpu_va); | ||
310 | |||
311 | f->channel = nvgpu_vzalloc(g, f->num_channels * sizeof(*f->channel)); | ||
312 | f->tsg = nvgpu_vzalloc(g, f->num_channels * sizeof(*f->tsg)); | ||
313 | f->engine_info = nvgpu_kzalloc(g, f->max_engines * | ||
314 | sizeof(*f->engine_info)); | ||
315 | f->active_engines_list = nvgpu_kzalloc(g, f->max_engines * sizeof(u32)); | ||
316 | |||
317 | if (!(f->channel && f->tsg && f->engine_info && f->active_engines_list)) { | ||
318 | err = -ENOMEM; | ||
319 | goto clean_up; | ||
320 | } | ||
321 | memset(f->active_engines_list, 0xff, (f->max_engines * sizeof(u32))); | ||
322 | |||
323 | g->ops.fifo.init_engine_info(f); | ||
324 | |||
325 | init_runlist(g, f); | ||
326 | |||
327 | nvgpu_init_list_node(&f->free_chs); | ||
328 | nvgpu_mutex_init(&f->free_chs_mutex); | ||
329 | |||
330 | for (chid = 0; chid < f->num_channels; chid++) { | ||
331 | f->channel[chid].userd_iova = | ||
332 | nvgpu_mem_get_addr(g, &f->userd) + | ||
333 | chid * f->userd_entry_size; | ||
334 | f->channel[chid].userd_gpu_va = | ||
335 | f->userd.gpu_va + chid * f->userd_entry_size; | ||
336 | |||
337 | gk20a_init_channel_support(g, chid); | ||
338 | gk20a_init_tsg_support(g, chid); | ||
339 | } | ||
340 | nvgpu_mutex_init(&f->tsg_inuse_mutex); | ||
341 | |||
342 | err = nvgpu_channel_worker_init(g); | ||
343 | if (err) | ||
344 | goto clean_up; | ||
345 | |||
346 | f->deferred_reset_pending = false; | ||
347 | nvgpu_mutex_init(&f->deferred_reset_mutex); | ||
348 | |||
349 | f->channel_base = priv->constants.channel_base; | ||
350 | |||
351 | f->sw_ready = true; | ||
352 | |||
353 | gk20a_dbg_fn("done"); | ||
354 | return 0; | ||
355 | |||
356 | clean_up: | ||
357 | gk20a_dbg_fn("fail"); | ||
358 | /* FIXME: unmap from bar1 */ | ||
359 | nvgpu_dma_free(g, &f->userd); | ||
360 | |||
361 | memset(&f->userd, 0, sizeof(f->userd)); | ||
362 | |||
363 | nvgpu_vfree(g, f->channel); | ||
364 | f->channel = NULL; | ||
365 | nvgpu_vfree(g, f->tsg); | ||
366 | f->tsg = NULL; | ||
367 | nvgpu_kfree(g, f->engine_info); | ||
368 | f->engine_info = NULL; | ||
369 | nvgpu_kfree(g, f->active_engines_list); | ||
370 | f->active_engines_list = NULL; | ||
371 | |||
372 | return err; | ||
373 | } | ||
374 | |||
375 | int vgpu_init_fifo_setup_hw(struct gk20a *g) | ||
376 | { | ||
377 | gk20a_dbg_fn(""); | ||
378 | |||
379 | /* test write, read through bar1 @ userd region before | ||
380 | * turning on the snooping */ | ||
381 | { | ||
382 | struct fifo_gk20a *f = &g->fifo; | ||
383 | u32 v, v1 = 0x33, v2 = 0x55; | ||
384 | |||
385 | u32 bar1_vaddr = f->userd.gpu_va; | ||
386 | volatile u32 *cpu_vaddr = f->userd.cpu_va; | ||
387 | |||
388 | gk20a_dbg_info("test bar1 @ vaddr 0x%x", | ||
389 | bar1_vaddr); | ||
390 | |||
391 | v = gk20a_bar1_readl(g, bar1_vaddr); | ||
392 | |||
393 | *cpu_vaddr = v1; | ||
394 | nvgpu_mb(); | ||
395 | |||
396 | if (v1 != gk20a_bar1_readl(g, bar1_vaddr)) { | ||
397 | nvgpu_err(g, "bar1 broken @ gk20a!"); | ||
398 | return -EINVAL; | ||
399 | } | ||
400 | |||
401 | gk20a_bar1_writel(g, bar1_vaddr, v2); | ||
402 | |||
403 | if (v2 != gk20a_bar1_readl(g, bar1_vaddr)) { | ||
404 | nvgpu_err(g, "bar1 broken @ gk20a!"); | ||
405 | return -EINVAL; | ||
406 | } | ||
407 | |||
408 | /* is it visible to the cpu? */ | ||
409 | if (*cpu_vaddr != v2) { | ||
410 | nvgpu_err(g, "cpu didn't see bar1 write @ %p!", | ||
411 | cpu_vaddr); | ||
412 | } | ||
413 | |||
414 | /* put it back */ | ||
415 | gk20a_bar1_writel(g, bar1_vaddr, v); | ||
416 | } | ||
417 | |||
418 | gk20a_dbg_fn("done"); | ||
419 | |||
420 | return 0; | ||
421 | } | ||
422 | |||
423 | int vgpu_init_fifo_support(struct gk20a *g) | ||
424 | { | ||
425 | u32 err; | ||
426 | |||
427 | gk20a_dbg_fn(""); | ||
428 | |||
429 | err = vgpu_init_fifo_setup_sw(g); | ||
430 | if (err) | ||
431 | return err; | ||
432 | |||
433 | if (g->ops.fifo.init_fifo_setup_hw) | ||
434 | err = g->ops.fifo.init_fifo_setup_hw(g); | ||
435 | return err; | ||
436 | } | ||
437 | |||
438 | int vgpu_fifo_preempt_channel(struct gk20a *g, u32 chid) | ||
439 | { | ||
440 | struct fifo_gk20a *f = &g->fifo; | ||
441 | struct channel_gk20a *ch = &f->channel[chid]; | ||
442 | struct tegra_vgpu_cmd_msg msg; | ||
443 | struct tegra_vgpu_channel_config_params *p = | ||
444 | &msg.params.channel_config; | ||
445 | int err; | ||
446 | |||
447 | gk20a_dbg_fn(""); | ||
448 | |||
449 | if (!nvgpu_atomic_read(&ch->bound)) | ||
450 | return 0; | ||
451 | |||
452 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_PREEMPT; | ||
453 | msg.handle = vgpu_get_handle(g); | ||
454 | p->handle = ch->virt_ctx; | ||
455 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
456 | |||
457 | if (err || msg.ret) { | ||
458 | nvgpu_err(g, | ||
459 | "preempt channel %d failed", chid); | ||
460 | err = -ENOMEM; | ||
461 | } | ||
462 | |||
463 | return err; | ||
464 | } | ||
465 | |||
466 | int vgpu_fifo_preempt_tsg(struct gk20a *g, u32 tsgid) | ||
467 | { | ||
468 | struct tegra_vgpu_cmd_msg msg; | ||
469 | struct tegra_vgpu_tsg_preempt_params *p = | ||
470 | &msg.params.tsg_preempt; | ||
471 | int err; | ||
472 | |||
473 | gk20a_dbg_fn(""); | ||
474 | |||
475 | msg.cmd = TEGRA_VGPU_CMD_TSG_PREEMPT; | ||
476 | msg.handle = vgpu_get_handle(g); | ||
477 | p->tsg_id = tsgid; | ||
478 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
479 | err = err ? err : msg.ret; | ||
480 | |||
481 | if (err) { | ||
482 | nvgpu_err(g, | ||
483 | "preempt tsg %u failed", tsgid); | ||
484 | } | ||
485 | |||
486 | return err; | ||
487 | } | ||
488 | |||
489 | static int vgpu_submit_runlist(struct gk20a *g, u64 handle, u8 runlist_id, | ||
490 | u16 *runlist, u32 num_entries) | ||
491 | { | ||
492 | struct tegra_vgpu_cmd_msg msg; | ||
493 | struct tegra_vgpu_runlist_params *p; | ||
494 | int err; | ||
495 | void *oob_handle; | ||
496 | void *oob; | ||
497 | size_t size, oob_size; | ||
498 | |||
499 | oob_handle = tegra_gr_comm_oob_get_ptr(TEGRA_GR_COMM_CTX_CLIENT, | ||
500 | tegra_gr_comm_get_server_vmid(), TEGRA_VGPU_QUEUE_CMD, | ||
501 | &oob, &oob_size); | ||
502 | if (!oob_handle) | ||
503 | return -EINVAL; | ||
504 | |||
505 | size = sizeof(*runlist) * num_entries; | ||
506 | if (oob_size < size) { | ||
507 | err = -ENOMEM; | ||
508 | goto done; | ||
509 | } | ||
510 | |||
511 | msg.cmd = TEGRA_VGPU_CMD_SUBMIT_RUNLIST; | ||
512 | msg.handle = handle; | ||
513 | p = &msg.params.runlist; | ||
514 | p->runlist_id = runlist_id; | ||
515 | p->num_entries = num_entries; | ||
516 | |||
517 | memcpy(oob, runlist, size); | ||
518 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
519 | |||
520 | err = (err || msg.ret) ? -1 : 0; | ||
521 | |||
522 | done: | ||
523 | tegra_gr_comm_oob_put_ptr(oob_handle); | ||
524 | return err; | ||
525 | } | ||
526 | |||
527 | static int vgpu_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id, | ||
528 | u32 chid, bool add, | ||
529 | bool wait_for_finish) | ||
530 | { | ||
531 | struct fifo_gk20a *f = &g->fifo; | ||
532 | struct fifo_runlist_info_gk20a *runlist; | ||
533 | u16 *runlist_entry = NULL; | ||
534 | u32 count = 0; | ||
535 | |||
536 | gk20a_dbg_fn(""); | ||
537 | |||
538 | runlist = &f->runlist_info[runlist_id]; | ||
539 | |||
540 | /* valid channel, add/remove it from active list. | ||
541 | Otherwise, keep active list untouched for suspend/resume. */ | ||
542 | if (chid != (u32)~0) { | ||
543 | if (add) { | ||
544 | if (test_and_set_bit(chid, | ||
545 | runlist->active_channels) == 1) | ||
546 | return 0; | ||
547 | } else { | ||
548 | if (test_and_clear_bit(chid, | ||
549 | runlist->active_channels) == 0) | ||
550 | return 0; | ||
551 | } | ||
552 | } | ||
553 | |||
554 | if (chid != (u32)~0 || /* add/remove a valid channel */ | ||
555 | add /* resume to add all channels back */) { | ||
556 | u32 cid; | ||
557 | |||
558 | runlist_entry = runlist->mem[0].cpu_va; | ||
559 | for_each_set_bit(cid, | ||
560 | runlist->active_channels, f->num_channels) { | ||
561 | gk20a_dbg_info("add channel %d to runlist", cid); | ||
562 | runlist_entry[0] = cid; | ||
563 | runlist_entry++; | ||
564 | count++; | ||
565 | } | ||
566 | } else /* suspend to remove all channels */ | ||
567 | count = 0; | ||
568 | |||
569 | return vgpu_submit_runlist(g, vgpu_get_handle(g), runlist_id, | ||
570 | runlist->mem[0].cpu_va, count); | ||
571 | } | ||
572 | |||
573 | /* add/remove a channel from runlist | ||
574 | special cases below: runlist->active_channels will NOT be changed. | ||
575 | (chid == ~0 && !add) means remove all active channels from runlist. | ||
576 | (chid == ~0 && add) means restore all active channels on runlist. */ | ||
577 | int vgpu_fifo_update_runlist(struct gk20a *g, u32 runlist_id, | ||
578 | u32 chid, bool add, bool wait_for_finish) | ||
579 | { | ||
580 | struct fifo_runlist_info_gk20a *runlist = NULL; | ||
581 | struct fifo_gk20a *f = &g->fifo; | ||
582 | u32 ret = 0; | ||
583 | |||
584 | gk20a_dbg_fn(""); | ||
585 | |||
586 | runlist = &f->runlist_info[runlist_id]; | ||
587 | |||
588 | nvgpu_mutex_acquire(&runlist->mutex); | ||
589 | |||
590 | ret = vgpu_fifo_update_runlist_locked(g, runlist_id, chid, add, | ||
591 | wait_for_finish); | ||
592 | |||
593 | nvgpu_mutex_release(&runlist->mutex); | ||
594 | return ret; | ||
595 | } | ||
596 | |||
597 | int vgpu_fifo_wait_engine_idle(struct gk20a *g) | ||
598 | { | ||
599 | gk20a_dbg_fn(""); | ||
600 | |||
601 | return 0; | ||
602 | } | ||
603 | |||
604 | static int vgpu_fifo_tsg_set_runlist_interleave(struct gk20a *g, | ||
605 | u32 tsgid, | ||
606 | u32 runlist_id, | ||
607 | u32 new_level) | ||
608 | { | ||
609 | struct tegra_vgpu_cmd_msg msg = {0}; | ||
610 | struct tegra_vgpu_tsg_runlist_interleave_params *p = | ||
611 | &msg.params.tsg_interleave; | ||
612 | int err; | ||
613 | |||
614 | gk20a_dbg_fn(""); | ||
615 | |||
616 | msg.cmd = TEGRA_VGPU_CMD_TSG_SET_RUNLIST_INTERLEAVE; | ||
617 | msg.handle = vgpu_get_handle(g); | ||
618 | p->tsg_id = tsgid; | ||
619 | p->level = new_level; | ||
620 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
621 | WARN_ON(err || msg.ret); | ||
622 | return err ? err : msg.ret; | ||
623 | } | ||
624 | |||
625 | int vgpu_fifo_set_runlist_interleave(struct gk20a *g, | ||
626 | u32 id, | ||
627 | bool is_tsg, | ||
628 | u32 runlist_id, | ||
629 | u32 new_level) | ||
630 | { | ||
631 | struct tegra_vgpu_cmd_msg msg; | ||
632 | struct tegra_vgpu_channel_runlist_interleave_params *p = | ||
633 | &msg.params.channel_interleave; | ||
634 | struct channel_gk20a *ch; | ||
635 | int err; | ||
636 | |||
637 | gk20a_dbg_fn(""); | ||
638 | |||
639 | if (is_tsg) | ||
640 | return vgpu_fifo_tsg_set_runlist_interleave(g, id, | ||
641 | runlist_id, new_level); | ||
642 | |||
643 | ch = &g->fifo.channel[id]; | ||
644 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE; | ||
645 | msg.handle = vgpu_get_handle(ch->g); | ||
646 | p->handle = ch->virt_ctx; | ||
647 | p->level = new_level; | ||
648 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
649 | WARN_ON(err || msg.ret); | ||
650 | return err ? err : msg.ret; | ||
651 | } | ||
652 | |||
653 | int vgpu_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice) | ||
654 | { | ||
655 | struct tegra_vgpu_cmd_msg msg; | ||
656 | struct tegra_vgpu_channel_timeslice_params *p = | ||
657 | &msg.params.channel_timeslice; | ||
658 | int err; | ||
659 | |||
660 | gk20a_dbg_fn(""); | ||
661 | |||
662 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_TIMESLICE; | ||
663 | msg.handle = vgpu_get_handle(ch->g); | ||
664 | p->handle = ch->virt_ctx; | ||
665 | p->timeslice_us = timeslice; | ||
666 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
667 | err = err ? err : msg.ret; | ||
668 | WARN_ON(err); | ||
669 | if (!err) | ||
670 | ch->timeslice_us = p->timeslice_us; | ||
671 | return err; | ||
672 | } | ||
673 | |||
674 | int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch, | ||
675 | u32 err_code, bool verbose) | ||
676 | { | ||
677 | struct tsg_gk20a *tsg = NULL; | ||
678 | struct channel_gk20a *ch_tsg = NULL; | ||
679 | struct gk20a *g = ch->g; | ||
680 | struct tegra_vgpu_cmd_msg msg = {0}; | ||
681 | struct tegra_vgpu_channel_config_params *p = | ||
682 | &msg.params.channel_config; | ||
683 | int err; | ||
684 | |||
685 | gk20a_dbg_fn(""); | ||
686 | |||
687 | if (gk20a_is_channel_marked_as_tsg(ch)) { | ||
688 | tsg = &g->fifo.tsg[ch->tsgid]; | ||
689 | |||
690 | nvgpu_rwsem_down_read(&tsg->ch_list_lock); | ||
691 | |||
692 | list_for_each_entry(ch_tsg, &tsg->ch_list, ch_entry) { | ||
693 | if (gk20a_channel_get(ch_tsg)) { | ||
694 | gk20a_set_error_notifier(ch_tsg, err_code); | ||
695 | ch_tsg->has_timedout = true; | ||
696 | gk20a_channel_put(ch_tsg); | ||
697 | } | ||
698 | } | ||
699 | |||
700 | nvgpu_rwsem_up_read(&tsg->ch_list_lock); | ||
701 | } else { | ||
702 | gk20a_set_error_notifier(ch, err_code); | ||
703 | ch->has_timedout = true; | ||
704 | } | ||
705 | |||
706 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_FORCE_RESET; | ||
707 | msg.handle = vgpu_get_handle(ch->g); | ||
708 | p->handle = ch->virt_ctx; | ||
709 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
710 | WARN_ON(err || msg.ret); | ||
711 | if (!err) | ||
712 | gk20a_channel_abort(ch, false); | ||
713 | return err ? err : msg.ret; | ||
714 | } | ||
715 | |||
716 | static void vgpu_fifo_set_ctx_mmu_error_ch(struct gk20a *g, | ||
717 | struct channel_gk20a *ch) | ||
718 | { | ||
719 | nvgpu_mutex_acquire(&ch->error_notifier_mutex); | ||
720 | if (ch->error_notifier_ref) { | ||
721 | if (ch->error_notifier->status == 0xffff) { | ||
722 | /* If error code is already set, this mmu fault | ||
723 | * was triggered as part of recovery from other | ||
724 | * error condition. | ||
725 | * Don't overwrite error flag. */ | ||
726 | } else { | ||
727 | gk20a_set_error_notifier_locked(ch, | ||
728 | NVGPU_CHANNEL_FIFO_ERROR_MMU_ERR_FLT); | ||
729 | } | ||
730 | } | ||
731 | nvgpu_mutex_release(&ch->error_notifier_mutex); | ||
732 | |||
733 | /* mark channel as faulted */ | ||
734 | ch->has_timedout = true; | ||
735 | nvgpu_smp_wmb(); | ||
736 | /* unblock pending waits */ | ||
737 | nvgpu_cond_broadcast_interruptible(&ch->semaphore_wq); | ||
738 | nvgpu_cond_broadcast_interruptible(&ch->notifier_wq); | ||
739 | } | ||
740 | |||
741 | static void vgpu_fifo_set_ctx_mmu_error_ch_tsg(struct gk20a *g, | ||
742 | struct channel_gk20a *ch) | ||
743 | { | ||
744 | struct tsg_gk20a *tsg = NULL; | ||
745 | struct channel_gk20a *ch_tsg = NULL; | ||
746 | |||
747 | if (gk20a_is_channel_marked_as_tsg(ch)) { | ||
748 | tsg = &g->fifo.tsg[ch->tsgid]; | ||
749 | |||
750 | nvgpu_rwsem_down_read(&tsg->ch_list_lock); | ||
751 | |||
752 | list_for_each_entry(ch_tsg, &tsg->ch_list, ch_entry) { | ||
753 | if (gk20a_channel_get(ch_tsg)) { | ||
754 | vgpu_fifo_set_ctx_mmu_error_ch(g, ch_tsg); | ||
755 | gk20a_channel_put(ch_tsg); | ||
756 | } | ||
757 | } | ||
758 | |||
759 | nvgpu_rwsem_up_read(&tsg->ch_list_lock); | ||
760 | } else { | ||
761 | vgpu_fifo_set_ctx_mmu_error_ch(g, ch); | ||
762 | } | ||
763 | } | ||
764 | |||
765 | int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info) | ||
766 | { | ||
767 | struct fifo_gk20a *f = &g->fifo; | ||
768 | struct channel_gk20a *ch = gk20a_channel_get(&f->channel[info->chid]); | ||
769 | |||
770 | gk20a_dbg_fn(""); | ||
771 | if (!ch) | ||
772 | return 0; | ||
773 | |||
774 | nvgpu_err(g, "fifo intr (%d) on ch %u", | ||
775 | info->type, info->chid); | ||
776 | |||
777 | trace_gk20a_channel_reset(ch->chid, ch->tsgid); | ||
778 | |||
779 | switch (info->type) { | ||
780 | case TEGRA_VGPU_FIFO_INTR_PBDMA: | ||
781 | gk20a_set_error_notifier(ch, NVGPU_CHANNEL_PBDMA_ERROR); | ||
782 | break; | ||
783 | case TEGRA_VGPU_FIFO_INTR_CTXSW_TIMEOUT: | ||
784 | gk20a_set_error_notifier(ch, | ||
785 | NVGPU_CHANNEL_FIFO_ERROR_IDLE_TIMEOUT); | ||
786 | break; | ||
787 | case TEGRA_VGPU_FIFO_INTR_MMU_FAULT: | ||
788 | vgpu_fifo_set_ctx_mmu_error_ch_tsg(g, ch); | ||
789 | gk20a_channel_abort(ch, false); | ||
790 | break; | ||
791 | default: | ||
792 | WARN_ON(1); | ||
793 | break; | ||
794 | } | ||
795 | |||
796 | gk20a_channel_put(ch); | ||
797 | return 0; | ||
798 | } | ||
799 | |||
800 | int vgpu_fifo_nonstall_isr(struct gk20a *g, | ||
801 | struct tegra_vgpu_fifo_nonstall_intr_info *info) | ||
802 | { | ||
803 | gk20a_dbg_fn(""); | ||
804 | |||
805 | switch (info->type) { | ||
806 | case TEGRA_VGPU_FIFO_NONSTALL_INTR_CHANNEL: | ||
807 | gk20a_channel_semaphore_wakeup(g, false); | ||
808 | break; | ||
809 | default: | ||
810 | WARN_ON(1); | ||
811 | break; | ||
812 | } | ||
813 | |||
814 | return 0; | ||
815 | } | ||
816 | |||
817 | u32 vgpu_fifo_default_timeslice_us(struct gk20a *g) | ||
818 | { | ||
819 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | ||
820 | |||
821 | return priv->constants.default_timeslice_us; | ||
822 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.h b/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.h new file mode 100644 index 00000000..62a3a256 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.h | |||
@@ -0,0 +1,59 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #ifndef _FIFO_VGPU_H_ | ||
18 | #define _FIFO_VGPU_H_ | ||
19 | |||
20 | #include <nvgpu/types.h> | ||
21 | |||
22 | struct gk20a; | ||
23 | struct channel_gk20a; | ||
24 | struct fifo_gk20a; | ||
25 | struct tsg_gk20a; | ||
26 | |||
27 | int vgpu_init_fifo_setup_hw(struct gk20a *g); | ||
28 | void vgpu_channel_bind(struct channel_gk20a *ch); | ||
29 | void vgpu_channel_unbind(struct channel_gk20a *ch); | ||
30 | int vgpu_channel_alloc_inst(struct gk20a *g, struct channel_gk20a *ch); | ||
31 | void vgpu_channel_free_inst(struct gk20a *g, struct channel_gk20a *ch); | ||
32 | void vgpu_channel_enable(struct channel_gk20a *ch); | ||
33 | void vgpu_channel_disable(struct channel_gk20a *ch); | ||
34 | int vgpu_channel_setup_ramfc(struct channel_gk20a *ch, u64 gpfifo_base, | ||
35 | u32 gpfifo_entries, | ||
36 | unsigned long acquire_timeout, u32 flags); | ||
37 | int vgpu_fifo_init_engine_info(struct fifo_gk20a *f); | ||
38 | int vgpu_fifo_preempt_channel(struct gk20a *g, u32 chid); | ||
39 | int vgpu_fifo_preempt_tsg(struct gk20a *g, u32 tsgid); | ||
40 | int vgpu_fifo_update_runlist(struct gk20a *g, u32 runlist_id, | ||
41 | u32 chid, bool add, bool wait_for_finish); | ||
42 | int vgpu_fifo_wait_engine_idle(struct gk20a *g); | ||
43 | int vgpu_fifo_set_runlist_interleave(struct gk20a *g, | ||
44 | u32 id, | ||
45 | bool is_tsg, | ||
46 | u32 runlist_id, | ||
47 | u32 new_level); | ||
48 | int vgpu_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice); | ||
49 | int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch, | ||
50 | u32 err_code, bool verbose); | ||
51 | u32 vgpu_fifo_default_timeslice_us(struct gk20a *g); | ||
52 | int vgpu_tsg_open(struct tsg_gk20a *tsg); | ||
53 | int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg, | ||
54 | struct channel_gk20a *ch); | ||
55 | int vgpu_tsg_unbind_channel(struct channel_gk20a *ch); | ||
56 | int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice); | ||
57 | int vgpu_enable_tsg(struct tsg_gk20a *tsg); | ||
58 | |||
59 | #endif | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.c new file mode 100644 index 00000000..260ce080 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.c | |||
@@ -0,0 +1,63 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include <nvgpu/enabled.h> | ||
18 | |||
19 | #include "gk20a/gk20a.h" | ||
20 | #include "gk20a/css_gr_gk20a.h" | ||
21 | #include "common/linux/vgpu/css_vgpu.h" | ||
22 | #include "vgpu_gr_gm20b.h" | ||
23 | |||
24 | void vgpu_gr_gm20b_init_cyclestats(struct gk20a *g) | ||
25 | { | ||
26 | #if defined(CONFIG_GK20A_CYCLE_STATS) | ||
27 | bool snapshots_supported = true; | ||
28 | |||
29 | /* cyclestats not supported on vgpu */ | ||
30 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_CYCLE_STATS, false); | ||
31 | |||
32 | g->gr.max_css_buffer_size = vgpu_css_get_buffer_size(g); | ||
33 | |||
34 | /* snapshots not supported if the buffer size is 0 */ | ||
35 | if (g->gr.max_css_buffer_size == 0) | ||
36 | snapshots_supported = false; | ||
37 | |||
38 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_CYCLE_STATS_SNAPSHOT, | ||
39 | snapshots_supported); | ||
40 | #endif | ||
41 | } | ||
42 | |||
43 | int vgpu_gm20b_init_fs_state(struct gk20a *g) | ||
44 | { | ||
45 | struct gr_gk20a *gr = &g->gr; | ||
46 | u32 tpc_index, gpc_index; | ||
47 | u32 sm_id = 0; | ||
48 | |||
49 | gk20a_dbg_fn(""); | ||
50 | |||
51 | for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) { | ||
52 | for (tpc_index = 0; tpc_index < gr->gpc_tpc_count[gpc_index]; | ||
53 | tpc_index++) { | ||
54 | g->gr.sm_to_cluster[sm_id].tpc_index = tpc_index; | ||
55 | g->gr.sm_to_cluster[sm_id].gpc_index = gpc_index; | ||
56 | |||
57 | sm_id++; | ||
58 | } | ||
59 | } | ||
60 | |||
61 | gr->no_of_sm = sm_id; | ||
62 | return 0; | ||
63 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.h b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.h new file mode 100644 index 00000000..f17de450 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_gr_gm20b.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #ifndef __VGPU_GR_GM20B_H__ | ||
18 | #define __VGPU_GR_GM20B_H__ | ||
19 | |||
20 | #include "gk20a/gk20a.h" | ||
21 | |||
22 | void vgpu_gr_gm20b_init_cyclestats(struct gk20a *g); | ||
23 | int vgpu_gm20b_init_fs_state(struct gk20a *g); | ||
24 | |||
25 | #endif | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c new file mode 100644 index 00000000..1a2d378a --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c | |||
@@ -0,0 +1,582 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include "gm20b/hal_gm20b.h" | ||
18 | #include "common/linux/vgpu/vgpu.h" | ||
19 | #include "common/linux/vgpu/fifo_vgpu.h" | ||
20 | #include "common/linux/vgpu/gr_vgpu.h" | ||
21 | #include "common/linux/vgpu/ltc_vgpu.h" | ||
22 | #include "common/linux/vgpu/mm_vgpu.h" | ||
23 | #include "common/linux/vgpu/dbg_vgpu.h" | ||
24 | #include "common/linux/vgpu/fecs_trace_vgpu.h" | ||
25 | #include "common/linux/vgpu/css_vgpu.h" | ||
26 | #include "vgpu_gr_gm20b.h" | ||
27 | |||
28 | #include "gk20a/bus_gk20a.h" | ||
29 | #include "gk20a/flcn_gk20a.h" | ||
30 | #include "gk20a/mc_gk20a.h" | ||
31 | #include "gk20a/fb_gk20a.h" | ||
32 | |||
33 | #include "gm20b/gr_gm20b.h" | ||
34 | #include "gm20b/fifo_gm20b.h" | ||
35 | #include "gm20b/acr_gm20b.h" | ||
36 | #include "gm20b/pmu_gm20b.h" | ||
37 | #include "gm20b/fb_gm20b.h" | ||
38 | #include "gm20b/bus_gm20b.h" | ||
39 | #include "gm20b/regops_gm20b.h" | ||
40 | #include "gm20b/clk_gm20b.h" | ||
41 | #include "gm20b/therm_gm20b.h" | ||
42 | #include "gm20b/mm_gm20b.h" | ||
43 | #include "gm20b/gr_ctx_gm20b.h" | ||
44 | #include "gm20b/gm20b_gating_reglist.h" | ||
45 | #include "gm20b/ltc_gm20b.h" | ||
46 | |||
47 | #include <nvgpu/enabled.h> | ||
48 | |||
49 | #include <nvgpu/hw/gm20b/hw_fuse_gm20b.h> | ||
50 | #include <nvgpu/hw/gm20b/hw_pwr_gm20b.h> | ||
51 | #include <nvgpu/hw/gm20b/hw_fifo_gm20b.h> | ||
52 | #include <nvgpu/hw/gm20b/hw_ram_gm20b.h> | ||
53 | |||
54 | static const struct gpu_ops vgpu_gm20b_ops = { | ||
55 | .ltc = { | ||
56 | .determine_L2_size_bytes = vgpu_determine_L2_size_bytes, | ||
57 | .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, | ||
58 | .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, | ||
59 | .init_cbc = gm20b_ltc_init_cbc, | ||
60 | .init_fs_state = vgpu_ltc_init_fs_state, | ||
61 | .init_comptags = vgpu_ltc_init_comptags, | ||
62 | .cbc_ctrl = NULL, | ||
63 | .isr = gm20b_ltc_isr, | ||
64 | .cbc_fix_config = gm20b_ltc_cbc_fix_config, | ||
65 | .flush = gm20b_flush_ltc, | ||
66 | .set_enabled = gm20b_ltc_set_enabled, | ||
67 | }, | ||
68 | .ce2 = { | ||
69 | .isr_stall = gk20a_ce2_isr, | ||
70 | .isr_nonstall = gk20a_ce2_nonstall_isr, | ||
71 | .get_num_pce = vgpu_ce_get_num_pce, | ||
72 | }, | ||
73 | .gr = { | ||
74 | .get_patch_slots = gr_gk20a_get_patch_slots, | ||
75 | .init_gpc_mmu = gr_gm20b_init_gpc_mmu, | ||
76 | .bundle_cb_defaults = gr_gm20b_bundle_cb_defaults, | ||
77 | .cb_size_default = gr_gm20b_cb_size_default, | ||
78 | .calc_global_ctx_buffer_size = | ||
79 | gr_gm20b_calc_global_ctx_buffer_size, | ||
80 | .commit_global_attrib_cb = gr_gm20b_commit_global_attrib_cb, | ||
81 | .commit_global_bundle_cb = gr_gm20b_commit_global_bundle_cb, | ||
82 | .commit_global_cb_manager = gr_gm20b_commit_global_cb_manager, | ||
83 | .commit_global_pagepool = gr_gm20b_commit_global_pagepool, | ||
84 | .handle_sw_method = gr_gm20b_handle_sw_method, | ||
85 | .set_alpha_circular_buffer_size = | ||
86 | gr_gm20b_set_alpha_circular_buffer_size, | ||
87 | .set_circular_buffer_size = gr_gm20b_set_circular_buffer_size, | ||
88 | .enable_hww_exceptions = gr_gk20a_enable_hww_exceptions, | ||
89 | .is_valid_class = gr_gm20b_is_valid_class, | ||
90 | .is_valid_gfx_class = gr_gm20b_is_valid_gfx_class, | ||
91 | .is_valid_compute_class = gr_gm20b_is_valid_compute_class, | ||
92 | .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs, | ||
93 | .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs, | ||
94 | .init_fs_state = vgpu_gm20b_init_fs_state, | ||
95 | .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask, | ||
96 | .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, | ||
97 | .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode, | ||
98 | .set_gpc_tpc_mask = gr_gm20b_set_gpc_tpc_mask, | ||
99 | .get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask, | ||
100 | .free_channel_ctx = vgpu_gr_free_channel_ctx, | ||
101 | .alloc_obj_ctx = vgpu_gr_alloc_obj_ctx, | ||
102 | .bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull, | ||
103 | .get_zcull_info = vgpu_gr_get_zcull_info, | ||
104 | .is_tpc_addr = gr_gm20b_is_tpc_addr, | ||
105 | .get_tpc_num = gr_gm20b_get_tpc_num, | ||
106 | .detect_sm_arch = vgpu_gr_detect_sm_arch, | ||
107 | .add_zbc_color = gr_gk20a_add_zbc_color, | ||
108 | .add_zbc_depth = gr_gk20a_add_zbc_depth, | ||
109 | .zbc_set_table = vgpu_gr_add_zbc, | ||
110 | .zbc_query_table = vgpu_gr_query_zbc, | ||
111 | .pmu_save_zbc = gk20a_pmu_save_zbc, | ||
112 | .add_zbc = gr_gk20a_add_zbc, | ||
113 | .pagepool_default_size = gr_gm20b_pagepool_default_size, | ||
114 | .init_ctx_state = vgpu_gr_init_ctx_state, | ||
115 | .alloc_gr_ctx = vgpu_gr_alloc_gr_ctx, | ||
116 | .free_gr_ctx = vgpu_gr_free_gr_ctx, | ||
117 | .update_ctxsw_preemption_mode = | ||
118 | gr_gm20b_update_ctxsw_preemption_mode, | ||
119 | .dump_gr_regs = NULL, | ||
120 | .update_pc_sampling = gr_gm20b_update_pc_sampling, | ||
121 | .get_fbp_en_mask = vgpu_gr_get_fbp_en_mask, | ||
122 | .get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp, | ||
123 | .get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc, | ||
124 | .get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask, | ||
125 | .get_max_fbps_count = vgpu_gr_get_max_fbps_count, | ||
126 | .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info, | ||
127 | .wait_empty = gr_gk20a_wait_idle, | ||
128 | .init_cyclestats = vgpu_gr_gm20b_init_cyclestats, | ||
129 | .set_sm_debug_mode = vgpu_gr_set_sm_debug_mode, | ||
130 | .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs, | ||
131 | .bpt_reg_info = gr_gm20b_bpt_reg_info, | ||
132 | .get_access_map = gr_gm20b_get_access_map, | ||
133 | .handle_fecs_error = gk20a_gr_handle_fecs_error, | ||
134 | .handle_sm_exception = gr_gk20a_handle_sm_exception, | ||
135 | .handle_tex_exception = gr_gk20a_handle_tex_exception, | ||
136 | .enable_gpc_exceptions = gk20a_gr_enable_gpc_exceptions, | ||
137 | .enable_exceptions = gk20a_gr_enable_exceptions, | ||
138 | .get_lrf_tex_ltc_dram_override = NULL, | ||
139 | .update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode, | ||
140 | .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode, | ||
141 | .record_sm_error_state = gm20b_gr_record_sm_error_state, | ||
142 | .update_sm_error_state = gm20b_gr_update_sm_error_state, | ||
143 | .clear_sm_error_state = vgpu_gr_clear_sm_error_state, | ||
144 | .suspend_contexts = vgpu_gr_suspend_contexts, | ||
145 | .resume_contexts = vgpu_gr_resume_contexts, | ||
146 | .get_preemption_mode_flags = gr_gm20b_get_preemption_mode_flags, | ||
147 | .init_sm_id_table = gr_gk20a_init_sm_id_table, | ||
148 | .load_smid_config = gr_gm20b_load_smid_config, | ||
149 | .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering, | ||
150 | .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, | ||
151 | .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr, | ||
152 | .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr, | ||
153 | .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr, | ||
154 | .setup_rop_mapping = gr_gk20a_setup_rop_mapping, | ||
155 | .program_zcull_mapping = gr_gk20a_program_zcull_mapping, | ||
156 | .commit_global_timeslice = gr_gk20a_commit_global_timeslice, | ||
157 | .commit_inst = vgpu_gr_commit_inst, | ||
158 | .write_zcull_ptr = gr_gk20a_write_zcull_ptr, | ||
159 | .write_pm_ptr = gr_gk20a_write_pm_ptr, | ||
160 | .init_elcg_mode = gr_gk20a_init_elcg_mode, | ||
161 | .load_tpc_mask = gr_gm20b_load_tpc_mask, | ||
162 | .inval_icache = gr_gk20a_inval_icache, | ||
163 | .trigger_suspend = gr_gk20a_trigger_suspend, | ||
164 | .wait_for_pause = gr_gk20a_wait_for_pause, | ||
165 | .resume_from_pause = gr_gk20a_resume_from_pause, | ||
166 | .clear_sm_errors = gr_gk20a_clear_sm_errors, | ||
167 | .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions, | ||
168 | .get_esr_sm_sel = gk20a_gr_get_esr_sm_sel, | ||
169 | .sm_debugger_attached = gk20a_gr_sm_debugger_attached, | ||
170 | .suspend_single_sm = gk20a_gr_suspend_single_sm, | ||
171 | .suspend_all_sms = gk20a_gr_suspend_all_sms, | ||
172 | .resume_single_sm = gk20a_gr_resume_single_sm, | ||
173 | .resume_all_sms = gk20a_gr_resume_all_sms, | ||
174 | .get_sm_hww_warp_esr = gk20a_gr_get_sm_hww_warp_esr, | ||
175 | .get_sm_hww_global_esr = gk20a_gr_get_sm_hww_global_esr, | ||
176 | .get_sm_no_lock_down_hww_global_esr_mask = | ||
177 | gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask, | ||
178 | .lock_down_sm = gk20a_gr_lock_down_sm, | ||
179 | .wait_for_sm_lock_down = gk20a_gr_wait_for_sm_lock_down, | ||
180 | .clear_sm_hww = gm20b_gr_clear_sm_hww, | ||
181 | .init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf, | ||
182 | .get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs, | ||
183 | .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce, | ||
184 | .init_ctxsw_hdr_data = gk20a_gr_init_ctxsw_hdr_data, | ||
185 | .set_boosted_ctx = NULL, | ||
186 | .update_boosted_ctx = NULL, | ||
187 | }, | ||
188 | .fb = { | ||
189 | .reset = fb_gk20a_reset, | ||
190 | .init_hw = gk20a_fb_init_hw, | ||
191 | .init_fs_state = fb_gm20b_init_fs_state, | ||
192 | .set_mmu_page_size = gm20b_fb_set_mmu_page_size, | ||
193 | .set_use_full_comp_tag_line = | ||
194 | gm20b_fb_set_use_full_comp_tag_line, | ||
195 | .compression_page_size = gm20b_fb_compression_page_size, | ||
196 | .compressible_page_size = gm20b_fb_compressible_page_size, | ||
197 | .vpr_info_fetch = gm20b_fb_vpr_info_fetch, | ||
198 | .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info, | ||
199 | .read_wpr_info = gm20b_fb_read_wpr_info, | ||
200 | .is_debug_mode_enabled = NULL, | ||
201 | .set_debug_mode = vgpu_mm_mmu_set_debug_mode, | ||
202 | .tlb_invalidate = vgpu_mm_tlb_invalidate, | ||
203 | }, | ||
204 | .clock_gating = { | ||
205 | .slcg_bus_load_gating_prod = | ||
206 | gm20b_slcg_bus_load_gating_prod, | ||
207 | .slcg_ce2_load_gating_prod = | ||
208 | gm20b_slcg_ce2_load_gating_prod, | ||
209 | .slcg_chiplet_load_gating_prod = | ||
210 | gm20b_slcg_chiplet_load_gating_prod, | ||
211 | .slcg_ctxsw_firmware_load_gating_prod = | ||
212 | gm20b_slcg_ctxsw_firmware_load_gating_prod, | ||
213 | .slcg_fb_load_gating_prod = | ||
214 | gm20b_slcg_fb_load_gating_prod, | ||
215 | .slcg_fifo_load_gating_prod = | ||
216 | gm20b_slcg_fifo_load_gating_prod, | ||
217 | .slcg_gr_load_gating_prod = | ||
218 | gr_gm20b_slcg_gr_load_gating_prod, | ||
219 | .slcg_ltc_load_gating_prod = | ||
220 | ltc_gm20b_slcg_ltc_load_gating_prod, | ||
221 | .slcg_perf_load_gating_prod = | ||
222 | gm20b_slcg_perf_load_gating_prod, | ||
223 | .slcg_priring_load_gating_prod = | ||
224 | gm20b_slcg_priring_load_gating_prod, | ||
225 | .slcg_pmu_load_gating_prod = | ||
226 | gm20b_slcg_pmu_load_gating_prod, | ||
227 | .slcg_therm_load_gating_prod = | ||
228 | gm20b_slcg_therm_load_gating_prod, | ||
229 | .slcg_xbar_load_gating_prod = | ||
230 | gm20b_slcg_xbar_load_gating_prod, | ||
231 | .blcg_bus_load_gating_prod = | ||
232 | gm20b_blcg_bus_load_gating_prod, | ||
233 | .blcg_ctxsw_firmware_load_gating_prod = | ||
234 | gm20b_blcg_ctxsw_firmware_load_gating_prod, | ||
235 | .blcg_fb_load_gating_prod = | ||
236 | gm20b_blcg_fb_load_gating_prod, | ||
237 | .blcg_fifo_load_gating_prod = | ||
238 | gm20b_blcg_fifo_load_gating_prod, | ||
239 | .blcg_gr_load_gating_prod = | ||
240 | gm20b_blcg_gr_load_gating_prod, | ||
241 | .blcg_ltc_load_gating_prod = | ||
242 | gm20b_blcg_ltc_load_gating_prod, | ||
243 | .blcg_pwr_csb_load_gating_prod = | ||
244 | gm20b_blcg_pwr_csb_load_gating_prod, | ||
245 | .blcg_xbar_load_gating_prod = | ||
246 | gm20b_blcg_xbar_load_gating_prod, | ||
247 | .blcg_pmu_load_gating_prod = | ||
248 | gm20b_blcg_pmu_load_gating_prod, | ||
249 | .pg_gr_load_gating_prod = | ||
250 | gr_gm20b_pg_gr_load_gating_prod, | ||
251 | }, | ||
252 | .fifo = { | ||
253 | .init_fifo_setup_hw = vgpu_init_fifo_setup_hw, | ||
254 | .bind_channel = vgpu_channel_bind, | ||
255 | .unbind_channel = vgpu_channel_unbind, | ||
256 | .disable_channel = vgpu_channel_disable, | ||
257 | .enable_channel = vgpu_channel_enable, | ||
258 | .alloc_inst = vgpu_channel_alloc_inst, | ||
259 | .free_inst = vgpu_channel_free_inst, | ||
260 | .setup_ramfc = vgpu_channel_setup_ramfc, | ||
261 | .channel_set_timeslice = vgpu_channel_set_timeslice, | ||
262 | .default_timeslice_us = vgpu_fifo_default_timeslice_us, | ||
263 | .setup_userd = gk20a_fifo_setup_userd, | ||
264 | .userd_gp_get = gk20a_fifo_userd_gp_get, | ||
265 | .userd_gp_put = gk20a_fifo_userd_gp_put, | ||
266 | .userd_pb_get = gk20a_fifo_userd_pb_get, | ||
267 | .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, | ||
268 | .preempt_channel = vgpu_fifo_preempt_channel, | ||
269 | .preempt_tsg = vgpu_fifo_preempt_tsg, | ||
270 | .enable_tsg = vgpu_enable_tsg, | ||
271 | .disable_tsg = gk20a_disable_tsg, | ||
272 | .tsg_verify_channel_status = NULL, | ||
273 | .tsg_verify_status_ctx_reload = NULL, | ||
274 | .update_runlist = vgpu_fifo_update_runlist, | ||
275 | .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault, | ||
276 | .get_mmu_fault_info = gk20a_fifo_get_mmu_fault_info, | ||
277 | .wait_engine_idle = vgpu_fifo_wait_engine_idle, | ||
278 | .get_num_fifos = gm20b_fifo_get_num_fifos, | ||
279 | .get_pbdma_signature = gk20a_fifo_get_pbdma_signature, | ||
280 | .set_runlist_interleave = vgpu_fifo_set_runlist_interleave, | ||
281 | .tsg_set_timeslice = vgpu_tsg_set_timeslice, | ||
282 | .tsg_open = vgpu_tsg_open, | ||
283 | .force_reset_ch = vgpu_fifo_force_reset_ch, | ||
284 | .engine_enum_from_type = gk20a_fifo_engine_enum_from_type, | ||
285 | .device_info_data_parse = gm20b_device_info_data_parse, | ||
286 | .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v, | ||
287 | .init_engine_info = vgpu_fifo_init_engine_info, | ||
288 | .runlist_entry_size = ram_rl_entry_size_v, | ||
289 | .get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry, | ||
290 | .get_ch_runlist_entry = gk20a_get_ch_runlist_entry, | ||
291 | .is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc, | ||
292 | .dump_pbdma_status = gk20a_dump_pbdma_status, | ||
293 | .dump_eng_status = gk20a_dump_eng_status, | ||
294 | .dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc, | ||
295 | .intr_0_error_mask = gk20a_fifo_intr_0_error_mask, | ||
296 | .is_preempt_pending = gk20a_fifo_is_preempt_pending, | ||
297 | .init_pbdma_intr_descs = gm20b_fifo_init_pbdma_intr_descs, | ||
298 | .reset_enable_hw = gk20a_init_fifo_reset_enable_hw, | ||
299 | .teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg, | ||
300 | .handle_sched_error = gk20a_fifo_handle_sched_error, | ||
301 | .handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0, | ||
302 | .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1, | ||
303 | .tsg_bind_channel = vgpu_tsg_bind_channel, | ||
304 | .tsg_unbind_channel = vgpu_tsg_unbind_channel, | ||
305 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | ||
306 | .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf, | ||
307 | .free_syncpt_buf = gk20a_fifo_free_syncpt_buf, | ||
308 | .add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd, | ||
309 | .get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size, | ||
310 | .add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd, | ||
311 | .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size, | ||
312 | #endif | ||
313 | }, | ||
314 | .gr_ctx = { | ||
315 | .get_netlist_name = gr_gm20b_get_netlist_name, | ||
316 | .is_fw_defined = gr_gm20b_is_firmware_defined, | ||
317 | }, | ||
318 | .mm = { | ||
319 | .support_sparse = gm20b_mm_support_sparse, | ||
320 | .gmmu_map = vgpu_locked_gmmu_map, | ||
321 | .gmmu_unmap = vgpu_locked_gmmu_unmap, | ||
322 | .vm_bind_channel = vgpu_vm_bind_channel, | ||
323 | .fb_flush = vgpu_mm_fb_flush, | ||
324 | .l2_invalidate = vgpu_mm_l2_invalidate, | ||
325 | .l2_flush = vgpu_mm_l2_flush, | ||
326 | .cbc_clean = gk20a_mm_cbc_clean, | ||
327 | .set_big_page_size = gm20b_mm_set_big_page_size, | ||
328 | .get_big_page_sizes = gm20b_mm_get_big_page_sizes, | ||
329 | .get_default_big_page_size = gm20b_mm_get_default_big_page_size, | ||
330 | .gpu_phys_addr = gm20b_gpu_phys_addr, | ||
331 | .get_iommu_bit = gk20a_mm_get_iommu_bit, | ||
332 | .get_mmu_levels = gk20a_mm_get_mmu_levels, | ||
333 | .init_pdb = gk20a_mm_init_pdb, | ||
334 | .init_mm_setup_hw = NULL, | ||
335 | .is_bar1_supported = gm20b_mm_is_bar1_supported, | ||
336 | .init_inst_block = gk20a_init_inst_block, | ||
337 | .mmu_fault_pending = gk20a_fifo_mmu_fault_pending, | ||
338 | .get_kind_invalid = gm20b_get_kind_invalid, | ||
339 | .get_kind_pitch = gm20b_get_kind_pitch, | ||
340 | }, | ||
341 | .therm = { | ||
342 | .init_therm_setup_hw = gm20b_init_therm_setup_hw, | ||
343 | .elcg_init_idle_filters = gk20a_elcg_init_idle_filters, | ||
344 | }, | ||
345 | .pmu = { | ||
346 | .pmu_setup_elpg = gm20b_pmu_setup_elpg, | ||
347 | .pmu_get_queue_head = pwr_pmu_queue_head_r, | ||
348 | .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v, | ||
349 | .pmu_get_queue_tail = pwr_pmu_queue_tail_r, | ||
350 | .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v, | ||
351 | .pmu_queue_head = gk20a_pmu_queue_head, | ||
352 | .pmu_queue_tail = gk20a_pmu_queue_tail, | ||
353 | .pmu_msgq_tail = gk20a_pmu_msgq_tail, | ||
354 | .pmu_mutex_size = pwr_pmu_mutex__size_1_v, | ||
355 | .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, | ||
356 | .pmu_mutex_release = gk20a_pmu_mutex_release, | ||
357 | .write_dmatrfbase = gm20b_write_dmatrfbase, | ||
358 | .pmu_elpg_statistics = gk20a_pmu_elpg_statistics, | ||
359 | .pmu_pg_init_param = NULL, | ||
360 | .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list, | ||
361 | .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list, | ||
362 | .pmu_is_lpwr_feature_supported = NULL, | ||
363 | .pmu_lpwr_enable_pg = NULL, | ||
364 | .pmu_lpwr_disable_pg = NULL, | ||
365 | .pmu_pg_param_post_init = NULL, | ||
366 | .dump_secure_fuses = pmu_dump_security_fuses_gm20b, | ||
367 | .reset_engine = gk20a_pmu_engine_reset, | ||
368 | .is_engine_in_reset = gk20a_pmu_is_engine_in_reset, | ||
369 | }, | ||
370 | .clk = { | ||
371 | .init_clk_support = gm20b_init_clk_support, | ||
372 | .suspend_clk_support = gm20b_suspend_clk_support, | ||
373 | #ifdef CONFIG_DEBUG_FS | ||
374 | .init_debugfs = gm20b_clk_init_debugfs, | ||
375 | #endif | ||
376 | .get_voltage = gm20b_clk_get_voltage, | ||
377 | .get_gpcclk_clock_counter = gm20b_clk_get_gpcclk_clock_counter, | ||
378 | .pll_reg_write = gm20b_clk_pll_reg_write, | ||
379 | .get_pll_debug_data = gm20b_clk_get_pll_debug_data, | ||
380 | }, | ||
381 | .regops = { | ||
382 | .get_global_whitelist_ranges = | ||
383 | gm20b_get_global_whitelist_ranges, | ||
384 | .get_global_whitelist_ranges_count = | ||
385 | gm20b_get_global_whitelist_ranges_count, | ||
386 | .get_context_whitelist_ranges = | ||
387 | gm20b_get_context_whitelist_ranges, | ||
388 | .get_context_whitelist_ranges_count = | ||
389 | gm20b_get_context_whitelist_ranges_count, | ||
390 | .get_runcontrol_whitelist = gm20b_get_runcontrol_whitelist, | ||
391 | .get_runcontrol_whitelist_count = | ||
392 | gm20b_get_runcontrol_whitelist_count, | ||
393 | .get_runcontrol_whitelist_ranges = | ||
394 | gm20b_get_runcontrol_whitelist_ranges, | ||
395 | .get_runcontrol_whitelist_ranges_count = | ||
396 | gm20b_get_runcontrol_whitelist_ranges_count, | ||
397 | .get_qctl_whitelist = gm20b_get_qctl_whitelist, | ||
398 | .get_qctl_whitelist_count = gm20b_get_qctl_whitelist_count, | ||
399 | .get_qctl_whitelist_ranges = gm20b_get_qctl_whitelist_ranges, | ||
400 | .get_qctl_whitelist_ranges_count = | ||
401 | gm20b_get_qctl_whitelist_ranges_count, | ||
402 | .apply_smpc_war = gm20b_apply_smpc_war, | ||
403 | }, | ||
404 | .mc = { | ||
405 | .intr_enable = mc_gk20a_intr_enable, | ||
406 | .intr_unit_config = mc_gk20a_intr_unit_config, | ||
407 | .isr_stall = mc_gk20a_isr_stall, | ||
408 | .intr_stall = mc_gk20a_intr_stall, | ||
409 | .intr_stall_pause = mc_gk20a_intr_stall_pause, | ||
410 | .intr_stall_resume = mc_gk20a_intr_stall_resume, | ||
411 | .intr_nonstall = mc_gk20a_intr_nonstall, | ||
412 | .intr_nonstall_pause = mc_gk20a_intr_nonstall_pause, | ||
413 | .intr_nonstall_resume = mc_gk20a_intr_nonstall_resume, | ||
414 | .enable = gk20a_mc_enable, | ||
415 | .disable = gk20a_mc_disable, | ||
416 | .reset = gk20a_mc_reset, | ||
417 | .boot_0 = gk20a_mc_boot_0, | ||
418 | .is_intr1_pending = mc_gk20a_is_intr1_pending, | ||
419 | }, | ||
420 | .debug = { | ||
421 | .show_dump = NULL, | ||
422 | }, | ||
423 | .dbg_session_ops = { | ||
424 | .exec_reg_ops = vgpu_exec_regops, | ||
425 | .dbg_set_powergate = vgpu_dbg_set_powergate, | ||
426 | .check_and_set_global_reservation = | ||
427 | vgpu_check_and_set_global_reservation, | ||
428 | .check_and_set_context_reservation = | ||
429 | vgpu_check_and_set_context_reservation, | ||
430 | .release_profiler_reservation = | ||
431 | vgpu_release_profiler_reservation, | ||
432 | .perfbuffer_enable = vgpu_perfbuffer_enable, | ||
433 | .perfbuffer_disable = vgpu_perfbuffer_disable, | ||
434 | }, | ||
435 | .bus = { | ||
436 | .init_hw = gk20a_bus_init_hw, | ||
437 | .isr = gk20a_bus_isr, | ||
438 | .read_ptimer = vgpu_read_ptimer, | ||
439 | .get_timestamps_zipper = vgpu_get_timestamps_zipper, | ||
440 | .bar1_bind = gm20b_bus_bar1_bind, | ||
441 | }, | ||
442 | #if defined(CONFIG_GK20A_CYCLE_STATS) | ||
443 | .css = { | ||
444 | .enable_snapshot = vgpu_css_enable_snapshot_buffer, | ||
445 | .disable_snapshot = vgpu_css_release_snapshot_buffer, | ||
446 | .check_data_available = vgpu_css_flush_snapshots, | ||
447 | .detach_snapshot = vgpu_css_detach, | ||
448 | .set_handled_snapshots = NULL, | ||
449 | .allocate_perfmon_ids = NULL, | ||
450 | .release_perfmon_ids = NULL, | ||
451 | }, | ||
452 | #endif | ||
453 | .falcon = { | ||
454 | .falcon_hal_sw_init = gk20a_falcon_hal_sw_init, | ||
455 | }, | ||
456 | .priv_ring = { | ||
457 | .isr = gk20a_priv_ring_isr, | ||
458 | }, | ||
459 | .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics, | ||
460 | .get_litter_value = gm20b_get_litter_value, | ||
461 | }; | ||
462 | |||
463 | int vgpu_gm20b_init_hal(struct gk20a *g) | ||
464 | { | ||
465 | struct gpu_ops *gops = &g->ops; | ||
466 | u32 val; | ||
467 | |||
468 | gops->ltc = vgpu_gm20b_ops.ltc; | ||
469 | gops->ce2 = vgpu_gm20b_ops.ce2; | ||
470 | gops->gr = vgpu_gm20b_ops.gr; | ||
471 | gops->fb = vgpu_gm20b_ops.fb; | ||
472 | gops->clock_gating = vgpu_gm20b_ops.clock_gating; | ||
473 | gops->fifo = vgpu_gm20b_ops.fifo; | ||
474 | gops->gr_ctx = vgpu_gm20b_ops.gr_ctx; | ||
475 | gops->mm = vgpu_gm20b_ops.mm; | ||
476 | gops->therm = vgpu_gm20b_ops.therm; | ||
477 | gops->pmu = vgpu_gm20b_ops.pmu; | ||
478 | /* | ||
479 | * clk must be assigned member by member | ||
480 | * since some clk ops are assigned during probe prior to HAL init | ||
481 | */ | ||
482 | gops->clk.init_clk_support = vgpu_gm20b_ops.clk.init_clk_support; | ||
483 | gops->clk.suspend_clk_support = vgpu_gm20b_ops.clk.suspend_clk_support; | ||
484 | gops->clk.get_voltage = vgpu_gm20b_ops.clk.get_voltage; | ||
485 | gops->clk.get_gpcclk_clock_counter = | ||
486 | vgpu_gm20b_ops.clk.get_gpcclk_clock_counter; | ||
487 | gops->clk.pll_reg_write = vgpu_gm20b_ops.clk.pll_reg_write; | ||
488 | gops->clk.get_pll_debug_data = vgpu_gm20b_ops.clk.get_pll_debug_data; | ||
489 | |||
490 | gops->regops = vgpu_gm20b_ops.regops; | ||
491 | gops->mc = vgpu_gm20b_ops.mc; | ||
492 | gops->dbg_session_ops = vgpu_gm20b_ops.dbg_session_ops; | ||
493 | gops->debug = vgpu_gm20b_ops.debug; | ||
494 | gops->bus = vgpu_gm20b_ops.bus; | ||
495 | #if defined(CONFIG_GK20A_CYCLE_STATS) | ||
496 | gops->css = vgpu_gm20b_ops.css; | ||
497 | #endif | ||
498 | gops->falcon = vgpu_gm20b_ops.falcon; | ||
499 | |||
500 | gops->priv_ring = vgpu_gm20b_ops.priv_ring; | ||
501 | |||
502 | /* Lone functions */ | ||
503 | gops->chip_init_gpu_characteristics = | ||
504 | vgpu_gm20b_ops.chip_init_gpu_characteristics; | ||
505 | gops->get_litter_value = vgpu_gm20b_ops.get_litter_value; | ||
506 | |||
507 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); | ||
508 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
509 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); | ||
510 | |||
511 | #ifdef CONFIG_TEGRA_ACR | ||
512 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | ||
513 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
514 | } else { | ||
515 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); | ||
516 | if (!val) { | ||
517 | gk20a_dbg_info("priv security is disabled in HW"); | ||
518 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
519 | } else { | ||
520 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
521 | } | ||
522 | } | ||
523 | #else | ||
524 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | ||
525 | gk20a_dbg_info("running ASIM with PRIV security disabled"); | ||
526 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
527 | } else { | ||
528 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); | ||
529 | if (!val) { | ||
530 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
531 | } else { | ||
532 | gk20a_dbg_info("priv security is not supported but enabled"); | ||
533 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
534 | return -EPERM; | ||
535 | } | ||
536 | } | ||
537 | #endif | ||
538 | |||
539 | /* priv security dependent ops */ | ||
540 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { | ||
541 | /* Add in ops from gm20b acr */ | ||
542 | gops->pmu.is_pmu_supported = gm20b_is_pmu_supported; | ||
543 | gops->pmu.prepare_ucode = prepare_ucode_blob; | ||
544 | gops->pmu.pmu_setup_hw_and_bootstrap = gm20b_bootstrap_hs_flcn; | ||
545 | gops->pmu.is_lazy_bootstrap = gm20b_is_lazy_bootstrap; | ||
546 | gops->pmu.is_priv_load = gm20b_is_priv_load; | ||
547 | gops->pmu.get_wpr = gm20b_wpr_info; | ||
548 | gops->pmu.alloc_blob_space = gm20b_alloc_blob_space; | ||
549 | gops->pmu.pmu_populate_loader_cfg = | ||
550 | gm20b_pmu_populate_loader_cfg; | ||
551 | gops->pmu.flcn_populate_bl_dmem_desc = | ||
552 | gm20b_flcn_populate_bl_dmem_desc; | ||
553 | gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt; | ||
554 | gops->pmu.falcon_clear_halt_interrupt_status = | ||
555 | clear_halt_interrupt_status; | ||
556 | gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1; | ||
557 | |||
558 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; | ||
559 | gops->pmu.load_lsfalcon_ucode = gm20b_load_falcon_ucode; | ||
560 | |||
561 | gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode; | ||
562 | } else { | ||
563 | /* Inherit from gk20a */ | ||
564 | gops->pmu.is_pmu_supported = gk20a_is_pmu_supported; | ||
565 | gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob; | ||
566 | gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1; | ||
567 | gops->pmu.pmu_nsbootstrap = pmu_bootstrap; | ||
568 | |||
569 | gops->pmu.load_lsfalcon_ucode = NULL; | ||
570 | gops->pmu.init_wpr_region = NULL; | ||
571 | |||
572 | gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode; | ||
573 | } | ||
574 | |||
575 | __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); | ||
576 | g->pmu_lsf_pmu_wpr_init_done = 0; | ||
577 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; | ||
578 | |||
579 | g->name = "gm20b"; | ||
580 | |||
581 | return 0; | ||
582 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fifo_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fifo_gp10b.c new file mode 100644 index 00000000..cc006f76 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fifo_gp10b.c | |||
@@ -0,0 +1,24 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include "vgpu_fifo_gp10b.h" | ||
18 | |||
19 | void vgpu_gp10b_init_fifo_ops(struct gpu_ops *gops) | ||
20 | { | ||
21 | /* syncpoint protection not supported yet */ | ||
22 | gops->fifo.resetup_ramfc = NULL; | ||
23 | gops->fifo.reschedule_runlist = NULL; | ||
24 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_gr_gp10b.c new file mode 100644 index 00000000..efc9c595 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_gr_gp10b.c | |||
@@ -0,0 +1,332 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include <nvgpu/kmem.h> | ||
18 | #include <nvgpu/dma.h> | ||
19 | #include <nvgpu/bug.h> | ||
20 | |||
21 | #include "common/linux/vgpu/vgpu.h" | ||
22 | #include "common/linux/vgpu/gm20b/vgpu_gr_gm20b.h" | ||
23 | |||
24 | #include "vgpu_gr_gp10b.h" | ||
25 | |||
26 | #include <nvgpu/hw/gp10b/hw_gr_gp10b.h> | ||
27 | |||
28 | void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, | ||
29 | struct gr_ctx_desc *gr_ctx) | ||
30 | { | ||
31 | struct tegra_vgpu_cmd_msg msg = {0}; | ||
32 | struct tegra_vgpu_gr_ctx_params *p = &msg.params.gr_ctx; | ||
33 | int err; | ||
34 | |||
35 | gk20a_dbg_fn(""); | ||
36 | |||
37 | if (!gr_ctx || !gr_ctx->mem.gpu_va) | ||
38 | return; | ||
39 | |||
40 | msg.cmd = TEGRA_VGPU_CMD_GR_CTX_FREE; | ||
41 | msg.handle = vgpu_get_handle(g); | ||
42 | p->gr_ctx_handle = gr_ctx->virt_ctx; | ||
43 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
44 | WARN_ON(err || msg.ret); | ||
45 | |||
46 | __nvgpu_vm_free_va(vm, gr_ctx->mem.gpu_va, gmmu_page_size_kernel); | ||
47 | |||
48 | nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.pagepool_ctxsw_buffer); | ||
49 | nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer); | ||
50 | nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer); | ||
51 | nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer); | ||
52 | |||
53 | nvgpu_kfree(g, gr_ctx); | ||
54 | } | ||
55 | |||
56 | int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, | ||
57 | struct gr_ctx_desc **__gr_ctx, | ||
58 | struct vm_gk20a *vm, | ||
59 | u32 class, | ||
60 | u32 flags) | ||
61 | { | ||
62 | struct gr_ctx_desc *gr_ctx; | ||
63 | u32 graphics_preempt_mode = 0; | ||
64 | u32 compute_preempt_mode = 0; | ||
65 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | ||
66 | int err; | ||
67 | |||
68 | gk20a_dbg_fn(""); | ||
69 | |||
70 | err = vgpu_gr_alloc_gr_ctx(g, __gr_ctx, vm, class, flags); | ||
71 | if (err) | ||
72 | return err; | ||
73 | |||
74 | gr_ctx = *__gr_ctx; | ||
75 | |||
76 | if (flags & NVGPU_OBJ_CTX_FLAGS_SUPPORT_GFXP) | ||
77 | graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; | ||
78 | if (flags & NVGPU_OBJ_CTX_FLAGS_SUPPORT_CILP) | ||
79 | compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP; | ||
80 | |||
81 | if (priv->constants.force_preempt_mode && !graphics_preempt_mode && | ||
82 | !compute_preempt_mode) { | ||
83 | graphics_preempt_mode = g->ops.gr.is_valid_gfx_class(g, class) ? | ||
84 | NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP : 0; | ||
85 | compute_preempt_mode = | ||
86 | g->ops.gr.is_valid_compute_class(g, class) ? | ||
87 | NVGPU_PREEMPTION_MODE_COMPUTE_CTA : 0; | ||
88 | } | ||
89 | |||
90 | if (graphics_preempt_mode || compute_preempt_mode) { | ||
91 | if (g->ops.gr.set_ctxsw_preemption_mode) { | ||
92 | err = g->ops.gr.set_ctxsw_preemption_mode(g, gr_ctx, vm, | ||
93 | class, graphics_preempt_mode, compute_preempt_mode); | ||
94 | if (err) { | ||
95 | nvgpu_err(g, | ||
96 | "set_ctxsw_preemption_mode failed"); | ||
97 | goto fail; | ||
98 | } | ||
99 | } else { | ||
100 | err = -ENOSYS; | ||
101 | goto fail; | ||
102 | } | ||
103 | } | ||
104 | |||
105 | gk20a_dbg_fn("done"); | ||
106 | return err; | ||
107 | |||
108 | fail: | ||
109 | vgpu_gr_gp10b_free_gr_ctx(g, vm, gr_ctx); | ||
110 | return err; | ||
111 | } | ||
112 | |||
113 | int vgpu_gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g, | ||
114 | struct gr_ctx_desc *gr_ctx, | ||
115 | struct vm_gk20a *vm, u32 class, | ||
116 | u32 graphics_preempt_mode, | ||
117 | u32 compute_preempt_mode) | ||
118 | { | ||
119 | struct tegra_vgpu_cmd_msg msg = {}; | ||
120 | struct tegra_vgpu_gr_bind_ctxsw_buffers_params *p = | ||
121 | &msg.params.gr_bind_ctxsw_buffers; | ||
122 | int err = 0; | ||
123 | |||
124 | if (g->ops.gr.is_valid_gfx_class(g, class) && | ||
125 | g->gr.t18x.ctx_vars.force_preemption_gfxp) | ||
126 | graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; | ||
127 | |||
128 | if (g->ops.gr.is_valid_compute_class(g, class) && | ||
129 | g->gr.t18x.ctx_vars.force_preemption_cilp) | ||
130 | compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP; | ||
131 | |||
132 | /* check for invalid combinations */ | ||
133 | if ((graphics_preempt_mode == 0) && (compute_preempt_mode == 0)) | ||
134 | return -EINVAL; | ||
135 | |||
136 | if ((graphics_preempt_mode == NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP) && | ||
137 | (compute_preempt_mode == NVGPU_PREEMPTION_MODE_COMPUTE_CILP)) | ||
138 | return -EINVAL; | ||
139 | |||
140 | /* set preemption modes */ | ||
141 | switch (graphics_preempt_mode) { | ||
142 | case NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP: | ||
143 | { | ||
144 | u32 spill_size = | ||
145 | gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() * | ||
146 | gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(); | ||
147 | u32 pagepool_size = g->ops.gr.pagepool_default_size(g) * | ||
148 | gr_scc_pagepool_total_pages_byte_granularity_v(); | ||
149 | u32 betacb_size = g->gr.attrib_cb_default_size + | ||
150 | (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() - | ||
151 | gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()); | ||
152 | u32 attrib_cb_size = (betacb_size + g->gr.alpha_cb_size) * | ||
153 | gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() * | ||
154 | g->gr.max_tpc_count; | ||
155 | struct nvgpu_mem *desc; | ||
156 | |||
157 | attrib_cb_size = ALIGN(attrib_cb_size, 128); | ||
158 | |||
159 | gk20a_dbg_info("gfxp context preempt size=%d", | ||
160 | g->gr.t18x.ctx_vars.preempt_image_size); | ||
161 | gk20a_dbg_info("gfxp context spill size=%d", spill_size); | ||
162 | gk20a_dbg_info("gfxp context pagepool size=%d", pagepool_size); | ||
163 | gk20a_dbg_info("gfxp context attrib cb size=%d", | ||
164 | attrib_cb_size); | ||
165 | |||
166 | err = gr_gp10b_alloc_buffer(vm, | ||
167 | g->gr.t18x.ctx_vars.preempt_image_size, | ||
168 | &gr_ctx->t18x.preempt_ctxsw_buffer); | ||
169 | if (err) { | ||
170 | err = -ENOMEM; | ||
171 | goto fail; | ||
172 | } | ||
173 | desc = &gr_ctx->t18x.preempt_ctxsw_buffer; | ||
174 | p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->gpu_va; | ||
175 | p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->size; | ||
176 | |||
177 | err = gr_gp10b_alloc_buffer(vm, | ||
178 | spill_size, | ||
179 | &gr_ctx->t18x.spill_ctxsw_buffer); | ||
180 | if (err) { | ||
181 | err = -ENOMEM; | ||
182 | goto fail; | ||
183 | } | ||
184 | desc = &gr_ctx->t18x.spill_ctxsw_buffer; | ||
185 | p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->gpu_va; | ||
186 | p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->size; | ||
187 | |||
188 | err = gr_gp10b_alloc_buffer(vm, | ||
189 | pagepool_size, | ||
190 | &gr_ctx->t18x.pagepool_ctxsw_buffer); | ||
191 | if (err) { | ||
192 | err = -ENOMEM; | ||
193 | goto fail; | ||
194 | } | ||
195 | desc = &gr_ctx->t18x.pagepool_ctxsw_buffer; | ||
196 | p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = | ||
197 | desc->gpu_va; | ||
198 | p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = desc->size; | ||
199 | |||
200 | err = gr_gp10b_alloc_buffer(vm, | ||
201 | attrib_cb_size, | ||
202 | &gr_ctx->t18x.betacb_ctxsw_buffer); | ||
203 | if (err) { | ||
204 | err = -ENOMEM; | ||
205 | goto fail; | ||
206 | } | ||
207 | desc = &gr_ctx->t18x.betacb_ctxsw_buffer; | ||
208 | p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] = | ||
209 | desc->gpu_va; | ||
210 | p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] = desc->size; | ||
211 | |||
212 | gr_ctx->graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; | ||
213 | p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_GFX_GFXP; | ||
214 | break; | ||
215 | } | ||
216 | case NVGPU_PREEMPTION_MODE_GRAPHICS_WFI: | ||
217 | gr_ctx->graphics_preempt_mode = graphics_preempt_mode; | ||
218 | break; | ||
219 | |||
220 | default: | ||
221 | break; | ||
222 | } | ||
223 | |||
224 | if (g->ops.gr.is_valid_compute_class(g, class)) { | ||
225 | switch (compute_preempt_mode) { | ||
226 | case NVGPU_PREEMPTION_MODE_COMPUTE_WFI: | ||
227 | gr_ctx->compute_preempt_mode = | ||
228 | NVGPU_PREEMPTION_MODE_COMPUTE_WFI; | ||
229 | p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_WFI; | ||
230 | break; | ||
231 | case NVGPU_PREEMPTION_MODE_COMPUTE_CTA: | ||
232 | gr_ctx->compute_preempt_mode = | ||
233 | NVGPU_PREEMPTION_MODE_COMPUTE_CTA; | ||
234 | p->mode = | ||
235 | TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CTA; | ||
236 | break; | ||
237 | case NVGPU_PREEMPTION_MODE_COMPUTE_CILP: | ||
238 | gr_ctx->compute_preempt_mode = | ||
239 | NVGPU_PREEMPTION_MODE_COMPUTE_CILP; | ||
240 | p->mode = | ||
241 | TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CILP; | ||
242 | break; | ||
243 | default: | ||
244 | break; | ||
245 | } | ||
246 | } | ||
247 | |||
248 | if (gr_ctx->graphics_preempt_mode || gr_ctx->compute_preempt_mode) { | ||
249 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS; | ||
250 | msg.handle = vgpu_get_handle(g); | ||
251 | p->gr_ctx_handle = gr_ctx->virt_ctx; | ||
252 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
253 | if (err || msg.ret) { | ||
254 | err = -ENOMEM; | ||
255 | goto fail; | ||
256 | } | ||
257 | } | ||
258 | |||
259 | return err; | ||
260 | |||
261 | fail: | ||
262 | nvgpu_err(g, "%s failed %d", __func__, err); | ||
263 | return err; | ||
264 | } | ||
265 | |||
266 | int vgpu_gr_gp10b_set_preemption_mode(struct channel_gk20a *ch, | ||
267 | u32 graphics_preempt_mode, | ||
268 | u32 compute_preempt_mode) | ||
269 | { | ||
270 | struct gr_ctx_desc *gr_ctx = ch->ch_ctx.gr_ctx; | ||
271 | struct gk20a *g = ch->g; | ||
272 | struct tsg_gk20a *tsg; | ||
273 | struct vm_gk20a *vm; | ||
274 | u32 class; | ||
275 | int err; | ||
276 | |||
277 | class = ch->obj_class; | ||
278 | if (!class) | ||
279 | return -EINVAL; | ||
280 | |||
281 | /* skip setting anything if both modes are already set */ | ||
282 | if (graphics_preempt_mode && | ||
283 | (graphics_preempt_mode == gr_ctx->graphics_preempt_mode)) | ||
284 | graphics_preempt_mode = 0; | ||
285 | |||
286 | if (compute_preempt_mode && | ||
287 | (compute_preempt_mode == gr_ctx->compute_preempt_mode)) | ||
288 | compute_preempt_mode = 0; | ||
289 | |||
290 | if (graphics_preempt_mode == 0 && compute_preempt_mode == 0) | ||
291 | return 0; | ||
292 | |||
293 | if (gk20a_is_channel_marked_as_tsg(ch)) { | ||
294 | tsg = &g->fifo.tsg[ch->tsgid]; | ||
295 | vm = tsg->vm; | ||
296 | } else { | ||
297 | vm = ch->vm; | ||
298 | } | ||
299 | |||
300 | if (g->ops.gr.set_ctxsw_preemption_mode) { | ||
301 | err = g->ops.gr.set_ctxsw_preemption_mode(g, gr_ctx, vm, class, | ||
302 | graphics_preempt_mode, | ||
303 | compute_preempt_mode); | ||
304 | if (err) { | ||
305 | nvgpu_err(g, "set_ctxsw_preemption_mode failed"); | ||
306 | return err; | ||
307 | } | ||
308 | } else { | ||
309 | err = -ENOSYS; | ||
310 | } | ||
311 | |||
312 | return err; | ||
313 | } | ||
314 | |||
315 | int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g) | ||
316 | { | ||
317 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | ||
318 | int err; | ||
319 | |||
320 | gk20a_dbg_fn(""); | ||
321 | |||
322 | err = vgpu_gr_init_ctx_state(g); | ||
323 | if (err) | ||
324 | return err; | ||
325 | |||
326 | g->gr.t18x.ctx_vars.preempt_image_size = | ||
327 | priv->constants.preempt_ctx_size; | ||
328 | if (!g->gr.t18x.ctx_vars.preempt_image_size) | ||
329 | return -EINVAL; | ||
330 | |||
331 | return 0; | ||
332 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_gr_gp10b.h b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_gr_gp10b.h new file mode 100644 index 00000000..a11dab7d --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_gr_gp10b.h | |||
@@ -0,0 +1,39 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #ifndef __VGPU_GR_GP10B_H__ | ||
18 | #define __VGPU_GR_GP10B_H__ | ||
19 | |||
20 | #include "gk20a/gk20a.h" | ||
21 | |||
22 | void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, | ||
23 | struct gr_ctx_desc *gr_ctx); | ||
24 | int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, | ||
25 | struct gr_ctx_desc **__gr_ctx, | ||
26 | struct vm_gk20a *vm, | ||
27 | u32 class, | ||
28 | u32 flags); | ||
29 | int vgpu_gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g, | ||
30 | struct gr_ctx_desc *gr_ctx, | ||
31 | struct vm_gk20a *vm, u32 class, | ||
32 | u32 graphics_preempt_mode, | ||
33 | u32 compute_preempt_mode); | ||
34 | int vgpu_gr_gp10b_set_preemption_mode(struct channel_gk20a *ch, | ||
35 | u32 graphics_preempt_mode, | ||
36 | u32 compute_preempt_mode); | ||
37 | int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g); | ||
38 | |||
39 | #endif | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c new file mode 100644 index 00000000..da4ca10c --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -0,0 +1,624 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include "common/linux/vgpu/vgpu.h" | ||
18 | #include "common/linux/vgpu/fifo_vgpu.h" | ||
19 | #include "common/linux/vgpu/gr_vgpu.h" | ||
20 | #include "common/linux/vgpu/ltc_vgpu.h" | ||
21 | #include "common/linux/vgpu/mm_vgpu.h" | ||
22 | #include "common/linux/vgpu/dbg_vgpu.h" | ||
23 | #include "common/linux/vgpu/fecs_trace_vgpu.h" | ||
24 | #include "common/linux/vgpu/css_vgpu.h" | ||
25 | #include "gp10b/gp10b.h" | ||
26 | #include "gp10b/hal_gp10b.h" | ||
27 | #include "common/linux/vgpu/gm20b/vgpu_gr_gm20b.h" | ||
28 | #include "vgpu_gr_gp10b.h" | ||
29 | #include "vgpu_mm_gp10b.h" | ||
30 | |||
31 | #include "gk20a/bus_gk20a.h" | ||
32 | #include "gk20a/pramin_gk20a.h" | ||
33 | #include "gk20a/flcn_gk20a.h" | ||
34 | #include "gk20a/mc_gk20a.h" | ||
35 | #include "gk20a/fb_gk20a.h" | ||
36 | |||
37 | #include "gp10b/mc_gp10b.h" | ||
38 | #include "gp10b/ltc_gp10b.h" | ||
39 | #include "gp10b/mm_gp10b.h" | ||
40 | #include "gp10b/ce_gp10b.h" | ||
41 | #include "gp10b/fb_gp10b.h" | ||
42 | #include "gp10b/pmu_gp10b.h" | ||
43 | #include "gp10b/gr_ctx_gp10b.h" | ||
44 | #include "gp10b/fifo_gp10b.h" | ||
45 | #include "gp10b/gp10b_gating_reglist.h" | ||
46 | #include "gp10b/regops_gp10b.h" | ||
47 | #include "gp10b/therm_gp10b.h" | ||
48 | #include "gp10b/priv_ring_gp10b.h" | ||
49 | |||
50 | #include "gm20b/ltc_gm20b.h" | ||
51 | #include "gm20b/gr_gm20b.h" | ||
52 | #include "gm20b/fifo_gm20b.h" | ||
53 | #include "gm20b/acr_gm20b.h" | ||
54 | #include "gm20b/pmu_gm20b.h" | ||
55 | #include "gm20b/fb_gm20b.h" | ||
56 | #include "gm20b/mm_gm20b.h" | ||
57 | |||
58 | #include <nvgpu/enabled.h> | ||
59 | |||
60 | #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> | ||
61 | #include <nvgpu/hw/gp10b/hw_fifo_gp10b.h> | ||
62 | #include <nvgpu/hw/gp10b/hw_ram_gp10b.h> | ||
63 | #include <nvgpu/hw/gp10b/hw_top_gp10b.h> | ||
64 | #include <nvgpu/hw/gp10b/hw_pram_gp10b.h> | ||
65 | #include <nvgpu/hw/gp10b/hw_pwr_gp10b.h> | ||
66 | |||
67 | static const struct gpu_ops vgpu_gp10b_ops = { | ||
68 | .ltc = { | ||
69 | .determine_L2_size_bytes = vgpu_determine_L2_size_bytes, | ||
70 | .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, | ||
71 | .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, | ||
72 | .init_cbc = gm20b_ltc_init_cbc, | ||
73 | .init_fs_state = vgpu_ltc_init_fs_state, | ||
74 | .init_comptags = vgpu_ltc_init_comptags, | ||
75 | .cbc_ctrl = NULL, | ||
76 | .isr = gp10b_ltc_isr, | ||
77 | .cbc_fix_config = gm20b_ltc_cbc_fix_config, | ||
78 | .flush = gm20b_flush_ltc, | ||
79 | .set_enabled = gp10b_ltc_set_enabled, | ||
80 | }, | ||
81 | .ce2 = { | ||
82 | .isr_stall = gp10b_ce_isr, | ||
83 | .isr_nonstall = gp10b_ce_nonstall_isr, | ||
84 | .get_num_pce = vgpu_ce_get_num_pce, | ||
85 | }, | ||
86 | .gr = { | ||
87 | .get_patch_slots = gr_gk20a_get_patch_slots, | ||
88 | .init_gpc_mmu = gr_gm20b_init_gpc_mmu, | ||
89 | .bundle_cb_defaults = gr_gm20b_bundle_cb_defaults, | ||
90 | .cb_size_default = gr_gp10b_cb_size_default, | ||
91 | .calc_global_ctx_buffer_size = | ||
92 | gr_gp10b_calc_global_ctx_buffer_size, | ||
93 | .commit_global_attrib_cb = gr_gp10b_commit_global_attrib_cb, | ||
94 | .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb, | ||
95 | .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager, | ||
96 | .commit_global_pagepool = gr_gp10b_commit_global_pagepool, | ||
97 | .handle_sw_method = gr_gp10b_handle_sw_method, | ||
98 | .set_alpha_circular_buffer_size = | ||
99 | gr_gp10b_set_alpha_circular_buffer_size, | ||
100 | .set_circular_buffer_size = gr_gp10b_set_circular_buffer_size, | ||
101 | .enable_hww_exceptions = gr_gk20a_enable_hww_exceptions, | ||
102 | .is_valid_class = gr_gp10b_is_valid_class, | ||
103 | .is_valid_gfx_class = gr_gp10b_is_valid_gfx_class, | ||
104 | .is_valid_compute_class = gr_gp10b_is_valid_compute_class, | ||
105 | .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs, | ||
106 | .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs, | ||
107 | .init_fs_state = vgpu_gm20b_init_fs_state, | ||
108 | .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask, | ||
109 | .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, | ||
110 | .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode, | ||
111 | .set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask, | ||
112 | .get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask, | ||
113 | .free_channel_ctx = vgpu_gr_free_channel_ctx, | ||
114 | .alloc_obj_ctx = vgpu_gr_alloc_obj_ctx, | ||
115 | .bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull, | ||
116 | .get_zcull_info = vgpu_gr_get_zcull_info, | ||
117 | .is_tpc_addr = gr_gm20b_is_tpc_addr, | ||
118 | .get_tpc_num = gr_gm20b_get_tpc_num, | ||
119 | .detect_sm_arch = vgpu_gr_detect_sm_arch, | ||
120 | .add_zbc_color = gr_gp10b_add_zbc_color, | ||
121 | .add_zbc_depth = gr_gp10b_add_zbc_depth, | ||
122 | .zbc_set_table = vgpu_gr_add_zbc, | ||
123 | .zbc_query_table = vgpu_gr_query_zbc, | ||
124 | .pmu_save_zbc = gk20a_pmu_save_zbc, | ||
125 | .add_zbc = gr_gk20a_add_zbc, | ||
126 | .pagepool_default_size = gr_gp10b_pagepool_default_size, | ||
127 | .init_ctx_state = vgpu_gr_gp10b_init_ctx_state, | ||
128 | .alloc_gr_ctx = vgpu_gr_gp10b_alloc_gr_ctx, | ||
129 | .free_gr_ctx = vgpu_gr_gp10b_free_gr_ctx, | ||
130 | .update_ctxsw_preemption_mode = | ||
131 | gr_gp10b_update_ctxsw_preemption_mode, | ||
132 | .dump_gr_regs = NULL, | ||
133 | .update_pc_sampling = gr_gm20b_update_pc_sampling, | ||
134 | .get_fbp_en_mask = vgpu_gr_get_fbp_en_mask, | ||
135 | .get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp, | ||
136 | .get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc, | ||
137 | .get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask, | ||
138 | .get_max_fbps_count = vgpu_gr_get_max_fbps_count, | ||
139 | .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info, | ||
140 | .wait_empty = gr_gp10b_wait_empty, | ||
141 | .init_cyclestats = vgpu_gr_gm20b_init_cyclestats, | ||
142 | .set_sm_debug_mode = vgpu_gr_set_sm_debug_mode, | ||
143 | .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs, | ||
144 | .bpt_reg_info = gr_gm20b_bpt_reg_info, | ||
145 | .get_access_map = gr_gp10b_get_access_map, | ||
146 | .handle_fecs_error = gr_gp10b_handle_fecs_error, | ||
147 | .handle_sm_exception = gr_gp10b_handle_sm_exception, | ||
148 | .handle_tex_exception = gr_gp10b_handle_tex_exception, | ||
149 | .enable_gpc_exceptions = gk20a_gr_enable_gpc_exceptions, | ||
150 | .enable_exceptions = gk20a_gr_enable_exceptions, | ||
151 | .get_lrf_tex_ltc_dram_override = get_ecc_override_val, | ||
152 | .update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode, | ||
153 | .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode, | ||
154 | .record_sm_error_state = gm20b_gr_record_sm_error_state, | ||
155 | .update_sm_error_state = gm20b_gr_update_sm_error_state, | ||
156 | .clear_sm_error_state = vgpu_gr_clear_sm_error_state, | ||
157 | .suspend_contexts = vgpu_gr_suspend_contexts, | ||
158 | .resume_contexts = vgpu_gr_resume_contexts, | ||
159 | .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, | ||
160 | .init_sm_id_table = gr_gk20a_init_sm_id_table, | ||
161 | .load_smid_config = gr_gp10b_load_smid_config, | ||
162 | .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering, | ||
163 | .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, | ||
164 | .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr, | ||
165 | .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr, | ||
166 | .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr, | ||
167 | .setup_rop_mapping = gr_gk20a_setup_rop_mapping, | ||
168 | .program_zcull_mapping = gr_gk20a_program_zcull_mapping, | ||
169 | .commit_global_timeslice = gr_gk20a_commit_global_timeslice, | ||
170 | .commit_inst = vgpu_gr_commit_inst, | ||
171 | .write_zcull_ptr = gr_gk20a_write_zcull_ptr, | ||
172 | .write_pm_ptr = gr_gk20a_write_pm_ptr, | ||
173 | .init_elcg_mode = gr_gk20a_init_elcg_mode, | ||
174 | .load_tpc_mask = gr_gm20b_load_tpc_mask, | ||
175 | .inval_icache = gr_gk20a_inval_icache, | ||
176 | .trigger_suspend = gr_gk20a_trigger_suspend, | ||
177 | .wait_for_pause = gr_gk20a_wait_for_pause, | ||
178 | .resume_from_pause = gr_gk20a_resume_from_pause, | ||
179 | .clear_sm_errors = gr_gk20a_clear_sm_errors, | ||
180 | .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions, | ||
181 | .get_esr_sm_sel = gk20a_gr_get_esr_sm_sel, | ||
182 | .sm_debugger_attached = gk20a_gr_sm_debugger_attached, | ||
183 | .suspend_single_sm = gk20a_gr_suspend_single_sm, | ||
184 | .suspend_all_sms = gk20a_gr_suspend_all_sms, | ||
185 | .resume_single_sm = gk20a_gr_resume_single_sm, | ||
186 | .resume_all_sms = gk20a_gr_resume_all_sms, | ||
187 | .get_sm_hww_warp_esr = gp10b_gr_get_sm_hww_warp_esr, | ||
188 | .get_sm_hww_global_esr = gk20a_gr_get_sm_hww_global_esr, | ||
189 | .get_sm_no_lock_down_hww_global_esr_mask = | ||
190 | gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask, | ||
191 | .lock_down_sm = gk20a_gr_lock_down_sm, | ||
192 | .wait_for_sm_lock_down = gk20a_gr_wait_for_sm_lock_down, | ||
193 | .clear_sm_hww = gm20b_gr_clear_sm_hww, | ||
194 | .init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf, | ||
195 | .get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs, | ||
196 | .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce, | ||
197 | .set_boosted_ctx = NULL, | ||
198 | .set_preemption_mode = vgpu_gr_gp10b_set_preemption_mode, | ||
199 | .set_czf_bypass = gr_gp10b_set_czf_bypass, | ||
200 | .init_czf_bypass = gr_gp10b_init_czf_bypass, | ||
201 | .pre_process_sm_exception = gr_gp10b_pre_process_sm_exception, | ||
202 | .set_preemption_buffer_va = gr_gp10b_set_preemption_buffer_va, | ||
203 | .init_preemption_state = gr_gp10b_init_preemption_state, | ||
204 | .update_boosted_ctx = NULL, | ||
205 | .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3, | ||
206 | .create_gr_sysfs = gr_gp10b_create_sysfs, | ||
207 | .set_ctxsw_preemption_mode = | ||
208 | vgpu_gr_gp10b_set_ctxsw_preemption_mode, | ||
209 | .init_ctxsw_hdr_data = gr_gp10b_init_ctxsw_hdr_data, | ||
210 | }, | ||
211 | .fb = { | ||
212 | .reset = fb_gk20a_reset, | ||
213 | .init_hw = gk20a_fb_init_hw, | ||
214 | .init_fs_state = fb_gm20b_init_fs_state, | ||
215 | .set_mmu_page_size = gm20b_fb_set_mmu_page_size, | ||
216 | .set_use_full_comp_tag_line = | ||
217 | gm20b_fb_set_use_full_comp_tag_line, | ||
218 | .compression_page_size = gp10b_fb_compression_page_size, | ||
219 | .compressible_page_size = gp10b_fb_compressible_page_size, | ||
220 | .vpr_info_fetch = gm20b_fb_vpr_info_fetch, | ||
221 | .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info, | ||
222 | .read_wpr_info = gm20b_fb_read_wpr_info, | ||
223 | .is_debug_mode_enabled = NULL, | ||
224 | .set_debug_mode = vgpu_mm_mmu_set_debug_mode, | ||
225 | .tlb_invalidate = vgpu_mm_tlb_invalidate, | ||
226 | }, | ||
227 | .clock_gating = { | ||
228 | .slcg_bus_load_gating_prod = | ||
229 | gp10b_slcg_bus_load_gating_prod, | ||
230 | .slcg_ce2_load_gating_prod = | ||
231 | gp10b_slcg_ce2_load_gating_prod, | ||
232 | .slcg_chiplet_load_gating_prod = | ||
233 | gp10b_slcg_chiplet_load_gating_prod, | ||
234 | .slcg_ctxsw_firmware_load_gating_prod = | ||
235 | gp10b_slcg_ctxsw_firmware_load_gating_prod, | ||
236 | .slcg_fb_load_gating_prod = | ||
237 | gp10b_slcg_fb_load_gating_prod, | ||
238 | .slcg_fifo_load_gating_prod = | ||
239 | gp10b_slcg_fifo_load_gating_prod, | ||
240 | .slcg_gr_load_gating_prod = | ||
241 | gr_gp10b_slcg_gr_load_gating_prod, | ||
242 | .slcg_ltc_load_gating_prod = | ||
243 | ltc_gp10b_slcg_ltc_load_gating_prod, | ||
244 | .slcg_perf_load_gating_prod = | ||
245 | gp10b_slcg_perf_load_gating_prod, | ||
246 | .slcg_priring_load_gating_prod = | ||
247 | gp10b_slcg_priring_load_gating_prod, | ||
248 | .slcg_pmu_load_gating_prod = | ||
249 | gp10b_slcg_pmu_load_gating_prod, | ||
250 | .slcg_therm_load_gating_prod = | ||
251 | gp10b_slcg_therm_load_gating_prod, | ||
252 | .slcg_xbar_load_gating_prod = | ||
253 | gp10b_slcg_xbar_load_gating_prod, | ||
254 | .blcg_bus_load_gating_prod = | ||
255 | gp10b_blcg_bus_load_gating_prod, | ||
256 | .blcg_ce_load_gating_prod = | ||
257 | gp10b_blcg_ce_load_gating_prod, | ||
258 | .blcg_ctxsw_firmware_load_gating_prod = | ||
259 | gp10b_blcg_ctxsw_firmware_load_gating_prod, | ||
260 | .blcg_fb_load_gating_prod = | ||
261 | gp10b_blcg_fb_load_gating_prod, | ||
262 | .blcg_fifo_load_gating_prod = | ||
263 | gp10b_blcg_fifo_load_gating_prod, | ||
264 | .blcg_gr_load_gating_prod = | ||
265 | gp10b_blcg_gr_load_gating_prod, | ||
266 | .blcg_ltc_load_gating_prod = | ||
267 | gp10b_blcg_ltc_load_gating_prod, | ||
268 | .blcg_pwr_csb_load_gating_prod = | ||
269 | gp10b_blcg_pwr_csb_load_gating_prod, | ||
270 | .blcg_pmu_load_gating_prod = | ||
271 | gp10b_blcg_pmu_load_gating_prod, | ||
272 | .blcg_xbar_load_gating_prod = | ||
273 | gp10b_blcg_xbar_load_gating_prod, | ||
274 | .pg_gr_load_gating_prod = | ||
275 | gr_gp10b_pg_gr_load_gating_prod, | ||
276 | }, | ||
277 | .fifo = { | ||
278 | .init_fifo_setup_hw = vgpu_init_fifo_setup_hw, | ||
279 | .bind_channel = vgpu_channel_bind, | ||
280 | .unbind_channel = vgpu_channel_unbind, | ||
281 | .disable_channel = vgpu_channel_disable, | ||
282 | .enable_channel = vgpu_channel_enable, | ||
283 | .alloc_inst = vgpu_channel_alloc_inst, | ||
284 | .free_inst = vgpu_channel_free_inst, | ||
285 | .setup_ramfc = vgpu_channel_setup_ramfc, | ||
286 | .channel_set_timeslice = vgpu_channel_set_timeslice, | ||
287 | .default_timeslice_us = vgpu_fifo_default_timeslice_us, | ||
288 | .setup_userd = gk20a_fifo_setup_userd, | ||
289 | .userd_gp_get = gk20a_fifo_userd_gp_get, | ||
290 | .userd_gp_put = gk20a_fifo_userd_gp_put, | ||
291 | .userd_pb_get = gk20a_fifo_userd_pb_get, | ||
292 | .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, | ||
293 | .preempt_channel = vgpu_fifo_preempt_channel, | ||
294 | .preempt_tsg = vgpu_fifo_preempt_tsg, | ||
295 | .enable_tsg = vgpu_enable_tsg, | ||
296 | .disable_tsg = gk20a_disable_tsg, | ||
297 | .tsg_verify_channel_status = NULL, | ||
298 | .tsg_verify_status_ctx_reload = NULL, | ||
299 | .reschedule_runlist = NULL, | ||
300 | .update_runlist = vgpu_fifo_update_runlist, | ||
301 | .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault, | ||
302 | .get_mmu_fault_info = gp10b_fifo_get_mmu_fault_info, | ||
303 | .wait_engine_idle = vgpu_fifo_wait_engine_idle, | ||
304 | .get_num_fifos = gm20b_fifo_get_num_fifos, | ||
305 | .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, | ||
306 | .set_runlist_interleave = vgpu_fifo_set_runlist_interleave, | ||
307 | .tsg_set_timeslice = vgpu_tsg_set_timeslice, | ||
308 | .tsg_open = vgpu_tsg_open, | ||
309 | .force_reset_ch = vgpu_fifo_force_reset_ch, | ||
310 | .engine_enum_from_type = gp10b_fifo_engine_enum_from_type, | ||
311 | .device_info_data_parse = gp10b_device_info_data_parse, | ||
312 | .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v, | ||
313 | .init_engine_info = vgpu_fifo_init_engine_info, | ||
314 | .runlist_entry_size = ram_rl_entry_size_v, | ||
315 | .get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry, | ||
316 | .get_ch_runlist_entry = gk20a_get_ch_runlist_entry, | ||
317 | .is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc, | ||
318 | .dump_pbdma_status = gk20a_dump_pbdma_status, | ||
319 | .dump_eng_status = gk20a_dump_eng_status, | ||
320 | .dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc, | ||
321 | .intr_0_error_mask = gk20a_fifo_intr_0_error_mask, | ||
322 | .is_preempt_pending = gk20a_fifo_is_preempt_pending, | ||
323 | .init_pbdma_intr_descs = gp10b_fifo_init_pbdma_intr_descs, | ||
324 | .reset_enable_hw = gk20a_init_fifo_reset_enable_hw, | ||
325 | .teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg, | ||
326 | .handle_sched_error = gk20a_fifo_handle_sched_error, | ||
327 | .handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0, | ||
328 | .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1, | ||
329 | .tsg_bind_channel = vgpu_tsg_bind_channel, | ||
330 | .tsg_unbind_channel = vgpu_tsg_unbind_channel, | ||
331 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | ||
332 | .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf, | ||
333 | .free_syncpt_buf = gk20a_fifo_free_syncpt_buf, | ||
334 | .add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd, | ||
335 | .get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size, | ||
336 | .add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd, | ||
337 | .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size, | ||
338 | #endif | ||
339 | .resetup_ramfc = NULL, | ||
340 | .device_info_fault_id = top_device_info_data_fault_id_enum_v, | ||
341 | }, | ||
342 | .gr_ctx = { | ||
343 | .get_netlist_name = gr_gp10b_get_netlist_name, | ||
344 | .is_fw_defined = gr_gp10b_is_firmware_defined, | ||
345 | }, | ||
346 | #ifdef CONFIG_GK20A_CTXSW_TRACE | ||
347 | .fecs_trace = { | ||
348 | .alloc_user_buffer = vgpu_alloc_user_buffer, | ||
349 | .free_user_buffer = vgpu_free_user_buffer, | ||
350 | .mmap_user_buffer = vgpu_mmap_user_buffer, | ||
351 | .init = vgpu_fecs_trace_init, | ||
352 | .deinit = vgpu_fecs_trace_deinit, | ||
353 | .enable = vgpu_fecs_trace_enable, | ||
354 | .disable = vgpu_fecs_trace_disable, | ||
355 | .is_enabled = vgpu_fecs_trace_is_enabled, | ||
356 | .reset = NULL, | ||
357 | .flush = NULL, | ||
358 | .poll = vgpu_fecs_trace_poll, | ||
359 | .bind_channel = NULL, | ||
360 | .unbind_channel = NULL, | ||
361 | .max_entries = vgpu_fecs_trace_max_entries, | ||
362 | .set_filter = vgpu_fecs_trace_set_filter, | ||
363 | }, | ||
364 | #endif /* CONFIG_GK20A_CTXSW_TRACE */ | ||
365 | .mm = { | ||
366 | /* FIXME: add support for sparse mappings */ | ||
367 | .support_sparse = NULL, | ||
368 | .gmmu_map = vgpu_gp10b_locked_gmmu_map, | ||
369 | .gmmu_unmap = vgpu_locked_gmmu_unmap, | ||
370 | .vm_bind_channel = vgpu_vm_bind_channel, | ||
371 | .fb_flush = vgpu_mm_fb_flush, | ||
372 | .l2_invalidate = vgpu_mm_l2_invalidate, | ||
373 | .l2_flush = vgpu_mm_l2_flush, | ||
374 | .cbc_clean = gk20a_mm_cbc_clean, | ||
375 | .set_big_page_size = gm20b_mm_set_big_page_size, | ||
376 | .get_big_page_sizes = gm20b_mm_get_big_page_sizes, | ||
377 | .get_default_big_page_size = gp10b_mm_get_default_big_page_size, | ||
378 | .gpu_phys_addr = gm20b_gpu_phys_addr, | ||
379 | .get_iommu_bit = gk20a_mm_get_iommu_bit, | ||
380 | .get_mmu_levels = gp10b_mm_get_mmu_levels, | ||
381 | .init_pdb = gp10b_mm_init_pdb, | ||
382 | .init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw, | ||
383 | .is_bar1_supported = gm20b_mm_is_bar1_supported, | ||
384 | .init_inst_block = gk20a_init_inst_block, | ||
385 | .mmu_fault_pending = gk20a_fifo_mmu_fault_pending, | ||
386 | .init_bar2_vm = gb10b_init_bar2_vm, | ||
387 | .init_bar2_mm_hw_setup = gb10b_init_bar2_mm_hw_setup, | ||
388 | .remove_bar2_vm = gp10b_remove_bar2_vm, | ||
389 | .get_kind_invalid = gm20b_get_kind_invalid, | ||
390 | .get_kind_pitch = gm20b_get_kind_pitch, | ||
391 | }, | ||
392 | .pramin = { | ||
393 | .enter = gk20a_pramin_enter, | ||
394 | .exit = gk20a_pramin_exit, | ||
395 | .data032_r = pram_data032_r, | ||
396 | }, | ||
397 | .therm = { | ||
398 | .init_therm_setup_hw = gp10b_init_therm_setup_hw, | ||
399 | .elcg_init_idle_filters = gp10b_elcg_init_idle_filters, | ||
400 | }, | ||
401 | .pmu = { | ||
402 | .pmu_setup_elpg = gp10b_pmu_setup_elpg, | ||
403 | .pmu_get_queue_head = pwr_pmu_queue_head_r, | ||
404 | .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v, | ||
405 | .pmu_get_queue_tail = pwr_pmu_queue_tail_r, | ||
406 | .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v, | ||
407 | .pmu_queue_head = gk20a_pmu_queue_head, | ||
408 | .pmu_queue_tail = gk20a_pmu_queue_tail, | ||
409 | .pmu_msgq_tail = gk20a_pmu_msgq_tail, | ||
410 | .pmu_mutex_size = pwr_pmu_mutex__size_1_v, | ||
411 | .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, | ||
412 | .pmu_mutex_release = gk20a_pmu_mutex_release, | ||
413 | .write_dmatrfbase = gp10b_write_dmatrfbase, | ||
414 | .pmu_elpg_statistics = gp10b_pmu_elpg_statistics, | ||
415 | .pmu_pg_init_param = gp10b_pg_gr_init, | ||
416 | .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list, | ||
417 | .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list, | ||
418 | .dump_secure_fuses = pmu_dump_security_fuses_gp10b, | ||
419 | .reset_engine = gk20a_pmu_engine_reset, | ||
420 | .is_engine_in_reset = gk20a_pmu_is_engine_in_reset, | ||
421 | }, | ||
422 | .regops = { | ||
423 | .get_global_whitelist_ranges = | ||
424 | gp10b_get_global_whitelist_ranges, | ||
425 | .get_global_whitelist_ranges_count = | ||
426 | gp10b_get_global_whitelist_ranges_count, | ||
427 | .get_context_whitelist_ranges = | ||
428 | gp10b_get_context_whitelist_ranges, | ||
429 | .get_context_whitelist_ranges_count = | ||
430 | gp10b_get_context_whitelist_ranges_count, | ||
431 | .get_runcontrol_whitelist = gp10b_get_runcontrol_whitelist, | ||
432 | .get_runcontrol_whitelist_count = | ||
433 | gp10b_get_runcontrol_whitelist_count, | ||
434 | .get_runcontrol_whitelist_ranges = | ||
435 | gp10b_get_runcontrol_whitelist_ranges, | ||
436 | .get_runcontrol_whitelist_ranges_count = | ||
437 | gp10b_get_runcontrol_whitelist_ranges_count, | ||
438 | .get_qctl_whitelist = gp10b_get_qctl_whitelist, | ||
439 | .get_qctl_whitelist_count = gp10b_get_qctl_whitelist_count, | ||
440 | .get_qctl_whitelist_ranges = gp10b_get_qctl_whitelist_ranges, | ||
441 | .get_qctl_whitelist_ranges_count = | ||
442 | gp10b_get_qctl_whitelist_ranges_count, | ||
443 | .apply_smpc_war = gp10b_apply_smpc_war, | ||
444 | }, | ||
445 | .mc = { | ||
446 | .intr_enable = mc_gp10b_intr_enable, | ||
447 | .intr_unit_config = mc_gp10b_intr_unit_config, | ||
448 | .isr_stall = mc_gp10b_isr_stall, | ||
449 | .intr_stall = mc_gp10b_intr_stall, | ||
450 | .intr_stall_pause = mc_gp10b_intr_stall_pause, | ||
451 | .intr_stall_resume = mc_gp10b_intr_stall_resume, | ||
452 | .intr_nonstall = mc_gp10b_intr_nonstall, | ||
453 | .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, | ||
454 | .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, | ||
455 | .enable = gk20a_mc_enable, | ||
456 | .disable = gk20a_mc_disable, | ||
457 | .reset = gk20a_mc_reset, | ||
458 | .boot_0 = gk20a_mc_boot_0, | ||
459 | .is_intr1_pending = mc_gp10b_is_intr1_pending, | ||
460 | }, | ||
461 | .debug = { | ||
462 | .show_dump = NULL, | ||
463 | }, | ||
464 | .dbg_session_ops = { | ||
465 | .exec_reg_ops = vgpu_exec_regops, | ||
466 | .dbg_set_powergate = vgpu_dbg_set_powergate, | ||
467 | .check_and_set_global_reservation = | ||
468 | vgpu_check_and_set_global_reservation, | ||
469 | .check_and_set_context_reservation = | ||
470 | vgpu_check_and_set_context_reservation, | ||
471 | .release_profiler_reservation = | ||
472 | vgpu_release_profiler_reservation, | ||
473 | .perfbuffer_enable = vgpu_perfbuffer_enable, | ||
474 | .perfbuffer_disable = vgpu_perfbuffer_disable, | ||
475 | }, | ||
476 | .bus = { | ||
477 | .init_hw = gk20a_bus_init_hw, | ||
478 | .isr = gk20a_bus_isr, | ||
479 | .read_ptimer = vgpu_read_ptimer, | ||
480 | .get_timestamps_zipper = vgpu_get_timestamps_zipper, | ||
481 | .bar1_bind = gk20a_bus_bar1_bind, | ||
482 | }, | ||
483 | #if defined(CONFIG_GK20A_CYCLE_STATS) | ||
484 | .css = { | ||
485 | .enable_snapshot = vgpu_css_enable_snapshot_buffer, | ||
486 | .disable_snapshot = vgpu_css_release_snapshot_buffer, | ||
487 | .check_data_available = vgpu_css_flush_snapshots, | ||
488 | .detach_snapshot = vgpu_css_detach, | ||
489 | .set_handled_snapshots = NULL, | ||
490 | .allocate_perfmon_ids = NULL, | ||
491 | .release_perfmon_ids = NULL, | ||
492 | }, | ||
493 | #endif | ||
494 | .falcon = { | ||
495 | .falcon_hal_sw_init = gk20a_falcon_hal_sw_init, | ||
496 | }, | ||
497 | .priv_ring = { | ||
498 | .isr = gp10b_priv_ring_isr, | ||
499 | }, | ||
500 | .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics, | ||
501 | .get_litter_value = gp10b_get_litter_value, | ||
502 | }; | ||
503 | |||
504 | int vgpu_gp10b_init_hal(struct gk20a *g) | ||
505 | { | ||
506 | struct gpu_ops *gops = &g->ops; | ||
507 | u32 val; | ||
508 | |||
509 | gops->ltc = vgpu_gp10b_ops.ltc; | ||
510 | gops->ce2 = vgpu_gp10b_ops.ce2; | ||
511 | gops->gr = vgpu_gp10b_ops.gr; | ||
512 | gops->fb = vgpu_gp10b_ops.fb; | ||
513 | gops->clock_gating = vgpu_gp10b_ops.clock_gating; | ||
514 | gops->fifo = vgpu_gp10b_ops.fifo; | ||
515 | gops->gr_ctx = vgpu_gp10b_ops.gr_ctx; | ||
516 | gops->fecs_trace = vgpu_gp10b_ops.fecs_trace; | ||
517 | gops->mm = vgpu_gp10b_ops.mm; | ||
518 | gops->pramin = vgpu_gp10b_ops.pramin; | ||
519 | gops->therm = vgpu_gp10b_ops.therm; | ||
520 | gops->pmu = vgpu_gp10b_ops.pmu; | ||
521 | gops->regops = vgpu_gp10b_ops.regops; | ||
522 | gops->mc = vgpu_gp10b_ops.mc; | ||
523 | gops->debug = vgpu_gp10b_ops.debug; | ||
524 | gops->dbg_session_ops = vgpu_gp10b_ops.dbg_session_ops; | ||
525 | gops->bus = vgpu_gp10b_ops.bus; | ||
526 | #if defined(CONFIG_GK20A_CYCLE_STATS) | ||
527 | gops->css = vgpu_gp10b_ops.css; | ||
528 | #endif | ||
529 | gops->falcon = vgpu_gp10b_ops.falcon; | ||
530 | |||
531 | gops->priv_ring = vgpu_gp10b_ops.priv_ring; | ||
532 | |||
533 | /* Lone Functions */ | ||
534 | gops->chip_init_gpu_characteristics = | ||
535 | vgpu_gp10b_ops.chip_init_gpu_characteristics; | ||
536 | gops->get_litter_value = vgpu_gp10b_ops.get_litter_value; | ||
537 | |||
538 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); | ||
539 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); | ||
540 | |||
541 | #ifdef CONFIG_TEGRA_ACR | ||
542 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | ||
543 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
544 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
545 | } else if (g->is_virtual) { | ||
546 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
547 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | ||
548 | } else { | ||
549 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); | ||
550 | if (val) { | ||
551 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
552 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | ||
553 | } else { | ||
554 | gk20a_dbg_info("priv security is disabled in HW"); | ||
555 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
556 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
557 | } | ||
558 | } | ||
559 | #else | ||
560 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | ||
561 | gk20a_dbg_info("running simulator with PRIV security disabled"); | ||
562 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
563 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
564 | } else { | ||
565 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); | ||
566 | if (val) { | ||
567 | gk20a_dbg_info("priv security is not supported but enabled"); | ||
568 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
569 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | ||
570 | return -EPERM; | ||
571 | } else { | ||
572 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
573 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
574 | } | ||
575 | } | ||
576 | #endif | ||
577 | |||
578 | /* priv security dependent ops */ | ||
579 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { | ||
580 | /* Add in ops from gm20b acr */ | ||
581 | gops->pmu.is_pmu_supported = gm20b_is_pmu_supported, | ||
582 | gops->pmu.prepare_ucode = prepare_ucode_blob, | ||
583 | gops->pmu.pmu_setup_hw_and_bootstrap = gm20b_bootstrap_hs_flcn, | ||
584 | gops->pmu.is_lazy_bootstrap = gm20b_is_lazy_bootstrap, | ||
585 | gops->pmu.is_priv_load = gm20b_is_priv_load, | ||
586 | gops->pmu.get_wpr = gm20b_wpr_info, | ||
587 | gops->pmu.alloc_blob_space = gm20b_alloc_blob_space, | ||
588 | gops->pmu.pmu_populate_loader_cfg = | ||
589 | gm20b_pmu_populate_loader_cfg, | ||
590 | gops->pmu.flcn_populate_bl_dmem_desc = | ||
591 | gm20b_flcn_populate_bl_dmem_desc, | ||
592 | gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt, | ||
593 | gops->pmu.falcon_clear_halt_interrupt_status = | ||
594 | clear_halt_interrupt_status, | ||
595 | gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1, | ||
596 | |||
597 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; | ||
598 | gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; | ||
599 | gops->pmu.is_lazy_bootstrap = gp10b_is_lazy_bootstrap; | ||
600 | gops->pmu.is_priv_load = gp10b_is_priv_load; | ||
601 | |||
602 | gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode; | ||
603 | } else { | ||
604 | /* Inherit from gk20a */ | ||
605 | gops->pmu.is_pmu_supported = gk20a_is_pmu_supported, | ||
606 | gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob, | ||
607 | gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1, | ||
608 | gops->pmu.pmu_nsbootstrap = pmu_bootstrap, | ||
609 | |||
610 | gops->pmu.load_lsfalcon_ucode = NULL; | ||
611 | gops->pmu.init_wpr_region = NULL; | ||
612 | gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1; | ||
613 | |||
614 | gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode; | ||
615 | } | ||
616 | |||
617 | __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); | ||
618 | g->pmu_lsf_pmu_wpr_init_done = 0; | ||
619 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; | ||
620 | |||
621 | g->name = "gp10b"; | ||
622 | |||
623 | return 0; | ||
624 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.c new file mode 100644 index 00000000..9eb140a3 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.c | |||
@@ -0,0 +1,197 @@ | |||
1 | /* | ||
2 | * Virtualized GPU Memory Management | ||
3 | * | ||
4 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
17 | */ | ||
18 | |||
19 | #include <uapi/linux/nvgpu.h> | ||
20 | |||
21 | #include "common/linux/vgpu/vgpu.h" | ||
22 | #include "vgpu_mm_gp10b.h" | ||
23 | #include "gk20a/mm_gk20a.h" | ||
24 | |||
25 | #include <nvgpu/bug.h> | ||
26 | |||
27 | int vgpu_gp10b_init_mm_setup_hw(struct gk20a *g) | ||
28 | { | ||
29 | g->mm.bypass_smmu = true; | ||
30 | g->mm.disable_bigpage = true; | ||
31 | return 0; | ||
32 | } | ||
33 | |||
34 | static inline int add_mem_desc(struct tegra_vgpu_mem_desc *mem_desc, | ||
35 | u64 addr, u64 size, size_t *oob_size) | ||
36 | { | ||
37 | if (*oob_size < sizeof(*mem_desc)) | ||
38 | return -ENOMEM; | ||
39 | |||
40 | mem_desc->addr = addr; | ||
41 | mem_desc->length = size; | ||
42 | *oob_size -= sizeof(*mem_desc); | ||
43 | return 0; | ||
44 | } | ||
45 | |||
46 | u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm, | ||
47 | u64 map_offset, | ||
48 | struct nvgpu_sgt *sgt, | ||
49 | u64 buffer_offset, | ||
50 | u64 size, | ||
51 | int pgsz_idx, | ||
52 | u8 kind_v, | ||
53 | u32 ctag_offset, | ||
54 | u32 flags, | ||
55 | int rw_flag, | ||
56 | bool clear_ctags, | ||
57 | bool sparse, | ||
58 | bool priv, | ||
59 | struct vm_gk20a_mapping_batch *batch, | ||
60 | enum nvgpu_aperture aperture) | ||
61 | { | ||
62 | int err = 0; | ||
63 | struct gk20a *g = gk20a_from_vm(vm); | ||
64 | struct tegra_vgpu_cmd_msg msg; | ||
65 | struct tegra_vgpu_as_map_ex_params *p = &msg.params.as_map_ex; | ||
66 | struct tegra_vgpu_mem_desc *mem_desc; | ||
67 | u32 page_size = vm->gmmu_page_sizes[pgsz_idx]; | ||
68 | u64 buffer_size = PAGE_ALIGN(size); | ||
69 | u64 space_to_skip = buffer_offset; | ||
70 | u32 mem_desc_count = 0, i; | ||
71 | void *handle = NULL; | ||
72 | size_t oob_size; | ||
73 | u8 prot; | ||
74 | void *sgl; | ||
75 | |||
76 | gk20a_dbg_fn(""); | ||
77 | |||
78 | /* FIXME: add support for sparse mappings */ | ||
79 | |||
80 | if (WARN_ON(!sgt) || WARN_ON(!g->mm.bypass_smmu)) | ||
81 | return 0; | ||
82 | |||
83 | if (space_to_skip & (page_size - 1)) | ||
84 | return 0; | ||
85 | |||
86 | memset(&msg, 0, sizeof(msg)); | ||
87 | |||
88 | /* Allocate (or validate when map_offset != 0) the virtual address. */ | ||
89 | if (!map_offset) { | ||
90 | map_offset = __nvgpu_vm_alloc_va(vm, size, pgsz_idx); | ||
91 | if (!map_offset) { | ||
92 | nvgpu_err(g, "failed to allocate va space"); | ||
93 | err = -ENOMEM; | ||
94 | goto fail; | ||
95 | } | ||
96 | } | ||
97 | |||
98 | handle = tegra_gr_comm_oob_get_ptr(TEGRA_GR_COMM_CTX_CLIENT, | ||
99 | tegra_gr_comm_get_server_vmid(), | ||
100 | TEGRA_VGPU_QUEUE_CMD, | ||
101 | (void **)&mem_desc, &oob_size); | ||
102 | if (!handle) { | ||
103 | err = -EINVAL; | ||
104 | goto fail; | ||
105 | } | ||
106 | sgl = sgt->sgl; | ||
107 | while (sgl) { | ||
108 | u64 phys_addr; | ||
109 | u64 chunk_length; | ||
110 | |||
111 | /* | ||
112 | * Cut out sgl ents for space_to_skip. | ||
113 | */ | ||
114 | if (space_to_skip && | ||
115 | space_to_skip >= nvgpu_sgt_get_length(sgt, sgl)) { | ||
116 | space_to_skip -= nvgpu_sgt_get_length(sgt, sgl); | ||
117 | sgl = nvgpu_sgt_get_next(sgt, sgl); | ||
118 | continue; | ||
119 | } | ||
120 | |||
121 | phys_addr = nvgpu_sgt_get_phys(sgt, sgl) + space_to_skip; | ||
122 | chunk_length = min(size, | ||
123 | nvgpu_sgt_get_length(sgt, sgl) - space_to_skip); | ||
124 | |||
125 | if (add_mem_desc(&mem_desc[mem_desc_count++], phys_addr, | ||
126 | chunk_length, &oob_size)) { | ||
127 | err = -ENOMEM; | ||
128 | goto fail; | ||
129 | } | ||
130 | |||
131 | space_to_skip = 0; | ||
132 | size -= chunk_length; | ||
133 | sgl = nvgpu_sgt_get_next(sgt, sgl); | ||
134 | |||
135 | if (size == 0) | ||
136 | break; | ||
137 | } | ||
138 | |||
139 | if (rw_flag == gk20a_mem_flag_read_only) | ||
140 | prot = TEGRA_VGPU_MAP_PROT_READ_ONLY; | ||
141 | else if (rw_flag == gk20a_mem_flag_write_only) | ||
142 | prot = TEGRA_VGPU_MAP_PROT_WRITE_ONLY; | ||
143 | else | ||
144 | prot = TEGRA_VGPU_MAP_PROT_NONE; | ||
145 | |||
146 | if (pgsz_idx == gmmu_page_size_kernel) { | ||
147 | if (page_size == vm->gmmu_page_sizes[gmmu_page_size_small]) { | ||
148 | pgsz_idx = gmmu_page_size_small; | ||
149 | } else if (page_size == | ||
150 | vm->gmmu_page_sizes[gmmu_page_size_big]) { | ||
151 | pgsz_idx = gmmu_page_size_big; | ||
152 | } else { | ||
153 | nvgpu_err(g, "invalid kernel page size %d", | ||
154 | page_size); | ||
155 | goto fail; | ||
156 | } | ||
157 | } | ||
158 | |||
159 | msg.cmd = TEGRA_VGPU_CMD_AS_MAP_EX; | ||
160 | msg.handle = vgpu_get_handle(g); | ||
161 | p->handle = vm->handle; | ||
162 | p->gpu_va = map_offset; | ||
163 | p->size = buffer_size; | ||
164 | p->mem_desc_count = mem_desc_count; | ||
165 | p->pgsz_idx = pgsz_idx; | ||
166 | p->iova = 0; | ||
167 | p->kind = kind_v; | ||
168 | p->cacheable = (flags & NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE) ? 1 : 0; | ||
169 | p->prot = prot; | ||
170 | p->ctag_offset = ctag_offset; | ||
171 | p->clear_ctags = clear_ctags; | ||
172 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
173 | if (err || msg.ret) | ||
174 | goto fail; | ||
175 | |||
176 | /* TLB invalidate handled on server side */ | ||
177 | |||
178 | tegra_gr_comm_oob_put_ptr(handle); | ||
179 | return map_offset; | ||
180 | fail: | ||
181 | if (handle) | ||
182 | tegra_gr_comm_oob_put_ptr(handle); | ||
183 | nvgpu_err(g, "Failed: err=%d, msg.ret=%d", err, msg.ret); | ||
184 | nvgpu_err(g, | ||
185 | " Map: %-5s GPU virt %#-12llx +%#-9llx " | ||
186 | "phys offset: %#-4llx; pgsz: %3dkb perm=%-2s | " | ||
187 | "kind=%#02x APT=%-6s", | ||
188 | vm->name, map_offset, buffer_size, buffer_offset, | ||
189 | vm->gmmu_page_sizes[pgsz_idx] >> 10, | ||
190 | nvgpu_gmmu_perm_str(rw_flag), | ||
191 | kind_v, "SYSMEM"); | ||
192 | for (i = 0; i < mem_desc_count; i++) | ||
193 | nvgpu_err(g, " > 0x%010llx + 0x%llx", | ||
194 | mem_desc[i].addr, mem_desc[i].length); | ||
195 | |||
196 | return 0; | ||
197 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.h b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.h new file mode 100644 index 00000000..0a477dd0 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.h | |||
@@ -0,0 +1,39 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #ifndef __VGPU_MM_GP10B_H__ | ||
18 | #define __VGPU_MM_GP10B_H__ | ||
19 | |||
20 | #include "gk20a/gk20a.h" | ||
21 | |||
22 | u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm, | ||
23 | u64 map_offset, | ||
24 | struct nvgpu_sgt *sgt, | ||
25 | u64 buffer_offset, | ||
26 | u64 size, | ||
27 | int pgsz_idx, | ||
28 | u8 kind_v, | ||
29 | u32 ctag_offset, | ||
30 | u32 flags, | ||
31 | int rw_flag, | ||
32 | bool clear_ctags, | ||
33 | bool sparse, | ||
34 | bool priv, | ||
35 | struct vm_gk20a_mapping_batch *batch, | ||
36 | enum nvgpu_aperture aperture); | ||
37 | int vgpu_gp10b_init_mm_setup_hw(struct gk20a *g); | ||
38 | |||
39 | #endif | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.c new file mode 100644 index 00000000..dd2ae306 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.c | |||
@@ -0,0 +1,1214 @@ | |||
1 | /* | ||
2 | * Virtualized GPU Graphics | ||
3 | * | ||
4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
17 | */ | ||
18 | |||
19 | #include <uapi/linux/nvgpu.h> | ||
20 | |||
21 | #include <nvgpu/kmem.h> | ||
22 | #include <nvgpu/bug.h> | ||
23 | |||
24 | #include "vgpu.h" | ||
25 | #include "gr_vgpu.h" | ||
26 | #include "gk20a/dbg_gpu_gk20a.h" | ||
27 | |||
28 | #include <nvgpu/hw/gk20a/hw_gr_gk20a.h> | ||
29 | |||
30 | void vgpu_gr_detect_sm_arch(struct gk20a *g) | ||
31 | { | ||
32 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | ||
33 | |||
34 | gk20a_dbg_fn(""); | ||
35 | |||
36 | g->params.sm_arch_sm_version = | ||
37 | priv->constants.sm_arch_sm_version; | ||
38 | g->params.sm_arch_spa_version = | ||
39 | priv->constants.sm_arch_spa_version; | ||
40 | g->params.sm_arch_warp_count = | ||
41 | priv->constants.sm_arch_warp_count; | ||
42 | } | ||
43 | |||
44 | int vgpu_gr_commit_inst(struct channel_gk20a *c, u64 gpu_va) | ||
45 | { | ||
46 | struct tegra_vgpu_cmd_msg msg; | ||
47 | struct tegra_vgpu_ch_ctx_params *p = &msg.params.ch_ctx; | ||
48 | int err; | ||
49 | |||
50 | gk20a_dbg_fn(""); | ||
51 | |||
52 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_COMMIT_GR_CTX; | ||
53 | msg.handle = vgpu_get_handle(c->g); | ||
54 | p->handle = c->virt_ctx; | ||
55 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
56 | |||
57 | return (err || msg.ret) ? -1 : 0; | ||
58 | } | ||
59 | |||
60 | static int vgpu_gr_commit_global_ctx_buffers(struct gk20a *g, | ||
61 | struct channel_gk20a *c, bool patch) | ||
62 | { | ||
63 | struct tegra_vgpu_cmd_msg msg; | ||
64 | struct tegra_vgpu_ch_ctx_params *p = &msg.params.ch_ctx; | ||
65 | int err; | ||
66 | |||
67 | gk20a_dbg_fn(""); | ||
68 | |||
69 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_COMMIT_GR_GLOBAL_CTX; | ||
70 | msg.handle = vgpu_get_handle(g); | ||
71 | p->handle = c->virt_ctx; | ||
72 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
73 | |||
74 | return (err || msg.ret) ? -1 : 0; | ||
75 | } | ||
76 | |||
77 | /* load saved fresh copy of gloden image into channel gr_ctx */ | ||
78 | static int vgpu_gr_load_golden_ctx_image(struct gk20a *g, | ||
79 | struct channel_gk20a *c) | ||
80 | { | ||
81 | struct tegra_vgpu_cmd_msg msg; | ||
82 | struct tegra_vgpu_ch_ctx_params *p = &msg.params.ch_ctx; | ||
83 | int err; | ||
84 | |||
85 | gk20a_dbg_fn(""); | ||
86 | |||
87 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_LOAD_GR_GOLDEN_CTX; | ||
88 | msg.handle = vgpu_get_handle(g); | ||
89 | p->handle = c->virt_ctx; | ||
90 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
91 | |||
92 | return (err || msg.ret) ? -1 : 0; | ||
93 | } | ||
94 | |||
95 | int vgpu_gr_init_ctx_state(struct gk20a *g) | ||
96 | { | ||
97 | struct gr_gk20a *gr = &g->gr; | ||
98 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | ||
99 | |||
100 | gk20a_dbg_fn(""); | ||
101 | |||
102 | g->gr.ctx_vars.golden_image_size = priv->constants.golden_ctx_size; | ||
103 | g->gr.ctx_vars.zcull_ctxsw_image_size = priv->constants.zcull_ctx_size; | ||
104 | g->gr.ctx_vars.pm_ctxsw_image_size = priv->constants.hwpm_ctx_size; | ||
105 | if (!g->gr.ctx_vars.golden_image_size || | ||
106 | !g->gr.ctx_vars.zcull_ctxsw_image_size || | ||
107 | !g->gr.ctx_vars.pm_ctxsw_image_size) | ||
108 | return -ENXIO; | ||
109 | |||
110 | gr->ctx_vars.buffer_size = g->gr.ctx_vars.golden_image_size; | ||
111 | g->gr.ctx_vars.priv_access_map_size = 512 * 1024; | ||
112 | return 0; | ||
113 | } | ||
114 | |||
115 | static int vgpu_gr_alloc_global_ctx_buffers(struct gk20a *g) | ||
116 | { | ||
117 | struct gr_gk20a *gr = &g->gr; | ||
118 | int attr_buffer_size; | ||
119 | |||
120 | u32 cb_buffer_size = gr->bundle_cb_default_size * | ||
121 | gr_scc_bundle_cb_size_div_256b_byte_granularity_v(); | ||
122 | |||
123 | u32 pagepool_buffer_size = g->ops.gr.pagepool_default_size(g) * | ||
124 | gr_scc_pagepool_total_pages_byte_granularity_v(); | ||
125 | |||
126 | gk20a_dbg_fn(""); | ||
127 | |||
128 | attr_buffer_size = g->ops.gr.calc_global_ctx_buffer_size(g); | ||
129 | |||
130 | gk20a_dbg_info("cb_buffer_size : %d", cb_buffer_size); | ||
131 | gr->global_ctx_buffer[CIRCULAR].mem.size = cb_buffer_size; | ||
132 | |||
133 | gk20a_dbg_info("pagepool_buffer_size : %d", pagepool_buffer_size); | ||
134 | gr->global_ctx_buffer[PAGEPOOL].mem.size = pagepool_buffer_size; | ||
135 | |||
136 | gk20a_dbg_info("attr_buffer_size : %d", attr_buffer_size); | ||
137 | gr->global_ctx_buffer[ATTRIBUTE].mem.size = attr_buffer_size; | ||
138 | |||
139 | gk20a_dbg_info("priv access map size : %d", | ||
140 | gr->ctx_vars.priv_access_map_size); | ||
141 | gr->global_ctx_buffer[PRIV_ACCESS_MAP].mem.size = | ||
142 | gr->ctx_vars.priv_access_map_size; | ||
143 | |||
144 | return 0; | ||
145 | } | ||
146 | |||
147 | static int vgpu_gr_map_global_ctx_buffers(struct gk20a *g, | ||
148 | struct channel_gk20a *c) | ||
149 | { | ||
150 | struct tegra_vgpu_cmd_msg msg; | ||
151 | struct tegra_vgpu_ch_ctx_params *p = &msg.params.ch_ctx; | ||
152 | struct vm_gk20a *ch_vm = c->vm; | ||
153 | u64 *g_bfr_va = c->ch_ctx.global_ctx_buffer_va; | ||
154 | u64 *g_bfr_size = c->ch_ctx.global_ctx_buffer_size; | ||
155 | struct gr_gk20a *gr = &g->gr; | ||
156 | u64 gpu_va; | ||
157 | u32 i; | ||
158 | int err; | ||
159 | |||
160 | gk20a_dbg_fn(""); | ||
161 | |||
162 | /* FIXME: add VPR support */ | ||
163 | |||
164 | /* Circular Buffer */ | ||
165 | gpu_va = __nvgpu_vm_alloc_va(ch_vm, | ||
166 | gr->global_ctx_buffer[CIRCULAR].mem.size, | ||
167 | gmmu_page_size_kernel); | ||
168 | |||
169 | if (!gpu_va) | ||
170 | goto clean_up; | ||
171 | g_bfr_va[CIRCULAR_VA] = gpu_va; | ||
172 | g_bfr_size[CIRCULAR_VA] = gr->global_ctx_buffer[CIRCULAR].mem.size; | ||
173 | |||
174 | /* Attribute Buffer */ | ||
175 | gpu_va = __nvgpu_vm_alloc_va(ch_vm, | ||
176 | gr->global_ctx_buffer[ATTRIBUTE].mem.size, | ||
177 | gmmu_page_size_kernel); | ||
178 | |||
179 | if (!gpu_va) | ||
180 | goto clean_up; | ||
181 | g_bfr_va[ATTRIBUTE_VA] = gpu_va; | ||
182 | g_bfr_size[ATTRIBUTE_VA] = gr->global_ctx_buffer[ATTRIBUTE].mem.size; | ||
183 | |||
184 | /* Page Pool */ | ||
185 | gpu_va = __nvgpu_vm_alloc_va(ch_vm, | ||
186 | gr->global_ctx_buffer[PAGEPOOL].mem.size, | ||
187 | gmmu_page_size_kernel); | ||
188 | if (!gpu_va) | ||
189 | goto clean_up; | ||
190 | g_bfr_va[PAGEPOOL_VA] = gpu_va; | ||
191 | g_bfr_size[PAGEPOOL_VA] = gr->global_ctx_buffer[PAGEPOOL].mem.size; | ||
192 | |||
193 | /* Priv register Access Map */ | ||
194 | gpu_va = __nvgpu_vm_alloc_va(ch_vm, | ||
195 | gr->global_ctx_buffer[PRIV_ACCESS_MAP].mem.size, | ||
196 | gmmu_page_size_kernel); | ||
197 | if (!gpu_va) | ||
198 | goto clean_up; | ||
199 | g_bfr_va[PRIV_ACCESS_MAP_VA] = gpu_va; | ||
200 | g_bfr_size[PRIV_ACCESS_MAP_VA] = | ||
201 | gr->global_ctx_buffer[PRIV_ACCESS_MAP].mem.size; | ||
202 | |||
203 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_MAP_GR_GLOBAL_CTX; | ||
204 | msg.handle = vgpu_get_handle(g); | ||
205 | p->handle = c->virt_ctx; | ||
206 | p->cb_va = g_bfr_va[CIRCULAR_VA]; | ||
207 | p->attr_va = g_bfr_va[ATTRIBUTE_VA]; | ||
208 | p->page_pool_va = g_bfr_va[PAGEPOOL_VA]; | ||
209 | p->priv_access_map_va = g_bfr_va[PRIV_ACCESS_MAP_VA]; | ||
210 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
211 | if (err || msg.ret) | ||
212 | goto clean_up; | ||
213 | |||
214 | c->ch_ctx.global_ctx_buffer_mapped = true; | ||
215 | return 0; | ||
216 | |||
217 | clean_up: | ||
218 | for (i = 0; i < NR_GLOBAL_CTX_BUF_VA; i++) { | ||
219 | if (g_bfr_va[i]) { | ||
220 | __nvgpu_vm_free_va(ch_vm, g_bfr_va[i], | ||
221 | gmmu_page_size_kernel); | ||
222 | g_bfr_va[i] = 0; | ||
223 | } | ||
224 | } | ||
225 | return -ENOMEM; | ||
226 | } | ||
227 | |||
228 | static void vgpu_gr_unmap_global_ctx_buffers(struct channel_gk20a *c) | ||
229 | { | ||
230 | struct vm_gk20a *ch_vm = c->vm; | ||
231 | u64 *g_bfr_va = c->ch_ctx.global_ctx_buffer_va; | ||
232 | u64 *g_bfr_size = c->ch_ctx.global_ctx_buffer_size; | ||
233 | u32 i; | ||
234 | |||
235 | gk20a_dbg_fn(""); | ||
236 | |||
237 | if (c->ch_ctx.global_ctx_buffer_mapped) { | ||
238 | struct tegra_vgpu_cmd_msg msg; | ||
239 | struct tegra_vgpu_ch_ctx_params *p = &msg.params.ch_ctx; | ||
240 | int err; | ||
241 | |||
242 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_UNMAP_GR_GLOBAL_CTX; | ||
243 | msg.handle = vgpu_get_handle(c->g); | ||
244 | p->handle = c->virt_ctx; | ||
245 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
246 | WARN_ON(err || msg.ret); | ||
247 | } | ||
248 | |||
249 | for (i = 0; i < NR_GLOBAL_CTX_BUF_VA; i++) { | ||
250 | if (g_bfr_va[i]) { | ||
251 | __nvgpu_vm_free_va(ch_vm, g_bfr_va[i], | ||
252 | gmmu_page_size_kernel); | ||
253 | g_bfr_va[i] = 0; | ||
254 | g_bfr_size[i] = 0; | ||
255 | } | ||
256 | } | ||
257 | c->ch_ctx.global_ctx_buffer_mapped = false; | ||
258 | } | ||
259 | |||
260 | int vgpu_gr_alloc_gr_ctx(struct gk20a *g, | ||
261 | struct gr_ctx_desc **__gr_ctx, | ||
262 | struct vm_gk20a *vm, | ||
263 | u32 class, | ||
264 | u32 flags) | ||
265 | { | ||
266 | struct tegra_vgpu_cmd_msg msg = {0}; | ||
267 | struct tegra_vgpu_gr_ctx_params *p = &msg.params.gr_ctx; | ||
268 | struct gr_gk20a *gr = &g->gr; | ||
269 | struct gr_ctx_desc *gr_ctx; | ||
270 | int err; | ||
271 | |||
272 | gk20a_dbg_fn(""); | ||
273 | |||
274 | if (gr->ctx_vars.buffer_size == 0) | ||
275 | return 0; | ||
276 | |||
277 | /* alloc channel gr ctx buffer */ | ||
278 | gr->ctx_vars.buffer_size = gr->ctx_vars.golden_image_size; | ||
279 | gr->ctx_vars.buffer_total_size = gr->ctx_vars.golden_image_size; | ||
280 | |||
281 | gr_ctx = nvgpu_kzalloc(g, sizeof(*gr_ctx)); | ||
282 | if (!gr_ctx) | ||
283 | return -ENOMEM; | ||
284 | |||
285 | gr_ctx->mem.size = gr->ctx_vars.buffer_total_size; | ||
286 | gr_ctx->mem.gpu_va = __nvgpu_vm_alloc_va(vm, | ||
287 | gr_ctx->mem.size, | ||
288 | gmmu_page_size_kernel); | ||
289 | |||
290 | if (!gr_ctx->mem.gpu_va) { | ||
291 | nvgpu_kfree(g, gr_ctx); | ||
292 | return -ENOMEM; | ||
293 | } | ||
294 | |||
295 | msg.cmd = TEGRA_VGPU_CMD_GR_CTX_ALLOC; | ||
296 | msg.handle = vgpu_get_handle(g); | ||
297 | p->as_handle = vm->handle; | ||
298 | p->gr_ctx_va = gr_ctx->mem.gpu_va; | ||
299 | p->class_num = class; | ||
300 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
301 | err = err ? err : msg.ret; | ||
302 | |||
303 | if (unlikely(err)) { | ||
304 | nvgpu_err(g, "fail to alloc gr_ctx"); | ||
305 | __nvgpu_vm_free_va(vm, gr_ctx->mem.gpu_va, | ||
306 | gmmu_page_size_kernel); | ||
307 | nvgpu_kfree(g, gr_ctx); | ||
308 | } else { | ||
309 | gr_ctx->virt_ctx = p->gr_ctx_handle; | ||
310 | *__gr_ctx = gr_ctx; | ||
311 | } | ||
312 | |||
313 | return err; | ||
314 | } | ||
315 | |||
316 | void vgpu_gr_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, | ||
317 | struct gr_ctx_desc *gr_ctx) | ||
318 | { | ||
319 | gk20a_dbg_fn(""); | ||
320 | |||
321 | if (gr_ctx && gr_ctx->mem.gpu_va) { | ||
322 | struct tegra_vgpu_cmd_msg msg; | ||
323 | struct tegra_vgpu_gr_ctx_params *p = &msg.params.gr_ctx; | ||
324 | int err; | ||
325 | |||
326 | msg.cmd = TEGRA_VGPU_CMD_GR_CTX_FREE; | ||
327 | msg.handle = vgpu_get_handle(g); | ||
328 | p->gr_ctx_handle = gr_ctx->virt_ctx; | ||
329 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
330 | WARN_ON(err || msg.ret); | ||
331 | |||
332 | __nvgpu_vm_free_va(vm, gr_ctx->mem.gpu_va, | ||
333 | gmmu_page_size_kernel); | ||
334 | nvgpu_kfree(g, gr_ctx); | ||
335 | } | ||
336 | } | ||
337 | |||
338 | static void vgpu_gr_free_channel_gr_ctx(struct channel_gk20a *c) | ||
339 | { | ||
340 | gk20a_dbg_fn(""); | ||
341 | |||
342 | c->g->ops.gr.free_gr_ctx(c->g, c->vm, c->ch_ctx.gr_ctx); | ||
343 | c->ch_ctx.gr_ctx = NULL; | ||
344 | } | ||
345 | |||
346 | static int vgpu_gr_alloc_channel_patch_ctx(struct gk20a *g, | ||
347 | struct channel_gk20a *c) | ||
348 | { | ||
349 | struct patch_desc *patch_ctx = &c->ch_ctx.patch_ctx; | ||
350 | struct vm_gk20a *ch_vm = c->vm; | ||
351 | struct tegra_vgpu_cmd_msg msg; | ||
352 | struct tegra_vgpu_ch_ctx_params *p = &msg.params.ch_ctx; | ||
353 | int err; | ||
354 | |||
355 | gk20a_dbg_fn(""); | ||
356 | |||
357 | patch_ctx->mem.size = 128 * sizeof(u32); | ||
358 | patch_ctx->mem.gpu_va = __nvgpu_vm_alloc_va(ch_vm, | ||
359 | patch_ctx->mem.size, | ||
360 | gmmu_page_size_kernel); | ||
361 | if (!patch_ctx->mem.gpu_va) | ||
362 | return -ENOMEM; | ||
363 | |||
364 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_ALLOC_GR_PATCH_CTX; | ||
365 | msg.handle = vgpu_get_handle(g); | ||
366 | p->handle = c->virt_ctx; | ||
367 | p->patch_ctx_va = patch_ctx->mem.gpu_va; | ||
368 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
369 | if (err || msg.ret) { | ||
370 | __nvgpu_vm_free_va(ch_vm, patch_ctx->mem.gpu_va, | ||
371 | gmmu_page_size_kernel); | ||
372 | err = -ENOMEM; | ||
373 | } | ||
374 | |||
375 | return err; | ||
376 | } | ||
377 | |||
378 | static void vgpu_gr_free_channel_patch_ctx(struct channel_gk20a *c) | ||
379 | { | ||
380 | struct patch_desc *patch_ctx = &c->ch_ctx.patch_ctx; | ||
381 | struct vm_gk20a *ch_vm = c->vm; | ||
382 | |||
383 | gk20a_dbg_fn(""); | ||
384 | |||
385 | if (patch_ctx->mem.gpu_va) { | ||
386 | struct tegra_vgpu_cmd_msg msg; | ||
387 | struct tegra_vgpu_ch_ctx_params *p = &msg.params.ch_ctx; | ||
388 | int err; | ||
389 | |||
390 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_FREE_GR_PATCH_CTX; | ||
391 | msg.handle = vgpu_get_handle(c->g); | ||
392 | p->handle = c->virt_ctx; | ||
393 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
394 | WARN_ON(err || msg.ret); | ||
395 | |||
396 | __nvgpu_vm_free_va(ch_vm, patch_ctx->mem.gpu_va, | ||
397 | gmmu_page_size_kernel); | ||
398 | patch_ctx->mem.gpu_va = 0; | ||
399 | } | ||
400 | } | ||
401 | |||
402 | static void vgpu_gr_free_channel_pm_ctx(struct channel_gk20a *c) | ||
403 | { | ||
404 | struct tegra_vgpu_cmd_msg msg; | ||
405 | struct tegra_vgpu_channel_free_hwpm_ctx *p = &msg.params.free_hwpm_ctx; | ||
406 | struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx; | ||
407 | struct pm_ctx_desc *pm_ctx = &ch_ctx->pm_ctx; | ||
408 | int err; | ||
409 | |||
410 | gk20a_dbg_fn(""); | ||
411 | |||
412 | /* check if hwpm was ever initialized. If not, nothing to do */ | ||
413 | if (pm_ctx->mem.gpu_va == 0) | ||
414 | return; | ||
415 | |||
416 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_FREE_HWPM_CTX; | ||
417 | msg.handle = vgpu_get_handle(c->g); | ||
418 | p->handle = c->virt_ctx; | ||
419 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
420 | WARN_ON(err || msg.ret); | ||
421 | |||
422 | __nvgpu_vm_free_va(c->vm, pm_ctx->mem.gpu_va, | ||
423 | gmmu_page_size_kernel); | ||
424 | pm_ctx->mem.gpu_va = 0; | ||
425 | } | ||
426 | |||
427 | void vgpu_gr_free_channel_ctx(struct channel_gk20a *c, bool is_tsg) | ||
428 | { | ||
429 | gk20a_dbg_fn(""); | ||
430 | |||
431 | if (c->g->ops.fifo.free_channel_ctx_header) | ||
432 | c->g->ops.fifo.free_channel_ctx_header(c); | ||
433 | vgpu_gr_unmap_global_ctx_buffers(c); | ||
434 | vgpu_gr_free_channel_patch_ctx(c); | ||
435 | vgpu_gr_free_channel_pm_ctx(c); | ||
436 | if (!is_tsg) | ||
437 | vgpu_gr_free_channel_gr_ctx(c); | ||
438 | |||
439 | /* zcull_ctx, pm_ctx */ | ||
440 | |||
441 | memset(&c->ch_ctx, 0, sizeof(struct channel_ctx_gk20a)); | ||
442 | |||
443 | c->first_init = false; | ||
444 | } | ||
445 | |||
446 | static int vgpu_gr_ch_bind_gr_ctx(struct channel_gk20a *c) | ||
447 | { | ||
448 | struct gr_ctx_desc *gr_ctx = c->ch_ctx.gr_ctx; | ||
449 | struct tegra_vgpu_cmd_msg msg = {0}; | ||
450 | struct tegra_vgpu_channel_bind_gr_ctx_params *p = | ||
451 | &msg.params.ch_bind_gr_ctx; | ||
452 | int err; | ||
453 | |||
454 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTX; | ||
455 | msg.handle = vgpu_get_handle(c->g); | ||
456 | p->ch_handle = c->virt_ctx; | ||
457 | p->gr_ctx_handle = gr_ctx->virt_ctx; | ||
458 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
459 | err = err ? err : msg.ret; | ||
460 | WARN_ON(err); | ||
461 | |||
462 | return err; | ||
463 | } | ||
464 | |||
465 | static int vgpu_gr_tsg_bind_gr_ctx(struct tsg_gk20a *tsg) | ||
466 | { | ||
467 | struct gr_ctx_desc *gr_ctx = tsg->tsg_gr_ctx; | ||
468 | struct tegra_vgpu_cmd_msg msg = {0}; | ||
469 | struct tegra_vgpu_tsg_bind_gr_ctx_params *p = | ||
470 | &msg.params.tsg_bind_gr_ctx; | ||
471 | int err; | ||
472 | |||
473 | msg.cmd = TEGRA_VGPU_CMD_TSG_BIND_GR_CTX; | ||
474 | msg.handle = vgpu_get_handle(tsg->g); | ||
475 | p->tsg_id = tsg->tsgid; | ||
476 | p->gr_ctx_handle = gr_ctx->virt_ctx; | ||
477 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
478 | err = err ? err : msg.ret; | ||
479 | WARN_ON(err); | ||
480 | |||
481 | return err; | ||
482 | } | ||
483 | |||
484 | int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags) | ||
485 | { | ||
486 | struct gk20a *g = c->g; | ||
487 | struct fifo_gk20a *f = &g->fifo; | ||
488 | struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx; | ||
489 | struct tsg_gk20a *tsg = NULL; | ||
490 | int err = 0; | ||
491 | |||
492 | gk20a_dbg_fn(""); | ||
493 | |||
494 | /* an address space needs to have been bound at this point.*/ | ||
495 | if (!gk20a_channel_as_bound(c)) { | ||
496 | nvgpu_err(g, "not bound to address space at time" | ||
497 | " of grctx allocation"); | ||
498 | return -EINVAL; | ||
499 | } | ||
500 | |||
501 | if (!g->ops.gr.is_valid_class(g, class_num)) { | ||
502 | nvgpu_err(g, "invalid obj class 0x%x", class_num); | ||
503 | err = -EINVAL; | ||
504 | goto out; | ||
505 | } | ||
506 | c->obj_class = class_num; | ||
507 | |||
508 | if (gk20a_is_channel_marked_as_tsg(c)) | ||
509 | tsg = &f->tsg[c->tsgid]; | ||
510 | |||
511 | if (!tsg) { | ||
512 | /* allocate gr ctx buffer */ | ||
513 | if (!ch_ctx->gr_ctx) { | ||
514 | err = g->ops.gr.alloc_gr_ctx(g, &c->ch_ctx.gr_ctx, | ||
515 | c->vm, | ||
516 | class_num, | ||
517 | flags); | ||
518 | if (!err) | ||
519 | err = vgpu_gr_ch_bind_gr_ctx(c); | ||
520 | if (err) { | ||
521 | nvgpu_err(g, "fail to allocate gr ctx buffer"); | ||
522 | goto out; | ||
523 | } | ||
524 | } else { | ||
525 | /*TBD: needs to be more subtle about which is | ||
526 | * being allocated as some are allowed to be | ||
527 | * allocated along same channel */ | ||
528 | nvgpu_err(g, | ||
529 | "too many classes alloc'd on same channel"); | ||
530 | err = -EINVAL; | ||
531 | goto out; | ||
532 | } | ||
533 | } else { | ||
534 | if (!tsg->tsg_gr_ctx) { | ||
535 | tsg->vm = c->vm; | ||
536 | nvgpu_vm_get(tsg->vm); | ||
537 | err = g->ops.gr.alloc_gr_ctx(g, &tsg->tsg_gr_ctx, | ||
538 | c->vm, | ||
539 | class_num, | ||
540 | flags); | ||
541 | if (!err) | ||
542 | err = vgpu_gr_tsg_bind_gr_ctx(tsg); | ||
543 | if (err) { | ||
544 | nvgpu_err(g, | ||
545 | "fail to allocate TSG gr ctx buffer, err=%d", err); | ||
546 | nvgpu_vm_put(tsg->vm); | ||
547 | tsg->vm = NULL; | ||
548 | goto out; | ||
549 | } | ||
550 | } | ||
551 | |||
552 | ch_ctx->gr_ctx = tsg->tsg_gr_ctx; | ||
553 | err = vgpu_gr_ch_bind_gr_ctx(c); | ||
554 | if (err) { | ||
555 | nvgpu_err(g, "fail to bind gr ctx buffer"); | ||
556 | goto out; | ||
557 | } | ||
558 | } | ||
559 | |||
560 | /* commit gr ctx buffer */ | ||
561 | err = g->ops.gr.commit_inst(c, ch_ctx->gr_ctx->mem.gpu_va); | ||
562 | if (err) { | ||
563 | nvgpu_err(g, "fail to commit gr ctx buffer"); | ||
564 | goto out; | ||
565 | } | ||
566 | |||
567 | /* allocate patch buffer */ | ||
568 | if (ch_ctx->patch_ctx.mem.priv.pages == NULL) { | ||
569 | err = vgpu_gr_alloc_channel_patch_ctx(g, c); | ||
570 | if (err) { | ||
571 | nvgpu_err(g, "fail to allocate patch buffer"); | ||
572 | goto out; | ||
573 | } | ||
574 | } | ||
575 | |||
576 | /* map global buffer to channel gpu_va and commit */ | ||
577 | if (!ch_ctx->global_ctx_buffer_mapped) { | ||
578 | err = vgpu_gr_map_global_ctx_buffers(g, c); | ||
579 | if (err) { | ||
580 | nvgpu_err(g, "fail to map global ctx buffer"); | ||
581 | goto out; | ||
582 | } | ||
583 | gr_gk20a_elpg_protected_call(g, | ||
584 | vgpu_gr_commit_global_ctx_buffers(g, c, true)); | ||
585 | } | ||
586 | |||
587 | /* load golden image */ | ||
588 | if (!c->first_init) { | ||
589 | err = gr_gk20a_elpg_protected_call(g, | ||
590 | vgpu_gr_load_golden_ctx_image(g, c)); | ||
591 | if (err) { | ||
592 | nvgpu_err(g, "fail to load golden ctx image"); | ||
593 | goto out; | ||
594 | } | ||
595 | c->first_init = true; | ||
596 | } | ||
597 | |||
598 | gk20a_dbg_fn("done"); | ||
599 | return 0; | ||
600 | out: | ||
601 | /* 1. gr_ctx, patch_ctx and global ctx buffer mapping | ||
602 | can be reused so no need to release them. | ||
603 | 2. golden image load is a one time thing so if | ||
604 | they pass, no need to undo. */ | ||
605 | nvgpu_err(g, "fail"); | ||
606 | return err; | ||
607 | } | ||
608 | |||
609 | static int vgpu_gr_init_gr_config(struct gk20a *g, struct gr_gk20a *gr) | ||
610 | { | ||
611 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | ||
612 | u32 gpc_index; | ||
613 | int err = -ENOMEM; | ||
614 | |||
615 | gk20a_dbg_fn(""); | ||
616 | |||
617 | gr->max_gpc_count = priv->constants.max_gpc_count; | ||
618 | gr->gpc_count = priv->constants.gpc_count; | ||
619 | gr->max_tpc_per_gpc_count = priv->constants.max_tpc_per_gpc_count; | ||
620 | |||
621 | gr->max_tpc_count = gr->max_gpc_count * gr->max_tpc_per_gpc_count; | ||
622 | |||
623 | gr->gpc_tpc_count = nvgpu_kzalloc(g, gr->gpc_count * sizeof(u32)); | ||
624 | if (!gr->gpc_tpc_count) | ||
625 | goto cleanup; | ||
626 | |||
627 | gr->gpc_tpc_mask = nvgpu_kzalloc(g, gr->gpc_count * sizeof(u32)); | ||
628 | if (!gr->gpc_tpc_mask) | ||
629 | goto cleanup; | ||
630 | |||
631 | gr->sm_to_cluster = nvgpu_kzalloc(g, gr->gpc_count * | ||
632 | gr->max_tpc_per_gpc_count * | ||
633 | sizeof(struct sm_info)); | ||
634 | if (!gr->sm_to_cluster) | ||
635 | goto cleanup; | ||
636 | |||
637 | gr->tpc_count = 0; | ||
638 | for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) { | ||
639 | gr->gpc_tpc_count[gpc_index] = | ||
640 | priv->constants.gpc_tpc_count[gpc_index]; | ||
641 | |||
642 | gr->tpc_count += gr->gpc_tpc_count[gpc_index]; | ||
643 | |||
644 | if (g->ops.gr.get_gpc_tpc_mask) | ||
645 | gr->gpc_tpc_mask[gpc_index] = | ||
646 | g->ops.gr.get_gpc_tpc_mask(g, gpc_index); | ||
647 | } | ||
648 | |||
649 | g->ops.gr.bundle_cb_defaults(g); | ||
650 | g->ops.gr.cb_size_default(g); | ||
651 | g->ops.gr.calc_global_ctx_buffer_size(g); | ||
652 | err = g->ops.gr.init_fs_state(g); | ||
653 | if (err) | ||
654 | goto cleanup; | ||
655 | return 0; | ||
656 | cleanup: | ||
657 | nvgpu_err(g, "out of memory"); | ||
658 | |||
659 | nvgpu_kfree(g, gr->gpc_tpc_count); | ||
660 | gr->gpc_tpc_count = NULL; | ||
661 | |||
662 | nvgpu_kfree(g, gr->gpc_tpc_mask); | ||
663 | gr->gpc_tpc_mask = NULL; | ||
664 | |||
665 | return err; | ||
666 | } | ||
667 | |||
668 | int vgpu_gr_bind_ctxsw_zcull(struct gk20a *g, struct gr_gk20a *gr, | ||
669 | struct channel_gk20a *c, u64 zcull_va, | ||
670 | u32 mode) | ||
671 | { | ||
672 | struct tegra_vgpu_cmd_msg msg; | ||
673 | struct tegra_vgpu_zcull_bind_params *p = &msg.params.zcull_bind; | ||
674 | int err; | ||
675 | |||
676 | gk20a_dbg_fn(""); | ||
677 | |||
678 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_BIND_ZCULL; | ||
679 | msg.handle = vgpu_get_handle(g); | ||
680 | p->handle = c->virt_ctx; | ||
681 | p->zcull_va = zcull_va; | ||
682 | p->mode = mode; | ||
683 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
684 | |||
685 | return (err || msg.ret) ? -ENOMEM : 0; | ||
686 | } | ||
687 | |||
688 | int vgpu_gr_get_zcull_info(struct gk20a *g, struct gr_gk20a *gr, | ||
689 | struct gr_zcull_info *zcull_params) | ||
690 | { | ||
691 | struct tegra_vgpu_cmd_msg msg; | ||
692 | struct tegra_vgpu_zcull_info_params *p = &msg.params.zcull_info; | ||
693 | int err; | ||
694 | |||
695 | gk20a_dbg_fn(""); | ||
696 | |||
697 | msg.cmd = TEGRA_VGPU_CMD_GET_ZCULL_INFO; | ||
698 | msg.handle = vgpu_get_handle(g); | ||
699 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
700 | if (err || msg.ret) | ||
701 | return -ENOMEM; | ||
702 | |||
703 | zcull_params->width_align_pixels = p->width_align_pixels; | ||
704 | zcull_params->height_align_pixels = p->height_align_pixels; | ||
705 | zcull_params->pixel_squares_by_aliquots = p->pixel_squares_by_aliquots; | ||
706 | zcull_params->aliquot_total = p->aliquot_total; | ||
707 | zcull_params->region_byte_multiplier = p->region_byte_multiplier; | ||
708 | zcull_params->region_header_size = p->region_header_size; | ||
709 | zcull_params->subregion_header_size = p->subregion_header_size; | ||
710 | zcull_params->subregion_width_align_pixels = | ||
711 | p->subregion_width_align_pixels; | ||
712 | zcull_params->subregion_height_align_pixels = | ||
713 | p->subregion_height_align_pixels; | ||
714 | zcull_params->subregion_count = p->subregion_count; | ||
715 | |||
716 | return 0; | ||
717 | } | ||
718 | |||
719 | u32 vgpu_gr_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | ||
720 | { | ||
721 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | ||
722 | |||
723 | return priv->constants.gpc_tpc_mask[gpc_index]; | ||
724 | } | ||
725 | |||
726 | u32 vgpu_gr_get_max_fbps_count(struct gk20a *g) | ||
727 | { | ||
728 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | ||
729 | |||
730 | gk20a_dbg_fn(""); | ||
731 | |||
732 | return priv->constants.num_fbps; | ||
733 | } | ||
734 | |||
735 | u32 vgpu_gr_get_fbp_en_mask(struct gk20a *g) | ||
736 | { | ||
737 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | ||
738 | |||
739 | gk20a_dbg_fn(""); | ||
740 | |||
741 | return priv->constants.fbp_en_mask; | ||
742 | } | ||
743 | |||
744 | u32 vgpu_gr_get_max_ltc_per_fbp(struct gk20a *g) | ||
745 | { | ||
746 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | ||
747 | |||
748 | gk20a_dbg_fn(""); | ||
749 | |||
750 | return priv->constants.ltc_per_fbp; | ||
751 | } | ||
752 | |||
753 | u32 vgpu_gr_get_max_lts_per_ltc(struct gk20a *g) | ||
754 | { | ||
755 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | ||
756 | |||
757 | gk20a_dbg_fn(""); | ||
758 | |||
759 | return priv->constants.max_lts_per_ltc; | ||
760 | } | ||
761 | |||
762 | u32 *vgpu_gr_rop_l2_en_mask(struct gk20a *g) | ||
763 | { | ||
764 | /* no one use it yet */ | ||
765 | return NULL; | ||
766 | } | ||
767 | |||
768 | int vgpu_gr_add_zbc(struct gk20a *g, struct gr_gk20a *gr, | ||
769 | struct zbc_entry *zbc_val) | ||
770 | { | ||
771 | struct tegra_vgpu_cmd_msg msg = {0}; | ||
772 | struct tegra_vgpu_zbc_set_table_params *p = &msg.params.zbc_set_table; | ||
773 | int err; | ||
774 | |||
775 | gk20a_dbg_fn(""); | ||
776 | |||
777 | msg.cmd = TEGRA_VGPU_CMD_ZBC_SET_TABLE; | ||
778 | msg.handle = vgpu_get_handle(g); | ||
779 | |||
780 | p->type = zbc_val->type; | ||
781 | p->format = zbc_val->format; | ||
782 | switch (p->type) { | ||
783 | case GK20A_ZBC_TYPE_COLOR: | ||
784 | memcpy(p->color_ds, zbc_val->color_ds, sizeof(p->color_ds)); | ||
785 | memcpy(p->color_l2, zbc_val->color_l2, sizeof(p->color_l2)); | ||
786 | break; | ||
787 | case GK20A_ZBC_TYPE_DEPTH: | ||
788 | p->depth = zbc_val->depth; | ||
789 | break; | ||
790 | default: | ||
791 | return -EINVAL; | ||
792 | } | ||
793 | |||
794 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
795 | |||
796 | return (err || msg.ret) ? -ENOMEM : 0; | ||
797 | } | ||
798 | |||
799 | int vgpu_gr_query_zbc(struct gk20a *g, struct gr_gk20a *gr, | ||
800 | struct zbc_query_params *query_params) | ||
801 | { | ||
802 | struct tegra_vgpu_cmd_msg msg = {0}; | ||
803 | struct tegra_vgpu_zbc_query_table_params *p = | ||
804 | &msg.params.zbc_query_table; | ||
805 | int err; | ||
806 | |||
807 | gk20a_dbg_fn(""); | ||
808 | |||
809 | msg.cmd = TEGRA_VGPU_CMD_ZBC_QUERY_TABLE; | ||
810 | msg.handle = vgpu_get_handle(g); | ||
811 | |||
812 | p->type = query_params->type; | ||
813 | p->index_size = query_params->index_size; | ||
814 | |||
815 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
816 | if (err || msg.ret) | ||
817 | return -ENOMEM; | ||
818 | |||
819 | switch (query_params->type) { | ||
820 | case GK20A_ZBC_TYPE_COLOR: | ||
821 | memcpy(query_params->color_ds, p->color_ds, | ||
822 | sizeof(query_params->color_ds)); | ||
823 | memcpy(query_params->color_l2, p->color_l2, | ||
824 | sizeof(query_params->color_l2)); | ||
825 | break; | ||
826 | case GK20A_ZBC_TYPE_DEPTH: | ||
827 | query_params->depth = p->depth; | ||
828 | break; | ||
829 | case GK20A_ZBC_TYPE_INVALID: | ||
830 | query_params->index_size = p->index_size; | ||
831 | break; | ||
832 | default: | ||
833 | return -EINVAL; | ||
834 | } | ||
835 | query_params->ref_cnt = p->ref_cnt; | ||
836 | query_params->format = p->format; | ||
837 | |||
838 | return 0; | ||
839 | } | ||
840 | |||
841 | static void vgpu_remove_gr_support(struct gr_gk20a *gr) | ||
842 | { | ||
843 | gk20a_dbg_fn(""); | ||
844 | |||
845 | gk20a_comptag_allocator_destroy(gr->g, &gr->comp_tags); | ||
846 | |||
847 | nvgpu_kfree(gr->g, gr->sm_error_states); | ||
848 | gr->sm_error_states = NULL; | ||
849 | |||
850 | nvgpu_kfree(gr->g, gr->gpc_tpc_mask); | ||
851 | gr->gpc_tpc_mask = NULL; | ||
852 | |||
853 | nvgpu_kfree(gr->g, gr->sm_to_cluster); | ||
854 | gr->sm_to_cluster = NULL; | ||
855 | |||
856 | nvgpu_kfree(gr->g, gr->gpc_tpc_count); | ||
857 | gr->gpc_tpc_count = NULL; | ||
858 | } | ||
859 | |||
860 | static int vgpu_gr_init_gr_setup_sw(struct gk20a *g) | ||
861 | { | ||
862 | struct gr_gk20a *gr = &g->gr; | ||
863 | int err; | ||
864 | |||
865 | gk20a_dbg_fn(""); | ||
866 | |||
867 | if (gr->sw_ready) { | ||
868 | gk20a_dbg_fn("skip init"); | ||
869 | return 0; | ||
870 | } | ||
871 | |||
872 | gr->g = g; | ||
873 | |||
874 | #if defined(CONFIG_GK20A_CYCLE_STATS) | ||
875 | nvgpu_mutex_init(&g->gr.cs_lock); | ||
876 | #endif | ||
877 | |||
878 | err = vgpu_gr_init_gr_config(g, gr); | ||
879 | if (err) | ||
880 | goto clean_up; | ||
881 | |||
882 | err = g->ops.gr.init_ctx_state(g); | ||
883 | if (err) | ||
884 | goto clean_up; | ||
885 | |||
886 | err = g->ops.ltc.init_comptags(g, gr); | ||
887 | if (err) | ||
888 | goto clean_up; | ||
889 | |||
890 | err = vgpu_gr_alloc_global_ctx_buffers(g); | ||
891 | if (err) | ||
892 | goto clean_up; | ||
893 | |||
894 | nvgpu_mutex_init(&gr->ctx_mutex); | ||
895 | |||
896 | gr->sm_error_states = nvgpu_kzalloc(g, | ||
897 | sizeof(struct nvgpu_gr_sm_error_state) * | ||
898 | gr->no_of_sm); | ||
899 | if (!gr->sm_error_states) { | ||
900 | err = -ENOMEM; | ||
901 | goto clean_up; | ||
902 | } | ||
903 | |||
904 | gr->remove_support = vgpu_remove_gr_support; | ||
905 | gr->sw_ready = true; | ||
906 | |||
907 | gk20a_dbg_fn("done"); | ||
908 | return 0; | ||
909 | |||
910 | clean_up: | ||
911 | nvgpu_err(g, "fail"); | ||
912 | vgpu_remove_gr_support(gr); | ||
913 | return err; | ||
914 | } | ||
915 | |||
916 | int vgpu_init_gr_support(struct gk20a *g) | ||
917 | { | ||
918 | gk20a_dbg_fn(""); | ||
919 | |||
920 | return vgpu_gr_init_gr_setup_sw(g); | ||
921 | } | ||
922 | |||
923 | int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info) | ||
924 | { | ||
925 | struct fifo_gk20a *f = &g->fifo; | ||
926 | struct channel_gk20a *ch = gk20a_channel_get(&f->channel[info->chid]); | ||
927 | |||
928 | gk20a_dbg_fn(""); | ||
929 | if (!ch) | ||
930 | return 0; | ||
931 | |||
932 | if (info->type != TEGRA_VGPU_GR_INTR_NOTIFY && | ||
933 | info->type != TEGRA_VGPU_GR_INTR_SEMAPHORE) | ||
934 | nvgpu_err(g, "gr intr (%d) on ch %u", info->type, info->chid); | ||
935 | |||
936 | switch (info->type) { | ||
937 | case TEGRA_VGPU_GR_INTR_NOTIFY: | ||
938 | nvgpu_cond_broadcast_interruptible(&ch->notifier_wq); | ||
939 | break; | ||
940 | case TEGRA_VGPU_GR_INTR_SEMAPHORE: | ||
941 | nvgpu_cond_broadcast_interruptible(&ch->semaphore_wq); | ||
942 | break; | ||
943 | case TEGRA_VGPU_GR_INTR_SEMAPHORE_TIMEOUT: | ||
944 | gk20a_set_error_notifier(ch, | ||
945 | NVGPU_CHANNEL_GR_SEMAPHORE_TIMEOUT); | ||
946 | break; | ||
947 | case TEGRA_VGPU_GR_INTR_ILLEGAL_NOTIFY: | ||
948 | gk20a_set_error_notifier(ch, | ||
949 | NVGPU_CHANNEL_GR_ILLEGAL_NOTIFY); | ||
950 | case TEGRA_VGPU_GR_INTR_ILLEGAL_METHOD: | ||
951 | break; | ||
952 | case TEGRA_VGPU_GR_INTR_ILLEGAL_CLASS: | ||
953 | gk20a_set_error_notifier(ch, | ||
954 | NVGPU_CHANNEL_GR_ERROR_SW_NOTIFY); | ||
955 | break; | ||
956 | case TEGRA_VGPU_GR_INTR_FECS_ERROR: | ||
957 | break; | ||
958 | case TEGRA_VGPU_GR_INTR_CLASS_ERROR: | ||
959 | gk20a_set_error_notifier(ch, | ||
960 | NVGPU_CHANNEL_GR_ERROR_SW_NOTIFY); | ||
961 | break; | ||
962 | case TEGRA_VGPU_GR_INTR_FIRMWARE_METHOD: | ||
963 | gk20a_set_error_notifier(ch, | ||
964 | NVGPU_CHANNEL_GR_ERROR_SW_NOTIFY); | ||
965 | break; | ||
966 | case TEGRA_VGPU_GR_INTR_EXCEPTION: | ||
967 | gk20a_set_error_notifier(ch, | ||
968 | NVGPU_CHANNEL_GR_ERROR_SW_NOTIFY); | ||
969 | break; | ||
970 | case TEGRA_VGPU_GR_INTR_SM_EXCEPTION: | ||
971 | gk20a_dbg_gpu_post_events(ch); | ||
972 | break; | ||
973 | default: | ||
974 | WARN_ON(1); | ||
975 | break; | ||
976 | } | ||
977 | |||
978 | gk20a_channel_put(ch); | ||
979 | return 0; | ||
980 | } | ||
981 | |||
982 | int vgpu_gr_nonstall_isr(struct gk20a *g, | ||
983 | struct tegra_vgpu_gr_nonstall_intr_info *info) | ||
984 | { | ||
985 | gk20a_dbg_fn(""); | ||
986 | |||
987 | switch (info->type) { | ||
988 | case TEGRA_VGPU_GR_NONSTALL_INTR_SEMAPHORE: | ||
989 | gk20a_channel_semaphore_wakeup(g, true); | ||
990 | break; | ||
991 | default: | ||
992 | WARN_ON(1); | ||
993 | break; | ||
994 | } | ||
995 | |||
996 | return 0; | ||
997 | } | ||
998 | |||
999 | int vgpu_gr_set_sm_debug_mode(struct gk20a *g, | ||
1000 | struct channel_gk20a *ch, u64 sms, bool enable) | ||
1001 | { | ||
1002 | struct tegra_vgpu_cmd_msg msg; | ||
1003 | struct tegra_vgpu_sm_debug_mode *p = &msg.params.sm_debug_mode; | ||
1004 | int err; | ||
1005 | |||
1006 | gk20a_dbg_fn(""); | ||
1007 | |||
1008 | msg.cmd = TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE; | ||
1009 | msg.handle = vgpu_get_handle(g); | ||
1010 | p->handle = ch->virt_ctx; | ||
1011 | p->sms = sms; | ||
1012 | p->enable = (u32)enable; | ||
1013 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
1014 | WARN_ON(err || msg.ret); | ||
1015 | |||
1016 | return err ? err : msg.ret; | ||
1017 | } | ||
1018 | |||
1019 | int vgpu_gr_update_smpc_ctxsw_mode(struct gk20a *g, | ||
1020 | struct channel_gk20a *ch, bool enable) | ||
1021 | { | ||
1022 | struct tegra_vgpu_cmd_msg msg; | ||
1023 | struct tegra_vgpu_channel_set_ctxsw_mode *p = &msg.params.set_ctxsw_mode; | ||
1024 | int err; | ||
1025 | |||
1026 | gk20a_dbg_fn(""); | ||
1027 | |||
1028 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_SMPC_CTXSW_MODE; | ||
1029 | msg.handle = vgpu_get_handle(g); | ||
1030 | p->handle = ch->virt_ctx; | ||
1031 | |||
1032 | if (enable) | ||
1033 | p->mode = TEGRA_VGPU_CTXSW_MODE_CTXSW; | ||
1034 | else | ||
1035 | p->mode = TEGRA_VGPU_CTXSW_MODE_NO_CTXSW; | ||
1036 | |||
1037 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
1038 | WARN_ON(err || msg.ret); | ||
1039 | |||
1040 | return err ? err : msg.ret; | ||
1041 | } | ||
1042 | |||
1043 | int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g, | ||
1044 | struct channel_gk20a *ch, bool enable) | ||
1045 | { | ||
1046 | struct channel_ctx_gk20a *ch_ctx = &ch->ch_ctx; | ||
1047 | struct pm_ctx_desc *pm_ctx = &ch_ctx->pm_ctx; | ||
1048 | struct tegra_vgpu_cmd_msg msg; | ||
1049 | struct tegra_vgpu_channel_set_ctxsw_mode *p = &msg.params.set_ctxsw_mode; | ||
1050 | int err; | ||
1051 | |||
1052 | gk20a_dbg_fn(""); | ||
1053 | |||
1054 | if (enable) { | ||
1055 | p->mode = TEGRA_VGPU_CTXSW_MODE_CTXSW; | ||
1056 | |||
1057 | /* Allocate buffer if necessary */ | ||
1058 | if (pm_ctx->mem.gpu_va == 0) { | ||
1059 | pm_ctx->mem.gpu_va = __nvgpu_vm_alloc_va(ch->vm, | ||
1060 | g->gr.ctx_vars.pm_ctxsw_image_size, | ||
1061 | gmmu_page_size_kernel); | ||
1062 | |||
1063 | if (!pm_ctx->mem.gpu_va) | ||
1064 | return -ENOMEM; | ||
1065 | pm_ctx->mem.size = g->gr.ctx_vars.pm_ctxsw_image_size; | ||
1066 | } | ||
1067 | } else | ||
1068 | p->mode = TEGRA_VGPU_CTXSW_MODE_NO_CTXSW; | ||
1069 | |||
1070 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_HWPM_CTXSW_MODE; | ||
1071 | msg.handle = vgpu_get_handle(g); | ||
1072 | p->handle = ch->virt_ctx; | ||
1073 | p->gpu_va = pm_ctx->mem.gpu_va; | ||
1074 | |||
1075 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
1076 | WARN_ON(err || msg.ret); | ||
1077 | |||
1078 | return err ? err : msg.ret; | ||
1079 | } | ||
1080 | |||
1081 | int vgpu_gr_clear_sm_error_state(struct gk20a *g, | ||
1082 | struct channel_gk20a *ch, u32 sm_id) | ||
1083 | { | ||
1084 | struct gr_gk20a *gr = &g->gr; | ||
1085 | struct tegra_vgpu_cmd_msg msg; | ||
1086 | struct tegra_vgpu_clear_sm_error_state *p = | ||
1087 | &msg.params.clear_sm_error_state; | ||
1088 | int err; | ||
1089 | |||
1090 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); | ||
1091 | msg.cmd = TEGRA_VGPU_CMD_CLEAR_SM_ERROR_STATE; | ||
1092 | msg.handle = vgpu_get_handle(g); | ||
1093 | p->handle = ch->virt_ctx; | ||
1094 | p->sm_id = sm_id; | ||
1095 | |||
1096 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
1097 | WARN_ON(err || msg.ret); | ||
1098 | |||
1099 | memset(&gr->sm_error_states[sm_id], 0, sizeof(*gr->sm_error_states)); | ||
1100 | nvgpu_mutex_release(&g->dbg_sessions_lock); | ||
1101 | |||
1102 | return err ? err : msg.ret; | ||
1103 | |||
1104 | |||
1105 | return 0; | ||
1106 | } | ||
1107 | |||
1108 | static int vgpu_gr_suspend_resume_contexts(struct gk20a *g, | ||
1109 | struct dbg_session_gk20a *dbg_s, | ||
1110 | int *ctx_resident_ch_fd, u32 cmd) | ||
1111 | { | ||
1112 | struct dbg_session_channel_data *ch_data; | ||
1113 | struct tegra_vgpu_cmd_msg msg; | ||
1114 | struct tegra_vgpu_suspend_resume_contexts *p; | ||
1115 | size_t n; | ||
1116 | int channel_fd = -1; | ||
1117 | int err = 0; | ||
1118 | void *handle = NULL; | ||
1119 | u16 *oob; | ||
1120 | size_t oob_size; | ||
1121 | |||
1122 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); | ||
1123 | nvgpu_mutex_acquire(&dbg_s->ch_list_lock); | ||
1124 | |||
1125 | handle = tegra_gr_comm_oob_get_ptr(TEGRA_GR_COMM_CTX_CLIENT, | ||
1126 | tegra_gr_comm_get_server_vmid(), TEGRA_VGPU_QUEUE_CMD, | ||
1127 | (void **)&oob, &oob_size); | ||
1128 | if (!handle) { | ||
1129 | err = -EINVAL; | ||
1130 | goto done; | ||
1131 | } | ||
1132 | |||
1133 | n = 0; | ||
1134 | list_for_each_entry(ch_data, &dbg_s->ch_list, ch_entry) | ||
1135 | n++; | ||
1136 | |||
1137 | if (oob_size < n * sizeof(u16)) { | ||
1138 | err = -ENOMEM; | ||
1139 | goto done; | ||
1140 | } | ||
1141 | |||
1142 | msg.cmd = cmd; | ||
1143 | msg.handle = vgpu_get_handle(g); | ||
1144 | p = &msg.params.suspend_contexts; | ||
1145 | p->num_channels = n; | ||
1146 | n = 0; | ||
1147 | list_for_each_entry(ch_data, &dbg_s->ch_list, ch_entry) | ||
1148 | oob[n++] = (u16)ch_data->chid; | ||
1149 | |||
1150 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
1151 | if (err || msg.ret) { | ||
1152 | err = -ENOMEM; | ||
1153 | goto done; | ||
1154 | } | ||
1155 | |||
1156 | if (p->resident_chid != (u16)~0) { | ||
1157 | list_for_each_entry(ch_data, &dbg_s->ch_list, ch_entry) { | ||
1158 | if (ch_data->chid == p->resident_chid) { | ||
1159 | channel_fd = ch_data->channel_fd; | ||
1160 | break; | ||
1161 | } | ||
1162 | } | ||
1163 | } | ||
1164 | |||
1165 | done: | ||
1166 | if (handle) | ||
1167 | tegra_gr_comm_oob_put_ptr(handle); | ||
1168 | nvgpu_mutex_release(&dbg_s->ch_list_lock); | ||
1169 | nvgpu_mutex_release(&g->dbg_sessions_lock); | ||
1170 | *ctx_resident_ch_fd = channel_fd; | ||
1171 | return err; | ||
1172 | } | ||
1173 | |||
1174 | int vgpu_gr_suspend_contexts(struct gk20a *g, | ||
1175 | struct dbg_session_gk20a *dbg_s, | ||
1176 | int *ctx_resident_ch_fd) | ||
1177 | { | ||
1178 | return vgpu_gr_suspend_resume_contexts(g, dbg_s, | ||
1179 | ctx_resident_ch_fd, TEGRA_VGPU_CMD_SUSPEND_CONTEXTS); | ||
1180 | } | ||
1181 | |||
1182 | int vgpu_gr_resume_contexts(struct gk20a *g, | ||
1183 | struct dbg_session_gk20a *dbg_s, | ||
1184 | int *ctx_resident_ch_fd) | ||
1185 | { | ||
1186 | return vgpu_gr_suspend_resume_contexts(g, dbg_s, | ||
1187 | ctx_resident_ch_fd, TEGRA_VGPU_CMD_RESUME_CONTEXTS); | ||
1188 | } | ||
1189 | |||
1190 | void vgpu_gr_handle_sm_esr_event(struct gk20a *g, | ||
1191 | struct tegra_vgpu_sm_esr_info *info) | ||
1192 | { | ||
1193 | struct nvgpu_gr_sm_error_state *sm_error_states; | ||
1194 | |||
1195 | if (info->sm_id >= g->gr.no_of_sm) { | ||
1196 | nvgpu_err(g, "invalid smd_id %d / %d", | ||
1197 | info->sm_id, g->gr.no_of_sm); | ||
1198 | return; | ||
1199 | } | ||
1200 | |||
1201 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); | ||
1202 | |||
1203 | sm_error_states = &g->gr.sm_error_states[info->sm_id]; | ||
1204 | |||
1205 | sm_error_states->hww_global_esr = info->hww_global_esr; | ||
1206 | sm_error_states->hww_warp_esr = info->hww_warp_esr; | ||
1207 | sm_error_states->hww_warp_esr_pc = info->hww_warp_esr_pc; | ||
1208 | sm_error_states->hww_global_esr_report_mask = | ||
1209 | info->hww_global_esr_report_mask; | ||
1210 | sm_error_states->hww_warp_esr_report_mask = | ||
1211 | info->hww_warp_esr_report_mask; | ||
1212 | |||
1213 | nvgpu_mutex_release(&g->dbg_sessions_lock); | ||
1214 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.h b/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.h new file mode 100644 index 00000000..7815201e --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gr_vgpu.h | |||
@@ -0,0 +1,64 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #ifndef _GR_VGPU_H_ | ||
18 | #define _GR_VGPU_H_ | ||
19 | |||
20 | #include <nvgpu/types.h> | ||
21 | |||
22 | struct gk20a; | ||
23 | struct channel_gk20a; | ||
24 | struct gr_gk20a; | ||
25 | struct gr_zcull_info; | ||
26 | struct zbc_entry; | ||
27 | struct zbc_query_params; | ||
28 | struct dbg_session_gk20a; | ||
29 | |||
30 | void vgpu_gr_detect_sm_arch(struct gk20a *g); | ||
31 | void vgpu_gr_free_channel_ctx(struct channel_gk20a *c, bool is_tsg); | ||
32 | int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags); | ||
33 | int vgpu_gr_bind_ctxsw_zcull(struct gk20a *g, struct gr_gk20a *gr, | ||
34 | struct channel_gk20a *c, u64 zcull_va, | ||
35 | u32 mode); | ||
36 | int vgpu_gr_get_zcull_info(struct gk20a *g, struct gr_gk20a *gr, | ||
37 | struct gr_zcull_info *zcull_params); | ||
38 | u32 vgpu_gr_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index); | ||
39 | u32 vgpu_gr_get_max_fbps_count(struct gk20a *g); | ||
40 | u32 vgpu_gr_get_fbp_en_mask(struct gk20a *g); | ||
41 | u32 vgpu_gr_get_max_ltc_per_fbp(struct gk20a *g); | ||
42 | u32 vgpu_gr_get_max_lts_per_ltc(struct gk20a *g); | ||
43 | u32 *vgpu_gr_rop_l2_en_mask(struct gk20a *g); | ||
44 | int vgpu_gr_add_zbc(struct gk20a *g, struct gr_gk20a *gr, | ||
45 | struct zbc_entry *zbc_val); | ||
46 | int vgpu_gr_query_zbc(struct gk20a *g, struct gr_gk20a *gr, | ||
47 | struct zbc_query_params *query_params); | ||
48 | int vgpu_gr_set_sm_debug_mode(struct gk20a *g, | ||
49 | struct channel_gk20a *ch, u64 sms, bool enable); | ||
50 | int vgpu_gr_update_smpc_ctxsw_mode(struct gk20a *g, | ||
51 | struct channel_gk20a *ch, bool enable); | ||
52 | int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g, | ||
53 | struct channel_gk20a *ch, bool enable); | ||
54 | int vgpu_gr_clear_sm_error_state(struct gk20a *g, | ||
55 | struct channel_gk20a *ch, u32 sm_id); | ||
56 | int vgpu_gr_suspend_contexts(struct gk20a *g, | ||
57 | struct dbg_session_gk20a *dbg_s, | ||
58 | int *ctx_resident_ch_fd); | ||
59 | int vgpu_gr_resume_contexts(struct gk20a *g, | ||
60 | struct dbg_session_gk20a *dbg_s, | ||
61 | int *ctx_resident_ch_fd); | ||
62 | int vgpu_gr_commit_inst(struct channel_gk20a *c, u64 gpu_va); | ||
63 | |||
64 | #endif | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/platform_gv11b_vgpu_tegra.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/platform_gv11b_vgpu_tegra.c new file mode 100644 index 00000000..3b9d63e8 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/platform_gv11b_vgpu_tegra.c | |||
@@ -0,0 +1,99 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include "gk20a/gk20a.h" | ||
18 | #include "common/linux/vgpu/clk_vgpu.h" | ||
19 | #include "common/linux/platform_gk20a.h" | ||
20 | #include "common/linux/os_linux.h" | ||
21 | |||
22 | #include <nvgpu/nvhost.h> | ||
23 | #include <nvgpu/nvhost_t19x.h> | ||
24 | |||
25 | #include <linux/platform_device.h> | ||
26 | |||
27 | static int gv11b_vgpu_probe(struct device *dev) | ||
28 | { | ||
29 | struct platform_device *pdev = to_platform_device(dev); | ||
30 | struct gk20a_platform *platform = dev_get_drvdata(dev); | ||
31 | struct resource *r; | ||
32 | void __iomem *regs; | ||
33 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(platform->g); | ||
34 | struct gk20a *g = platform->g; | ||
35 | int ret; | ||
36 | |||
37 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "usermode"); | ||
38 | if (!r) { | ||
39 | dev_err(dev, "failed to get usermode regs\n"); | ||
40 | return -ENXIO; | ||
41 | } | ||
42 | regs = devm_ioremap_resource(dev, r); | ||
43 | if (IS_ERR(regs)) { | ||
44 | dev_err(dev, "failed to map usermode regs\n"); | ||
45 | return PTR_ERR(regs); | ||
46 | } | ||
47 | l->t19x.usermode_regs = regs; | ||
48 | |||
49 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | ||
50 | ret = nvgpu_get_nvhost_dev(g); | ||
51 | if (ret) { | ||
52 | l->t19x.usermode_regs = NULL; | ||
53 | return ret; | ||
54 | } | ||
55 | |||
56 | ret = nvgpu_nvhost_syncpt_unit_interface_get_aperture(g->nvhost_dev, | ||
57 | &g->syncpt_unit_base, | ||
58 | &g->syncpt_unit_size); | ||
59 | if (ret) { | ||
60 | dev_err(dev, "Failed to get syncpt interface"); | ||
61 | return -ENOSYS; | ||
62 | } | ||
63 | g->syncpt_size = nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(1); | ||
64 | nvgpu_info(g, "syncpt_unit_base %llx syncpt_unit_size %zx size %x\n", | ||
65 | g->syncpt_unit_base, g->syncpt_unit_size, g->syncpt_size); | ||
66 | #endif | ||
67 | vgpu_init_clk_support(platform->g); | ||
68 | |||
69 | return 0; | ||
70 | } | ||
71 | |||
72 | struct gk20a_platform gv11b_vgpu_tegra_platform = { | ||
73 | .has_syncpoints = true, | ||
74 | .aggressive_sync_destroy_thresh = 64, | ||
75 | |||
76 | /* power management configuration */ | ||
77 | .can_railgate_init = false, | ||
78 | .can_elpg_init = false, | ||
79 | .enable_slcg = false, | ||
80 | .enable_blcg = false, | ||
81 | .enable_elcg = false, | ||
82 | .enable_elpg = false, | ||
83 | .enable_aelpg = false, | ||
84 | .can_slcg = false, | ||
85 | .can_blcg = false, | ||
86 | .can_elcg = false, | ||
87 | |||
88 | .ch_wdt_timeout_ms = 5000, | ||
89 | |||
90 | .probe = gv11b_vgpu_probe, | ||
91 | |||
92 | .clk_round_rate = vgpu_clk_round_rate, | ||
93 | .get_clk_freqs = vgpu_clk_get_freqs, | ||
94 | |||
95 | /* frequency scaling configuration */ | ||
96 | .devfreq_governor = "userspace", | ||
97 | |||
98 | .virtual_dev = true, | ||
99 | }; | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.c new file mode 100644 index 00000000..710e4b90 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.c | |||
@@ -0,0 +1,111 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include <gk20a/gk20a.h> | ||
18 | |||
19 | #include "common/linux/vgpu/vgpu.h" | ||
20 | #include "gv11b/fifo_gv11b.h" | ||
21 | #include <nvgpu/nvhost_t19x.h> | ||
22 | |||
23 | #include <linux/tegra_vgpu.h> | ||
24 | |||
25 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | ||
26 | int vgpu_gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, | ||
27 | u32 syncpt_id, struct nvgpu_mem *syncpt_buf) | ||
28 | { | ||
29 | int err; | ||
30 | struct gk20a *g = c->g; | ||
31 | struct vm_gk20a *vm = c->vm; | ||
32 | struct tegra_vgpu_cmd_msg msg = {}; | ||
33 | struct tegra_vgpu_map_syncpt_params *p = &msg.params.t19x.map_syncpt; | ||
34 | |||
35 | /* | ||
36 | * Add ro map for complete sync point shim range in vm. | ||
37 | * All channels sharing same vm will share same ro mapping. | ||
38 | * Create rw map for current channel sync point. | ||
39 | */ | ||
40 | if (!vm->syncpt_ro_map_gpu_va) { | ||
41 | vm->syncpt_ro_map_gpu_va = __nvgpu_vm_alloc_va(vm, | ||
42 | g->syncpt_unit_size, | ||
43 | gmmu_page_size_kernel); | ||
44 | if (!vm->syncpt_ro_map_gpu_va) { | ||
45 | nvgpu_err(g, "allocating read-only va space failed"); | ||
46 | return -ENOMEM; | ||
47 | } | ||
48 | |||
49 | msg.cmd = TEGRA_VGPU_CMD_MAP_SYNCPT; | ||
50 | msg.handle = vgpu_get_handle(g); | ||
51 | p->as_handle = c->vm->handle; | ||
52 | p->gpu_va = vm->syncpt_ro_map_gpu_va; | ||
53 | p->len = g->syncpt_unit_size; | ||
54 | p->offset = 0; | ||
55 | p->prot = TEGRA_VGPU_MAP_PROT_READ_ONLY; | ||
56 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
57 | err = err ? err : msg.ret; | ||
58 | if (err) { | ||
59 | nvgpu_err(g, | ||
60 | "mapping read-only va space failed err %d", | ||
61 | err); | ||
62 | __nvgpu_vm_free_va(c->vm, vm->syncpt_ro_map_gpu_va, | ||
63 | gmmu_page_size_kernel); | ||
64 | vm->syncpt_ro_map_gpu_va = 0; | ||
65 | return err; | ||
66 | } | ||
67 | } | ||
68 | |||
69 | syncpt_buf->gpu_va = __nvgpu_vm_alloc_va(c->vm, g->syncpt_size, | ||
70 | gmmu_page_size_kernel); | ||
71 | if (!syncpt_buf->gpu_va) { | ||
72 | nvgpu_err(g, "allocating syncpt va space failed"); | ||
73 | return -ENOMEM; | ||
74 | } | ||
75 | |||
76 | msg.cmd = TEGRA_VGPU_CMD_MAP_SYNCPT; | ||
77 | msg.handle = vgpu_get_handle(g); | ||
78 | p->as_handle = c->vm->handle; | ||
79 | p->gpu_va = syncpt_buf->gpu_va; | ||
80 | p->len = g->syncpt_size; | ||
81 | p->offset = | ||
82 | nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(syncpt_id); | ||
83 | p->prot = TEGRA_VGPU_MAP_PROT_NONE; | ||
84 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
85 | err = err ? err : msg.ret; | ||
86 | if (err) { | ||
87 | nvgpu_err(g, "mapping syncpt va space failed err %d", err); | ||
88 | __nvgpu_vm_free_va(c->vm, syncpt_buf->gpu_va, | ||
89 | gmmu_page_size_kernel); | ||
90 | return err; | ||
91 | } | ||
92 | |||
93 | return 0; | ||
94 | } | ||
95 | #endif /* CONFIG_TEGRA_GK20A_NVHOST */ | ||
96 | |||
97 | int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g) | ||
98 | { | ||
99 | struct fifo_gk20a *f = &g->fifo; | ||
100 | int err; | ||
101 | |||
102 | err = vgpu_get_attribute(vgpu_get_handle(g), | ||
103 | TEGRA_VGPU_ATTRIB_MAX_SUBCTX_COUNT, | ||
104 | &f->t19x.max_subctx_count); | ||
105 | if (err) { | ||
106 | nvgpu_err(g, "get max_subctx_count failed %d", err); | ||
107 | return err; | ||
108 | } | ||
109 | |||
110 | return 0; | ||
111 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.h b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.h new file mode 100644 index 00000000..c2e75680 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #ifndef _VGPU_FIFO_GV11B_H_ | ||
18 | #define _VGPU_FIFO_GV11B_H_ | ||
19 | |||
20 | struct gk20a; | ||
21 | |||
22 | int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g); | ||
23 | int vgpu_gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, | ||
24 | u32 syncpt_id, struct nvgpu_mem *syncpt_buf); | ||
25 | #endif | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gr_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gr_gv11b.c new file mode 100644 index 00000000..69e5b2ce --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gr_gv11b.c | |||
@@ -0,0 +1,34 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include "gk20a/gk20a.h" | ||
18 | #include "common/linux/vgpu/gr_vgpu.h" | ||
19 | #include "vgpu_subctx_gv11b.h" | ||
20 | |||
21 | int vgpu_gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va) | ||
22 | { | ||
23 | int err; | ||
24 | |||
25 | err = vgpu_gv11b_alloc_subctx_header(c); | ||
26 | if (err) | ||
27 | return err; | ||
28 | |||
29 | err = vgpu_gr_commit_inst(c, gpu_va); | ||
30 | if (err) | ||
31 | vgpu_gv11b_free_subctx_header(c); | ||
32 | |||
33 | return err; | ||
34 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gr_gv11b.h b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gr_gv11b.h new file mode 100644 index 00000000..0208012d --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gr_gv11b.h | |||
@@ -0,0 +1,24 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #ifndef _VGPU_GR_GV11B_H_ | ||
18 | #define _VGPU_GR_GV11B_H_ | ||
19 | |||
20 | struct channel_gk20a; | ||
21 | |||
22 | int vgpu_gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va); | ||
23 | |||
24 | #endif | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.c new file mode 100644 index 00000000..9ba1892b --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.c | |||
@@ -0,0 +1,40 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include "gk20a/gk20a.h" | ||
18 | |||
19 | #include <nvgpu/enabled.h> | ||
20 | #include <nvgpu/enabled_t19x.h> | ||
21 | |||
22 | #include "common/linux/vgpu/vgpu.h" | ||
23 | #include "vgpu_gv11b.h" | ||
24 | |||
25 | int vgpu_gv11b_init_gpu_characteristics(struct gk20a *g) | ||
26 | { | ||
27 | int err; | ||
28 | |||
29 | gk20a_dbg_fn(""); | ||
30 | |||
31 | err = vgpu_init_gpu_characteristics(g); | ||
32 | if (err) { | ||
33 | nvgpu_err(g, "vgpu_init_gpu_characteristics failed, err %d\n", err); | ||
34 | return err; | ||
35 | } | ||
36 | |||
37 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true); | ||
38 | |||
39 | return 0; | ||
40 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.h b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.h new file mode 100644 index 00000000..84ebfa17 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.h | |||
@@ -0,0 +1,24 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #ifndef _VGPU_GV11B_H_ | ||
18 | #define _VGPU_GV11B_H_ | ||
19 | |||
20 | struct gk20a; | ||
21 | |||
22 | int vgpu_gv11b_init_gpu_characteristics(struct gk20a *g); | ||
23 | |||
24 | #endif | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c new file mode 100644 index 00000000..6b5a1b0d --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c | |||
@@ -0,0 +1,637 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include <gk20a/gk20a.h> | ||
18 | #include <gv11b/hal_gv11b.h> | ||
19 | |||
20 | #include "common/linux/vgpu/vgpu.h" | ||
21 | #include "common/linux/vgpu/fifo_vgpu.h" | ||
22 | #include "common/linux/vgpu/gr_vgpu.h" | ||
23 | #include "common/linux/vgpu/ltc_vgpu.h" | ||
24 | #include "common/linux/vgpu/mm_vgpu.h" | ||
25 | #include "common/linux/vgpu/dbg_vgpu.h" | ||
26 | #include "common/linux/vgpu/fecs_trace_vgpu.h" | ||
27 | #include "common/linux/vgpu/css_vgpu.h" | ||
28 | #include "common/linux/vgpu/vgpu_t19x.h" | ||
29 | #include "common/linux/vgpu/gm20b/vgpu_gr_gm20b.h" | ||
30 | #include "common/linux/vgpu/gp10b/vgpu_mm_gp10b.h" | ||
31 | #include "common/linux/vgpu/gp10b/vgpu_gr_gp10b.h" | ||
32 | |||
33 | #include <gk20a/fb_gk20a.h> | ||
34 | #include <gk20a/flcn_gk20a.h> | ||
35 | #include <gk20a/bus_gk20a.h> | ||
36 | #include <gk20a/mc_gk20a.h> | ||
37 | |||
38 | #include <gm20b/gr_gm20b.h> | ||
39 | #include <gm20b/fb_gm20b.h> | ||
40 | #include <gm20b/fifo_gm20b.h> | ||
41 | #include <gm20b/pmu_gm20b.h> | ||
42 | #include <gm20b/mm_gm20b.h> | ||
43 | #include <gm20b/acr_gm20b.h> | ||
44 | #include <gm20b/ltc_gm20b.h> | ||
45 | |||
46 | #include <gp10b/fb_gp10b.h> | ||
47 | #include <gp10b/pmu_gp10b.h> | ||
48 | #include <gp10b/mm_gp10b.h> | ||
49 | #include <gp10b/mc_gp10b.h> | ||
50 | #include <gp10b/ce_gp10b.h> | ||
51 | #include <gp10b/fifo_gp10b.h> | ||
52 | #include <gp10b/therm_gp10b.h> | ||
53 | #include <gp10b/priv_ring_gp10b.h> | ||
54 | #include <gp10b/ltc_gp10b.h> | ||
55 | |||
56 | #include <gp106/pmu_gp106.h> | ||
57 | #include <gp106/acr_gp106.h> | ||
58 | |||
59 | #include <gv11b/fb_gv11b.h> | ||
60 | #include <gv11b/pmu_gv11b.h> | ||
61 | #include <gv11b/acr_gv11b.h> | ||
62 | #include <gv11b/mm_gv11b.h> | ||
63 | #include <gv11b/mc_gv11b.h> | ||
64 | #include <gv11b/ce_gv11b.h> | ||
65 | #include <gv11b/fifo_gv11b.h> | ||
66 | #include <gv11b/therm_gv11b.h> | ||
67 | #include <gv11b/regops_gv11b.h> | ||
68 | #include <gv11b/gr_ctx_gv11b.h> | ||
69 | #include <gv11b/ltc_gv11b.h> | ||
70 | #include <gv11b/gv11b_gating_reglist.h> | ||
71 | |||
72 | #include <gv100/gr_gv100.h> | ||
73 | |||
74 | #include <nvgpu/enabled.h> | ||
75 | |||
76 | #include "vgpu_gv11b.h" | ||
77 | #include "vgpu_gr_gv11b.h" | ||
78 | #include "vgpu_fifo_gv11b.h" | ||
79 | #include "vgpu_subctx_gv11b.h" | ||
80 | #include "vgpu_tsg_gv11b.h" | ||
81 | |||
82 | #include <nvgpu/hw/gv11b/hw_fuse_gv11b.h> | ||
83 | #include <nvgpu/hw/gv11b/hw_fifo_gv11b.h> | ||
84 | #include <nvgpu/hw/gv11b/hw_ram_gv11b.h> | ||
85 | #include <nvgpu/hw/gv11b/hw_top_gv11b.h> | ||
86 | #include <nvgpu/hw/gv11b/hw_pwr_gv11b.h> | ||
87 | |||
88 | static const struct gpu_ops vgpu_gv11b_ops = { | ||
89 | .ltc = { | ||
90 | .determine_L2_size_bytes = vgpu_determine_L2_size_bytes, | ||
91 | .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry, | ||
92 | .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, | ||
93 | .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, | ||
94 | .init_cbc = NULL, | ||
95 | .init_fs_state = vgpu_ltc_init_fs_state, | ||
96 | .init_comptags = vgpu_ltc_init_comptags, | ||
97 | .cbc_ctrl = NULL, | ||
98 | .isr = gv11b_ltc_isr, | ||
99 | .cbc_fix_config = gv11b_ltc_cbc_fix_config, | ||
100 | .flush = gm20b_flush_ltc, | ||
101 | .set_enabled = gp10b_ltc_set_enabled, | ||
102 | }, | ||
103 | .ce2 = { | ||
104 | .isr_stall = gv11b_ce_isr, | ||
105 | .isr_nonstall = gp10b_ce_nonstall_isr, | ||
106 | .get_num_pce = vgpu_ce_get_num_pce, | ||
107 | }, | ||
108 | .gr = { | ||
109 | .init_gpc_mmu = gr_gv11b_init_gpc_mmu, | ||
110 | .bundle_cb_defaults = gr_gv11b_bundle_cb_defaults, | ||
111 | .cb_size_default = gr_gv11b_cb_size_default, | ||
112 | .calc_global_ctx_buffer_size = | ||
113 | gr_gv11b_calc_global_ctx_buffer_size, | ||
114 | .commit_global_attrib_cb = gr_gv11b_commit_global_attrib_cb, | ||
115 | .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb, | ||
116 | .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager, | ||
117 | .commit_global_pagepool = gr_gp10b_commit_global_pagepool, | ||
118 | .handle_sw_method = gr_gv11b_handle_sw_method, | ||
119 | .set_alpha_circular_buffer_size = | ||
120 | gr_gv11b_set_alpha_circular_buffer_size, | ||
121 | .set_circular_buffer_size = gr_gv11b_set_circular_buffer_size, | ||
122 | .enable_hww_exceptions = gr_gv11b_enable_hww_exceptions, | ||
123 | .is_valid_class = gr_gv11b_is_valid_class, | ||
124 | .is_valid_gfx_class = gr_gv11b_is_valid_gfx_class, | ||
125 | .is_valid_compute_class = gr_gv11b_is_valid_compute_class, | ||
126 | .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs, | ||
127 | .get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs, | ||
128 | .init_fs_state = vgpu_gm20b_init_fs_state, | ||
129 | .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask, | ||
130 | .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, | ||
131 | .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode, | ||
132 | .set_gpc_tpc_mask = gr_gv11b_set_gpc_tpc_mask, | ||
133 | .get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask, | ||
134 | .free_channel_ctx = vgpu_gr_free_channel_ctx, | ||
135 | .alloc_obj_ctx = vgpu_gr_alloc_obj_ctx, | ||
136 | .bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull, | ||
137 | .get_zcull_info = vgpu_gr_get_zcull_info, | ||
138 | .is_tpc_addr = gr_gm20b_is_tpc_addr, | ||
139 | .get_tpc_num = gr_gm20b_get_tpc_num, | ||
140 | .detect_sm_arch = vgpu_gr_detect_sm_arch, | ||
141 | .add_zbc_color = gr_gp10b_add_zbc_color, | ||
142 | .add_zbc_depth = gr_gp10b_add_zbc_depth, | ||
143 | .zbc_set_table = vgpu_gr_add_zbc, | ||
144 | .zbc_query_table = vgpu_gr_query_zbc, | ||
145 | .pmu_save_zbc = gk20a_pmu_save_zbc, | ||
146 | .add_zbc = gr_gk20a_add_zbc, | ||
147 | .pagepool_default_size = gr_gv11b_pagepool_default_size, | ||
148 | .init_ctx_state = vgpu_gr_gp10b_init_ctx_state, | ||
149 | .alloc_gr_ctx = vgpu_gr_gp10b_alloc_gr_ctx, | ||
150 | .free_gr_ctx = vgpu_gr_gp10b_free_gr_ctx, | ||
151 | .update_ctxsw_preemption_mode = | ||
152 | gr_gp10b_update_ctxsw_preemption_mode, | ||
153 | .dump_gr_regs = NULL, | ||
154 | .update_pc_sampling = gr_gm20b_update_pc_sampling, | ||
155 | .get_fbp_en_mask = vgpu_gr_get_fbp_en_mask, | ||
156 | .get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp, | ||
157 | .get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc, | ||
158 | .get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask, | ||
159 | .get_max_fbps_count = vgpu_gr_get_max_fbps_count, | ||
160 | .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info, | ||
161 | .wait_empty = gr_gv11b_wait_empty, | ||
162 | .init_cyclestats = vgpu_gr_gm20b_init_cyclestats, | ||
163 | .set_sm_debug_mode = vgpu_gr_set_sm_debug_mode, | ||
164 | .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs, | ||
165 | .bpt_reg_info = gv11b_gr_bpt_reg_info, | ||
166 | .get_access_map = gr_gv11b_get_access_map, | ||
167 | .handle_fecs_error = gr_gv11b_handle_fecs_error, | ||
168 | .handle_sm_exception = gr_gk20a_handle_sm_exception, | ||
169 | .handle_tex_exception = gr_gv11b_handle_tex_exception, | ||
170 | .enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions, | ||
171 | .enable_exceptions = gr_gv11b_enable_exceptions, | ||
172 | .get_lrf_tex_ltc_dram_override = get_ecc_override_val, | ||
173 | .update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode, | ||
174 | .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode, | ||
175 | .record_sm_error_state = gv11b_gr_record_sm_error_state, | ||
176 | .update_sm_error_state = gv11b_gr_update_sm_error_state, | ||
177 | .clear_sm_error_state = vgpu_gr_clear_sm_error_state, | ||
178 | .suspend_contexts = vgpu_gr_suspend_contexts, | ||
179 | .resume_contexts = vgpu_gr_resume_contexts, | ||
180 | .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, | ||
181 | .init_sm_id_table = gr_gv100_init_sm_id_table, | ||
182 | .load_smid_config = gr_gv11b_load_smid_config, | ||
183 | .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering, | ||
184 | .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, | ||
185 | .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr, | ||
186 | .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr, | ||
187 | .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr, | ||
188 | .setup_rop_mapping = gr_gv11b_setup_rop_mapping, | ||
189 | .program_zcull_mapping = gr_gv11b_program_zcull_mapping, | ||
190 | .commit_global_timeslice = gr_gv11b_commit_global_timeslice, | ||
191 | .commit_inst = vgpu_gr_gv11b_commit_inst, | ||
192 | .write_zcull_ptr = gr_gv11b_write_zcull_ptr, | ||
193 | .write_pm_ptr = gr_gv11b_write_pm_ptr, | ||
194 | .init_elcg_mode = gr_gv11b_init_elcg_mode, | ||
195 | .load_tpc_mask = gr_gv11b_load_tpc_mask, | ||
196 | .inval_icache = gr_gk20a_inval_icache, | ||
197 | .trigger_suspend = gv11b_gr_sm_trigger_suspend, | ||
198 | .wait_for_pause = gr_gk20a_wait_for_pause, | ||
199 | .resume_from_pause = gv11b_gr_resume_from_pause, | ||
200 | .clear_sm_errors = gr_gk20a_clear_sm_errors, | ||
201 | .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions, | ||
202 | .get_esr_sm_sel = gv11b_gr_get_esr_sm_sel, | ||
203 | .sm_debugger_attached = gv11b_gr_sm_debugger_attached, | ||
204 | .suspend_single_sm = gv11b_gr_suspend_single_sm, | ||
205 | .suspend_all_sms = gv11b_gr_suspend_all_sms, | ||
206 | .resume_single_sm = gv11b_gr_resume_single_sm, | ||
207 | .resume_all_sms = gv11b_gr_resume_all_sms, | ||
208 | .get_sm_hww_warp_esr = gv11b_gr_get_sm_hww_warp_esr, | ||
209 | .get_sm_hww_global_esr = gv11b_gr_get_sm_hww_global_esr, | ||
210 | .get_sm_no_lock_down_hww_global_esr_mask = | ||
211 | gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask, | ||
212 | .lock_down_sm = gv11b_gr_lock_down_sm, | ||
213 | .wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down, | ||
214 | .clear_sm_hww = gv11b_gr_clear_sm_hww, | ||
215 | .init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf, | ||
216 | .get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs, | ||
217 | .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce, | ||
218 | .set_boosted_ctx = NULL, | ||
219 | .set_preemption_mode = vgpu_gr_gp10b_set_preemption_mode, | ||
220 | .set_czf_bypass = NULL, | ||
221 | .pre_process_sm_exception = gr_gv11b_pre_process_sm_exception, | ||
222 | .set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va, | ||
223 | .init_preemption_state = NULL, | ||
224 | .update_boosted_ctx = NULL, | ||
225 | .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3, | ||
226 | .create_gr_sysfs = gr_gv11b_create_sysfs, | ||
227 | .set_ctxsw_preemption_mode = vgpu_gr_gp10b_set_ctxsw_preemption_mode, | ||
228 | .is_etpc_addr = gv11b_gr_pri_is_etpc_addr, | ||
229 | .egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table, | ||
230 | .handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception, | ||
231 | .zbc_s_query_table = gr_gv11b_zbc_s_query_table, | ||
232 | .load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl, | ||
233 | .handle_gpc_gpcmmu_exception = | ||
234 | gr_gv11b_handle_gpc_gpcmmu_exception, | ||
235 | .add_zbc_type_s = gr_gv11b_add_zbc_type_s, | ||
236 | .get_egpc_base = gv11b_gr_get_egpc_base, | ||
237 | .get_egpc_etpc_num = gv11b_gr_get_egpc_etpc_num, | ||
238 | .handle_gpc_gpccs_exception = | ||
239 | gr_gv11b_handle_gpc_gpccs_exception, | ||
240 | .load_zbc_s_tbl = gr_gv11b_load_stencil_tbl, | ||
241 | .access_smpc_reg = gv11b_gr_access_smpc_reg, | ||
242 | .is_egpc_addr = gv11b_gr_pri_is_egpc_addr, | ||
243 | .add_zbc_s = gr_gv11b_add_zbc_stencil, | ||
244 | .handle_gcc_exception = gr_gv11b_handle_gcc_exception, | ||
245 | .init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle, | ||
246 | .handle_tpc_sm_ecc_exception = | ||
247 | gr_gv11b_handle_tpc_sm_ecc_exception, | ||
248 | .decode_egpc_addr = gv11b_gr_decode_egpc_addr, | ||
249 | .init_ctxsw_hdr_data = gr_gp10b_init_ctxsw_hdr_data, | ||
250 | }, | ||
251 | .fb = { | ||
252 | .reset = gv11b_fb_reset, | ||
253 | .init_hw = gk20a_fb_init_hw, | ||
254 | .init_fs_state = gv11b_fb_init_fs_state, | ||
255 | .init_cbc = gv11b_fb_init_cbc, | ||
256 | .set_mmu_page_size = gm20b_fb_set_mmu_page_size, | ||
257 | .set_use_full_comp_tag_line = | ||
258 | gm20b_fb_set_use_full_comp_tag_line, | ||
259 | .compression_page_size = gp10b_fb_compression_page_size, | ||
260 | .compressible_page_size = gp10b_fb_compressible_page_size, | ||
261 | .vpr_info_fetch = gm20b_fb_vpr_info_fetch, | ||
262 | .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info, | ||
263 | .read_wpr_info = gm20b_fb_read_wpr_info, | ||
264 | .is_debug_mode_enabled = NULL, | ||
265 | .set_debug_mode = vgpu_mm_mmu_set_debug_mode, | ||
266 | .tlb_invalidate = vgpu_mm_tlb_invalidate, | ||
267 | .hub_isr = gv11b_fb_hub_isr, | ||
268 | }, | ||
269 | .clock_gating = { | ||
270 | .slcg_bus_load_gating_prod = | ||
271 | gv11b_slcg_bus_load_gating_prod, | ||
272 | .slcg_ce2_load_gating_prod = | ||
273 | gv11b_slcg_ce2_load_gating_prod, | ||
274 | .slcg_chiplet_load_gating_prod = | ||
275 | gv11b_slcg_chiplet_load_gating_prod, | ||
276 | .slcg_ctxsw_firmware_load_gating_prod = | ||
277 | gv11b_slcg_ctxsw_firmware_load_gating_prod, | ||
278 | .slcg_fb_load_gating_prod = | ||
279 | gv11b_slcg_fb_load_gating_prod, | ||
280 | .slcg_fifo_load_gating_prod = | ||
281 | gv11b_slcg_fifo_load_gating_prod, | ||
282 | .slcg_gr_load_gating_prod = | ||
283 | gr_gv11b_slcg_gr_load_gating_prod, | ||
284 | .slcg_ltc_load_gating_prod = | ||
285 | ltc_gv11b_slcg_ltc_load_gating_prod, | ||
286 | .slcg_perf_load_gating_prod = | ||
287 | gv11b_slcg_perf_load_gating_prod, | ||
288 | .slcg_priring_load_gating_prod = | ||
289 | gv11b_slcg_priring_load_gating_prod, | ||
290 | .slcg_pmu_load_gating_prod = | ||
291 | gv11b_slcg_pmu_load_gating_prod, | ||
292 | .slcg_therm_load_gating_prod = | ||
293 | gv11b_slcg_therm_load_gating_prod, | ||
294 | .slcg_xbar_load_gating_prod = | ||
295 | gv11b_slcg_xbar_load_gating_prod, | ||
296 | .blcg_bus_load_gating_prod = | ||
297 | gv11b_blcg_bus_load_gating_prod, | ||
298 | .blcg_ce_load_gating_prod = | ||
299 | gv11b_blcg_ce_load_gating_prod, | ||
300 | .blcg_ctxsw_firmware_load_gating_prod = | ||
301 | gv11b_blcg_ctxsw_firmware_load_gating_prod, | ||
302 | .blcg_fb_load_gating_prod = | ||
303 | gv11b_blcg_fb_load_gating_prod, | ||
304 | .blcg_fifo_load_gating_prod = | ||
305 | gv11b_blcg_fifo_load_gating_prod, | ||
306 | .blcg_gr_load_gating_prod = | ||
307 | gv11b_blcg_gr_load_gating_prod, | ||
308 | .blcg_ltc_load_gating_prod = | ||
309 | gv11b_blcg_ltc_load_gating_prod, | ||
310 | .blcg_pwr_csb_load_gating_prod = | ||
311 | gv11b_blcg_pwr_csb_load_gating_prod, | ||
312 | .blcg_pmu_load_gating_prod = | ||
313 | gv11b_blcg_pmu_load_gating_prod, | ||
314 | .blcg_xbar_load_gating_prod = | ||
315 | gv11b_blcg_xbar_load_gating_prod, | ||
316 | .pg_gr_load_gating_prod = | ||
317 | gr_gv11b_pg_gr_load_gating_prod, | ||
318 | }, | ||
319 | .fifo = { | ||
320 | .init_fifo_setup_hw = vgpu_gv11b_init_fifo_setup_hw, | ||
321 | .bind_channel = vgpu_channel_bind, | ||
322 | .unbind_channel = vgpu_channel_unbind, | ||
323 | .disable_channel = vgpu_channel_disable, | ||
324 | .enable_channel = vgpu_channel_enable, | ||
325 | .alloc_inst = vgpu_channel_alloc_inst, | ||
326 | .free_inst = vgpu_channel_free_inst, | ||
327 | .setup_ramfc = vgpu_channel_setup_ramfc, | ||
328 | .channel_set_timeslice = vgpu_channel_set_timeslice, | ||
329 | .default_timeslice_us = vgpu_fifo_default_timeslice_us, | ||
330 | .setup_userd = gk20a_fifo_setup_userd, | ||
331 | .userd_gp_get = gv11b_userd_gp_get, | ||
332 | .userd_gp_put = gv11b_userd_gp_put, | ||
333 | .userd_pb_get = gv11b_userd_pb_get, | ||
334 | .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, | ||
335 | .preempt_channel = vgpu_fifo_preempt_channel, | ||
336 | .preempt_tsg = vgpu_fifo_preempt_tsg, | ||
337 | .enable_tsg = vgpu_enable_tsg, | ||
338 | .disable_tsg = gk20a_disable_tsg, | ||
339 | .tsg_verify_channel_status = NULL, | ||
340 | .tsg_verify_status_ctx_reload = NULL, | ||
341 | /* TODO: implement it for CE fault */ | ||
342 | .tsg_verify_status_faulted = NULL, | ||
343 | .update_runlist = vgpu_fifo_update_runlist, | ||
344 | .trigger_mmu_fault = NULL, | ||
345 | .get_mmu_fault_info = NULL, | ||
346 | .wait_engine_idle = vgpu_fifo_wait_engine_idle, | ||
347 | .get_num_fifos = gv11b_fifo_get_num_fifos, | ||
348 | .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, | ||
349 | .set_runlist_interleave = vgpu_fifo_set_runlist_interleave, | ||
350 | .tsg_set_timeslice = vgpu_tsg_set_timeslice, | ||
351 | .tsg_open = vgpu_tsg_open, | ||
352 | .force_reset_ch = vgpu_fifo_force_reset_ch, | ||
353 | .engine_enum_from_type = gp10b_fifo_engine_enum_from_type, | ||
354 | .device_info_data_parse = gp10b_device_info_data_parse, | ||
355 | .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v, | ||
356 | .init_engine_info = vgpu_fifo_init_engine_info, | ||
357 | .runlist_entry_size = ram_rl_entry_size_v, | ||
358 | .get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry, | ||
359 | .get_ch_runlist_entry = gv11b_get_ch_runlist_entry, | ||
360 | .is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc, | ||
361 | .dump_pbdma_status = gk20a_dump_pbdma_status, | ||
362 | .dump_eng_status = gv11b_dump_eng_status, | ||
363 | .dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc, | ||
364 | .intr_0_error_mask = gv11b_fifo_intr_0_error_mask, | ||
365 | .is_preempt_pending = gv11b_fifo_is_preempt_pending, | ||
366 | .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs, | ||
367 | .reset_enable_hw = gv11b_init_fifo_reset_enable_hw, | ||
368 | .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg, | ||
369 | .handle_sched_error = gv11b_fifo_handle_sched_error, | ||
370 | .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0, | ||
371 | .handle_pbdma_intr_1 = gv11b_fifo_handle_pbdma_intr_1, | ||
372 | .init_eng_method_buffers = gv11b_fifo_init_eng_method_buffers, | ||
373 | .deinit_eng_method_buffers = | ||
374 | gv11b_fifo_deinit_eng_method_buffers, | ||
375 | .tsg_bind_channel = vgpu_gv11b_tsg_bind_channel, | ||
376 | .tsg_unbind_channel = vgpu_tsg_unbind_channel, | ||
377 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | ||
378 | .alloc_syncpt_buf = vgpu_gv11b_fifo_alloc_syncpt_buf, | ||
379 | .free_syncpt_buf = gv11b_fifo_free_syncpt_buf, | ||
380 | .add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd, | ||
381 | .get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size, | ||
382 | .add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd, | ||
383 | .get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size, | ||
384 | #endif | ||
385 | .resetup_ramfc = NULL, | ||
386 | .reschedule_runlist = NULL, | ||
387 | .device_info_fault_id = top_device_info_data_fault_id_enum_v, | ||
388 | .free_channel_ctx_header = vgpu_gv11b_free_subctx_header, | ||
389 | .preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg, | ||
390 | .handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout, | ||
391 | }, | ||
392 | .gr_ctx = { | ||
393 | .get_netlist_name = gr_gv11b_get_netlist_name, | ||
394 | .is_fw_defined = gr_gv11b_is_firmware_defined, | ||
395 | }, | ||
396 | #ifdef CONFIG_GK20A_CTXSW_TRACE | ||
397 | .fecs_trace = { | ||
398 | .alloc_user_buffer = NULL, | ||
399 | .free_user_buffer = NULL, | ||
400 | .mmap_user_buffer = NULL, | ||
401 | .init = NULL, | ||
402 | .deinit = NULL, | ||
403 | .enable = NULL, | ||
404 | .disable = NULL, | ||
405 | .is_enabled = NULL, | ||
406 | .reset = NULL, | ||
407 | .flush = NULL, | ||
408 | .poll = NULL, | ||
409 | .bind_channel = NULL, | ||
410 | .unbind_channel = NULL, | ||
411 | .max_entries = NULL, | ||
412 | }, | ||
413 | #endif /* CONFIG_GK20A_CTXSW_TRACE */ | ||
414 | .mm = { | ||
415 | /* FIXME: add support for sparse mappings */ | ||
416 | .support_sparse = NULL, | ||
417 | .gmmu_map = vgpu_gp10b_locked_gmmu_map, | ||
418 | .gmmu_unmap = vgpu_locked_gmmu_unmap, | ||
419 | .vm_bind_channel = vgpu_vm_bind_channel, | ||
420 | .fb_flush = vgpu_mm_fb_flush, | ||
421 | .l2_invalidate = vgpu_mm_l2_invalidate, | ||
422 | .l2_flush = vgpu_mm_l2_flush, | ||
423 | .cbc_clean = gk20a_mm_cbc_clean, | ||
424 | .set_big_page_size = gm20b_mm_set_big_page_size, | ||
425 | .get_big_page_sizes = gm20b_mm_get_big_page_sizes, | ||
426 | .get_default_big_page_size = gp10b_mm_get_default_big_page_size, | ||
427 | .gpu_phys_addr = gm20b_gpu_phys_addr, | ||
428 | .get_iommu_bit = gk20a_mm_get_iommu_bit, | ||
429 | .get_mmu_levels = gp10b_mm_get_mmu_levels, | ||
430 | .init_pdb = gp10b_mm_init_pdb, | ||
431 | .init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw, | ||
432 | .is_bar1_supported = gv11b_mm_is_bar1_supported, | ||
433 | .init_inst_block = gv11b_init_inst_block, | ||
434 | .mmu_fault_pending = gv11b_mm_mmu_fault_pending, | ||
435 | .get_kind_invalid = gm20b_get_kind_invalid, | ||
436 | .get_kind_pitch = gm20b_get_kind_pitch, | ||
437 | .init_bar2_vm = gb10b_init_bar2_vm, | ||
438 | .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup, | ||
439 | .remove_bar2_vm = gv11b_mm_remove_bar2_vm, | ||
440 | .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy, | ||
441 | }, | ||
442 | .therm = { | ||
443 | .init_therm_setup_hw = gp10b_init_therm_setup_hw, | ||
444 | .elcg_init_idle_filters = gv11b_elcg_init_idle_filters, | ||
445 | }, | ||
446 | .pmu = { | ||
447 | .pmu_setup_elpg = gp10b_pmu_setup_elpg, | ||
448 | .pmu_get_queue_head = pwr_pmu_queue_head_r, | ||
449 | .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v, | ||
450 | .pmu_get_queue_tail = pwr_pmu_queue_tail_r, | ||
451 | .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v, | ||
452 | .pmu_queue_head = gk20a_pmu_queue_head, | ||
453 | .pmu_queue_tail = gk20a_pmu_queue_tail, | ||
454 | .pmu_msgq_tail = gk20a_pmu_msgq_tail, | ||
455 | .pmu_mutex_size = pwr_pmu_mutex__size_1_v, | ||
456 | .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, | ||
457 | .pmu_mutex_release = gk20a_pmu_mutex_release, | ||
458 | .write_dmatrfbase = gp10b_write_dmatrfbase, | ||
459 | .pmu_elpg_statistics = gp106_pmu_elpg_statistics, | ||
460 | .pmu_pg_init_param = gv11b_pg_gr_init, | ||
461 | .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list, | ||
462 | .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list, | ||
463 | .dump_secure_fuses = pmu_dump_security_fuses_gp10b, | ||
464 | .reset_engine = gp106_pmu_engine_reset, | ||
465 | .is_engine_in_reset = gp106_pmu_is_engine_in_reset, | ||
466 | .pmu_nsbootstrap = gv11b_pmu_bootstrap, | ||
467 | .pmu_pg_set_sub_feature_mask = gv11b_pg_set_subfeature_mask, | ||
468 | .is_pmu_supported = gv11b_is_pmu_supported, | ||
469 | }, | ||
470 | .regops = { | ||
471 | .get_global_whitelist_ranges = | ||
472 | gv11b_get_global_whitelist_ranges, | ||
473 | .get_global_whitelist_ranges_count = | ||
474 | gv11b_get_global_whitelist_ranges_count, | ||
475 | .get_context_whitelist_ranges = | ||
476 | gv11b_get_context_whitelist_ranges, | ||
477 | .get_context_whitelist_ranges_count = | ||
478 | gv11b_get_context_whitelist_ranges_count, | ||
479 | .get_runcontrol_whitelist = gv11b_get_runcontrol_whitelist, | ||
480 | .get_runcontrol_whitelist_count = | ||
481 | gv11b_get_runcontrol_whitelist_count, | ||
482 | .get_runcontrol_whitelist_ranges = | ||
483 | gv11b_get_runcontrol_whitelist_ranges, | ||
484 | .get_runcontrol_whitelist_ranges_count = | ||
485 | gv11b_get_runcontrol_whitelist_ranges_count, | ||
486 | .get_qctl_whitelist = gv11b_get_qctl_whitelist, | ||
487 | .get_qctl_whitelist_count = gv11b_get_qctl_whitelist_count, | ||
488 | .get_qctl_whitelist_ranges = gv11b_get_qctl_whitelist_ranges, | ||
489 | .get_qctl_whitelist_ranges_count = | ||
490 | gv11b_get_qctl_whitelist_ranges_count, | ||
491 | .apply_smpc_war = gv11b_apply_smpc_war, | ||
492 | }, | ||
493 | .mc = { | ||
494 | .intr_enable = mc_gv11b_intr_enable, | ||
495 | .intr_unit_config = mc_gp10b_intr_unit_config, | ||
496 | .isr_stall = mc_gp10b_isr_stall, | ||
497 | .intr_stall = mc_gp10b_intr_stall, | ||
498 | .intr_stall_pause = mc_gp10b_intr_stall_pause, | ||
499 | .intr_stall_resume = mc_gp10b_intr_stall_resume, | ||
500 | .intr_nonstall = mc_gp10b_intr_nonstall, | ||
501 | .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, | ||
502 | .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, | ||
503 | .enable = gk20a_mc_enable, | ||
504 | .disable = gk20a_mc_disable, | ||
505 | .reset = gk20a_mc_reset, | ||
506 | .boot_0 = gk20a_mc_boot_0, | ||
507 | .is_intr1_pending = mc_gp10b_is_intr1_pending, | ||
508 | .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending, | ||
509 | }, | ||
510 | .debug = { | ||
511 | .show_dump = NULL, | ||
512 | }, | ||
513 | .dbg_session_ops = { | ||
514 | .exec_reg_ops = vgpu_exec_regops, | ||
515 | .dbg_set_powergate = vgpu_dbg_set_powergate, | ||
516 | .check_and_set_global_reservation = | ||
517 | vgpu_check_and_set_global_reservation, | ||
518 | .check_and_set_context_reservation = | ||
519 | vgpu_check_and_set_context_reservation, | ||
520 | .release_profiler_reservation = | ||
521 | vgpu_release_profiler_reservation, | ||
522 | .perfbuffer_enable = vgpu_perfbuffer_enable, | ||
523 | .perfbuffer_disable = vgpu_perfbuffer_disable, | ||
524 | }, | ||
525 | .bus = { | ||
526 | .init_hw = gk20a_bus_init_hw, | ||
527 | .isr = gk20a_bus_isr, | ||
528 | .read_ptimer = vgpu_read_ptimer, | ||
529 | .get_timestamps_zipper = vgpu_get_timestamps_zipper, | ||
530 | .bar1_bind = NULL, | ||
531 | }, | ||
532 | #if defined(CONFIG_GK20A_CYCLE_STATS) | ||
533 | .css = { | ||
534 | .enable_snapshot = vgpu_css_enable_snapshot_buffer, | ||
535 | .disable_snapshot = vgpu_css_release_snapshot_buffer, | ||
536 | .check_data_available = vgpu_css_flush_snapshots, | ||
537 | .set_handled_snapshots = NULL, | ||
538 | .allocate_perfmon_ids = NULL, | ||
539 | .release_perfmon_ids = NULL, | ||
540 | }, | ||
541 | #endif | ||
542 | .falcon = { | ||
543 | .falcon_hal_sw_init = gk20a_falcon_hal_sw_init, | ||
544 | }, | ||
545 | .priv_ring = { | ||
546 | .isr = gp10b_priv_ring_isr, | ||
547 | }, | ||
548 | .chip_init_gpu_characteristics = vgpu_gv11b_init_gpu_characteristics, | ||
549 | .get_litter_value = gv11b_get_litter_value, | ||
550 | }; | ||
551 | |||
552 | int vgpu_gv11b_init_hal(struct gk20a *g) | ||
553 | { | ||
554 | struct gpu_ops *gops = &g->ops; | ||
555 | u32 val; | ||
556 | bool priv_security; | ||
557 | |||
558 | gops->ltc = vgpu_gv11b_ops.ltc; | ||
559 | gops->ce2 = vgpu_gv11b_ops.ce2; | ||
560 | gops->gr = vgpu_gv11b_ops.gr; | ||
561 | gops->fb = vgpu_gv11b_ops.fb; | ||
562 | gops->clock_gating = vgpu_gv11b_ops.clock_gating; | ||
563 | gops->fifo = vgpu_gv11b_ops.fifo; | ||
564 | gops->gr_ctx = vgpu_gv11b_ops.gr_ctx; | ||
565 | gops->mm = vgpu_gv11b_ops.mm; | ||
566 | gops->fecs_trace = vgpu_gv11b_ops.fecs_trace; | ||
567 | gops->therm = vgpu_gv11b_ops.therm; | ||
568 | gops->pmu = vgpu_gv11b_ops.pmu; | ||
569 | gops->regops = vgpu_gv11b_ops.regops; | ||
570 | gops->mc = vgpu_gv11b_ops.mc; | ||
571 | gops->debug = vgpu_gv11b_ops.debug; | ||
572 | gops->dbg_session_ops = vgpu_gv11b_ops.dbg_session_ops; | ||
573 | gops->bus = vgpu_gv11b_ops.bus; | ||
574 | #if defined(CONFIG_GK20A_CYCLE_STATS) | ||
575 | gops->css = vgpu_gv11b_ops.css; | ||
576 | #endif | ||
577 | gops->falcon = vgpu_gv11b_ops.falcon; | ||
578 | gops->priv_ring = vgpu_gv11b_ops.priv_ring; | ||
579 | |||
580 | /* Lone functions */ | ||
581 | gops->chip_init_gpu_characteristics = | ||
582 | vgpu_gv11b_ops.chip_init_gpu_characteristics; | ||
583 | gops->get_litter_value = vgpu_gv11b_ops.get_litter_value; | ||
584 | |||
585 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); | ||
586 | if (val) { | ||
587 | priv_security = true; | ||
588 | pr_err("priv security is enabled\n"); | ||
589 | } else { | ||
590 | priv_security = false; | ||
591 | pr_err("priv security is disabled\n"); | ||
592 | } | ||
593 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, false); | ||
594 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, priv_security); | ||
595 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, priv_security); | ||
596 | |||
597 | /* priv security dependent ops */ | ||
598 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { | ||
599 | /* Add in ops from gm20b acr */ | ||
600 | gops->pmu.prepare_ucode = gp106_prepare_ucode_blob, | ||
601 | gops->pmu.pmu_setup_hw_and_bootstrap = gv11b_bootstrap_hs_flcn, | ||
602 | gops->pmu.get_wpr = gm20b_wpr_info, | ||
603 | gops->pmu.alloc_blob_space = gm20b_alloc_blob_space, | ||
604 | gops->pmu.pmu_populate_loader_cfg = | ||
605 | gp106_pmu_populate_loader_cfg, | ||
606 | gops->pmu.flcn_populate_bl_dmem_desc = | ||
607 | gp106_flcn_populate_bl_dmem_desc, | ||
608 | gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt, | ||
609 | gops->pmu.falcon_clear_halt_interrupt_status = | ||
610 | clear_halt_interrupt_status, | ||
611 | gops->pmu.init_falcon_setup_hw = gv11b_init_pmu_setup_hw1, | ||
612 | |||
613 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; | ||
614 | gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; | ||
615 | gops->pmu.is_lazy_bootstrap = gv11b_is_lazy_bootstrap, | ||
616 | gops->pmu.is_priv_load = gv11b_is_priv_load, | ||
617 | |||
618 | gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode; | ||
619 | } else { | ||
620 | /* Inherit from gk20a */ | ||
621 | gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob, | ||
622 | gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1, | ||
623 | |||
624 | gops->pmu.load_lsfalcon_ucode = NULL; | ||
625 | gops->pmu.init_wpr_region = NULL; | ||
626 | gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1; | ||
627 | |||
628 | gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode; | ||
629 | } | ||
630 | |||
631 | __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); | ||
632 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; | ||
633 | |||
634 | g->name = "gv11b"; | ||
635 | |||
636 | return 0; | ||
637 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_subctx_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_subctx_gv11b.c new file mode 100644 index 00000000..6d8785e4 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_subctx_gv11b.c | |||
@@ -0,0 +1,73 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include "gk20a/gk20a.h" | ||
18 | #include "common/linux/vgpu/vgpu.h" | ||
19 | #include <linux/tegra_vgpu.h> | ||
20 | |||
21 | int vgpu_gv11b_alloc_subctx_header(struct channel_gk20a *c) | ||
22 | { | ||
23 | struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; | ||
24 | struct tegra_vgpu_cmd_msg msg = {}; | ||
25 | struct tegra_vgpu_alloc_ctx_header_params *p = | ||
26 | &msg.params.t19x.alloc_ctx_header; | ||
27 | struct gr_gk20a *gr = &c->g->gr; | ||
28 | int err; | ||
29 | |||
30 | msg.cmd = TEGRA_VGPU_CMD_ALLOC_CTX_HEADER; | ||
31 | msg.handle = vgpu_get_handle(c->g); | ||
32 | p->ch_handle = c->virt_ctx; | ||
33 | p->ctx_header_va = __nvgpu_vm_alloc_va(c->vm, | ||
34 | gr->ctx_vars.golden_image_size, | ||
35 | gmmu_page_size_kernel); | ||
36 | if (!p->ctx_header_va) { | ||
37 | nvgpu_err(c->g, "alloc va failed for ctx_header"); | ||
38 | return -ENOMEM; | ||
39 | } | ||
40 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
41 | err = err ? err : msg.ret; | ||
42 | if (unlikely(err)) { | ||
43 | nvgpu_err(c->g, "alloc ctx_header failed err %d", err); | ||
44 | __nvgpu_vm_free_va(c->vm, p->ctx_header_va, | ||
45 | gmmu_page_size_kernel); | ||
46 | return err; | ||
47 | } | ||
48 | ctx->mem.gpu_va = p->ctx_header_va; | ||
49 | |||
50 | return err; | ||
51 | } | ||
52 | |||
53 | void vgpu_gv11b_free_subctx_header(struct channel_gk20a *c) | ||
54 | { | ||
55 | struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; | ||
56 | struct tegra_vgpu_cmd_msg msg = {}; | ||
57 | struct tegra_vgpu_free_ctx_header_params *p = | ||
58 | &msg.params.t19x.free_ctx_header; | ||
59 | int err; | ||
60 | |||
61 | if (ctx->mem.gpu_va) { | ||
62 | msg.cmd = TEGRA_VGPU_CMD_FREE_CTX_HEADER; | ||
63 | msg.handle = vgpu_get_handle(c->g); | ||
64 | p->ch_handle = c->virt_ctx; | ||
65 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
66 | err = err ? err : msg.ret; | ||
67 | if (unlikely(err)) | ||
68 | nvgpu_err(c->g, "free ctx_header failed err %d", err); | ||
69 | __nvgpu_vm_free_va(c->vm, ctx->mem.gpu_va, | ||
70 | gmmu_page_size_kernel); | ||
71 | ctx->mem.gpu_va = 0; | ||
72 | } | ||
73 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_subctx_gv11b.h b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_subctx_gv11b.h new file mode 100644 index 00000000..dfd7109e --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_subctx_gv11b.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #ifndef _VGPU_SUBCTX_GV11B_H_ | ||
18 | #define _VGPU_SUBCTX_GV11B_H_ | ||
19 | |||
20 | struct channel_gk20a; | ||
21 | |||
22 | int vgpu_gv11b_alloc_subctx_header(struct channel_gk20a *c); | ||
23 | void vgpu_gv11b_free_subctx_header(struct channel_gk20a *c); | ||
24 | |||
25 | #endif | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_tsg_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_tsg_gv11b.c new file mode 100644 index 00000000..094ccc44 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_tsg_gv11b.c | |||
@@ -0,0 +1,53 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include <linux/tegra_vgpu.h> | ||
18 | #include "gk20a/gk20a.h" | ||
19 | #include "common/linux/vgpu/vgpu.h" | ||
20 | |||
21 | #include "vgpu_tsg_gv11b.h" | ||
22 | |||
23 | int vgpu_gv11b_tsg_bind_channel(struct tsg_gk20a *tsg, | ||
24 | struct channel_gk20a *ch) | ||
25 | { | ||
26 | struct tegra_vgpu_cmd_msg msg = {}; | ||
27 | struct tegra_vgpu_tsg_bind_channel_ex_params *p = | ||
28 | &msg.params.t19x.tsg_bind_channel_ex; | ||
29 | int err; | ||
30 | |||
31 | gk20a_dbg_fn(""); | ||
32 | |||
33 | err = gk20a_tsg_bind_channel(tsg, ch); | ||
34 | if (err) | ||
35 | return err; | ||
36 | |||
37 | msg.cmd = TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX; | ||
38 | msg.handle = vgpu_get_handle(tsg->g); | ||
39 | p->tsg_id = tsg->tsgid; | ||
40 | p->ch_handle = ch->virt_ctx; | ||
41 | p->subctx_id = ch->t19x.subctx_id; | ||
42 | p->runqueue_sel = ch->t19x.runqueue_sel; | ||
43 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
44 | err = err ? err : msg.ret; | ||
45 | if (err) { | ||
46 | nvgpu_err(tsg->g, | ||
47 | "vgpu_gv11b_tsg_bind_channel failed, ch %d tsgid %d", | ||
48 | ch->chid, tsg->tsgid); | ||
49 | gk20a_tsg_unbind_channel(ch); | ||
50 | } | ||
51 | |||
52 | return err; | ||
53 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_tsg_gv11b.h b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_tsg_gv11b.h new file mode 100644 index 00000000..6334cdbb --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_tsg_gv11b.h | |||
@@ -0,0 +1,23 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #ifndef _VGPU_TSG_GV11B_H_ | ||
18 | #define _VGPU_TSG_GV11B_H_ | ||
19 | |||
20 | int vgpu_gv11b_tsg_bind_channel(struct tsg_gk20a *tsg, | ||
21 | struct channel_gk20a *ch); | ||
22 | |||
23 | #endif | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/ltc_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/ltc_vgpu.c new file mode 100644 index 00000000..627ad1a8 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/ltc_vgpu.c | |||
@@ -0,0 +1,61 @@ | |||
1 | /* | ||
2 | * Virtualized GPU L2 | ||
3 | * | ||
4 | * Copyright (c) 2014-2017 NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
17 | */ | ||
18 | |||
19 | #include "vgpu.h" | ||
20 | #include "ltc_vgpu.h" | ||
21 | |||
22 | int vgpu_determine_L2_size_bytes(struct gk20a *g) | ||
23 | { | ||
24 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | ||
25 | |||
26 | gk20a_dbg_fn(""); | ||
27 | |||
28 | return priv->constants.l2_size; | ||
29 | } | ||
30 | |||
31 | int vgpu_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) | ||
32 | { | ||
33 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | ||
34 | u32 max_comptag_lines = 0; | ||
35 | int err; | ||
36 | |||
37 | gk20a_dbg_fn(""); | ||
38 | |||
39 | gr->cacheline_size = priv->constants.cacheline_size; | ||
40 | gr->comptags_per_cacheline = priv->constants.comptags_per_cacheline; | ||
41 | gr->slices_per_ltc = priv->constants.slices_per_ltc; | ||
42 | max_comptag_lines = priv->constants.comptag_lines; | ||
43 | |||
44 | if (max_comptag_lines < 2) | ||
45 | return -ENXIO; | ||
46 | |||
47 | err = gk20a_comptag_allocator_init(g, &gr->comp_tags, max_comptag_lines); | ||
48 | if (err) | ||
49 | return err; | ||
50 | |||
51 | return 0; | ||
52 | } | ||
53 | |||
54 | void vgpu_ltc_init_fs_state(struct gk20a *g) | ||
55 | { | ||
56 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | ||
57 | |||
58 | gk20a_dbg_fn(""); | ||
59 | |||
60 | g->ltc_count = priv->constants.ltc_count; | ||
61 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/ltc_vgpu.h b/drivers/gpu/nvgpu/common/linux/vgpu/ltc_vgpu.h new file mode 100644 index 00000000..7b368ef5 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/ltc_vgpu.h | |||
@@ -0,0 +1,27 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #ifndef _LTC_VGPU_H_ | ||
18 | #define _LTC_VGPU_H_ | ||
19 | |||
20 | struct gk20a; | ||
21 | struct gr_gk20a; | ||
22 | |||
23 | int vgpu_determine_L2_size_bytes(struct gk20a *g); | ||
24 | int vgpu_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr); | ||
25 | void vgpu_ltc_init_fs_state(struct gk20a *g); | ||
26 | |||
27 | #endif | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.c new file mode 100644 index 00000000..f8c5c406 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.c | |||
@@ -0,0 +1,363 @@ | |||
1 | /* | ||
2 | * Virtualized GPU Memory Management | ||
3 | * | ||
4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
17 | */ | ||
18 | |||
19 | #include <linux/dma-mapping.h> | ||
20 | #include <uapi/linux/nvgpu.h> | ||
21 | |||
22 | #include <nvgpu/kmem.h> | ||
23 | #include <nvgpu/dma.h> | ||
24 | #include <nvgpu/bug.h> | ||
25 | #include <nvgpu/vm.h> | ||
26 | #include <nvgpu/vm_area.h> | ||
27 | |||
28 | #include <nvgpu/vgpu/vm.h> | ||
29 | |||
30 | #include <nvgpu/linux/vm.h> | ||
31 | #include <nvgpu/linux/nvgpu_mem.h> | ||
32 | |||
33 | #include "vgpu.h" | ||
34 | #include "mm_vgpu.h" | ||
35 | #include "gk20a/mm_gk20a.h" | ||
36 | #include "gm20b/mm_gm20b.h" | ||
37 | |||
38 | static int vgpu_init_mm_setup_sw(struct gk20a *g) | ||
39 | { | ||
40 | struct mm_gk20a *mm = &g->mm; | ||
41 | |||
42 | gk20a_dbg_fn(""); | ||
43 | |||
44 | if (mm->sw_ready) { | ||
45 | gk20a_dbg_fn("skip init"); | ||
46 | return 0; | ||
47 | } | ||
48 | |||
49 | nvgpu_mutex_init(&mm->tlb_lock); | ||
50 | nvgpu_mutex_init(&mm->priv_lock); | ||
51 | |||
52 | mm->g = g; | ||
53 | |||
54 | /*TBD: make channel vm size configurable */ | ||
55 | mm->channel.user_size = NV_MM_DEFAULT_USER_SIZE; | ||
56 | mm->channel.kernel_size = NV_MM_DEFAULT_KERNEL_SIZE; | ||
57 | |||
58 | gk20a_dbg_info("channel vm size: user %dMB kernel %dMB", | ||
59 | (int)(mm->channel.user_size >> 20), | ||
60 | (int)(mm->channel.kernel_size >> 20)); | ||
61 | |||
62 | mm->sw_ready = true; | ||
63 | |||
64 | return 0; | ||
65 | } | ||
66 | |||
67 | int vgpu_init_mm_support(struct gk20a *g) | ||
68 | { | ||
69 | int err; | ||
70 | |||
71 | gk20a_dbg_fn(""); | ||
72 | |||
73 | err = vgpu_init_mm_setup_sw(g); | ||
74 | if (err) | ||
75 | return err; | ||
76 | |||
77 | if (g->ops.mm.init_mm_setup_hw) | ||
78 | err = g->ops.mm.init_mm_setup_hw(g); | ||
79 | |||
80 | return err; | ||
81 | } | ||
82 | |||
83 | u64 vgpu_locked_gmmu_map(struct vm_gk20a *vm, | ||
84 | u64 map_offset, | ||
85 | struct nvgpu_sgt *sgt, | ||
86 | u64 buffer_offset, | ||
87 | u64 size, | ||
88 | int pgsz_idx, | ||
89 | u8 kind_v, | ||
90 | u32 ctag_offset, | ||
91 | u32 flags, | ||
92 | int rw_flag, | ||
93 | bool clear_ctags, | ||
94 | bool sparse, | ||
95 | bool priv, | ||
96 | struct vm_gk20a_mapping_batch *batch, | ||
97 | enum nvgpu_aperture aperture) | ||
98 | { | ||
99 | int err = 0; | ||
100 | struct device *d = dev_from_vm(vm); | ||
101 | struct gk20a *g = gk20a_from_vm(vm); | ||
102 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(d); | ||
103 | struct tegra_vgpu_cmd_msg msg; | ||
104 | struct tegra_vgpu_as_map_params *p = &msg.params.as_map; | ||
105 | u64 addr = nvgpu_sgt_get_gpu_addr(g, sgt, sgt->sgl, NULL); | ||
106 | u8 prot; | ||
107 | |||
108 | gk20a_dbg_fn(""); | ||
109 | |||
110 | /* Allocate (or validate when map_offset != 0) the virtual address. */ | ||
111 | if (!map_offset) { | ||
112 | map_offset = __nvgpu_vm_alloc_va(vm, size, | ||
113 | pgsz_idx); | ||
114 | if (!map_offset) { | ||
115 | nvgpu_err(g, "failed to allocate va space"); | ||
116 | err = -ENOMEM; | ||
117 | goto fail; | ||
118 | } | ||
119 | } | ||
120 | |||
121 | if (rw_flag == gk20a_mem_flag_read_only) | ||
122 | prot = TEGRA_VGPU_MAP_PROT_READ_ONLY; | ||
123 | else if (rw_flag == gk20a_mem_flag_write_only) | ||
124 | prot = TEGRA_VGPU_MAP_PROT_WRITE_ONLY; | ||
125 | else | ||
126 | prot = TEGRA_VGPU_MAP_PROT_NONE; | ||
127 | |||
128 | msg.cmd = TEGRA_VGPU_CMD_AS_MAP; | ||
129 | msg.handle = vgpu_get_handle(g); | ||
130 | p->handle = vm->handle; | ||
131 | p->addr = addr; | ||
132 | p->gpu_va = map_offset; | ||
133 | p->size = size; | ||
134 | if (pgsz_idx == gmmu_page_size_kernel) { | ||
135 | u32 page_size = vm->gmmu_page_sizes[pgsz_idx]; | ||
136 | |||
137 | if (page_size == vm->gmmu_page_sizes[gmmu_page_size_small]) { | ||
138 | pgsz_idx = gmmu_page_size_small; | ||
139 | } else if (page_size == | ||
140 | vm->gmmu_page_sizes[gmmu_page_size_big]) { | ||
141 | pgsz_idx = gmmu_page_size_big; | ||
142 | } else { | ||
143 | nvgpu_err(g, "invalid kernel page size %d", | ||
144 | page_size); | ||
145 | goto fail; | ||
146 | } | ||
147 | } | ||
148 | p->pgsz_idx = pgsz_idx; | ||
149 | p->iova = mapping ? 1 : 0; | ||
150 | p->kind = kind_v; | ||
151 | p->cacheable = (flags & NVGPU_AS_MAP_BUFFER_FLAGS_CACHEABLE) ? 1 : 0; | ||
152 | p->prot = prot; | ||
153 | p->ctag_offset = ctag_offset; | ||
154 | p->clear_ctags = clear_ctags; | ||
155 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
156 | err = err ? err : msg.ret; | ||
157 | if (err) | ||
158 | goto fail; | ||
159 | |||
160 | /* TLB invalidate handled on server side */ | ||
161 | |||
162 | return map_offset; | ||
163 | fail: | ||
164 | nvgpu_err(g, "%s: failed with err=%d", __func__, err); | ||
165 | return 0; | ||
166 | } | ||
167 | |||
168 | void vgpu_locked_gmmu_unmap(struct vm_gk20a *vm, | ||
169 | u64 vaddr, | ||
170 | u64 size, | ||
171 | int pgsz_idx, | ||
172 | bool va_allocated, | ||
173 | int rw_flag, | ||
174 | bool sparse, | ||
175 | struct vm_gk20a_mapping_batch *batch) | ||
176 | { | ||
177 | struct gk20a *g = gk20a_from_vm(vm); | ||
178 | struct tegra_vgpu_cmd_msg msg; | ||
179 | struct tegra_vgpu_as_map_params *p = &msg.params.as_map; | ||
180 | int err; | ||
181 | |||
182 | gk20a_dbg_fn(""); | ||
183 | |||
184 | if (va_allocated) { | ||
185 | err = __nvgpu_vm_free_va(vm, vaddr, pgsz_idx); | ||
186 | if (err) { | ||
187 | dev_err(dev_from_vm(vm), | ||
188 | "failed to free va"); | ||
189 | return; | ||
190 | } | ||
191 | } | ||
192 | |||
193 | msg.cmd = TEGRA_VGPU_CMD_AS_UNMAP; | ||
194 | msg.handle = vgpu_get_handle(g); | ||
195 | p->handle = vm->handle; | ||
196 | p->gpu_va = vaddr; | ||
197 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
198 | if (err || msg.ret) | ||
199 | dev_err(dev_from_vm(vm), | ||
200 | "failed to update gmmu ptes on unmap"); | ||
201 | |||
202 | /* TLB invalidate handled on server side */ | ||
203 | } | ||
204 | |||
205 | /* | ||
206 | * This is called by the common VM init routine to handle vGPU specifics of | ||
207 | * intializing a VM on a vGPU. This alone is not enough to init a VM. See | ||
208 | * nvgpu_vm_init(). | ||
209 | */ | ||
210 | int vgpu_vm_init(struct gk20a *g, struct vm_gk20a *vm) | ||
211 | { | ||
212 | struct tegra_vgpu_cmd_msg msg; | ||
213 | struct tegra_vgpu_as_share_params *p = &msg.params.as_share; | ||
214 | int err; | ||
215 | |||
216 | msg.cmd = TEGRA_VGPU_CMD_AS_ALLOC_SHARE; | ||
217 | msg.handle = vgpu_get_handle(g); | ||
218 | p->size = vm->va_limit; | ||
219 | p->big_page_size = vm->big_page_size; | ||
220 | |||
221 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
222 | if (err || msg.ret) | ||
223 | return -ENOMEM; | ||
224 | |||
225 | vm->handle = p->handle; | ||
226 | |||
227 | return 0; | ||
228 | } | ||
229 | |||
230 | /* | ||
231 | * Similar to vgpu_vm_init() this is called as part of the cleanup path for | ||
232 | * VMs. This alone is not enough to remove a VM - see nvgpu_vm_remove(). | ||
233 | */ | ||
234 | void vgpu_vm_remove(struct vm_gk20a *vm) | ||
235 | { | ||
236 | struct gk20a *g = gk20a_from_vm(vm); | ||
237 | struct tegra_vgpu_cmd_msg msg; | ||
238 | struct tegra_vgpu_as_share_params *p = &msg.params.as_share; | ||
239 | int err; | ||
240 | |||
241 | msg.cmd = TEGRA_VGPU_CMD_AS_FREE_SHARE; | ||
242 | msg.handle = vgpu_get_handle(g); | ||
243 | p->handle = vm->handle; | ||
244 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
245 | WARN_ON(err || msg.ret); | ||
246 | } | ||
247 | |||
248 | u64 vgpu_bar1_map(struct gk20a *g, struct sg_table **sgt, u64 size) | ||
249 | { | ||
250 | struct dma_iommu_mapping *mapping = | ||
251 | to_dma_iommu_mapping(dev_from_gk20a(g)); | ||
252 | u64 addr = nvgpu_mem_get_addr_sgl(g, (*sgt)->sgl); | ||
253 | struct tegra_vgpu_cmd_msg msg; | ||
254 | struct tegra_vgpu_as_map_params *p = &msg.params.as_map; | ||
255 | int err; | ||
256 | |||
257 | msg.cmd = TEGRA_VGPU_CMD_MAP_BAR1; | ||
258 | msg.handle = vgpu_get_handle(g); | ||
259 | p->addr = addr; | ||
260 | p->size = size; | ||
261 | p->iova = mapping ? 1 : 0; | ||
262 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
263 | if (err || msg.ret) | ||
264 | addr = 0; | ||
265 | else | ||
266 | addr = p->gpu_va; | ||
267 | |||
268 | return addr; | ||
269 | } | ||
270 | |||
271 | int vgpu_vm_bind_channel(struct gk20a_as_share *as_share, | ||
272 | struct channel_gk20a *ch) | ||
273 | { | ||
274 | struct vm_gk20a *vm = as_share->vm; | ||
275 | struct tegra_vgpu_cmd_msg msg; | ||
276 | struct tegra_vgpu_as_bind_share_params *p = &msg.params.as_bind_share; | ||
277 | int err; | ||
278 | |||
279 | gk20a_dbg_fn(""); | ||
280 | |||
281 | ch->vm = vm; | ||
282 | msg.cmd = TEGRA_VGPU_CMD_AS_BIND_SHARE; | ||
283 | msg.handle = vgpu_get_handle(ch->g); | ||
284 | p->as_handle = vm->handle; | ||
285 | p->chan_handle = ch->virt_ctx; | ||
286 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
287 | |||
288 | if (err || msg.ret) { | ||
289 | ch->vm = NULL; | ||
290 | err = -ENOMEM; | ||
291 | } | ||
292 | |||
293 | if (ch->vm) | ||
294 | nvgpu_vm_get(ch->vm); | ||
295 | |||
296 | return err; | ||
297 | } | ||
298 | |||
299 | static void vgpu_cache_maint(u64 handle, u8 op) | ||
300 | { | ||
301 | struct tegra_vgpu_cmd_msg msg; | ||
302 | struct tegra_vgpu_cache_maint_params *p = &msg.params.cache_maint; | ||
303 | int err; | ||
304 | |||
305 | msg.cmd = TEGRA_VGPU_CMD_CACHE_MAINT; | ||
306 | msg.handle = handle; | ||
307 | p->op = op; | ||
308 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
309 | WARN_ON(err || msg.ret); | ||
310 | } | ||
311 | |||
312 | int vgpu_mm_fb_flush(struct gk20a *g) | ||
313 | { | ||
314 | |||
315 | gk20a_dbg_fn(""); | ||
316 | |||
317 | vgpu_cache_maint(vgpu_get_handle(g), TEGRA_VGPU_FB_FLUSH); | ||
318 | return 0; | ||
319 | } | ||
320 | |||
321 | void vgpu_mm_l2_invalidate(struct gk20a *g) | ||
322 | { | ||
323 | |||
324 | gk20a_dbg_fn(""); | ||
325 | |||
326 | vgpu_cache_maint(vgpu_get_handle(g), TEGRA_VGPU_L2_MAINT_INV); | ||
327 | } | ||
328 | |||
329 | void vgpu_mm_l2_flush(struct gk20a *g, bool invalidate) | ||
330 | { | ||
331 | u8 op; | ||
332 | |||
333 | gk20a_dbg_fn(""); | ||
334 | |||
335 | if (invalidate) | ||
336 | op = TEGRA_VGPU_L2_MAINT_FLUSH_INV; | ||
337 | else | ||
338 | op = TEGRA_VGPU_L2_MAINT_FLUSH; | ||
339 | |||
340 | vgpu_cache_maint(vgpu_get_handle(g), op); | ||
341 | } | ||
342 | |||
343 | void vgpu_mm_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb) | ||
344 | { | ||
345 | gk20a_dbg_fn(""); | ||
346 | |||
347 | nvgpu_err(g, "call to RM server not supported"); | ||
348 | } | ||
349 | |||
350 | void vgpu_mm_mmu_set_debug_mode(struct gk20a *g, bool enable) | ||
351 | { | ||
352 | struct tegra_vgpu_cmd_msg msg; | ||
353 | struct tegra_vgpu_mmu_debug_mode *p = &msg.params.mmu_debug_mode; | ||
354 | int err; | ||
355 | |||
356 | gk20a_dbg_fn(""); | ||
357 | |||
358 | msg.cmd = TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE; | ||
359 | msg.handle = vgpu_get_handle(g); | ||
360 | p->enable = (u32)enable; | ||
361 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
362 | WARN_ON(err || msg.ret); | ||
363 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.h b/drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.h new file mode 100644 index 00000000..eee54779 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/mm_vgpu.h | |||
@@ -0,0 +1,50 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #ifndef _MM_VGPU_H_ | ||
18 | #define _MM_VGPU_H_ | ||
19 | |||
20 | u64 vgpu_locked_gmmu_map(struct vm_gk20a *vm, | ||
21 | u64 map_offset, | ||
22 | struct nvgpu_sgt *sgt, | ||
23 | u64 buffer_offset, | ||
24 | u64 size, | ||
25 | int pgsz_idx, | ||
26 | u8 kind_v, | ||
27 | u32 ctag_offset, | ||
28 | u32 flags, | ||
29 | int rw_flag, | ||
30 | bool clear_ctags, | ||
31 | bool sparse, | ||
32 | bool priv, | ||
33 | struct vm_gk20a_mapping_batch *batch, | ||
34 | enum nvgpu_aperture aperture); | ||
35 | void vgpu_locked_gmmu_unmap(struct vm_gk20a *vm, | ||
36 | u64 vaddr, | ||
37 | u64 size, | ||
38 | int pgsz_idx, | ||
39 | bool va_allocated, | ||
40 | int rw_flag, | ||
41 | bool sparse, | ||
42 | struct vm_gk20a_mapping_batch *batch); | ||
43 | int vgpu_vm_bind_channel(struct gk20a_as_share *as_share, | ||
44 | struct channel_gk20a *ch); | ||
45 | int vgpu_mm_fb_flush(struct gk20a *g); | ||
46 | void vgpu_mm_l2_invalidate(struct gk20a *g); | ||
47 | void vgpu_mm_l2_flush(struct gk20a *g, bool invalidate); | ||
48 | void vgpu_mm_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb); | ||
49 | void vgpu_mm_mmu_set_debug_mode(struct gk20a *g, bool enable); | ||
50 | #endif | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/platform_vgpu_tegra.c b/drivers/gpu/nvgpu/common/linux/vgpu/platform_vgpu_tegra.c new file mode 100644 index 00000000..830b04ac --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/platform_vgpu_tegra.c | |||
@@ -0,0 +1,69 @@ | |||
1 | /* | ||
2 | * Tegra Virtualized GPU Platform Interface | ||
3 | * | ||
4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
17 | */ | ||
18 | |||
19 | #include "gk20a/gk20a.h" | ||
20 | #include "common/linux/platform_gk20a.h" | ||
21 | #include "clk_vgpu.h" | ||
22 | |||
23 | #include <nvgpu/nvhost.h> | ||
24 | |||
25 | static int gk20a_tegra_probe(struct device *dev) | ||
26 | { | ||
27 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | ||
28 | struct gk20a_platform *platform = dev_get_drvdata(dev); | ||
29 | int ret; | ||
30 | |||
31 | ret = nvgpu_get_nvhost_dev(platform->g); | ||
32 | if (ret) | ||
33 | return ret; | ||
34 | |||
35 | vgpu_init_clk_support(platform->g); | ||
36 | return 0; | ||
37 | #else | ||
38 | return 0; | ||
39 | #endif | ||
40 | } | ||
41 | |||
42 | struct gk20a_platform vgpu_tegra_platform = { | ||
43 | .has_syncpoints = true, | ||
44 | .aggressive_sync_destroy_thresh = 64, | ||
45 | |||
46 | /* power management configuration */ | ||
47 | .can_railgate_init = false, | ||
48 | .can_elpg_init = false, | ||
49 | .enable_slcg = false, | ||
50 | .enable_blcg = false, | ||
51 | .enable_elcg = false, | ||
52 | .enable_elpg = false, | ||
53 | .enable_aelpg = false, | ||
54 | .can_slcg = false, | ||
55 | .can_blcg = false, | ||
56 | .can_elcg = false, | ||
57 | |||
58 | .ch_wdt_timeout_ms = 5000, | ||
59 | |||
60 | .probe = gk20a_tegra_probe, | ||
61 | |||
62 | .clk_round_rate = vgpu_clk_round_rate, | ||
63 | .get_clk_freqs = vgpu_clk_get_freqs, | ||
64 | |||
65 | /* frequency scaling configuration */ | ||
66 | .devfreq_governor = "userspace", | ||
67 | |||
68 | .virtual_dev = true, | ||
69 | }; | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/sysfs_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/sysfs_vgpu.c new file mode 100644 index 00000000..4025aabd --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/sysfs_vgpu.c | |||
@@ -0,0 +1,49 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include <linux/device.h> | ||
18 | |||
19 | #include "vgpu.h" | ||
20 | |||
21 | static ssize_t vgpu_load_show(struct device *dev, | ||
22 | struct device_attribute *attr, | ||
23 | char *buf) | ||
24 | { | ||
25 | struct gk20a *g = get_gk20a(dev); | ||
26 | struct tegra_vgpu_cmd_msg msg = {0}; | ||
27 | struct tegra_vgpu_gpu_load_params *p = &msg.params.gpu_load; | ||
28 | int err; | ||
29 | |||
30 | msg.cmd = TEGRA_VGPU_CMD_GET_GPU_LOAD; | ||
31 | msg.handle = vgpu_get_handle(g); | ||
32 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
33 | if (err) | ||
34 | return err; | ||
35 | |||
36 | return snprintf(buf, PAGE_SIZE, "%u\n", p->load); | ||
37 | } | ||
38 | static DEVICE_ATTR(load, S_IRUGO, vgpu_load_show, NULL); | ||
39 | |||
40 | void vgpu_create_sysfs(struct device *dev) | ||
41 | { | ||
42 | if (device_create_file(dev, &dev_attr_load)) | ||
43 | dev_err(dev, "Failed to create vgpu sysfs attributes!\n"); | ||
44 | } | ||
45 | |||
46 | void vgpu_remove_sysfs(struct device *dev) | ||
47 | { | ||
48 | device_remove_file(dev, &dev_attr_load); | ||
49 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/tsg_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/tsg_vgpu.c new file mode 100644 index 00000000..c40e6f90 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/tsg_vgpu.c | |||
@@ -0,0 +1,136 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include <linux/tegra_vgpu.h> | ||
18 | |||
19 | #include "gk20a/gk20a.h" | ||
20 | #include "gk20a/channel_gk20a.h" | ||
21 | #include "gk20a/tsg_gk20a.h" | ||
22 | #include "common/linux/platform_gk20a.h" | ||
23 | #include "vgpu.h" | ||
24 | #include "fifo_vgpu.h" | ||
25 | |||
26 | #include <nvgpu/bug.h> | ||
27 | |||
28 | int vgpu_tsg_open(struct tsg_gk20a *tsg) | ||
29 | { | ||
30 | struct tegra_vgpu_cmd_msg msg = {}; | ||
31 | struct tegra_vgpu_tsg_open_params *p = | ||
32 | &msg.params.tsg_open; | ||
33 | int err; | ||
34 | |||
35 | gk20a_dbg_fn(""); | ||
36 | |||
37 | msg.cmd = TEGRA_VGPU_CMD_TSG_OPEN; | ||
38 | msg.handle = vgpu_get_handle(tsg->g); | ||
39 | p->tsg_id = tsg->tsgid; | ||
40 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
41 | err = err ? err : msg.ret; | ||
42 | if (err) { | ||
43 | nvgpu_err(tsg->g, | ||
44 | "vgpu_tsg_open failed, tsgid %d", tsg->tsgid); | ||
45 | } | ||
46 | |||
47 | return err; | ||
48 | } | ||
49 | |||
50 | int vgpu_enable_tsg(struct tsg_gk20a *tsg) | ||
51 | { | ||
52 | struct gk20a *g = tsg->g; | ||
53 | struct channel_gk20a *ch; | ||
54 | |||
55 | nvgpu_rwsem_down_read(&tsg->ch_list_lock); | ||
56 | nvgpu_list_for_each_entry(ch, &tsg->ch_list, channel_gk20a, ch_entry) | ||
57 | g->ops.fifo.enable_channel(ch); | ||
58 | nvgpu_rwsem_up_read(&tsg->ch_list_lock); | ||
59 | |||
60 | return 0; | ||
61 | } | ||
62 | |||
63 | int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg, | ||
64 | struct channel_gk20a *ch) | ||
65 | { | ||
66 | struct tegra_vgpu_cmd_msg msg = {}; | ||
67 | struct tegra_vgpu_tsg_bind_unbind_channel_params *p = | ||
68 | &msg.params.tsg_bind_unbind_channel; | ||
69 | int err; | ||
70 | |||
71 | gk20a_dbg_fn(""); | ||
72 | |||
73 | err = gk20a_tsg_bind_channel(tsg, ch); | ||
74 | if (err) | ||
75 | return err; | ||
76 | |||
77 | msg.cmd = TEGRA_VGPU_CMD_TSG_BIND_CHANNEL; | ||
78 | msg.handle = vgpu_get_handle(tsg->g); | ||
79 | p->tsg_id = tsg->tsgid; | ||
80 | p->ch_handle = ch->virt_ctx; | ||
81 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
82 | err = err ? err : msg.ret; | ||
83 | if (err) { | ||
84 | nvgpu_err(tsg->g, | ||
85 | "vgpu_tsg_bind_channel failed, ch %d tsgid %d", | ||
86 | ch->chid, tsg->tsgid); | ||
87 | gk20a_tsg_unbind_channel(ch); | ||
88 | } | ||
89 | |||
90 | return err; | ||
91 | } | ||
92 | |||
93 | int vgpu_tsg_unbind_channel(struct channel_gk20a *ch) | ||
94 | { | ||
95 | struct tegra_vgpu_cmd_msg msg = {}; | ||
96 | struct tegra_vgpu_tsg_bind_unbind_channel_params *p = | ||
97 | &msg.params.tsg_bind_unbind_channel; | ||
98 | int err; | ||
99 | |||
100 | gk20a_dbg_fn(""); | ||
101 | |||
102 | err = gk20a_tsg_unbind_channel(ch); | ||
103 | if (err) | ||
104 | return err; | ||
105 | |||
106 | msg.cmd = TEGRA_VGPU_CMD_TSG_UNBIND_CHANNEL; | ||
107 | msg.handle = vgpu_get_handle(ch->g); | ||
108 | p->ch_handle = ch->virt_ctx; | ||
109 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
110 | err = err ? err : msg.ret; | ||
111 | WARN_ON(err); | ||
112 | |||
113 | return err; | ||
114 | } | ||
115 | |||
116 | int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice) | ||
117 | { | ||
118 | struct tegra_vgpu_cmd_msg msg = {0}; | ||
119 | struct tegra_vgpu_tsg_timeslice_params *p = | ||
120 | &msg.params.tsg_timeslice; | ||
121 | int err; | ||
122 | |||
123 | gk20a_dbg_fn(""); | ||
124 | |||
125 | msg.cmd = TEGRA_VGPU_CMD_TSG_SET_TIMESLICE; | ||
126 | msg.handle = vgpu_get_handle(tsg->g); | ||
127 | p->tsg_id = tsg->tsgid; | ||
128 | p->timeslice_us = timeslice; | ||
129 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
130 | err = err ? err : msg.ret; | ||
131 | WARN_ON(err); | ||
132 | if (!err) | ||
133 | tsg->timeslice_us = timeslice; | ||
134 | |||
135 | return err; | ||
136 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.c new file mode 100644 index 00000000..7768b21d --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.c | |||
@@ -0,0 +1,776 @@ | |||
1 | /* | ||
2 | * Virtualized GPU | ||
3 | * | ||
4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
17 | */ | ||
18 | |||
19 | #include <linux/delay.h> | ||
20 | #include <linux/dma-mapping.h> | ||
21 | #include <linux/pm_runtime.h> | ||
22 | #include <linux/pm_qos.h> | ||
23 | #include <soc/tegra/chip-id.h> | ||
24 | #include <uapi/linux/nvgpu.h> | ||
25 | |||
26 | #include <nvgpu/kmem.h> | ||
27 | #include <nvgpu/bug.h> | ||
28 | #include <nvgpu/enabled.h> | ||
29 | #include <nvgpu/debug.h> | ||
30 | #include <nvgpu/bus.h> | ||
31 | #include <nvgpu/soc.h> | ||
32 | #include <nvgpu/ctxsw_trace.h> | ||
33 | |||
34 | #include "vgpu.h" | ||
35 | #include "fecs_trace_vgpu.h" | ||
36 | #include "clk_vgpu.h" | ||
37 | #include "gk20a/tsg_gk20a.h" | ||
38 | #include "gk20a/channel_gk20a.h" | ||
39 | #include "gm20b/hal_gm20b.h" | ||
40 | |||
41 | #include "common/linux/module.h" | ||
42 | #include "common/linux/os_linux.h" | ||
43 | #include "common/linux/ioctl.h" | ||
44 | #include "common/linux/scale.h" | ||
45 | #include "common/linux/driver_common.h" | ||
46 | |||
47 | #ifdef CONFIG_TEGRA_19x_GPU | ||
48 | #include "common/linux/vgpu/vgpu_t19x.h" | ||
49 | #include <nvgpu_gpuid_t19x.h> | ||
50 | #endif | ||
51 | |||
52 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> | ||
53 | |||
54 | static inline int vgpu_comm_init(struct platform_device *pdev) | ||
55 | { | ||
56 | size_t queue_sizes[] = { TEGRA_VGPU_QUEUE_SIZES }; | ||
57 | |||
58 | return tegra_gr_comm_init(pdev, TEGRA_GR_COMM_CTX_CLIENT, 3, | ||
59 | queue_sizes, TEGRA_VGPU_QUEUE_CMD, | ||
60 | ARRAY_SIZE(queue_sizes)); | ||
61 | } | ||
62 | |||
63 | static inline void vgpu_comm_deinit(void) | ||
64 | { | ||
65 | size_t queue_sizes[] = { TEGRA_VGPU_QUEUE_SIZES }; | ||
66 | |||
67 | tegra_gr_comm_deinit(TEGRA_GR_COMM_CTX_CLIENT, TEGRA_VGPU_QUEUE_CMD, | ||
68 | ARRAY_SIZE(queue_sizes)); | ||
69 | } | ||
70 | |||
71 | int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in, | ||
72 | size_t size_out) | ||
73 | { | ||
74 | void *handle; | ||
75 | size_t size = size_in; | ||
76 | void *data = msg; | ||
77 | int err; | ||
78 | |||
79 | err = tegra_gr_comm_sendrecv(TEGRA_GR_COMM_CTX_CLIENT, | ||
80 | tegra_gr_comm_get_server_vmid(), | ||
81 | TEGRA_VGPU_QUEUE_CMD, &handle, &data, &size); | ||
82 | if (!err) { | ||
83 | WARN_ON(size < size_out); | ||
84 | memcpy(msg, data, size_out); | ||
85 | tegra_gr_comm_release(handle); | ||
86 | } | ||
87 | |||
88 | return err; | ||
89 | } | ||
90 | |||
91 | static u64 vgpu_connect(void) | ||
92 | { | ||
93 | struct tegra_vgpu_cmd_msg msg; | ||
94 | struct tegra_vgpu_connect_params *p = &msg.params.connect; | ||
95 | int err; | ||
96 | |||
97 | msg.cmd = TEGRA_VGPU_CMD_CONNECT; | ||
98 | p->module = TEGRA_VGPU_MODULE_GPU; | ||
99 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
100 | |||
101 | return (err || msg.ret) ? 0 : p->handle; | ||
102 | } | ||
103 | |||
104 | int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value) | ||
105 | { | ||
106 | struct tegra_vgpu_cmd_msg msg; | ||
107 | struct tegra_vgpu_attrib_params *p = &msg.params.attrib; | ||
108 | int err; | ||
109 | |||
110 | msg.cmd = TEGRA_VGPU_CMD_GET_ATTRIBUTE; | ||
111 | msg.handle = handle; | ||
112 | p->attrib = attrib; | ||
113 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
114 | |||
115 | if (err || msg.ret) | ||
116 | return -1; | ||
117 | |||
118 | *value = p->value; | ||
119 | return 0; | ||
120 | } | ||
121 | |||
122 | static void vgpu_handle_channel_event(struct gk20a *g, | ||
123 | struct tegra_vgpu_channel_event_info *info) | ||
124 | { | ||
125 | if (info->id >= g->fifo.num_channels || | ||
126 | info->event_id >= NVGPU_IOCTL_CHANNEL_EVENT_ID_MAX) { | ||
127 | nvgpu_err(g, "invalid channel event"); | ||
128 | return; | ||
129 | } | ||
130 | |||
131 | if (info->is_tsg) { | ||
132 | struct tsg_gk20a *tsg = &g->fifo.tsg[info->id]; | ||
133 | |||
134 | gk20a_tsg_event_id_post_event(tsg, info->event_id); | ||
135 | } else { | ||
136 | struct channel_gk20a *ch = &g->fifo.channel[info->id]; | ||
137 | |||
138 | if (!gk20a_channel_get(ch)) { | ||
139 | nvgpu_err(g, "invalid channel %d for event %d", | ||
140 | (int)info->id, (int)info->event_id); | ||
141 | return; | ||
142 | } | ||
143 | gk20a_channel_event_id_post_event(ch, info->event_id); | ||
144 | gk20a_channel_put(ch); | ||
145 | } | ||
146 | } | ||
147 | |||
148 | |||
149 | |||
150 | static int vgpu_intr_thread(void *dev_id) | ||
151 | { | ||
152 | struct gk20a *g = dev_id; | ||
153 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | ||
154 | |||
155 | while (true) { | ||
156 | struct tegra_vgpu_intr_msg *msg; | ||
157 | u32 sender; | ||
158 | void *handle; | ||
159 | size_t size; | ||
160 | int err; | ||
161 | |||
162 | err = tegra_gr_comm_recv(TEGRA_GR_COMM_CTX_CLIENT, | ||
163 | TEGRA_VGPU_QUEUE_INTR, &handle, | ||
164 | (void **)&msg, &size, &sender); | ||
165 | if (err == -ETIME) | ||
166 | continue; | ||
167 | if (WARN_ON(err)) | ||
168 | continue; | ||
169 | |||
170 | if (msg->event == TEGRA_VGPU_EVENT_ABORT) { | ||
171 | tegra_gr_comm_release(handle); | ||
172 | break; | ||
173 | } | ||
174 | |||
175 | switch (msg->event) { | ||
176 | case TEGRA_VGPU_EVENT_INTR: | ||
177 | if (msg->unit == TEGRA_VGPU_INTR_GR) | ||
178 | vgpu_gr_isr(g, &msg->info.gr_intr); | ||
179 | else if (msg->unit == TEGRA_VGPU_NONSTALL_INTR_GR) | ||
180 | vgpu_gr_nonstall_isr(g, | ||
181 | &msg->info.gr_nonstall_intr); | ||
182 | else if (msg->unit == TEGRA_VGPU_INTR_FIFO) | ||
183 | vgpu_fifo_isr(g, &msg->info.fifo_intr); | ||
184 | else if (msg->unit == TEGRA_VGPU_NONSTALL_INTR_FIFO) | ||
185 | vgpu_fifo_nonstall_isr(g, | ||
186 | &msg->info.fifo_nonstall_intr); | ||
187 | else if (msg->unit == TEGRA_VGPU_NONSTALL_INTR_CE2) | ||
188 | vgpu_ce2_nonstall_isr(g, | ||
189 | &msg->info.ce2_nonstall_intr); | ||
190 | break; | ||
191 | case TEGRA_VGPU_EVENT_FECS_TRACE: | ||
192 | vgpu_fecs_trace_data_update(g); | ||
193 | break; | ||
194 | case TEGRA_VGPU_EVENT_CHANNEL: | ||
195 | vgpu_handle_channel_event(g, &msg->info.channel_event); | ||
196 | break; | ||
197 | case TEGRA_VGPU_EVENT_SM_ESR: | ||
198 | vgpu_gr_handle_sm_esr_event(g, &msg->info.sm_esr); | ||
199 | break; | ||
200 | default: | ||
201 | nvgpu_err(g, "unknown event %u", msg->event); | ||
202 | break; | ||
203 | } | ||
204 | |||
205 | tegra_gr_comm_release(handle); | ||
206 | } | ||
207 | |||
208 | while (!nvgpu_thread_should_stop(&priv->intr_handler)) | ||
209 | msleep(10); | ||
210 | return 0; | ||
211 | } | ||
212 | |||
213 | static void vgpu_remove_support(struct gk20a *g) | ||
214 | { | ||
215 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | ||
216 | struct vgpu_priv_data *priv = | ||
217 | vgpu_get_priv_data_from_dev(dev_from_gk20a(g)); | ||
218 | struct tegra_vgpu_intr_msg msg; | ||
219 | int err; | ||
220 | |||
221 | if (g->dbg_regops_tmp_buf) | ||
222 | nvgpu_kfree(g, g->dbg_regops_tmp_buf); | ||
223 | |||
224 | if (g->pmu.remove_support) | ||
225 | g->pmu.remove_support(&g->pmu); | ||
226 | |||
227 | if (g->gr.remove_support) | ||
228 | g->gr.remove_support(&g->gr); | ||
229 | |||
230 | if (g->fifo.remove_support) | ||
231 | g->fifo.remove_support(&g->fifo); | ||
232 | |||
233 | if (g->mm.remove_support) | ||
234 | g->mm.remove_support(&g->mm); | ||
235 | |||
236 | msg.event = TEGRA_VGPU_EVENT_ABORT; | ||
237 | err = tegra_gr_comm_send(TEGRA_GR_COMM_CTX_CLIENT, | ||
238 | TEGRA_GR_COMM_ID_SELF, TEGRA_VGPU_QUEUE_INTR, | ||
239 | &msg, sizeof(msg)); | ||
240 | WARN_ON(err); | ||
241 | nvgpu_thread_stop(&priv->intr_handler); | ||
242 | |||
243 | /* free mappings to registers, etc*/ | ||
244 | |||
245 | if (l->bar1) { | ||
246 | iounmap(l->bar1); | ||
247 | l->bar1 = NULL; | ||
248 | } | ||
249 | } | ||
250 | |||
251 | static void vgpu_init_vars(struct gk20a *g, struct gk20a_platform *platform) | ||
252 | { | ||
253 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | ||
254 | |||
255 | nvgpu_mutex_init(&g->poweron_lock); | ||
256 | nvgpu_mutex_init(&g->poweroff_lock); | ||
257 | l->regs_saved = l->regs; | ||
258 | l->bar1_saved = l->bar1; | ||
259 | |||
260 | nvgpu_init_list_node(&g->pending_sema_waits); | ||
261 | nvgpu_raw_spinlock_init(&g->pending_sema_waits_lock); | ||
262 | |||
263 | g->aggressive_sync_destroy = platform->aggressive_sync_destroy; | ||
264 | g->aggressive_sync_destroy_thresh = platform->aggressive_sync_destroy_thresh; | ||
265 | g->has_syncpoints = platform->has_syncpoints; | ||
266 | g->ptimer_src_freq = platform->ptimer_src_freq; | ||
267 | g->can_railgate = platform->can_railgate_init; | ||
268 | g->railgate_delay = platform->railgate_delay_init; | ||
269 | |||
270 | __nvgpu_set_enabled(g, NVGPU_MM_UNIFY_ADDRESS_SPACES, | ||
271 | platform->unify_address_spaces); | ||
272 | } | ||
273 | |||
274 | static int vgpu_init_support(struct platform_device *pdev) | ||
275 | { | ||
276 | struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
277 | struct gk20a *g = get_gk20a(&pdev->dev); | ||
278 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | ||
279 | void __iomem *regs; | ||
280 | int err = 0; | ||
281 | |||
282 | if (!r) { | ||
283 | nvgpu_err(g, "failed to get gk20a bar1"); | ||
284 | err = -ENXIO; | ||
285 | goto fail; | ||
286 | } | ||
287 | |||
288 | if (r->name && !strcmp(r->name, "/vgpu")) { | ||
289 | regs = devm_ioremap_resource(&pdev->dev, r); | ||
290 | if (IS_ERR(regs)) { | ||
291 | nvgpu_err(g, "failed to remap gk20a bar1"); | ||
292 | err = PTR_ERR(regs); | ||
293 | goto fail; | ||
294 | } | ||
295 | l->bar1 = regs; | ||
296 | l->bar1_mem = r; | ||
297 | } | ||
298 | |||
299 | nvgpu_mutex_init(&g->dbg_sessions_lock); | ||
300 | nvgpu_mutex_init(&g->client_lock); | ||
301 | |||
302 | nvgpu_init_list_node(&g->profiler_objects); | ||
303 | |||
304 | g->dbg_regops_tmp_buf = nvgpu_kzalloc(g, SZ_4K); | ||
305 | if (!g->dbg_regops_tmp_buf) { | ||
306 | nvgpu_err(g, "couldn't allocate regops tmp buf"); | ||
307 | return -ENOMEM; | ||
308 | } | ||
309 | g->dbg_regops_tmp_buf_ops = | ||
310 | SZ_4K / sizeof(g->dbg_regops_tmp_buf[0]); | ||
311 | |||
312 | g->remove_support = vgpu_remove_support; | ||
313 | return 0; | ||
314 | |||
315 | fail: | ||
316 | vgpu_remove_support(g); | ||
317 | return err; | ||
318 | } | ||
319 | |||
320 | int vgpu_pm_prepare_poweroff(struct device *dev) | ||
321 | { | ||
322 | struct gk20a *g = get_gk20a(dev); | ||
323 | int ret = 0; | ||
324 | |||
325 | gk20a_dbg_fn(""); | ||
326 | |||
327 | if (!g->power_on) | ||
328 | return 0; | ||
329 | |||
330 | ret = gk20a_channel_suspend(g); | ||
331 | if (ret) | ||
332 | return ret; | ||
333 | |||
334 | g->power_on = false; | ||
335 | |||
336 | return ret; | ||
337 | } | ||
338 | |||
339 | static void vgpu_detect_chip(struct gk20a *g) | ||
340 | { | ||
341 | struct nvgpu_gpu_params *p = &g->params; | ||
342 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | ||
343 | |||
344 | p->gpu_arch = priv->constants.arch; | ||
345 | p->gpu_impl = priv->constants.impl; | ||
346 | p->gpu_rev = priv->constants.rev; | ||
347 | |||
348 | gk20a_dbg_info("arch: %x, impl: %x, rev: %x\n", | ||
349 | p->gpu_arch, | ||
350 | p->gpu_impl, | ||
351 | p->gpu_rev); | ||
352 | } | ||
353 | |||
354 | int vgpu_init_gpu_characteristics(struct gk20a *g) | ||
355 | { | ||
356 | int err; | ||
357 | |||
358 | gk20a_dbg_fn(""); | ||
359 | |||
360 | err = gk20a_init_gpu_characteristics(g); | ||
361 | if (err) | ||
362 | return err; | ||
363 | |||
364 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_MAP_BUFFER_BATCH, false); | ||
365 | |||
366 | /* features vgpu does not support */ | ||
367 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_RESCHEDULE_RUNLIST, false); | ||
368 | |||
369 | return 0; | ||
370 | } | ||
371 | |||
372 | int vgpu_read_ptimer(struct gk20a *g, u64 *value) | ||
373 | { | ||
374 | struct tegra_vgpu_cmd_msg msg = {0}; | ||
375 | struct tegra_vgpu_read_ptimer_params *p = &msg.params.read_ptimer; | ||
376 | int err; | ||
377 | |||
378 | gk20a_dbg_fn(""); | ||
379 | |||
380 | msg.cmd = TEGRA_VGPU_CMD_READ_PTIMER; | ||
381 | msg.handle = vgpu_get_handle(g); | ||
382 | |||
383 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
384 | err = err ? err : msg.ret; | ||
385 | if (!err) | ||
386 | *value = p->time; | ||
387 | else | ||
388 | nvgpu_err(g, "vgpu read ptimer failed, err=%d", err); | ||
389 | |||
390 | return err; | ||
391 | } | ||
392 | |||
393 | int vgpu_get_timestamps_zipper(struct gk20a *g, | ||
394 | u32 source_id, u32 count, | ||
395 | struct nvgpu_cpu_time_correlation_sample *samples) | ||
396 | { | ||
397 | struct tegra_vgpu_cmd_msg msg = {0}; | ||
398 | struct tegra_vgpu_get_timestamps_zipper_params *p = | ||
399 | &msg.params.get_timestamps_zipper; | ||
400 | int err; | ||
401 | u32 i; | ||
402 | |||
403 | gk20a_dbg_fn(""); | ||
404 | |||
405 | if (count > TEGRA_VGPU_GET_TIMESTAMPS_ZIPPER_MAX_COUNT) { | ||
406 | nvgpu_err(g, "count %u overflow", count); | ||
407 | return -EINVAL; | ||
408 | } | ||
409 | |||
410 | msg.cmd = TEGRA_VGPU_CMD_GET_TIMESTAMPS_ZIPPER; | ||
411 | msg.handle = vgpu_get_handle(g); | ||
412 | p->source_id = TEGRA_VGPU_GET_TIMESTAMPS_ZIPPER_SRC_ID_TSC; | ||
413 | p->count = count; | ||
414 | |||
415 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
416 | err = err ? err : msg.ret; | ||
417 | if (err) { | ||
418 | nvgpu_err(g, "vgpu get timestamps zipper failed, err=%d", err); | ||
419 | return err; | ||
420 | } | ||
421 | |||
422 | for (i = 0; i < count; i++) { | ||
423 | samples[i].cpu_timestamp = p->samples[i].cpu_timestamp; | ||
424 | samples[i].gpu_timestamp = p->samples[i].gpu_timestamp; | ||
425 | } | ||
426 | |||
427 | return err; | ||
428 | } | ||
429 | |||
430 | static int vgpu_init_hal(struct gk20a *g) | ||
431 | { | ||
432 | u32 ver = g->params.gpu_arch + g->params.gpu_impl; | ||
433 | int err; | ||
434 | |||
435 | switch (ver) { | ||
436 | case GK20A_GPUID_GM20B: | ||
437 | case GK20A_GPUID_GM20B_B: | ||
438 | gk20a_dbg_info("gm20b detected"); | ||
439 | err = vgpu_gm20b_init_hal(g); | ||
440 | break; | ||
441 | case NVGPU_GPUID_GP10B: | ||
442 | gk20a_dbg_info("gp10b detected"); | ||
443 | err = vgpu_gp10b_init_hal(g); | ||
444 | break; | ||
445 | #ifdef CONFIG_TEGRA_19x_GPU | ||
446 | case TEGRA_19x_GPUID: | ||
447 | err = vgpu_t19x_init_hal(g); | ||
448 | break; | ||
449 | #endif | ||
450 | default: | ||
451 | nvgpu_err(g, "no support for %x", ver); | ||
452 | err = -ENODEV; | ||
453 | break; | ||
454 | } | ||
455 | |||
456 | return err; | ||
457 | } | ||
458 | |||
459 | int vgpu_pm_finalize_poweron(struct device *dev) | ||
460 | { | ||
461 | struct gk20a *g = get_gk20a(dev); | ||
462 | int err; | ||
463 | |||
464 | gk20a_dbg_fn(""); | ||
465 | |||
466 | if (g->power_on) | ||
467 | return 0; | ||
468 | |||
469 | g->power_on = true; | ||
470 | |||
471 | vgpu_detect_chip(g); | ||
472 | err = vgpu_init_hal(g); | ||
473 | if (err) | ||
474 | goto done; | ||
475 | |||
476 | if (g->ops.ltc.init_fs_state) | ||
477 | g->ops.ltc.init_fs_state(g); | ||
478 | |||
479 | err = vgpu_init_mm_support(g); | ||
480 | if (err) { | ||
481 | nvgpu_err(g, "failed to init gk20a mm"); | ||
482 | goto done; | ||
483 | } | ||
484 | |||
485 | err = vgpu_init_fifo_support(g); | ||
486 | if (err) { | ||
487 | nvgpu_err(g, "failed to init gk20a fifo"); | ||
488 | goto done; | ||
489 | } | ||
490 | |||
491 | err = vgpu_init_gr_support(g); | ||
492 | if (err) { | ||
493 | nvgpu_err(g, "failed to init gk20a gr"); | ||
494 | goto done; | ||
495 | } | ||
496 | |||
497 | err = g->ops.chip_init_gpu_characteristics(g); | ||
498 | if (err) { | ||
499 | nvgpu_err(g, "failed to init gk20a gpu characteristics"); | ||
500 | goto done; | ||
501 | } | ||
502 | |||
503 | gk20a_ctxsw_trace_init(g); | ||
504 | gk20a_sched_ctrl_init(g); | ||
505 | gk20a_channel_resume(g); | ||
506 | |||
507 | done: | ||
508 | return err; | ||
509 | } | ||
510 | |||
511 | static int vgpu_qos_notify(struct notifier_block *nb, | ||
512 | unsigned long n, void *data) | ||
513 | { | ||
514 | struct gk20a_scale_profile *profile = | ||
515 | container_of(nb, struct gk20a_scale_profile, | ||
516 | qos_notify_block); | ||
517 | struct gk20a *g = get_gk20a(profile->dev); | ||
518 | u32 max_freq; | ||
519 | int err; | ||
520 | |||
521 | gk20a_dbg_fn(""); | ||
522 | |||
523 | max_freq = (u32)pm_qos_read_max_bound(PM_QOS_GPU_FREQ_BOUNDS); | ||
524 | err = vgpu_clk_cap_rate(profile->dev, max_freq); | ||
525 | if (err) | ||
526 | nvgpu_err(g, "%s failed, err=%d", __func__, err); | ||
527 | |||
528 | return NOTIFY_OK; /* need notify call further */ | ||
529 | } | ||
530 | |||
531 | static int vgpu_pm_qos_init(struct device *dev) | ||
532 | { | ||
533 | struct gk20a *g = get_gk20a(dev); | ||
534 | struct gk20a_scale_profile *profile = g->scale_profile; | ||
535 | |||
536 | if (IS_ENABLED(CONFIG_GK20A_DEVFREQ)) { | ||
537 | if (!profile) | ||
538 | return -EINVAL; | ||
539 | } else { | ||
540 | profile = nvgpu_kzalloc(g, sizeof(*profile)); | ||
541 | if (!profile) | ||
542 | return -ENOMEM; | ||
543 | g->scale_profile = profile; | ||
544 | } | ||
545 | |||
546 | profile->dev = dev; | ||
547 | profile->qos_notify_block.notifier_call = vgpu_qos_notify; | ||
548 | pm_qos_add_max_notifier(PM_QOS_GPU_FREQ_BOUNDS, | ||
549 | &profile->qos_notify_block); | ||
550 | return 0; | ||
551 | } | ||
552 | |||
553 | static void vgpu_pm_qos_remove(struct device *dev) | ||
554 | { | ||
555 | struct gk20a *g = get_gk20a(dev); | ||
556 | |||
557 | pm_qos_remove_max_notifier(PM_QOS_GPU_FREQ_BOUNDS, | ||
558 | &g->scale_profile->qos_notify_block); | ||
559 | nvgpu_kfree(g, g->scale_profile); | ||
560 | g->scale_profile = NULL; | ||
561 | } | ||
562 | |||
563 | static int vgpu_pm_init(struct device *dev) | ||
564 | { | ||
565 | struct gk20a *g = get_gk20a(dev); | ||
566 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | ||
567 | unsigned long *freqs; | ||
568 | int num_freqs; | ||
569 | int err = 0; | ||
570 | |||
571 | gk20a_dbg_fn(""); | ||
572 | |||
573 | if (nvgpu_platform_is_simulation(g)) | ||
574 | return 0; | ||
575 | |||
576 | __pm_runtime_disable(dev, false); | ||
577 | |||
578 | if (IS_ENABLED(CONFIG_GK20A_DEVFREQ)) | ||
579 | gk20a_scale_init(dev); | ||
580 | |||
581 | if (l->devfreq) { | ||
582 | /* set min/max frequency based on frequency table */ | ||
583 | err = vgpu_clk_get_freqs(dev, &freqs, &num_freqs); | ||
584 | if (err) | ||
585 | return err; | ||
586 | |||
587 | if (num_freqs < 1) | ||
588 | return -EINVAL; | ||
589 | |||
590 | l->devfreq->min_freq = freqs[0]; | ||
591 | l->devfreq->max_freq = freqs[num_freqs - 1]; | ||
592 | } | ||
593 | |||
594 | err = vgpu_pm_qos_init(dev); | ||
595 | if (err) | ||
596 | return err; | ||
597 | |||
598 | return err; | ||
599 | } | ||
600 | |||
601 | static int vgpu_get_constants(struct gk20a *g) | ||
602 | { | ||
603 | struct tegra_vgpu_cmd_msg msg = {}; | ||
604 | struct tegra_vgpu_constants_params *p = &msg.params.constants; | ||
605 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | ||
606 | int err; | ||
607 | |||
608 | gk20a_dbg_fn(""); | ||
609 | |||
610 | msg.cmd = TEGRA_VGPU_CMD_GET_CONSTANTS; | ||
611 | msg.handle = vgpu_get_handle(g); | ||
612 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
613 | err = err ? err : msg.ret; | ||
614 | |||
615 | if (unlikely(err)) { | ||
616 | nvgpu_err(g, "%s failed, err=%d", __func__, err); | ||
617 | return err; | ||
618 | } | ||
619 | |||
620 | if (unlikely(p->gpc_count > TEGRA_VGPU_MAX_GPC_COUNT || | ||
621 | p->max_tpc_per_gpc_count > TEGRA_VGPU_MAX_TPC_COUNT_PER_GPC)) { | ||
622 | nvgpu_err(g, "gpc_count %d max_tpc_per_gpc %d overflow", | ||
623 | (int)p->gpc_count, (int)p->max_tpc_per_gpc_count); | ||
624 | return -EINVAL; | ||
625 | } | ||
626 | |||
627 | priv->constants = *p; | ||
628 | return 0; | ||
629 | } | ||
630 | |||
631 | int vgpu_probe(struct platform_device *pdev) | ||
632 | { | ||
633 | struct nvgpu_os_linux *l; | ||
634 | struct gk20a *gk20a; | ||
635 | int err; | ||
636 | struct device *dev = &pdev->dev; | ||
637 | struct gk20a_platform *platform = gk20a_get_platform(dev); | ||
638 | struct vgpu_priv_data *priv; | ||
639 | |||
640 | if (!platform) { | ||
641 | dev_err(dev, "no platform data\n"); | ||
642 | return -ENODATA; | ||
643 | } | ||
644 | |||
645 | gk20a_dbg_fn(""); | ||
646 | |||
647 | l = kzalloc(sizeof(*l), GFP_KERNEL); | ||
648 | if (!l) { | ||
649 | dev_err(dev, "couldn't allocate gk20a support"); | ||
650 | return -ENOMEM; | ||
651 | } | ||
652 | gk20a = &l->g; | ||
653 | nvgpu_init_gk20a(gk20a); | ||
654 | |||
655 | nvgpu_kmem_init(gk20a); | ||
656 | |||
657 | err = nvgpu_init_enabled_flags(gk20a); | ||
658 | if (err) { | ||
659 | kfree(gk20a); | ||
660 | return err; | ||
661 | } | ||
662 | |||
663 | l->dev = dev; | ||
664 | if (tegra_platform_is_vdk()) | ||
665 | __nvgpu_set_enabled(gk20a, NVGPU_IS_FMODEL, true); | ||
666 | |||
667 | gk20a->is_virtual = true; | ||
668 | |||
669 | priv = nvgpu_kzalloc(gk20a, sizeof(*priv)); | ||
670 | if (!priv) { | ||
671 | kfree(gk20a); | ||
672 | return -ENOMEM; | ||
673 | } | ||
674 | |||
675 | platform->g = gk20a; | ||
676 | platform->vgpu_priv = priv; | ||
677 | |||
678 | err = gk20a_user_init(dev, INTERFACE_NAME, &nvgpu_class); | ||
679 | if (err) | ||
680 | return err; | ||
681 | |||
682 | vgpu_init_support(pdev); | ||
683 | |||
684 | vgpu_init_vars(gk20a, platform); | ||
685 | |||
686 | init_rwsem(&l->busy_lock); | ||
687 | |||
688 | nvgpu_spinlock_init(&gk20a->mc_enable_lock); | ||
689 | |||
690 | gk20a->ch_wdt_timeout_ms = platform->ch_wdt_timeout_ms; | ||
691 | |||
692 | /* Initialize the platform interface. */ | ||
693 | err = platform->probe(dev); | ||
694 | if (err) { | ||
695 | if (err == -EPROBE_DEFER) | ||
696 | dev_info(dev, "platform probe failed"); | ||
697 | else | ||
698 | dev_err(dev, "platform probe failed"); | ||
699 | return err; | ||
700 | } | ||
701 | |||
702 | if (platform->late_probe) { | ||
703 | err = platform->late_probe(dev); | ||
704 | if (err) { | ||
705 | dev_err(dev, "late probe failed"); | ||
706 | return err; | ||
707 | } | ||
708 | } | ||
709 | |||
710 | err = vgpu_comm_init(pdev); | ||
711 | if (err) { | ||
712 | dev_err(dev, "failed to init comm interface\n"); | ||
713 | return -ENOSYS; | ||
714 | } | ||
715 | |||
716 | priv->virt_handle = vgpu_connect(); | ||
717 | if (!priv->virt_handle) { | ||
718 | dev_err(dev, "failed to connect to server node\n"); | ||
719 | vgpu_comm_deinit(); | ||
720 | return -ENOSYS; | ||
721 | } | ||
722 | |||
723 | err = vgpu_get_constants(gk20a); | ||
724 | if (err) { | ||
725 | vgpu_comm_deinit(); | ||
726 | return err; | ||
727 | } | ||
728 | |||
729 | err = vgpu_pm_init(dev); | ||
730 | if (err) { | ||
731 | dev_err(dev, "pm init failed"); | ||
732 | return err; | ||
733 | } | ||
734 | |||
735 | err = nvgpu_thread_create(&priv->intr_handler, gk20a, | ||
736 | vgpu_intr_thread, "gk20a"); | ||
737 | if (err) | ||
738 | return err; | ||
739 | |||
740 | gk20a_debug_init(gk20a, "gpu.0"); | ||
741 | |||
742 | /* Set DMA parameters to allow larger sgt lists */ | ||
743 | dev->dma_parms = &l->dma_parms; | ||
744 | dma_set_max_seg_size(dev, UINT_MAX); | ||
745 | |||
746 | gk20a->gr_idle_timeout_default = | ||
747 | CONFIG_GK20A_DEFAULT_TIMEOUT; | ||
748 | gk20a->timeouts_enabled = true; | ||
749 | |||
750 | vgpu_create_sysfs(dev); | ||
751 | gk20a_init_gr(gk20a); | ||
752 | |||
753 | nvgpu_ref_init(&gk20a->refcount); | ||
754 | |||
755 | return 0; | ||
756 | } | ||
757 | |||
758 | int vgpu_remove(struct platform_device *pdev) | ||
759 | { | ||
760 | struct device *dev = &pdev->dev; | ||
761 | struct gk20a *g = get_gk20a(dev); | ||
762 | gk20a_dbg_fn(""); | ||
763 | |||
764 | vgpu_pm_qos_remove(dev); | ||
765 | if (g->remove_support) | ||
766 | g->remove_support(g); | ||
767 | |||
768 | vgpu_comm_deinit(); | ||
769 | gk20a_sched_ctrl_cleanup(g); | ||
770 | gk20a_user_deinit(dev, &nvgpu_class); | ||
771 | vgpu_remove_sysfs(dev); | ||
772 | gk20a_get_platform(dev)->g = NULL; | ||
773 | gk20a_put(g); | ||
774 | |||
775 | return 0; | ||
776 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.h b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.h new file mode 100644 index 00000000..ac65dba3 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.h | |||
@@ -0,0 +1,188 @@ | |||
1 | /* | ||
2 | * Virtualized GPU Interfaces | ||
3 | * | ||
4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
17 | */ | ||
18 | |||
19 | #ifndef _VIRT_H_ | ||
20 | #define _VIRT_H_ | ||
21 | |||
22 | struct device; | ||
23 | struct tegra_vgpu_gr_intr_info; | ||
24 | struct tegra_vgpu_fifo_intr_info; | ||
25 | struct tegra_vgpu_cmd_msg; | ||
26 | struct gk20a_platform; | ||
27 | |||
28 | #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION | ||
29 | #include <linux/tegra_gr_comm.h> | ||
30 | #include <linux/tegra_vgpu.h> | ||
31 | #include "gk20a/gk20a.h" | ||
32 | #include "common/linux/platform_gk20a.h" | ||
33 | #include "common/linux/os_linux.h" | ||
34 | |||
35 | #include <nvgpu/thread.h> | ||
36 | |||
37 | struct vgpu_priv_data { | ||
38 | u64 virt_handle; | ||
39 | struct nvgpu_thread intr_handler; | ||
40 | struct tegra_vgpu_constants_params constants; | ||
41 | }; | ||
42 | |||
43 | static inline | ||
44 | struct vgpu_priv_data *vgpu_get_priv_data_from_dev(struct device *dev) | ||
45 | { | ||
46 | struct gk20a_platform *plat = gk20a_get_platform(dev); | ||
47 | |||
48 | return (struct vgpu_priv_data *)plat->vgpu_priv; | ||
49 | } | ||
50 | |||
51 | static inline struct vgpu_priv_data *vgpu_get_priv_data(struct gk20a *g) | ||
52 | { | ||
53 | return vgpu_get_priv_data_from_dev(dev_from_gk20a(g)); | ||
54 | } | ||
55 | |||
56 | static inline u64 vgpu_get_handle_from_dev(struct device *dev) | ||
57 | { | ||
58 | struct vgpu_priv_data *priv = vgpu_get_priv_data_from_dev(dev); | ||
59 | |||
60 | if (unlikely(!priv)) { | ||
61 | dev_err(dev, "invalid vgpu_priv_data in %s\n", __func__); | ||
62 | return INT_MAX; | ||
63 | } | ||
64 | |||
65 | return priv->virt_handle; | ||
66 | } | ||
67 | |||
68 | static inline u64 vgpu_get_handle(struct gk20a *g) | ||
69 | { | ||
70 | return vgpu_get_handle_from_dev(dev_from_gk20a(g)); | ||
71 | } | ||
72 | |||
73 | int vgpu_pm_prepare_poweroff(struct device *dev); | ||
74 | int vgpu_pm_finalize_poweron(struct device *dev); | ||
75 | int vgpu_probe(struct platform_device *dev); | ||
76 | int vgpu_remove(struct platform_device *dev); | ||
77 | u64 vgpu_bar1_map(struct gk20a *g, struct sg_table **sgt, u64 size); | ||
78 | int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info); | ||
79 | int vgpu_gr_nonstall_isr(struct gk20a *g, | ||
80 | struct tegra_vgpu_gr_nonstall_intr_info *info); | ||
81 | int vgpu_gr_alloc_gr_ctx(struct gk20a *g, | ||
82 | struct gr_ctx_desc **__gr_ctx, | ||
83 | struct vm_gk20a *vm, | ||
84 | u32 class, | ||
85 | u32 flags); | ||
86 | void vgpu_gr_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, | ||
87 | struct gr_ctx_desc *gr_ctx); | ||
88 | void vgpu_gr_handle_sm_esr_event(struct gk20a *g, | ||
89 | struct tegra_vgpu_sm_esr_info *info); | ||
90 | int vgpu_gr_init_ctx_state(struct gk20a *g); | ||
91 | int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info); | ||
92 | int vgpu_fifo_nonstall_isr(struct gk20a *g, | ||
93 | struct tegra_vgpu_fifo_nonstall_intr_info *info); | ||
94 | int vgpu_ce2_nonstall_isr(struct gk20a *g, | ||
95 | struct tegra_vgpu_ce2_nonstall_intr_info *info); | ||
96 | u32 vgpu_ce_get_num_pce(struct gk20a *g); | ||
97 | int vgpu_init_mm_support(struct gk20a *g); | ||
98 | int vgpu_init_gr_support(struct gk20a *g); | ||
99 | int vgpu_init_fifo_support(struct gk20a *g); | ||
100 | |||
101 | int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value); | ||
102 | int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in, | ||
103 | size_t size_out); | ||
104 | |||
105 | int vgpu_gm20b_init_hal(struct gk20a *g); | ||
106 | int vgpu_gp10b_init_hal(struct gk20a *g); | ||
107 | |||
108 | int vgpu_init_gpu_characteristics(struct gk20a *g); | ||
109 | |||
110 | void vgpu_create_sysfs(struct device *dev); | ||
111 | void vgpu_remove_sysfs(struct device *dev); | ||
112 | int vgpu_read_ptimer(struct gk20a *g, u64 *value); | ||
113 | int vgpu_get_timestamps_zipper(struct gk20a *g, | ||
114 | u32 source_id, u32 count, | ||
115 | struct nvgpu_cpu_time_correlation_sample *samples); | ||
116 | #else | ||
117 | static inline int vgpu_pm_prepare_poweroff(struct device *dev) | ||
118 | { | ||
119 | return -ENOSYS; | ||
120 | } | ||
121 | static inline int vgpu_pm_finalize_poweron(struct device *dev) | ||
122 | { | ||
123 | return -ENOSYS; | ||
124 | } | ||
125 | static inline int vgpu_probe(struct platform_device *dev) | ||
126 | { | ||
127 | return -ENOSYS; | ||
128 | } | ||
129 | static inline int vgpu_remove(struct platform_device *dev) | ||
130 | { | ||
131 | return -ENOSYS; | ||
132 | } | ||
133 | static inline u64 vgpu_bar1_map(struct gk20a *g, struct sg_table **sgt, | ||
134 | u64 size) | ||
135 | { | ||
136 | return 0; | ||
137 | } | ||
138 | static inline int vgpu_gr_isr(struct gk20a *g, | ||
139 | struct tegra_vgpu_gr_intr_info *info) | ||
140 | { | ||
141 | return 0; | ||
142 | } | ||
143 | static inline int vgpu_gr_alloc_gr_ctx(struct gk20a *g, | ||
144 | struct gr_ctx_desc **__gr_ctx, | ||
145 | struct vm_gk20a *vm, | ||
146 | u32 class, | ||
147 | u32 flags) | ||
148 | { | ||
149 | return -ENOSYS; | ||
150 | } | ||
151 | static inline void vgpu_gr_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, | ||
152 | struct gr_ctx_desc *gr_ctx) | ||
153 | { | ||
154 | } | ||
155 | static inline int vgpu_gr_init_ctx_state(struct gk20a *g) | ||
156 | { | ||
157 | return -ENOSYS; | ||
158 | } | ||
159 | static inline int vgpu_fifo_isr(struct gk20a *g, | ||
160 | struct tegra_vgpu_fifo_intr_info *info) | ||
161 | { | ||
162 | return 0; | ||
163 | } | ||
164 | static inline int vgpu_init_mm_support(struct gk20a *g) | ||
165 | { | ||
166 | return -ENOSYS; | ||
167 | } | ||
168 | static inline int vgpu_init_gr_support(struct gk20a *g) | ||
169 | { | ||
170 | return -ENOSYS; | ||
171 | } | ||
172 | static inline int vgpu_init_fifo_support(struct gk20a *g) | ||
173 | { | ||
174 | return -ENOSYS; | ||
175 | } | ||
176 | |||
177 | static inline int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value) | ||
178 | { | ||
179 | return -ENOSYS; | ||
180 | } | ||
181 | static inline int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in, | ||
182 | size_t size_out) | ||
183 | { | ||
184 | return -ENOSYS; | ||
185 | } | ||
186 | #endif | ||
187 | |||
188 | #endif | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/vgpu_t19x.h b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu_t19x.h new file mode 100644 index 00000000..faa5f772 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu_t19x.h | |||
@@ -0,0 +1,30 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #ifndef _VGPU_T19X_H_ | ||
18 | #define _VGPU_T19X_H_ | ||
19 | |||
20 | struct gk20a; | ||
21 | |||
22 | int vgpu_gv11b_init_hal(struct gk20a *g); | ||
23 | |||
24 | #define vgpu_t19x_init_hal(g) vgpu_gv11b_init_hal(g) | ||
25 | |||
26 | #define TEGRA_19x_VGPU_COMPAT_TEGRA "nvidia,gv11b-vgpu" | ||
27 | extern struct gk20a_platform gv11b_vgpu_tegra_platform; | ||
28 | #define t19x_vgpu_tegra_platform gv11b_vgpu_tegra_platform | ||
29 | |||
30 | #endif | ||