3 files changed, 4 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 220d646b..7e2c35dc 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -182,7 +182,7 @@ int gv11b_init_hal(struct gk20a *g)
         struct gpu_ops *gops = &g->ops;
         struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
 
-        *gops = gv11b_ops;
+        gops->clock_gating = gv11b_ops.clock_gating;
 
         /* boot in non-secure modes for time beeing */
         gops->privsecurity = 0;
diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c
index 892fa442..a2a6cfd3 100644
--- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c
+++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c
@@ -24,6 +24,7 @@
 
 #include "gk20a/platform_gk20a.h"
 #include "gk20a/gk20a.h"
+#include "tegra/linux/clk.h"
 
 #include "gp10b/platform_gp10b.h"
 
@@ -50,6 +51,7 @@ static int gv11b_tegra_probe(struct device *dev)
         platform->g->mm.vidmem_is_vidmem = platform->vidmem_is_vidmem;
 
         gp10b_tegra_get_clocks(dev);
+        nvgpu_linux_init_clk_support(platform->g);
 
         return 0;
 }
diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c
index 4cc45197..4784ee4a 100644
--- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c
@@ -37,7 +37,6 @@ static bool gv11b_is_pmu_supported(struct gk20a *g)
 static int gv11b_pmu_bootstrap(struct pmu_gk20a *pmu)
 {
         struct gk20a *g = gk20a_from_pmu(pmu);
-        struct gk20a_platform *platform = dev_get_drvdata(g->dev);
         struct mm_gk20a *mm = &g->mm;
         struct pmu_ucode_desc *desc = pmu->desc;
         u64 addr_code_lo, addr_data_lo, addr_load_lo;
@@ -64,7 +63,7 @@ static int gv11b_pmu_bootstrap(struct pmu_gk20a *pmu)
                 pmu, GK20A_PMU_DMAIDX_VIRT);
 
         g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu,
-                clk_get_rate(platform->clk[1]));
+                g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_PWRCLK));
 
         addr_args = (pwr_falcon_hwcfg_dmem_size_v(
                 gk20a_readl(g, pwr_falcon_hwcfg_r()))