1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
|
/*
* GV11B Tegra Platform Interface
*
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include <linux/of_platform.h>
#include <linux/debugfs.h>
#include <linux/dma-buf.h>
#include <linux/nvmap.h>
#include <linux/reset.h>
#include <linux/hashtable.h>
#include <uapi/linux/nvgpu.h>
#include "gk20a/platform_gk20a.h"
#include "gk20a/gk20a.h"
#include "tegra/linux/clk.h"
#include "gp10b/platform_gp10b.h"
#include "platform_tegra.h"
#include "gr_gv11b.h"
static int gv11b_tegra_probe(struct device *dev)
{
struct gk20a_platform *platform = dev_get_drvdata(dev);
platform->bypass_smmu = !device_is_iommuable(dev);
platform->disable_bigpage = false;
platform->g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close
= false;
platform->g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close
= false;
platform->g->gr.t18x.ctx_vars.force_preemption_gfxp = false;
platform->g->gr.t18x.ctx_vars.force_preemption_cilp = false;
/* soc memory accessed as system memory aperture */
platform->g->mm.vidmem_is_vidmem = platform->vidmem_is_vidmem;
gp10b_tegra_get_clocks(dev);
nvgpu_linux_init_clk_support(platform->g);
return 0;
}
static bool gv11b_tegra_is_railgated(struct device *dev)
{
bool ret = false;
return ret;
}
static int gv11b_tegra_railgate(struct device *dev)
{
return 0;
}
static int gv11b_tegra_unrailgate(struct device *dev)
{
int ret = 0;
return ret;
}
static int gv11b_tegra_suspend(struct device *dev)
{
return 0;
}
struct gk20a_platform t19x_gpu_tegra_platform = {
.has_syncpoints = false,
/* power management configuration */
/* ptimer src frequency in hz*/
.ptimer_src_freq = 31250000,
.probe = gv11b_tegra_probe,
/* power management callbacks */
.suspend = gv11b_tegra_suspend,
.railgate = gv11b_tegra_railgate,
.unrailgate = gv11b_tegra_unrailgate,
.is_railgated = gv11b_tegra_is_railgated,
.busy = gk20a_tegra_busy,
.idle = gk20a_tegra_idle,
.dump_platform_dependencies = gk20a_tegra_debug_dump,
.default_big_page_size = SZ_64K,
.soc_name = "tegra19x",
.vidmem_is_vidmem = true,
.reset_assert = gp10b_tegra_reset_assert,
.reset_deassert = gp10b_tegra_reset_deassert,
};
|
