diff options
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/Makefile | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c | 621 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h | 87 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 47 |
4 files changed, 732 insertions, 26 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/Makefile b/drivers/gpu/nvgpu/gp10b/Makefile index a51ba15e..f25f7b34 100644 --- a/drivers/gpu/nvgpu/gp10b/Makefile +++ b/drivers/gpu/nvgpu/gp10b/Makefile | |||
@@ -20,6 +20,7 @@ obj-$(CONFIG_GK20A) += \ | |||
20 | fb_gp10b.o \ | 20 | fb_gp10b.o \ |
21 | pmu_gp10b.o \ | 21 | pmu_gp10b.o \ |
22 | hal_gp10b.o \ | 22 | hal_gp10b.o \ |
23 | rpfb_gp10b.o | 23 | rpfb_gp10b.o \ |
24 | gp10b_gating_reglist.o | ||
24 | 25 | ||
25 | obj-$(CONFIG_TEGRA_GK20A) += platform_gp10b_tegra.o | 26 | obj-$(CONFIG_TEGRA_GK20A) += platform_gp10b_tegra.o |
diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c new file mode 100644 index 00000000..f8ee80c3 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c | |||
@@ -0,0 +1,621 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License as published by | ||
6 | * the Free Software Foundation; either version 2 of the License. | ||
7 | * | ||
8 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License along | ||
14 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
15 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | ||
16 | * | ||
17 | * This file is autogenerated. Do not edit. | ||
18 | */ | ||
19 | |||
20 | #ifndef __gp10b_gating_reglist_h__ | ||
21 | #define __gp10b_gating_reglist_h__ | ||
22 | |||
23 | #include <linux/types.h> | ||
24 | #include "gp10b_gating_reglist.h" | ||
25 | |||
26 | struct gating_desc { | ||
27 | u32 addr; | ||
28 | u32 prod; | ||
29 | u32 disable; | ||
30 | }; | ||
31 | /* slcg bus */ | ||
32 | static const struct gating_desc gp10b_slcg_bus[] = { | ||
33 | {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, | ||
34 | }; | ||
35 | |||
36 | /* slcg ce2 */ | ||
37 | static const struct gating_desc gp10b_slcg_ce2[] = { | ||
38 | {.addr = 0x00106f28, .prod = 0x00000000, .disable = 0x000007fe}, | ||
39 | }; | ||
40 | |||
41 | /* slcg chiplet */ | ||
42 | static const struct gating_desc gp10b_slcg_chiplet[] = { | ||
43 | {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, | ||
44 | {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, | ||
45 | {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, | ||
46 | {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007}, | ||
47 | }; | ||
48 | |||
49 | /* slcg fb */ | ||
50 | static const struct gating_desc gp10b_slcg_fb[] = { | ||
51 | {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
52 | {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
53 | }; | ||
54 | |||
55 | /* slcg fifo */ | ||
56 | static const struct gating_desc gp10b_slcg_fifo[] = { | ||
57 | {.addr = 0x000026ac, .prod = 0x00000100, .disable = 0x0001fffe}, | ||
58 | }; | ||
59 | |||
60 | /* slcg gr */ | ||
61 | static const struct gating_desc gp10b_slcg_gr[] = { | ||
62 | {.addr = 0x004041f4, .prod = 0x00000000, .disable = 0x03fffffe}, | ||
63 | {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
64 | {.addr = 0x00409894, .prod = 0x00000040, .disable = 0x03fffffe}, | ||
65 | {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, | ||
66 | {.addr = 0x00406004, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
67 | {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, | ||
68 | {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, | ||
69 | {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, | ||
70 | {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe}, | ||
71 | {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
72 | {.addr = 0x0041a894, .prod = 0x00000040, .disable = 0x03fffffe}, | ||
73 | {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, | ||
74 | {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
75 | {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, | ||
76 | {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x0000003e}, | ||
77 | {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, | ||
78 | {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
79 | {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, | ||
80 | {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
81 | {.addr = 0x00418c74, .prod = 0xffffffc0, .disable = 0xfffffffe}, | ||
82 | {.addr = 0x00418cf4, .prod = 0xfffffffc, .disable = 0xfffffffe}, | ||
83 | {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, | ||
84 | {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, | ||
85 | {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, | ||
86 | {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, | ||
87 | {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
88 | {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x0000ffff}, | ||
89 | {.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e}, | ||
90 | {.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
91 | {.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e}, | ||
92 | {.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e}, | ||
93 | {.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe}, | ||
94 | {.addr = 0x00419a6c, .prod = 0x00000000, .disable = 0x0000000e}, | ||
95 | {.addr = 0x00419a74, .prod = 0x00000000, .disable = 0x0000000e}, | ||
96 | {.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e}, | ||
97 | {.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e}, | ||
98 | {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, | ||
99 | {.addr = 0x00419cd8, .prod = 0x00000000, .disable = 0x001ffffe}, | ||
100 | {.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe}, | ||
101 | {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, | ||
102 | {.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe}, | ||
103 | {.addr = 0x00419fdc, .prod = 0xffedff00, .disable = 0xfffffffe}, | ||
104 | {.addr = 0x00419fe4, .prod = 0x00001b00, .disable = 0x00001ffe}, | ||
105 | {.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe}, | ||
106 | {.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
107 | {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, | ||
108 | {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, | ||
109 | {.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe}, | ||
110 | {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
111 | {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
112 | {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
113 | {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x0000ffff}, | ||
114 | }; | ||
115 | |||
116 | /* slcg ltc */ | ||
117 | static const struct gating_desc gp10b_slcg_ltc[] = { | ||
118 | {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
119 | {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
120 | }; | ||
121 | |||
122 | /* slcg perf */ | ||
123 | static const struct gating_desc gp10b_slcg_perf[] = { | ||
124 | {.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000}, | ||
125 | {.addr = 0x001bc018, .prod = 0x000001ff, .disable = 0x00000000}, | ||
126 | {.addr = 0x001b8018, .prod = 0x000001ff, .disable = 0x00000000}, | ||
127 | {.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000}, | ||
128 | }; | ||
129 | |||
130 | /* slcg PriRing */ | ||
131 | static const struct gating_desc gp10b_slcg_priring[] = { | ||
132 | {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, | ||
133 | }; | ||
134 | |||
135 | /* slcg pwr_csb */ | ||
136 | static const struct gating_desc gp10b_slcg_pwr_csb[] = { | ||
137 | {.addr = 0x00000134, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
138 | {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f}, | ||
139 | {.addr = 0x00000a74, .prod = 0x00000000, .disable = 0x00007ffe}, | ||
140 | {.addr = 0x000016b8, .prod = 0x00000000, .disable = 0x0000000f}, | ||
141 | }; | ||
142 | |||
143 | /* slcg pmu */ | ||
144 | static const struct gating_desc gp10b_slcg_pmu[] = { | ||
145 | {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
146 | {.addr = 0x0010aa74, .prod = 0x00000000, .disable = 0x00007ffe}, | ||
147 | {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, | ||
148 | }; | ||
149 | |||
150 | /* therm gr */ | ||
151 | static const struct gating_desc gp10b_slcg_therm[] = { | ||
152 | {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f}, | ||
153 | }; | ||
154 | |||
155 | /* slcg Xbar */ | ||
156 | static const struct gating_desc gp10b_slcg_xbar[] = { | ||
157 | {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
158 | {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
159 | }; | ||
160 | |||
161 | /* blcg bus */ | ||
162 | static const struct gating_desc gp10b_blcg_bus[] = { | ||
163 | {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, | ||
164 | }; | ||
165 | |||
166 | /* blcg ctxsw prog */ | ||
167 | static const struct gating_desc gp10b_blcg_ctxsw_prog[] = { | ||
168 | }; | ||
169 | |||
170 | /* blcg fb */ | ||
171 | static const struct gating_desc gp10b_blcg_fb[] = { | ||
172 | {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, | ||
173 | {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, | ||
174 | {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, | ||
175 | {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, | ||
176 | {.addr = 0x00100d1c, .prod = 0x00000042, .disable = 0x00000000}, | ||
177 | {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000}, | ||
178 | }; | ||
179 | |||
180 | /* blcg fifo */ | ||
181 | static const struct gating_desc gp10b_blcg_fifo[] = { | ||
182 | {.addr = 0x000026a4, .prod = 0x0000c242, .disable = 0x00000000}, | ||
183 | }; | ||
184 | |||
185 | /* blcg gr */ | ||
186 | static const struct gating_desc gp10b_blcg_gr[] = { | ||
187 | {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000}, | ||
188 | {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, | ||
189 | {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, | ||
190 | {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000}, | ||
191 | {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000}, | ||
192 | {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000}, | ||
193 | {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000}, | ||
194 | {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000}, | ||
195 | {.addr = 0x00407000, .prod = 0x4000c141, .disable = 0x00000000}, | ||
196 | {.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000}, | ||
197 | {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000}, | ||
198 | {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, | ||
199 | {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000}, | ||
200 | {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000}, | ||
201 | {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000}, | ||
202 | {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, | ||
203 | {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000}, | ||
204 | {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000}, | ||
205 | {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000}, | ||
206 | {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000}, | ||
207 | {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000}, | ||
208 | {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000}, | ||
209 | {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000}, | ||
210 | {.addr = 0x00418e0c, .prod = 0x0000c444, .disable = 0x00000000}, | ||
211 | {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000}, | ||
212 | {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, | ||
213 | {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000}, | ||
214 | {.addr = 0x00419a40, .prod = 0x0000c242, .disable = 0x00000000}, | ||
215 | {.addr = 0x00419a48, .prod = 0x0000c242, .disable = 0x00000000}, | ||
216 | {.addr = 0x00419a50, .prod = 0x0000c242, .disable = 0x00000000}, | ||
217 | {.addr = 0x00419a58, .prod = 0x0000c242, .disable = 0x00000000}, | ||
218 | {.addr = 0x00419a60, .prod = 0x0000c242, .disable = 0x00000000}, | ||
219 | {.addr = 0x00419a68, .prod = 0x0000c242, .disable = 0x00000000}, | ||
220 | {.addr = 0x00419a70, .prod = 0x0000c242, .disable = 0x00000000}, | ||
221 | {.addr = 0x00419a78, .prod = 0x0000c242, .disable = 0x00000000}, | ||
222 | {.addr = 0x00419a80, .prod = 0x0000c242, .disable = 0x00000000}, | ||
223 | {.addr = 0x00419868, .prod = 0x00008242, .disable = 0x00000000}, | ||
224 | {.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000}, | ||
225 | {.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000}, | ||
226 | {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000}, | ||
227 | {.addr = 0x00419fd0, .prod = 0x0000c044, .disable = 0x00000000}, | ||
228 | {.addr = 0x00419fd8, .prod = 0x0000c046, .disable = 0x00000000}, | ||
229 | {.addr = 0x00419fe0, .prod = 0x0000c044, .disable = 0x00000000}, | ||
230 | {.addr = 0x00419fe8, .prod = 0x0000c042, .disable = 0x00000000}, | ||
231 | {.addr = 0x00419ff0, .prod = 0x0000c045, .disable = 0x00000000}, | ||
232 | {.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000}, | ||
233 | {.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000}, | ||
234 | {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000}, | ||
235 | {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000}, | ||
236 | {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000}, | ||
237 | {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000}, | ||
238 | {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000}, | ||
239 | {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000}, | ||
240 | }; | ||
241 | |||
242 | /* blcg ltc */ | ||
243 | static const struct gating_desc gp10b_blcg_ltc[] = { | ||
244 | {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, | ||
245 | {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, | ||
246 | {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, | ||
247 | {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, | ||
248 | }; | ||
249 | |||
250 | /* blcg pwr_csb */ | ||
251 | static const struct gating_desc gp10b_blcg_pwr_csb[] = { | ||
252 | {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000}, | ||
253 | }; | ||
254 | |||
255 | /* blcg pmu */ | ||
256 | static const struct gating_desc gp10b_blcg_pmu[] = { | ||
257 | {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, | ||
258 | }; | ||
259 | |||
260 | /* blcg Xbar */ | ||
261 | static const struct gating_desc gp10b_blcg_xbar[] = { | ||
262 | {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000}, | ||
263 | {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000}, | ||
264 | }; | ||
265 | |||
266 | /* pg gr */ | ||
267 | static const struct gating_desc gp10b_pg_gr[] = { | ||
268 | }; | ||
269 | |||
270 | /* inline functions */ | ||
271 | void gp10b_slcg_bus_load_gating_prod(struct gk20a *g, | ||
272 | bool prod) | ||
273 | { | ||
274 | u32 i; | ||
275 | u32 size = sizeof(gp10b_slcg_bus) / sizeof(struct gating_desc); | ||
276 | for (i = 0; i < size; i++) { | ||
277 | if (prod) | ||
278 | gk20a_writel(g, gp10b_slcg_bus[i].addr, | ||
279 | gp10b_slcg_bus[i].prod); | ||
280 | else | ||
281 | gk20a_writel(g, gp10b_slcg_bus[i].addr, | ||
282 | gp10b_slcg_bus[i].disable); | ||
283 | } | ||
284 | } | ||
285 | |||
286 | void gp10b_slcg_ce2_load_gating_prod(struct gk20a *g, | ||
287 | bool prod) | ||
288 | { | ||
289 | u32 i; | ||
290 | u32 size = sizeof(gp10b_slcg_ce2) / sizeof(struct gating_desc); | ||
291 | for (i = 0; i < size; i++) { | ||
292 | if (prod) | ||
293 | gk20a_writel(g, gp10b_slcg_ce2[i].addr, | ||
294 | gp10b_slcg_ce2[i].prod); | ||
295 | else | ||
296 | gk20a_writel(g, gp10b_slcg_ce2[i].addr, | ||
297 | gp10b_slcg_ce2[i].disable); | ||
298 | } | ||
299 | } | ||
300 | |||
301 | void gp10b_slcg_chiplet_load_gating_prod(struct gk20a *g, | ||
302 | bool prod) | ||
303 | { | ||
304 | u32 i; | ||
305 | u32 size = sizeof(gp10b_slcg_chiplet) / sizeof(struct gating_desc); | ||
306 | for (i = 0; i < size; i++) { | ||
307 | if (prod) | ||
308 | gk20a_writel(g, gp10b_slcg_chiplet[i].addr, | ||
309 | gp10b_slcg_chiplet[i].prod); | ||
310 | else | ||
311 | gk20a_writel(g, gp10b_slcg_chiplet[i].addr, | ||
312 | gp10b_slcg_chiplet[i].disable); | ||
313 | } | ||
314 | } | ||
315 | |||
316 | void gp10b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | ||
317 | bool prod) | ||
318 | { | ||
319 | } | ||
320 | |||
321 | void gp10b_slcg_fb_load_gating_prod(struct gk20a *g, | ||
322 | bool prod) | ||
323 | { | ||
324 | u32 i; | ||
325 | u32 size = sizeof(gp10b_slcg_fb) / sizeof(struct gating_desc); | ||
326 | for (i = 0; i < size; i++) { | ||
327 | if (prod) | ||
328 | gk20a_writel(g, gp10b_slcg_fb[i].addr, | ||
329 | gp10b_slcg_fb[i].prod); | ||
330 | else | ||
331 | gk20a_writel(g, gp10b_slcg_fb[i].addr, | ||
332 | gp10b_slcg_fb[i].disable); | ||
333 | } | ||
334 | } | ||
335 | |||
336 | void gp10b_slcg_fifo_load_gating_prod(struct gk20a *g, | ||
337 | bool prod) | ||
338 | { | ||
339 | u32 i; | ||
340 | u32 size = sizeof(gp10b_slcg_fifo) / sizeof(struct gating_desc); | ||
341 | for (i = 0; i < size; i++) { | ||
342 | if (prod) | ||
343 | gk20a_writel(g, gp10b_slcg_fifo[i].addr, | ||
344 | gp10b_slcg_fifo[i].prod); | ||
345 | else | ||
346 | gk20a_writel(g, gp10b_slcg_fifo[i].addr, | ||
347 | gp10b_slcg_fifo[i].disable); | ||
348 | } | ||
349 | } | ||
350 | |||
351 | void gr_gp10b_slcg_gr_load_gating_prod(struct gk20a *g, | ||
352 | bool prod) | ||
353 | { | ||
354 | u32 i; | ||
355 | u32 size = sizeof(gp10b_slcg_gr) / sizeof(struct gating_desc); | ||
356 | for (i = 0; i < size; i++) { | ||
357 | if (prod) | ||
358 | gk20a_writel(g, gp10b_slcg_gr[i].addr, | ||
359 | gp10b_slcg_gr[i].prod); | ||
360 | else | ||
361 | gk20a_writel(g, gp10b_slcg_gr[i].addr, | ||
362 | gp10b_slcg_gr[i].disable); | ||
363 | } | ||
364 | } | ||
365 | |||
366 | void ltc_gp10b_slcg_ltc_load_gating_prod(struct gk20a *g, | ||
367 | bool prod) | ||
368 | { | ||
369 | u32 i; | ||
370 | u32 size = sizeof(gp10b_slcg_ltc) / sizeof(struct gating_desc); | ||
371 | for (i = 0; i < size; i++) { | ||
372 | if (prod) | ||
373 | gk20a_writel(g, gp10b_slcg_ltc[i].addr, | ||
374 | gp10b_slcg_ltc[i].prod); | ||
375 | else | ||
376 | gk20a_writel(g, gp10b_slcg_ltc[i].addr, | ||
377 | gp10b_slcg_ltc[i].disable); | ||
378 | } | ||
379 | } | ||
380 | |||
381 | void gp10b_slcg_perf_load_gating_prod(struct gk20a *g, | ||
382 | bool prod) | ||
383 | { | ||
384 | u32 i; | ||
385 | u32 size = sizeof(gp10b_slcg_perf) / sizeof(struct gating_desc); | ||
386 | for (i = 0; i < size; i++) { | ||
387 | if (prod) | ||
388 | gk20a_writel(g, gp10b_slcg_perf[i].addr, | ||
389 | gp10b_slcg_perf[i].prod); | ||
390 | else | ||
391 | gk20a_writel(g, gp10b_slcg_perf[i].addr, | ||
392 | gp10b_slcg_perf[i].disable); | ||
393 | } | ||
394 | } | ||
395 | |||
396 | void gp10b_slcg_priring_load_gating_prod(struct gk20a *g, | ||
397 | bool prod) | ||
398 | { | ||
399 | u32 i; | ||
400 | u32 size = sizeof(gp10b_slcg_priring) / sizeof(struct gating_desc); | ||
401 | for (i = 0; i < size; i++) { | ||
402 | if (prod) | ||
403 | gk20a_writel(g, gp10b_slcg_priring[i].addr, | ||
404 | gp10b_slcg_priring[i].prod); | ||
405 | else | ||
406 | gk20a_writel(g, gp10b_slcg_priring[i].addr, | ||
407 | gp10b_slcg_priring[i].disable); | ||
408 | } | ||
409 | } | ||
410 | |||
411 | void gp10b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, | ||
412 | bool prod) | ||
413 | { | ||
414 | u32 i; | ||
415 | u32 size = sizeof(gp10b_slcg_pwr_csb) / sizeof(struct gating_desc); | ||
416 | for (i = 0; i < size; i++) { | ||
417 | if (prod) | ||
418 | gk20a_writel(g, gp10b_slcg_pwr_csb[i].addr, | ||
419 | gp10b_slcg_pwr_csb[i].prod); | ||
420 | else | ||
421 | gk20a_writel(g, gp10b_slcg_pwr_csb[i].addr, | ||
422 | gp10b_slcg_pwr_csb[i].disable); | ||
423 | } | ||
424 | } | ||
425 | |||
426 | void gp10b_slcg_pmu_load_gating_prod(struct gk20a *g, | ||
427 | bool prod) | ||
428 | { | ||
429 | u32 i; | ||
430 | u32 size = sizeof(gp10b_slcg_pmu) / sizeof(struct gating_desc); | ||
431 | for (i = 0; i < size; i++) { | ||
432 | if (prod) | ||
433 | gk20a_writel(g, gp10b_slcg_pmu[i].addr, | ||
434 | gp10b_slcg_pmu[i].prod); | ||
435 | else | ||
436 | gk20a_writel(g, gp10b_slcg_pmu[i].addr, | ||
437 | gp10b_slcg_pmu[i].disable); | ||
438 | } | ||
439 | } | ||
440 | |||
441 | void gp10b_slcg_therm_load_gating_prod(struct gk20a *g, | ||
442 | bool prod) | ||
443 | { | ||
444 | u32 i; | ||
445 | u32 size = sizeof(gp10b_slcg_therm) / sizeof(struct gating_desc); | ||
446 | for (i = 0; i < size; i++) { | ||
447 | if (prod) | ||
448 | gk20a_writel(g, gp10b_slcg_therm[i].addr, | ||
449 | gp10b_slcg_therm[i].prod); | ||
450 | else | ||
451 | gk20a_writel(g, gp10b_slcg_therm[i].addr, | ||
452 | gp10b_slcg_therm[i].disable); | ||
453 | } | ||
454 | } | ||
455 | |||
456 | void gp10b_slcg_xbar_load_gating_prod(struct gk20a *g, | ||
457 | bool prod) | ||
458 | { | ||
459 | u32 i; | ||
460 | u32 size = sizeof(gp10b_slcg_xbar) / sizeof(struct gating_desc); | ||
461 | for (i = 0; i < size; i++) { | ||
462 | if (prod) | ||
463 | gk20a_writel(g, gp10b_slcg_xbar[i].addr, | ||
464 | gp10b_slcg_xbar[i].prod); | ||
465 | else | ||
466 | gk20a_writel(g, gp10b_slcg_xbar[i].addr, | ||
467 | gp10b_slcg_xbar[i].disable); | ||
468 | } | ||
469 | } | ||
470 | |||
471 | void gp10b_blcg_bus_load_gating_prod(struct gk20a *g, | ||
472 | bool prod) | ||
473 | { | ||
474 | u32 i; | ||
475 | u32 size = sizeof(gp10b_blcg_bus) / sizeof(struct gating_desc); | ||
476 | for (i = 0; i < size; i++) { | ||
477 | if (prod) | ||
478 | gk20a_writel(g, gp10b_blcg_bus[i].addr, | ||
479 | gp10b_blcg_bus[i].prod); | ||
480 | else | ||
481 | gk20a_writel(g, gp10b_blcg_bus[i].addr, | ||
482 | gp10b_blcg_bus[i].disable); | ||
483 | } | ||
484 | } | ||
485 | |||
486 | void gp10b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | ||
487 | bool prod) | ||
488 | { | ||
489 | u32 i; | ||
490 | u32 size = sizeof(gp10b_blcg_ctxsw_prog) / sizeof(struct gating_desc); | ||
491 | for (i = 0; i < size; i++) { | ||
492 | if (prod) | ||
493 | gk20a_writel(g, gp10b_blcg_ctxsw_prog[i].addr, | ||
494 | gp10b_blcg_ctxsw_prog[i].prod); | ||
495 | else | ||
496 | gk20a_writel(g, gp10b_blcg_ctxsw_prog[i].addr, | ||
497 | gp10b_blcg_ctxsw_prog[i].disable); | ||
498 | } | ||
499 | } | ||
500 | |||
501 | void gp10b_blcg_fb_load_gating_prod(struct gk20a *g, | ||
502 | bool prod) | ||
503 | { | ||
504 | u32 i; | ||
505 | u32 size = sizeof(gp10b_blcg_fb) / sizeof(struct gating_desc); | ||
506 | for (i = 0; i < size; i++) { | ||
507 | if (prod) | ||
508 | gk20a_writel(g, gp10b_blcg_fb[i].addr, | ||
509 | gp10b_blcg_fb[i].prod); | ||
510 | else | ||
511 | gk20a_writel(g, gp10b_blcg_fb[i].addr, | ||
512 | gp10b_blcg_fb[i].disable); | ||
513 | } | ||
514 | } | ||
515 | |||
516 | void gp10b_blcg_fifo_load_gating_prod(struct gk20a *g, | ||
517 | bool prod) | ||
518 | { | ||
519 | u32 i; | ||
520 | u32 size = sizeof(gp10b_blcg_fifo) / sizeof(struct gating_desc); | ||
521 | for (i = 0; i < size; i++) { | ||
522 | if (prod) | ||
523 | gk20a_writel(g, gp10b_blcg_fifo[i].addr, | ||
524 | gp10b_blcg_fifo[i].prod); | ||
525 | else | ||
526 | gk20a_writel(g, gp10b_blcg_fifo[i].addr, | ||
527 | gp10b_blcg_fifo[i].disable); | ||
528 | } | ||
529 | } | ||
530 | |||
531 | void gp10b_blcg_gr_load_gating_prod(struct gk20a *g, | ||
532 | bool prod) | ||
533 | { | ||
534 | u32 i; | ||
535 | u32 size = sizeof(gp10b_blcg_gr) / sizeof(struct gating_desc); | ||
536 | for (i = 0; i < size; i++) { | ||
537 | if (prod) | ||
538 | gk20a_writel(g, gp10b_blcg_gr[i].addr, | ||
539 | gp10b_blcg_gr[i].prod); | ||
540 | else | ||
541 | gk20a_writel(g, gp10b_blcg_gr[i].addr, | ||
542 | gp10b_blcg_gr[i].disable); | ||
543 | } | ||
544 | } | ||
545 | |||
546 | void gp10b_blcg_ltc_load_gating_prod(struct gk20a *g, | ||
547 | bool prod) | ||
548 | { | ||
549 | u32 i; | ||
550 | u32 size = sizeof(gp10b_blcg_ltc) / sizeof(struct gating_desc); | ||
551 | for (i = 0; i < size; i++) { | ||
552 | if (prod) | ||
553 | gk20a_writel(g, gp10b_blcg_ltc[i].addr, | ||
554 | gp10b_blcg_ltc[i].prod); | ||
555 | else | ||
556 | gk20a_writel(g, gp10b_blcg_ltc[i].addr, | ||
557 | gp10b_blcg_ltc[i].disable); | ||
558 | } | ||
559 | } | ||
560 | |||
561 | void gp10b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, | ||
562 | bool prod) | ||
563 | { | ||
564 | u32 i; | ||
565 | u32 size = sizeof(gp10b_blcg_pwr_csb) / sizeof(struct gating_desc); | ||
566 | for (i = 0; i < size; i++) { | ||
567 | if (prod) | ||
568 | gk20a_writel(g, gp10b_blcg_pwr_csb[i].addr, | ||
569 | gp10b_blcg_pwr_csb[i].prod); | ||
570 | else | ||
571 | gk20a_writel(g, gp10b_blcg_pwr_csb[i].addr, | ||
572 | gp10b_blcg_pwr_csb[i].disable); | ||
573 | } | ||
574 | } | ||
575 | |||
576 | void gp10b_blcg_pmu_load_gating_prod(struct gk20a *g, | ||
577 | bool prod) | ||
578 | { | ||
579 | u32 i; | ||
580 | u32 size = sizeof(gp10b_blcg_pmu) / sizeof(struct gating_desc); | ||
581 | for (i = 0; i < size; i++) { | ||
582 | if (prod) | ||
583 | gk20a_writel(g, gp10b_blcg_pmu[i].addr, | ||
584 | gp10b_blcg_pmu[i].prod); | ||
585 | else | ||
586 | gk20a_writel(g, gp10b_blcg_pmu[i].addr, | ||
587 | gp10b_blcg_pmu[i].disable); | ||
588 | } | ||
589 | } | ||
590 | |||
591 | void gp10b_blcg_xbar_load_gating_prod(struct gk20a *g, | ||
592 | bool prod) | ||
593 | { | ||
594 | u32 i; | ||
595 | u32 size = sizeof(gp10b_blcg_xbar) / sizeof(struct gating_desc); | ||
596 | for (i = 0; i < size; i++) { | ||
597 | if (prod) | ||
598 | gk20a_writel(g, gp10b_blcg_xbar[i].addr, | ||
599 | gp10b_blcg_xbar[i].prod); | ||
600 | else | ||
601 | gk20a_writel(g, gp10b_blcg_xbar[i].addr, | ||
602 | gp10b_blcg_xbar[i].disable); | ||
603 | } | ||
604 | } | ||
605 | |||
606 | void gr_gp10b_pg_gr_load_gating_prod(struct gk20a *g, | ||
607 | bool prod) | ||
608 | { | ||
609 | u32 i; | ||
610 | u32 size = sizeof(gp10b_pg_gr) / sizeof(struct gating_desc); | ||
611 | for (i = 0; i < size; i++) { | ||
612 | if (prod) | ||
613 | gk20a_writel(g, gp10b_pg_gr[i].addr, | ||
614 | gp10b_pg_gr[i].prod); | ||
615 | else | ||
616 | gk20a_writel(g, gp10b_pg_gr[i].addr, | ||
617 | gp10b_pg_gr[i].disable); | ||
618 | } | ||
619 | } | ||
620 | |||
621 | #endif /* __gp10b_gating_reglist_h__ */ | ||
diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h new file mode 100644 index 00000000..465a0b4d --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h | |||
@@ -0,0 +1,87 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2015, NVIDIA Corporation. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include "gk20a/gk20a.h" | ||
18 | |||
19 | void gp10b_slcg_bus_load_gating_prod(struct gk20a *g, | ||
20 | bool prod); | ||
21 | |||
22 | void gp10b_slcg_chiplet_load_gating_prod(struct gk20a *g, | ||
23 | bool prod); | ||
24 | |||
25 | void gp10b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | ||
26 | bool prod); | ||
27 | |||
28 | void gp10b_slcg_fb_load_gating_prod(struct gk20a *g, | ||
29 | bool prod); | ||
30 | |||
31 | void gp10b_slcg_fifo_load_gating_prod(struct gk20a *g, | ||
32 | bool prod); | ||
33 | |||
34 | void gr_gp10b_slcg_gr_load_gating_prod(struct gk20a *g, | ||
35 | bool prod); | ||
36 | |||
37 | void ltc_gp10b_slcg_ltc_load_gating_prod(struct gk20a *g, | ||
38 | bool prod); | ||
39 | |||
40 | void gp10b_slcg_perf_load_gating_prod(struct gk20a *g, | ||
41 | bool prod); | ||
42 | |||
43 | void gp10b_slcg_priring_load_gating_prod(struct gk20a *g, | ||
44 | bool prod); | ||
45 | |||
46 | void gp10b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, | ||
47 | bool prod); | ||
48 | |||
49 | void gp10b_slcg_pmu_load_gating_prod(struct gk20a *g, | ||
50 | bool prod); | ||
51 | |||
52 | void gp10b_slcg_therm_load_gating_prod(struct gk20a *g, | ||
53 | bool prod); | ||
54 | |||
55 | void gp10b_slcg_xbar_load_gating_prod(struct gk20a *g, | ||
56 | bool prod); | ||
57 | |||
58 | void gp10b_blcg_bus_load_gating_prod(struct gk20a *g, | ||
59 | bool prod); | ||
60 | |||
61 | void gp10b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | ||
62 | bool prod); | ||
63 | |||
64 | void gp10b_blcg_fb_load_gating_prod(struct gk20a *g, | ||
65 | bool prod); | ||
66 | |||
67 | void gp10b_blcg_fifo_load_gating_prod(struct gk20a *g, | ||
68 | bool prod); | ||
69 | |||
70 | void gp10b_blcg_gr_load_gating_prod(struct gk20a *g, | ||
71 | bool prod); | ||
72 | |||
73 | void gp10b_blcg_ltc_load_gating_prod(struct gk20a *g, | ||
74 | bool prod); | ||
75 | |||
76 | void gp10b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, | ||
77 | bool prod); | ||
78 | |||
79 | void gp10b_blcg_pmu_load_gating_prod(struct gk20a *g, | ||
80 | bool prod); | ||
81 | |||
82 | void gp10b_blcg_xbar_load_gating_prod(struct gk20a *g, | ||
83 | bool prod); | ||
84 | |||
85 | void gr_gp10b_pg_gr_load_gating_prod(struct gk20a *g, | ||
86 | bool prod); | ||
87 | |||
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 914d8089..9d099479 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -29,60 +29,57 @@ | |||
29 | #include "gp10b/pmu_gp10b.h" | 29 | #include "gp10b/pmu_gp10b.h" |
30 | #include "gp10b/gr_ctx_gp10b.h" | 30 | #include "gp10b/gr_ctx_gp10b.h" |
31 | #include "gp10b/fifo_gp10b.h" | 31 | #include "gp10b/fifo_gp10b.h" |
32 | #include "gp10b/gp10b_gating_reglist.h" | ||
32 | 33 | ||
33 | #include "gm20b/gr_gm20b.h" | 34 | #include "gm20b/gr_gm20b.h" |
34 | #include "gm20b/gm20b_gating_reglist.h" | ||
35 | #include "gm20b/fifo_gm20b.h" | 35 | #include "gm20b/fifo_gm20b.h" |
36 | #include "gp10b/fifo_gp10b.h" | ||
37 | #include "gm20b/pmu_gm20b.h" | 36 | #include "gm20b/pmu_gm20b.h" |
38 | #include "gm20b/clk_gm20b.h" | 37 | #include "gm20b/clk_gm20b.h" |
39 | 38 | ||
40 | static struct gpu_ops gp10b_ops = { | 39 | static struct gpu_ops gp10b_ops = { |
41 | .clock_gating = { | 40 | .clock_gating = { |
42 | .slcg_bus_load_gating_prod = | 41 | .slcg_bus_load_gating_prod = |
43 | gm20b_slcg_bus_load_gating_prod, | 42 | gp10b_slcg_bus_load_gating_prod, |
44 | .slcg_ce2_load_gating_prod = | ||
45 | gm20b_slcg_ce2_load_gating_prod, | ||
46 | .slcg_chiplet_load_gating_prod = | 43 | .slcg_chiplet_load_gating_prod = |
47 | gm20b_slcg_chiplet_load_gating_prod, | 44 | gp10b_slcg_chiplet_load_gating_prod, |
48 | .slcg_ctxsw_firmware_load_gating_prod = | 45 | .slcg_ctxsw_firmware_load_gating_prod = |
49 | gm20b_slcg_ctxsw_firmware_load_gating_prod, | 46 | gp10b_slcg_ctxsw_firmware_load_gating_prod, |
50 | .slcg_fb_load_gating_prod = | 47 | .slcg_fb_load_gating_prod = |
51 | gm20b_slcg_fb_load_gating_prod, | 48 | gp10b_slcg_fb_load_gating_prod, |
52 | .slcg_fifo_load_gating_prod = | 49 | .slcg_fifo_load_gating_prod = |
53 | gm20b_slcg_fifo_load_gating_prod, | 50 | gp10b_slcg_fifo_load_gating_prod, |
54 | .slcg_gr_load_gating_prod = | 51 | .slcg_gr_load_gating_prod = |
55 | gr_gm20b_slcg_gr_load_gating_prod, | 52 | gr_gp10b_slcg_gr_load_gating_prod, |
56 | .slcg_ltc_load_gating_prod = | 53 | .slcg_ltc_load_gating_prod = |
57 | ltc_gm20b_slcg_ltc_load_gating_prod, | 54 | ltc_gp10b_slcg_ltc_load_gating_prod, |
58 | .slcg_perf_load_gating_prod = | 55 | .slcg_perf_load_gating_prod = |
59 | gm20b_slcg_perf_load_gating_prod, | 56 | gp10b_slcg_perf_load_gating_prod, |
60 | .slcg_priring_load_gating_prod = | 57 | .slcg_priring_load_gating_prod = |
61 | gm20b_slcg_priring_load_gating_prod, | 58 | gp10b_slcg_priring_load_gating_prod, |
62 | .slcg_pmu_load_gating_prod = | 59 | .slcg_pmu_load_gating_prod = |
63 | gm20b_slcg_pmu_load_gating_prod, | 60 | gp10b_slcg_pmu_load_gating_prod, |
64 | .slcg_therm_load_gating_prod = | 61 | .slcg_therm_load_gating_prod = |
65 | gm20b_slcg_therm_load_gating_prod, | 62 | gp10b_slcg_therm_load_gating_prod, |
66 | .slcg_xbar_load_gating_prod = | 63 | .slcg_xbar_load_gating_prod = |
67 | gm20b_slcg_xbar_load_gating_prod, | 64 | gp10b_slcg_xbar_load_gating_prod, |
68 | .blcg_bus_load_gating_prod = | 65 | .blcg_bus_load_gating_prod = |
69 | gm20b_blcg_bus_load_gating_prod, | 66 | gp10b_blcg_bus_load_gating_prod, |
70 | .blcg_ctxsw_firmware_load_gating_prod = | 67 | .blcg_ctxsw_firmware_load_gating_prod = |
71 | gm20b_blcg_ctxsw_firmware_load_gating_prod, | 68 | gp10b_blcg_ctxsw_firmware_load_gating_prod, |
72 | .blcg_fb_load_gating_prod = | 69 | .blcg_fb_load_gating_prod = |
73 | gm20b_blcg_fb_load_gating_prod, | 70 | gp10b_blcg_fb_load_gating_prod, |
74 | .blcg_fifo_load_gating_prod = | 71 | .blcg_fifo_load_gating_prod = |
75 | gm20b_blcg_fifo_load_gating_prod, | 72 | gp10b_blcg_fifo_load_gating_prod, |
76 | .blcg_gr_load_gating_prod = | 73 | .blcg_gr_load_gating_prod = |
77 | gm20b_blcg_gr_load_gating_prod, | 74 | gp10b_blcg_gr_load_gating_prod, |
78 | .blcg_ltc_load_gating_prod = | 75 | .blcg_ltc_load_gating_prod = |
79 | gm20b_blcg_ltc_load_gating_prod, | 76 | gp10b_blcg_ltc_load_gating_prod, |
80 | .blcg_pwr_csb_load_gating_prod = | 77 | .blcg_pwr_csb_load_gating_prod = |
81 | gm20b_blcg_pwr_csb_load_gating_prod, | 78 | gp10b_blcg_pwr_csb_load_gating_prod, |
82 | .blcg_pmu_load_gating_prod = | 79 | .blcg_pmu_load_gating_prod = |
83 | gm20b_blcg_pmu_load_gating_prod, | 80 | gp10b_blcg_pmu_load_gating_prod, |
84 | .pg_gr_load_gating_prod = | 81 | .pg_gr_load_gating_prod = |
85 | gr_gm20b_pg_gr_load_gating_prod, | 82 | gr_gp10b_pg_gr_load_gating_prod, |
86 | } | 83 | } |
87 | }; | 84 | }; |
88 | 85 | ||