1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
|
/*
* GP10B Tegra HAL interface
*
* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*/
#include <linux/types.h>
#include <linux/printk.h>
#include <linux/types.h>
#include "gk20a/gk20a.h"
#include "gp10b/gr_gp10b.h"
#include "gp10b/mc_gp10b.h"
#include "gp10b/ltc_gp10b.h"
#include "gp10b/mm_gp10b.h"
#include "gp10b/ce2_gp10b.h"
#include "gp10b/fb_gp10b.h"
#include "gp10b/pmu_gp10b.h"
#include "gp10b/gr_ctx_gp10b.h"
#include "gp10b/fifo_gp10b.h"
#include "gp10b/gp10b_gating_reglist.h"
#include "gm20b/gr_gm20b.h"
#include "gm20b/fifo_gm20b.h"
#include "gm20b/pmu_gm20b.h"
#include "gm20b/clk_gm20b.h"
static struct gpu_ops gp10b_ops = {
.clock_gating = {
.slcg_bus_load_gating_prod =
gp10b_slcg_bus_load_gating_prod,
.slcg_chiplet_load_gating_prod =
gp10b_slcg_chiplet_load_gating_prod,
.slcg_ctxsw_firmware_load_gating_prod =
gp10b_slcg_ctxsw_firmware_load_gating_prod,
.slcg_fb_load_gating_prod =
gp10b_slcg_fb_load_gating_prod,
.slcg_fifo_load_gating_prod =
gp10b_slcg_fifo_load_gating_prod,
.slcg_gr_load_gating_prod =
gr_gp10b_slcg_gr_load_gating_prod,
.slcg_ltc_load_gating_prod =
ltc_gp10b_slcg_ltc_load_gating_prod,
.slcg_perf_load_gating_prod =
gp10b_slcg_perf_load_gating_prod,
.slcg_priring_load_gating_prod =
gp10b_slcg_priring_load_gating_prod,
.slcg_pmu_load_gating_prod =
gp10b_slcg_pmu_load_gating_prod,
.slcg_therm_load_gating_prod =
gp10b_slcg_therm_load_gating_prod,
.slcg_xbar_load_gating_prod =
gp10b_slcg_xbar_load_gating_prod,
.blcg_bus_load_gating_prod =
gp10b_blcg_bus_load_gating_prod,
.blcg_ctxsw_firmware_load_gating_prod =
gp10b_blcg_ctxsw_firmware_load_gating_prod,
.blcg_fb_load_gating_prod =
gp10b_blcg_fb_load_gating_prod,
.blcg_fifo_load_gating_prod =
gp10b_blcg_fifo_load_gating_prod,
.blcg_gr_load_gating_prod =
gp10b_blcg_gr_load_gating_prod,
.blcg_ltc_load_gating_prod =
gp10b_blcg_ltc_load_gating_prod,
.blcg_pwr_csb_load_gating_prod =
gp10b_blcg_pwr_csb_load_gating_prod,
.blcg_pmu_load_gating_prod =
gp10b_blcg_pmu_load_gating_prod,
.pg_gr_load_gating_prod =
gr_gp10b_pg_gr_load_gating_prod,
}
};
int gp10b_init_hal(struct gk20a *g)
{
struct gpu_ops *gops = &g->ops;
struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
*gops = gp10b_ops;
gops->privsecurity = 0;
gp10b_init_mc(gops);
gp10b_init_gr(gops);
gp10b_init_ltc(gops);
gp10b_init_fb(gops);
gp10b_init_fifo(gops);
gp10b_init_ce2(gops);
gp10b_init_gr_ctx(gops);
gp10b_init_mm(gops);
gp10b_init_pmu_ops(gops);
gm20b_init_clk_ops(gops);
gk20a_init_debug_ops(gops);
gops->name = "gp10b";
c->twod_class = FERMI_TWOD_A;
c->threed_class = PASCAL_A;
c->compute_class = PASCAL_COMPUTE_A;
c->gpfifo_class = PASCAL_CHANNEL_GPFIFO_A;
c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B;
c->dma_copy_class = MAXWELL_DMA_COPY_A;
return 0;
}
|
