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author | Richard Zhao <rizhao@nvidia.com> | 2017-08-08 18:45:33 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-08-28 22:34:22 -0400 |
commit | 0e0767672ae7e66d0ec249b8847f36c685fe995e (patch) | |
tree | 79a917b0200c85307475be9bdf59dedfbd56a30e /include | |
parent | 6365040db35fd01c8ebff39bd9dbc6c73c48fb17 (diff) |
gpu: nvgpu: vgpu: get engines info from RM server
- get engines info from constants
- remove according HAL from gp10b vgpu
Jira VFND-3797
Change-Id: If010e59c358ab0519cb0d8d6211c0bcc20fc3723
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1536179
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'include')
-rw-r--r-- | include/linux/tegra_vgpu.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index 3f73d357..1c486f5c 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h | |||
@@ -422,6 +422,23 @@ struct tegra_vgpu_gpu_clk_rate_params { | |||
422 | u32 rate; /* in kHz */ | 422 | u32 rate; /* in kHz */ |
423 | }; | 423 | }; |
424 | 424 | ||
425 | /* TEGRA_VGPU_MAX_ENGINES must be equal or greater than num_engines */ | ||
426 | #define TEGRA_VGPU_MAX_ENGINES 4 | ||
427 | struct tegra_vgpu_engines_info { | ||
428 | u32 num_engines; | ||
429 | struct engineinfo { | ||
430 | u32 engine_id; | ||
431 | u32 intr_mask; | ||
432 | u32 reset_mask; | ||
433 | u32 runlist_id; | ||
434 | u32 pbdma_id; | ||
435 | u32 inst_id; | ||
436 | u32 pri_base; | ||
437 | u32 engine_enum; | ||
438 | u32 fault_id; | ||
439 | } info[TEGRA_VGPU_MAX_ENGINES]; | ||
440 | }; | ||
441 | |||
425 | #define TEGRA_VGPU_MAX_GPC_COUNT 16 | 442 | #define TEGRA_VGPU_MAX_GPC_COUNT 16 |
426 | #define TEGRA_VGPU_MAX_TPC_COUNT_PER_GPC 16 | 443 | #define TEGRA_VGPU_MAX_TPC_COUNT_PER_GPC 16 |
427 | 444 | ||
@@ -459,6 +476,7 @@ struct tegra_vgpu_constants_params { | |||
459 | u32 default_timeslice_us; | 476 | u32 default_timeslice_us; |
460 | u32 preempt_ctx_size; | 477 | u32 preempt_ctx_size; |
461 | u32 channel_base; | 478 | u32 channel_base; |
479 | struct tegra_vgpu_engines_info engines_info; | ||
462 | }; | 480 | }; |
463 | 481 | ||
464 | struct tegra_vgpu_channel_cyclestats_snapshot_params { | 482 | struct tegra_vgpu_channel_cyclestats_snapshot_params { |