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authorDeepak Nibade <dnibade@nvidia.com>2017-11-16 02:21:19 -0500
committerDeepak Nibade <dnibade@nvidia.com>2017-11-16 02:21:35 -0500
commitba8dc318595f597308902ad16ffed89bdbe7000f (patch)
treee882886e0cbc05ac39473b95ead16ee50bd69c15 /include/linux/tegra_vgpu_t19x.h
parent69e032653df5aae335764f6346703a1e55c96a2d (diff)
parent77a90d0b8d2eb1bbb207ae5f46b357f2d7cd07ab (diff)
Merge remote-tracking branch 'remotes/origin/dev/linux-nvgpu-t19x' into linux-nvgpu
Bug 200363166 Change-Id: Ic662d7b44b673db28dc0aeba338ae67cf2a43d64 Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Diffstat (limited to 'include/linux/tegra_vgpu_t19x.h')
-rw-r--r--include/linux/tegra_vgpu_t19x.h55
1 files changed, 55 insertions, 0 deletions
diff --git a/include/linux/tegra_vgpu_t19x.h b/include/linux/tegra_vgpu_t19x.h
new file mode 100644
index 00000000..38dbbf60
--- /dev/null
+++ b/include/linux/tegra_vgpu_t19x.h
@@ -0,0 +1,55 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#ifndef __TEGRA_VGPU_T19X_H
15#define __TEGRA_VGPU_T19X_H
16
17#define TEGRA_VGPU_CMD_ALLOC_CTX_HEADER 100
18#define TEGRA_VGPU_CMD_FREE_CTX_HEADER 101
19#define TEGRA_VGPU_CMD_MAP_SYNCPT 102
20#define TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX 103
21
22struct tegra_vgpu_alloc_ctx_header_params {
23 u64 ch_handle;
24 u64 ctx_header_va;
25};
26
27struct tegra_vgpu_free_ctx_header_params {
28 u64 ch_handle;
29};
30
31struct tegra_vgpu_map_syncpt_params {
32 u64 as_handle;
33 u64 gpu_va;
34 u64 len;
35 u64 offset;
36 u8 prot;
37};
38
39struct tegra_vgpu_tsg_bind_channel_ex_params {
40 u32 tsg_id;
41 u64 ch_handle;
42 u32 subctx_id;
43 u32 runqueue_sel;
44};
45
46union tegra_vgpu_t19x_params {
47 struct tegra_vgpu_alloc_ctx_header_params alloc_ctx_header;
48 struct tegra_vgpu_free_ctx_header_params free_ctx_header;
49 struct tegra_vgpu_map_syncpt_params map_syncpt;
50 struct tegra_vgpu_tsg_bind_channel_ex_params tsg_bind_channel_ex;
51};
52
53#define TEGRA_VGPU_ATTRIB_MAX_SUBCTX_COUNT 100
54
55#endif