From 6a25181882cdda68dfa4680b35f12c11b47ea036 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Mon, 10 Apr 2017 15:32:59 -0700 Subject: gpu: nvgpu: vgpu: add basic t19x HALs - Added t19x vgpu platform data - Added basic vgpu HAL for gv11b. - Added subctx header HAL. Jira VFND-3796 Change-Id: I2b99364801b41d042b53e057f1a30e1194f354c3 Signed-off-by: Richard Zhao Reviewed-on: https://git-master/r/1474729 GVS: Gerrit_Virtual_Submit Reviewed-by: Aingara Paramakuru Reviewed-by: Terje Bergstrom --- include/linux/tegra_vgpu_t19x.h | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 include/linux/tegra_vgpu_t19x.h (limited to 'include/linux/tegra_vgpu_t19x.h') diff --git a/include/linux/tegra_vgpu_t19x.h b/include/linux/tegra_vgpu_t19x.h new file mode 100644 index 00000000..f473275d --- /dev/null +++ b/include/linux/tegra_vgpu_t19x.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __TEGRA_VGPU_T19X_H +#define __TEGRA_VGPU_T19X_H + +#define TEGRA_VGPU_CMD_ALLOC_CTX_HEADER 100 +#define TEGRA_VGPU_CMD_FREE_CTX_HEADER 101 + +struct tegra_vgpu_alloc_ctx_header_params { + u64 ch_handle; + u64 ctx_header_va; +}; + +struct tegra_vgpu_free_ctx_header_params { + u64 ch_handle; +}; + +union tegra_vgpu_t19x_params { + struct tegra_vgpu_alloc_ctx_header_params alloc_ctx_header; + struct tegra_vgpu_free_ctx_header_params free_ctx_header; +}; + +#endif -- cgit v1.2.2 From 1ac8f6477df7bd1e1b1c5922b1916ae6450c07ad Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Mon, 21 Aug 2017 15:36:11 -0700 Subject: gpu: nvgpu: vgpu: add TEGRA_VGPU_ATTRIB_MAX_SUBCTX_COUNT Get max subctx count from RM server. Jira VFND-3797 Change-Id: I95de2271a77bedfa8703231fa45da05c7d2da3e6 Signed-off-by: Richard Zhao Reviewed-on: https://git-master.nvidia.com/r/1543018 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- include/linux/tegra_vgpu_t19x.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/linux/tegra_vgpu_t19x.h') diff --git a/include/linux/tegra_vgpu_t19x.h b/include/linux/tegra_vgpu_t19x.h index f473275d..c2814f16 100644 --- a/include/linux/tegra_vgpu_t19x.h +++ b/include/linux/tegra_vgpu_t19x.h @@ -31,4 +31,6 @@ union tegra_vgpu_t19x_params { struct tegra_vgpu_free_ctx_header_params free_ctx_header; }; +#define TEGRA_VGPU_ATTRIB_MAX_SUBCTX_COUNT 100 + #endif -- cgit v1.2.2 From df4e88a21d51d5e098b66c3094fa91ae633777e5 Mon Sep 17 00:00:00 2001 From: Aparna Das Date: Fri, 4 Aug 2017 17:32:02 -0700 Subject: gpu: nvgpu: vgpu: add support for gv11b syncpoints In t19x, gv11b semaphore read and write operations are translated to host1x syncpoint read and write operations using semaphore syncpoint shim aperture. Implement relevant vgpu hal functions for this in fifo hal. Jira EVLR-1571 Change-Id: I6296cc6e592ea991e1c01bc9662d02fb063ff3c7 Signed-off-by: Aparna Das Reviewed-on: https://git-master.nvidia.com/r/1516367 Reviewed-by: mobile promotions Tested-by: mobile promotions --- include/linux/tegra_vgpu_t19x.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'include/linux/tegra_vgpu_t19x.h') diff --git a/include/linux/tegra_vgpu_t19x.h b/include/linux/tegra_vgpu_t19x.h index c2814f16..fe39230e 100644 --- a/include/linux/tegra_vgpu_t19x.h +++ b/include/linux/tegra_vgpu_t19x.h @@ -16,6 +16,7 @@ #define TEGRA_VGPU_CMD_ALLOC_CTX_HEADER 100 #define TEGRA_VGPU_CMD_FREE_CTX_HEADER 101 +#define TEGRA_VGPU_CMD_MAP_SYNCPT 102 struct tegra_vgpu_alloc_ctx_header_params { u64 ch_handle; @@ -26,9 +27,18 @@ struct tegra_vgpu_free_ctx_header_params { u64 ch_handle; }; +struct tegra_vgpu_map_syncpt_params { + u64 as_handle; + u64 gpu_va; + u64 len; + u64 offset; + u8 prot; +}; + union tegra_vgpu_t19x_params { struct tegra_vgpu_alloc_ctx_header_params alloc_ctx_header; struct tegra_vgpu_free_ctx_header_params free_ctx_header; + struct tegra_vgpu_map_syncpt_params map_syncpt; }; #define TEGRA_VGPU_ATTRIB_MAX_SUBCTX_COUNT 100 -- cgit v1.2.2 From 738bee03730a905d98361cd1260f9b79e3c12bf7 Mon Sep 17 00:00:00 2001 From: Thomas Fleury Date: Mon, 16 Oct 2017 08:58:59 -0700 Subject: gpu: nvgpu: vgpu: add vgpu_gv11b_tsg_bind_channel Add TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX command to pass subctx_id and runqueu_sel to RM server. Use this command in gv11b's implementation of gops->fifo.tsg_bind_channel. Jira EVLR-1751 Change-Id: I8ba69c95ea1c6bb7fa106588b6420ed543b2386b Signed-off-by: Thomas Fleury Reviewed-on: https://git-master.nvidia.com/r/1579840 Reviewed-by: svc-mobile-coverity Reviewed-by: Richard Zhao GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- include/linux/tegra_vgpu_t19x.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include/linux/tegra_vgpu_t19x.h') diff --git a/include/linux/tegra_vgpu_t19x.h b/include/linux/tegra_vgpu_t19x.h index fe39230e..38dbbf60 100644 --- a/include/linux/tegra_vgpu_t19x.h +++ b/include/linux/tegra_vgpu_t19x.h @@ -17,6 +17,7 @@ #define TEGRA_VGPU_CMD_ALLOC_CTX_HEADER 100 #define TEGRA_VGPU_CMD_FREE_CTX_HEADER 101 #define TEGRA_VGPU_CMD_MAP_SYNCPT 102 +#define TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX 103 struct tegra_vgpu_alloc_ctx_header_params { u64 ch_handle; @@ -35,10 +36,18 @@ struct tegra_vgpu_map_syncpt_params { u8 prot; }; +struct tegra_vgpu_tsg_bind_channel_ex_params { + u32 tsg_id; + u64 ch_handle; + u32 subctx_id; + u32 runqueue_sel; +}; + union tegra_vgpu_t19x_params { struct tegra_vgpu_alloc_ctx_header_params alloc_ctx_header; struct tegra_vgpu_free_ctx_header_params free_ctx_header; struct tegra_vgpu_map_syncpt_params map_syncpt; + struct tegra_vgpu_tsg_bind_channel_ex_params tsg_bind_channel_ex; }; #define TEGRA_VGPU_ATTRIB_MAX_SUBCTX_COUNT 100 -- cgit v1.2.2