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authorRichard Zhao <rizhao@nvidia.com>2016-06-28 20:08:54 -0400
committerVijayakumar Subbu <vsubbu@nvidia.com>2016-07-14 00:46:07 -0400
commitdc137541b032906e6db45e2f9853fbcff5e267a5 (patch)
treeefa1b5e4e80469d1a268998d19ac6a2fea6640a2 /include/linux/tegra_vgpu.h
parenta2831f098bb22e347009cd73e17946db14ee06ce (diff)
gpu: nvgpu: vgpu: add pm qos support
Send cmd to RM server to change clk rate when PM_QOS_GPU_FREQ_BOUNDS max changes. Bug 200206160 Change-Id: I7f19e5f711426517baf8e7f934bf41972012644b Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1172792 (cherry picked from commit 973c258fd85449c3862df2498362e358fd3682c9) Reviewed-on: http://git-master/r/1180892 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'include/linux/tegra_vgpu.h')
-rw-r--r--include/linux/tegra_vgpu.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h
index 6e8f5d53..c821f31a 100644
--- a/include/linux/tegra_vgpu.h
+++ b/include/linux/tegra_vgpu.h
@@ -97,6 +97,7 @@ enum {
97 TEGRA_VGPU_CMD_CHANNEL_ENABLE = 58, 97 TEGRA_VGPU_CMD_CHANNEL_ENABLE = 58,
98 TEGRA_VGPU_CMD_READ_PTIMER = 59, 98 TEGRA_VGPU_CMD_READ_PTIMER = 59,
99 TEGRA_VGPU_CMD_SET_POWERGATE = 60, 99 TEGRA_VGPU_CMD_SET_POWERGATE = 60,
100 TEGRA_VGPU_CMD_SET_GPU_CLK_RATE = 61,
100}; 101};
101 102
102struct tegra_vgpu_connect_params { 103struct tegra_vgpu_connect_params {
@@ -399,6 +400,10 @@ struct tegra_vgpu_set_powergate_params {
399 u32 mode; 400 u32 mode;
400}; 401};
401 402
403struct tegra_vgpu_gpu_clk_rate_params {
404 u32 rate; /* in kHz */
405};
406
402struct tegra_vgpu_cmd_msg { 407struct tegra_vgpu_cmd_msg {
403 u32 cmd; 408 u32 cmd;
404 int ret; 409 int ret;
@@ -441,6 +446,7 @@ struct tegra_vgpu_cmd_msg {
441 struct tegra_vgpu_tsg_runlist_interleave_params tsg_interleave; 446 struct tegra_vgpu_tsg_runlist_interleave_params tsg_interleave;
442 struct tegra_vgpu_read_ptimer_params read_ptimer; 447 struct tegra_vgpu_read_ptimer_params read_ptimer;
443 struct tegra_vgpu_set_powergate_params set_powergate; 448 struct tegra_vgpu_set_powergate_params set_powergate;
449 struct tegra_vgpu_gpu_clk_rate_params gpu_clk_rate;
444 char padding[192]; 450 char padding[192];
445 } params; 451 } params;
446}; 452};