From dc137541b032906e6db45e2f9853fbcff5e267a5 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Tue, 28 Jun 2016 17:08:54 -0700 Subject: gpu: nvgpu: vgpu: add pm qos support Send cmd to RM server to change clk rate when PM_QOS_GPU_FREQ_BOUNDS max changes. Bug 200206160 Change-Id: I7f19e5f711426517baf8e7f934bf41972012644b Signed-off-by: Richard Zhao Reviewed-on: http://git-master/r/1172792 (cherry picked from commit 973c258fd85449c3862df2498362e358fd3682c9) Reviewed-on: http://git-master/r/1180892 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: Vijayakumar Subbu --- include/linux/tegra_vgpu.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include/linux/tegra_vgpu.h') diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index 6e8f5d53..c821f31a 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h @@ -97,6 +97,7 @@ enum { TEGRA_VGPU_CMD_CHANNEL_ENABLE = 58, TEGRA_VGPU_CMD_READ_PTIMER = 59, TEGRA_VGPU_CMD_SET_POWERGATE = 60, + TEGRA_VGPU_CMD_SET_GPU_CLK_RATE = 61, }; struct tegra_vgpu_connect_params { @@ -399,6 +400,10 @@ struct tegra_vgpu_set_powergate_params { u32 mode; }; +struct tegra_vgpu_gpu_clk_rate_params { + u32 rate; /* in kHz */ +}; + struct tegra_vgpu_cmd_msg { u32 cmd; int ret; @@ -441,6 +446,7 @@ struct tegra_vgpu_cmd_msg { struct tegra_vgpu_tsg_runlist_interleave_params tsg_interleave; struct tegra_vgpu_read_ptimer_params read_ptimer; struct tegra_vgpu_set_powergate_params set_powergate; + struct tegra_vgpu_gpu_clk_rate_params gpu_clk_rate; char padding[192]; } params; }; -- cgit v1.2.2