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authorPeter Daifuku <pdaifuku@nvidia.com>2016-03-23 12:43:43 -0400
committerTerje Bergstrom <tbergstrom@nvidia.com>2016-04-08 15:34:50 -0400
commit6eeabfbdd08e48f924885952c80ff41aa2b534b7 (patch)
tree5cdba48865faa0b76e20d0994fa9de9e4c12deed /include/linux/tegra_vgpu.h
parente8bac374c0ed24f05bf389e1e8b5aca47f61bd3a (diff)
gpu: nvgpu: vgpu: virtualized SMPC/HWPM ctx switch
Add support for SMPC and HWPM context switching when virtualized Bug 1648200 JIRASW EVLR-219 JIRASW EVLR-253 Change-Id: I80a1613eaad87d8510f00d9aef001400d642ecdf Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1122034 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'include/linux/tegra_vgpu.h')
-rw-r--r--include/linux/tegra_vgpu.h25
1 files changed, 24 insertions, 1 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h
index c4dd81dd..979d454e 100644
--- a/include/linux/tegra_vgpu.h
+++ b/include/linux/tegra_vgpu.h
@@ -76,7 +76,14 @@ enum {
76 TEGRA_VGPU_CMD_REG_OPS, 76 TEGRA_VGPU_CMD_REG_OPS,
77 TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY, 77 TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY,
78 TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE, 78 TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE,
79 TEGRA_VGPU_CMD_CHANNEL_SET_TIMESLICE 79 TEGRA_VGPU_CMD_CHANNEL_SET_TIMESLICE,
80 RESVD1,
81 RESVD2,
82 RESVD3,
83 RESVD4,
84 TEGRA_VGPU_CMD_CHANNEL_SET_SMPC_CTXSW_MODE,
85 TEGRA_VGPU_CMD_CHANNEL_SET_HWPM_CTXSW_MODE,
86 TEGRA_VGPU_CMD_CHANNEL_FREE_HWPM_CTX,
80}; 87};
81 88
82struct tegra_vgpu_connect_params { 89struct tegra_vgpu_connect_params {
@@ -312,6 +319,20 @@ struct tegra_vgpu_channel_timeslice_params {
312 u32 timeslice_us; 319 u32 timeslice_us;
313}; 320};
314 321
322enum {
323 TEGRA_VGPU_CTXSW_MODE_NO_CTXSW = 0,
324 TEGRA_VGPU_CTXSW_MODE_CTXSW,
325};
326
327struct tegra_vgpu_channel_set_ctxsw_mode {
328 u64 handle;
329 u32 mode;
330};
331
332struct tegra_vgpu_channel_free_hwpm_ctx {
333 u64 handle;
334};
335
315struct tegra_vgpu_cmd_msg { 336struct tegra_vgpu_cmd_msg {
316 u32 cmd; 337 u32 cmd;
317 int ret; 338 int ret;
@@ -342,6 +363,8 @@ struct tegra_vgpu_cmd_msg {
342 struct tegra_vgpu_channel_priority_params channel_priority; 363 struct tegra_vgpu_channel_priority_params channel_priority;
343 struct tegra_vgpu_channel_runlist_interleave_params channel_interleave; 364 struct tegra_vgpu_channel_runlist_interleave_params channel_interleave;
344 struct tegra_vgpu_channel_timeslice_params channel_timeslice; 365 struct tegra_vgpu_channel_timeslice_params channel_timeslice;
366 struct tegra_vgpu_channel_set_ctxsw_mode set_ctxsw_mode;
367 struct tegra_vgpu_channel_free_hwpm_ctx free_hwpm_ctx;
345 char padding[192]; 368 char padding[192];
346 } params; 369 } params;
347}; 370};