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authorMahantesh Kumbar <mkumbar@nvidia.com>2017-02-01 04:58:05 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2017-02-09 16:44:31 -0500
commit2caa3a9361bb0c9e08a7bb788387a379c73bc848 (patch)
tree48569086420cbe0aa7029faee15eff2338cbdcfa /drivers
parente4a17d6379009adcd0ada768be6b0420f7f0f137 (diff)
gpu: nvgpu: PMU PG interface headers reorg
Moved Power Gating (PG) interface from pmu_api.h & pmu_gk20a.h to gpmuif_ap/pg header files. gpmuif_pg.h - PMU Command/Message Interfaces for power gating (PG) gpmuif_ap.h - PMU Command/Message Interfaces for Adaptive Power Jira NVGPU-19 Change-Id: I1eeee78bdf89d894f9a4731435cdb121f73b1e0f Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1297203 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/nvgpu/gk20a/pmu_api.h469
-rw-r--r--drivers/gpu/nvgpu/gk20a/pmu_gk20a.h81
-rw-r--r--drivers/gpu/nvgpu/pmuif/gpmuif_ap.h247
-rw-r--r--drivers/gpu/nvgpu/pmuif/gpmuif_pg.h311
-rw-r--r--drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h2
5 files changed, 574 insertions, 536 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_api.h b/drivers/gpu/nvgpu/gk20a/pmu_api.h
index d4af6bdb..6284f2f9 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_api.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_api.h
@@ -17,253 +17,6 @@
17#include <nvgpu/flcnif_cmn.h> 17#include <nvgpu/flcnif_cmn.h>
18#include "pmuif/gpmuif_pg_rppg.h" 18#include "pmuif/gpmuif_pg_rppg.h"
19 19
20/* PMU Command/Message Interfaces for Adaptive Power */
21/* Macro to get Histogram index */
22#define PMU_AP_HISTOGRAM(idx) (idx)
23#define PMU_AP_HISTOGRAM_CONT (4)
24
25/* Total number of histogram bins */
26#define PMU_AP_CFG_HISTOGRAM_BIN_N (16)
27
28/* Mapping between Idle counters and histograms */
29#define PMU_AP_IDLE_MASK_HIST_IDX_0 (2)
30#define PMU_AP_IDLE_MASK_HIST_IDX_1 (3)
31#define PMU_AP_IDLE_MASK_HIST_IDX_2 (5)
32#define PMU_AP_IDLE_MASK_HIST_IDX_3 (6)
33
34
35/* Mapping between AP_CTRLs and Histograms */
36#define PMU_AP_HISTOGRAM_IDX_GRAPHICS (PMU_AP_HISTOGRAM(1))
37
38/* Mapping between AP_CTRLs and Idle counters */
39#define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1)
40
41/* Adaptive Power Controls (AP_CTRL) */
42enum {
43 PMU_AP_CTRL_ID_GRAPHICS = 0x0,
44 PMU_AP_CTRL_ID_MAX,
45};
46
47/* AP_CTRL Statistics */
48struct pmu_ap_ctrl_stat {
49 /*
50 * Represents whether AP is active or not
51 */
52 u8 b_active;
53
54 /* Idle filter represented by histogram bin index */
55 u8 idle_filter_x;
56 u8 rsvd[2];
57
58 /* Total predicted power saving cycles. */
59 s32 power_saving_h_cycles;
60
61 /* Counts how many times AP gave us -ve power benefits. */
62 u32 bad_decision_count;
63
64 /*
65 * Number of times ap structure needs to skip AP iterations
66 * KICK_CTRL from kernel updates this parameter.
67 */
68 u32 skip_count;
69 u8 bin[PMU_AP_CFG_HISTOGRAM_BIN_N];
70};
71
72/* Parameters initialized by INITn APCTRL command */
73struct pmu_ap_ctrl_init_params {
74 /* Minimum idle filter value in Us */
75 u32 min_idle_filter_us;
76
77 /*
78 * Minimum Targeted Saving in Us. AP will update idle thresholds only
79 * if power saving achieved by updating idle thresholds is greater than
80 * Minimum targeted saving.
81 */
82 u32 min_target_saving_us;
83
84 /* Minimum targeted residency of power feature in Us */
85 u32 power_break_even_us;
86
87 /*
88 * Maximum number of allowed power feature cycles per sample.
89 *
90 * We are allowing at max "pgPerSampleMax" cycles in one iteration of AP
91 * AKA pgPerSampleMax in original algorithm.
92 */
93 u32 cycles_per_sample_max;
94};
95
96/* AP Commands/Message structures */
97
98/*
99 * Structure for Generic AP Commands
100 */
101struct pmu_ap_cmd_common {
102 u8 cmd_type;
103 u16 cmd_id;
104};
105
106/*
107 * Structure for INIT AP command
108 */
109struct pmu_ap_cmd_init {
110 u8 cmd_type;
111 u16 cmd_id;
112 u8 rsvd;
113 u32 pg_sampling_period_us;
114};
115
116/*
117 * Structure for Enable/Disable ApCtrl Commands
118 */
119struct pmu_ap_cmd_enable_ctrl {
120 u8 cmd_type;
121 u16 cmd_id;
122
123 u8 ctrl_id;
124};
125
126struct pmu_ap_cmd_disable_ctrl {
127 u8 cmd_type;
128 u16 cmd_id;
129
130 u8 ctrl_id;
131};
132
133/*
134 * Structure for INIT command
135 */
136struct pmu_ap_cmd_init_ctrl {
137 u8 cmd_type;
138 u16 cmd_id;
139 u8 ctrl_id;
140 struct pmu_ap_ctrl_init_params params;
141};
142
143struct pmu_ap_cmd_init_and_enable_ctrl {
144 u8 cmd_type;
145 u16 cmd_id;
146 u8 ctrl_id;
147 struct pmu_ap_ctrl_init_params params;
148};
149
150/*
151 * Structure for KICK_CTRL command
152 */
153struct pmu_ap_cmd_kick_ctrl {
154 u8 cmd_type;
155 u16 cmd_id;
156 u8 ctrl_id;
157
158 u32 skip_count;
159};
160
161/*
162 * Structure for PARAM command
163 */
164struct pmu_ap_cmd_param {
165 u8 cmd_type;
166 u16 cmd_id;
167 u8 ctrl_id;
168
169 u32 data;
170};
171
172/*
173 * Defines for AP commands
174 */
175enum {
176 PMU_AP_CMD_ID_INIT = 0x0,
177 PMU_AP_CMD_ID_INIT_AND_ENABLE_CTRL,
178 PMU_AP_CMD_ID_ENABLE_CTRL,
179 PMU_AP_CMD_ID_DISABLE_CTRL,
180 PMU_AP_CMD_ID_KICK_CTRL,
181};
182
183/*
184 * AP Command
185 */
186union pmu_ap_cmd {
187 u8 cmd_type;
188 struct pmu_ap_cmd_common cmn;
189 struct pmu_ap_cmd_init init;
190 struct pmu_ap_cmd_init_and_enable_ctrl init_and_enable_ctrl;
191 struct pmu_ap_cmd_enable_ctrl enable_ctrl;
192 struct pmu_ap_cmd_disable_ctrl disable_ctrl;
193 struct pmu_ap_cmd_kick_ctrl kick_ctrl;
194};
195
196/*
197 * Structure for generic AP Message
198 */
199struct pmu_ap_msg_common {
200 u8 msg_type;
201 u16 msg_id;
202};
203
204/*
205 * Structure for INIT_ACK Message
206 */
207struct pmu_ap_msg_init_ack {
208 u8 msg_type;
209 u16 msg_id;
210 u8 ctrl_id;
211 u32 stats_dmem_offset;
212};
213
214/*
215 * Defines for AP messages
216 */
217enum {
218 PMU_AP_MSG_ID_INIT_ACK = 0x0,
219};
220
221/*
222 * AP Message
223 */
224union pmu_ap_msg {
225 u8 msg_type;
226 struct pmu_ap_msg_common cmn;
227 struct pmu_ap_msg_init_ack init_ack;
228};
229
230/* Default Sampling Period of AELPG */
231#define APCTRL_SAMPLING_PERIOD_PG_DEFAULT_US (1000000)
232
233/* Default values of APCTRL parameters */
234#define APCTRL_MINIMUM_IDLE_FILTER_DEFAULT_US (100)
235#define APCTRL_MINIMUM_TARGET_SAVING_DEFAULT_US (10000)
236#define APCTRL_POWER_BREAKEVEN_DEFAULT_US (2000)
237#define APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT (200)
238
239/*
240 * Disable reason for Adaptive Power Controller
241 */
242enum {
243 APCTRL_DISABLE_REASON_RM_UNLOAD,
244 APCTRL_DISABLE_REASON_RMCTRL,
245};
246
247/*
248 * Adaptive Power Controller
249 */
250struct ap_ctrl {
251 u32 stats_dmem_offset;
252 u32 disable_reason_mask;
253 struct pmu_ap_ctrl_stat stat_cache;
254 u8 b_ready;
255};
256
257/*
258 * Adaptive Power structure
259 *
260 * ap structure provides generic infrastructure to make any power feature
261 * adaptive.
262 */
263struct pmu_ap {
264 u32 supported_mask;
265 struct ap_ctrl ap_ctrl[PMU_AP_CTRL_ID_MAX];
266};
267/*---------------------------------------------------------*/ 20/*---------------------------------------------------------*/
268 21
269/*perfmon task defines*/ 22/*perfmon task defines*/
@@ -399,228 +152,6 @@ struct pmu_perfmon_msg {
399 struct pmu_perfmon_msg_generic gen; 152 struct pmu_perfmon_msg_generic gen;
400 }; 153 };
401}; 154};
402/*---------------------------------------------------------*/
403/*ELPG/PG defines*/
404enum {
405 PMU_PG_ELPG_MSG_INIT_ACK,
406 PMU_PG_ELPG_MSG_DISALLOW_ACK,
407 PMU_PG_ELPG_MSG_ALLOW_ACK,
408 PMU_PG_ELPG_MSG_FREEZE_ACK,
409 PMU_PG_ELPG_MSG_FREEZE_ABORT,
410 PMU_PG_ELPG_MSG_UNFREEZE_ACK,
411};
412
413struct pmu_pg_msg_elpg_msg {
414 u8 msg_type;
415 u8 engine_id;
416 u16 msg;
417};
418
419enum {
420 PMU_PG_STAT_MSG_RESP_DMEM_OFFSET = 0,
421};
422
423struct pmu_pg_msg_stat {
424 u8 msg_type;
425 u8 engine_id;
426 u16 sub_msg_id;
427 u32 data;
428};
429
430enum {
431 PMU_PG_MSG_ENG_BUF_LOADED,
432 PMU_PG_MSG_ENG_BUF_UNLOADED,
433 PMU_PG_MSG_ENG_BUF_FAILED,
434};
435
436struct pmu_pg_msg_eng_buf_stat {
437 u8 msg_type;
438 u8 engine_id;
439 u8 buf_idx;
440 u8 status;
441};
442
443struct pmu_pg_msg {
444 union {
445 u8 msg_type;
446 struct pmu_pg_msg_elpg_msg elpg_msg;
447 struct pmu_pg_msg_stat stat;
448 struct pmu_pg_msg_eng_buf_stat eng_buf_stat;
449 /* TBD: other pg messages */
450 union pmu_ap_msg ap_msg;
451 struct nv_pmu_rppg_msg rppg_msg;
452 };
453};
454
455enum {
456 PMU_PG_ELPG_CMD_INIT,
457 PMU_PG_ELPG_CMD_DISALLOW,
458 PMU_PG_ELPG_CMD_ALLOW,
459 PMU_PG_ELPG_CMD_FREEZE,
460 PMU_PG_ELPG_CMD_UNFREEZE,
461};
462
463enum {
464 PMU_PG_CMD_ID_ELPG_CMD = 0,
465 PMU_PG_CMD_ID_ENG_BUF_LOAD,
466 PMU_PG_CMD_ID_ENG_BUF_UNLOAD,
467 PMU_PG_CMD_ID_PG_STAT,
468 PMU_PG_CMD_ID_PG_LOG_INIT,
469 PMU_PG_CMD_ID_PG_LOG_FLUSH,
470 PMU_PG_CMD_ID_PG_PARAM,
471 PMU_PG_CMD_ID_ELPG_INIT,
472 PMU_PG_CMD_ID_ELPG_POLL_CTXSAVE,
473 PMU_PG_CMD_ID_ELPG_ABORT_POLL,
474 PMU_PG_CMD_ID_ELPG_PWR_UP,
475 PMU_PG_CMD_ID_ELPG_DISALLOW,
476 PMU_PG_CMD_ID_ELPG_ALLOW,
477 PMU_PG_CMD_ID_AP,
478 RM_PMU_PG_CMD_ID_PSI,
479 RM_PMU_PG_CMD_ID_CG,
480 PMU_PG_CMD_ID_ZBC_TABLE_UPDATE,
481 PMU_PG_CMD_ID_PWR_RAIL_GATE_DISABLE = 0x20,
482 PMU_PG_CMD_ID_PWR_RAIL_GATE_ENABLE,
483 PMU_PG_CMD_ID_PWR_RAIL_SMU_MSG_DISABLE,
484 PMU_PMU_PG_CMD_ID_RPPG = 0x24,
485};
486
487struct pmu_pg_cmd_elpg_cmd {
488 u8 cmd_type;
489 u8 engine_id;
490 u16 cmd;
491};
492
493struct pmu_pg_cmd_eng_buf_load_v0 {
494 u8 cmd_type;
495 u8 engine_id;
496 u8 buf_idx;
497 u8 pad;
498 u16 buf_size;
499 u32 dma_base;
500 u8 dma_offset;
501 u8 dma_idx;
502};
503
504struct pmu_pg_cmd_eng_buf_load_v1 {
505 u8 cmd_type;
506 u8 engine_id;
507 u8 buf_idx;
508 u8 pad;
509 struct flcn_mem_desc {
510 struct falc_u64 dma_addr;
511 u16 dma_size;
512 u8 dma_idx;
513 } dma_desc;
514};
515
516struct pmu_pg_cmd_eng_buf_load_v2 {
517 u8 cmd_type;
518 u8 engine_id;
519 u8 buf_idx;
520 u8 pad;
521 struct flcn_mem_desc_v0 dma_desc;
522};
523
524enum {
525 PMU_PG_STAT_CMD_ALLOC_DMEM = 0,
526};
527
528#define PMU_PG_PARAM_CMD_GR_INIT_PARAM 0x0
529#define PMU_PG_PARAM_CMD_MS_INIT_PARAM 0x01
530#define PMU_PG_PARAM_CMD_MCLK_CHANGE 0x04
531#define PMU_PG_PARAM_CMD_POST_INIT 0x06
532
533#define PMU_PG_FEATURE_GR_SDIV_SLOWDOWN_ENABLED (1 << 0)
534#define PMU_PG_FEATURE_GR_POWER_GATING_ENABLED (1 << 2)
535#define PMU_PG_FEATURE_GR_RPPG_ENABLED (1 << 3)
536
537#define NVGPU_PMU_GR_FEATURE_MASK_RPPG (1 << 3)
538#define NVGPU_PMU_GR_FEATURE_MASK_ALL \
539 ( \
540 NVGPU_PMU_GR_FEATURE_MASK_RPPG \
541 )
542
543#define NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING (1 << 0)
544#define NVGPU_PMU_MS_FEATURE_MASK_SW_ASR (1 << 1)
545#define NVGPU_PMU_MS_FEATURE_MASK_RPPG (1 << 8)
546#define NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING (1 << 5)
547
548#define NVGPU_PMU_MS_FEATURE_MASK_ALL \
549 ( \
550 NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING |\
551 NVGPU_PMU_MS_FEATURE_MASK_SW_ASR |\
552 NVGPU_PMU_MS_FEATURE_MASK_RPPG |\
553 NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING \
554 )
555
556#define PG_REQUEST_TYPE_GLOBAL 0x0
557#define PG_REQUEST_TYPE_PSTATE 0x1
558
559struct pmu_pg_cmd_gr_init_param {
560 u8 cmd_type;
561 u16 sub_cmd_id;
562 u8 featuremask;
563};
564
565struct pmu_pg_cmd_ms_init_param {
566 u8 cmd_type;
567 u16 cmd_id;
568 u8 psi;
569 u8 idle_flipped_test_enabled;
570 u16 psiSettleTimeUs;
571 u8 rsvd[2];
572 u32 support_mask;
573 u32 abort_timeout_us;
574};
575
576struct pmu_pg_cmd_mclk_change {
577 u8 cmd_type;
578 u16 cmd_id;
579 u8 rsvd;
580 u32 data;
581};
582
583#define PG_VOLT_RAIL_IDX_MAX 2
584
585struct pmu_pg_volt_rail {
586 u8 volt_rail_idx;
587 u8 sleep_volt_dev_idx;
588 u8 sleep_vfe_idx;
589 u32 sleep_voltage_uv;
590 u32 therm_vid0_cache;
591 u32 therm_vid1_cache;
592};
593
594struct pmu_pg_cmd_post_init_param {
595 u8 cmd_type;
596 u16 cmd_id;
597 struct pmu_pg_volt_rail pg_volt_rail[PG_VOLT_RAIL_IDX_MAX];
598};
599
600struct pmu_pg_cmd_stat {
601 u8 cmd_type;
602 u8 engine_id;
603 u16 sub_cmd_id;
604 u32 data;
605};
606
607struct pmu_pg_cmd {
608 union {
609 u8 cmd_type;
610 struct pmu_pg_cmd_elpg_cmd elpg_cmd;
611 struct pmu_pg_cmd_eng_buf_load_v0 eng_buf_load_v0;
612 struct pmu_pg_cmd_eng_buf_load_v1 eng_buf_load_v1;
613 struct pmu_pg_cmd_eng_buf_load_v2 eng_buf_load_v2;
614 struct pmu_pg_cmd_stat stat;
615 struct pmu_pg_cmd_gr_init_param gr_init_param;
616 struct pmu_pg_cmd_ms_init_param ms_init_param;
617 struct pmu_pg_cmd_mclk_change mclk_change;
618 struct pmu_pg_cmd_post_init_param post_init;
619 /* TBD: other pg commands */
620 union pmu_ap_cmd ap_cmd;
621 struct nv_pmu_rppg_cmd rppg_cmd;
622 };
623};
624 155
625/*---------------------------------------------------------*/ 156/*---------------------------------------------------------*/
626/* ACR Commands/Message structures */ 157/* ACR Commands/Message structures */
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
index dc23005e..b4a69720 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
@@ -261,6 +261,7 @@ struct pmu_sequence {
261 void* cb_params; 261 void* cb_params;
262}; 262};
263 263
264/*PG defines used by nvpgu-pmu*/
264struct pmu_pg_stats_data { 265struct pmu_pg_stats_data {
265 u32 gating_cnt; 266 u32 gating_cnt;
266 u32 ingating_time; 267 u32 ingating_time;
@@ -269,79 +270,12 @@ struct pmu_pg_stats_data {
269 u32 avg_exit_latency_us; 270 u32 avg_exit_latency_us;
270}; 271};
271 272
272struct pmu_pg_stats_v2 {
273 u32 entry_count;
274 u32 exit_count;
275 u32 abort_count;
276 u32 detection_count;
277 u32 prevention_activate_count;
278 u32 prevention_deactivate_count;
279 u32 powered_up_time_us;
280 u32 entry_latency_us;
281 u32 exit_latency_us;
282 u32 resident_time_us;
283 u32 entry_latency_avg_us;
284 u32 exit_latency_avg_us;
285 u32 entry_latency_max_us;
286 u32 exit_latency_max_us;
287 u32 total_sleep_time_us;
288 u32 total_non_sleep_time_us;
289};
290
291struct pmu_pg_stats_v1 {
292 /* Number of time PMU successfully engaged sleep state */
293 u32 entry_count;
294 /* Number of time PMU exit sleep state */
295 u32 exit_count;
296 /* Number of time PMU aborted in entry sequence */
297 u32 abort_count;
298 /*
299 * Time for which GPU was neither in Sleep state not
300 * executing sleep sequence.
301 * */
302 u32 poweredup_timeus;
303 /* Entry and exit latency of current sleep cycle */
304 u32 entry_latency_us;
305 u32 exitlatencyus;
306 /* Resident time for current sleep cycle. */
307 u32 resident_timeus;
308 /* Rolling average entry and exit latencies */
309 u32 entrylatency_avgus;
310 u32 exitlatency_avgus;
311 /* Max entry and exit latencies */
312 u32 entrylatency_maxus;
313 u32 exitlatency_maxus;
314 /* Total time spent in sleep and non-sleep state */
315 u32 total_sleep_timeus;
316 u32 total_nonsleep_timeus;
317};
318
319struct pmu_pg_stats {
320 u64 pg_entry_start_timestamp;
321 u64 pg_ingating_start_timestamp;
322 u64 pg_exit_start_timestamp;
323 u64 pg_ungating_start_timestamp;
324 u32 pg_avg_entry_time_us;
325 u32 pg_ingating_cnt;
326 u32 pg_ingating_time_us;
327 u32 pg_avg_exit_time_us;
328 u32 pg_ungating_count;
329 u32 pg_ungating_time_us;
330 u32 pg_gating_cnt;
331 u32 pg_gating_deny_cnt;
332};
333
334#define PMU_PG_IDLE_THRESHOLD_SIM 1000 273#define PMU_PG_IDLE_THRESHOLD_SIM 1000
335#define PMU_PG_POST_POWERUP_IDLE_THRESHOLD_SIM 4000000 274#define PMU_PG_POST_POWERUP_IDLE_THRESHOLD_SIM 4000000
336/* TBD: QT or else ? */ 275/* TBD: QT or else ? */
337#define PMU_PG_IDLE_THRESHOLD 15000 276#define PMU_PG_IDLE_THRESHOLD 15000
338#define PMU_PG_POST_POWERUP_IDLE_THRESHOLD 1000000 277#define PMU_PG_POST_POWERUP_IDLE_THRESHOLD 1000000
339 278
340#define PMU_PG_ELPG_ENGINE_ID_GRAPHICS (0x00000000)
341#define PMU_PG_ELPG_ENGINE_ID_MS (0x00000004)
342#define PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE (0x00000005)
343#define PMU_PG_ELPG_ENGINE_MAX PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE
344
345#define PMU_PG_LPWR_FEATURE_RPPG 0x0 279#define PMU_PG_LPWR_FEATURE_RPPG 0x0
346#define PMU_PG_LPWR_FEATURE_MSCG 0x1 280#define PMU_PG_LPWR_FEATURE_MSCG 0x1
347 281
@@ -355,9 +289,22 @@ struct pmu_pg_stats {
355#define PMU_ELPG_STAT_OFF_ON_PENDING 4 /* elpg is off, caller has requested on, but ALLOW 289#define PMU_ELPG_STAT_OFF_ON_PENDING 4 /* elpg is off, caller has requested on, but ALLOW
356 cmd hasn't been sent due to ENABLE_ALLOW delay */ 290 cmd hasn't been sent due to ENABLE_ALLOW delay */
357 291
292#define PG_REQUEST_TYPE_GLOBAL 0x0
293#define PG_REQUEST_TYPE_PSTATE 0x1
294
358#define PMU_MSCG_DISABLED 0 295#define PMU_MSCG_DISABLED 0
359#define PMU_MSCG_ENABLED 1 296#define PMU_MSCG_ENABLED 1
360 297
298/* Default Sampling Period of AELPG */
299#define APCTRL_SAMPLING_PERIOD_PG_DEFAULT_US (1000000)
300
301/* Default values of APCTRL parameters */
302#define APCTRL_MINIMUM_IDLE_FILTER_DEFAULT_US (100)
303#define APCTRL_MINIMUM_TARGET_SAVING_DEFAULT_US (10000)
304#define APCTRL_POWER_BREAKEVEN_DEFAULT_US (2000)
305#define APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT (200)
306/*PG defines used by nvpgu-pmu*/
307
361/* Falcon Register index */ 308/* Falcon Register index */
362#define PMU_FALCON_REG_R0 (0) 309#define PMU_FALCON_REG_R0 (0)
363#define PMU_FALCON_REG_R1 (1) 310#define PMU_FALCON_REG_R1 (1)
diff --git a/drivers/gpu/nvgpu/pmuif/gpmuif_ap.h b/drivers/gpu/nvgpu/pmuif/gpmuif_ap.h
new file mode 100644
index 00000000..7e2f546c
--- /dev/null
+++ b/drivers/gpu/nvgpu/pmuif/gpmuif_ap.h
@@ -0,0 +1,247 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13#ifndef _GPMUIFAP_H_
14#define _GPMUIFAP_H_
15
16/* PMU Command/Message Interfaces for Adaptive Power */
17/* Macro to get Histogram index */
18#define PMU_AP_HISTOGRAM(idx) (idx)
19#define PMU_AP_HISTOGRAM_CONT (4)
20
21/* Total number of histogram bins */
22#define PMU_AP_CFG_HISTOGRAM_BIN_N (16)
23
24/* Mapping between Idle counters and histograms */
25#define PMU_AP_IDLE_MASK_HIST_IDX_0 (2)
26#define PMU_AP_IDLE_MASK_HIST_IDX_1 (3)
27#define PMU_AP_IDLE_MASK_HIST_IDX_2 (5)
28#define PMU_AP_IDLE_MASK_HIST_IDX_3 (6)
29
30
31/* Mapping between AP_CTRLs and Histograms */
32#define PMU_AP_HISTOGRAM_IDX_GRAPHICS (PMU_AP_HISTOGRAM(1))
33
34/* Mapping between AP_CTRLs and Idle counters */
35#define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1)
36
37/* Adaptive Power Controls (AP_CTRL) */
38enum {
39 PMU_AP_CTRL_ID_GRAPHICS = 0x0,
40 PMU_AP_CTRL_ID_MAX,
41};
42
43/* AP_CTRL Statistics */
44struct pmu_ap_ctrl_stat {
45 /*
46 * Represents whether AP is active or not
47 */
48 u8 b_active;
49
50 /* Idle filter represented by histogram bin index */
51 u8 idle_filter_x;
52 u8 rsvd[2];
53
54 /* Total predicted power saving cycles. */
55 s32 power_saving_h_cycles;
56
57 /* Counts how many times AP gave us -ve power benefits. */
58 u32 bad_decision_count;
59
60 /*
61 * Number of times ap structure needs to skip AP iterations
62 * KICK_CTRL from kernel updates this parameter.
63 */
64 u32 skip_count;
65 u8 bin[PMU_AP_CFG_HISTOGRAM_BIN_N];
66};
67
68/* Parameters initialized by INITn APCTRL command */
69struct pmu_ap_ctrl_init_params {
70 /* Minimum idle filter value in Us */
71 u32 min_idle_filter_us;
72
73 /*
74 * Minimum Targeted Saving in Us. AP will update idle thresholds only
75 * if power saving achieved by updating idle thresholds is greater than
76 * Minimum targeted saving.
77 */
78 u32 min_target_saving_us;
79
80 /* Minimum targeted residency of power feature in Us */
81 u32 power_break_even_us;
82
83 /*
84 * Maximum number of allowed power feature cycles per sample.
85 *
86 * We are allowing at max "pgPerSampleMax" cycles in one iteration of AP
87 * AKA pgPerSampleMax in original algorithm.
88 */
89 u32 cycles_per_sample_max;
90};
91
92/* AP Commands/Message structures */
93
94/*
95 * Structure for Generic AP Commands
96 */
97struct pmu_ap_cmd_common {
98 u8 cmd_type;
99 u16 cmd_id;
100};
101
102/*
103 * Structure for INIT AP command
104 */
105struct pmu_ap_cmd_init {
106 u8 cmd_type;
107 u16 cmd_id;
108 u8 rsvd;
109 u32 pg_sampling_period_us;
110};
111
112/*
113 * Structure for Enable/Disable ApCtrl Commands
114 */
115struct pmu_ap_cmd_enable_ctrl {
116 u8 cmd_type;
117 u16 cmd_id;
118
119 u8 ctrl_id;
120};
121
122struct pmu_ap_cmd_disable_ctrl {
123 u8 cmd_type;
124 u16 cmd_id;
125
126 u8 ctrl_id;
127};
128
129/*
130 * Structure for INIT command
131 */
132struct pmu_ap_cmd_init_ctrl {
133 u8 cmd_type;
134 u16 cmd_id;
135 u8 ctrl_id;
136 struct pmu_ap_ctrl_init_params params;
137};
138
139struct pmu_ap_cmd_init_and_enable_ctrl {
140 u8 cmd_type;
141 u16 cmd_id;
142 u8 ctrl_id;
143 struct pmu_ap_ctrl_init_params params;
144};
145
146/*
147 * Structure for KICK_CTRL command
148 */
149struct pmu_ap_cmd_kick_ctrl {
150 u8 cmd_type;
151 u16 cmd_id;
152 u8 ctrl_id;
153
154 u32 skip_count;
155};
156
157/*
158 * Structure for PARAM command
159 */
160struct pmu_ap_cmd_param {
161 u8 cmd_type;
162 u16 cmd_id;
163 u8 ctrl_id;
164
165 u32 data;
166};
167
168/*
169 * Defines for AP commands
170 */
171enum {
172 PMU_AP_CMD_ID_INIT = 0x0,
173 PMU_AP_CMD_ID_INIT_AND_ENABLE_CTRL,
174 PMU_AP_CMD_ID_ENABLE_CTRL,
175 PMU_AP_CMD_ID_DISABLE_CTRL,
176 PMU_AP_CMD_ID_KICK_CTRL,
177};
178
179/*
180 * AP Command
181 */
182union pmu_ap_cmd {
183 u8 cmd_type;
184 struct pmu_ap_cmd_common cmn;
185 struct pmu_ap_cmd_init init;
186 struct pmu_ap_cmd_init_and_enable_ctrl init_and_enable_ctrl;
187 struct pmu_ap_cmd_enable_ctrl enable_ctrl;
188 struct pmu_ap_cmd_disable_ctrl disable_ctrl;
189 struct pmu_ap_cmd_kick_ctrl kick_ctrl;
190};
191
192/*
193 * Structure for generic AP Message
194 */
195struct pmu_ap_msg_common {
196 u8 msg_type;
197 u16 msg_id;
198};
199
200/*
201 * Structure for INIT_ACK Message
202 */
203struct pmu_ap_msg_init_ack {
204 u8 msg_type;
205 u16 msg_id;
206 u8 ctrl_id;
207 u32 stats_dmem_offset;
208};
209
210/*
211 * Defines for AP messages
212 */
213enum {
214 PMU_AP_MSG_ID_INIT_ACK = 0x0,
215};
216
217/*
218 * AP Message
219 */
220union pmu_ap_msg {
221 u8 msg_type;
222 struct pmu_ap_msg_common cmn;
223 struct pmu_ap_msg_init_ack init_ack;
224};
225
226/*
227 * Adaptive Power Controller
228 */
229struct ap_ctrl {
230 u32 stats_dmem_offset;
231 u32 disable_reason_mask;
232 struct pmu_ap_ctrl_stat stat_cache;
233 u8 b_ready;
234};
235
236/*
237 * Adaptive Power structure
238 *
239 * ap structure provides generic infrastructure to make any power feature
240 * adaptive.
241 */
242struct pmu_ap {
243 u32 supported_mask;
244 struct ap_ctrl ap_ctrl[PMU_AP_CTRL_ID_MAX];
245};
246
247#endif /* _GPMUIFAP_H_*/
diff --git a/drivers/gpu/nvgpu/pmuif/gpmuif_pg.h b/drivers/gpu/nvgpu/pmuif/gpmuif_pg.h
new file mode 100644
index 00000000..8c71e2a2
--- /dev/null
+++ b/drivers/gpu/nvgpu/pmuif/gpmuif_pg.h
@@ -0,0 +1,311 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13#ifndef _GPMUIFPG_H_
14#define _GPMUIFPG_H_
15
16#include "gpmuif_ap.h"
17#include "gpmuif_pg_rppg.h"
18
19/*PG defines*/
20
21/* Identifier for each PG */
22#define PMU_PG_ELPG_ENGINE_ID_GRAPHICS (0x00000000)
23#define PMU_PG_ELPG_ENGINE_ID_MS (0x00000004)
24#define PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE (0x00000005)
25#define PMU_PG_ELPG_ENGINE_MAX PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE
26
27/* PG message */
28enum {
29 PMU_PG_ELPG_MSG_INIT_ACK,
30 PMU_PG_ELPG_MSG_DISALLOW_ACK,
31 PMU_PG_ELPG_MSG_ALLOW_ACK,
32 PMU_PG_ELPG_MSG_FREEZE_ACK,
33 PMU_PG_ELPG_MSG_FREEZE_ABORT,
34 PMU_PG_ELPG_MSG_UNFREEZE_ACK,
35};
36
37struct pmu_pg_msg_elpg_msg {
38 u8 msg_type;
39 u8 engine_id;
40 u16 msg;
41};
42
43enum {
44 PMU_PG_STAT_MSG_RESP_DMEM_OFFSET = 0,
45};
46
47struct pmu_pg_msg_stat {
48 u8 msg_type;
49 u8 engine_id;
50 u16 sub_msg_id;
51 u32 data;
52};
53
54enum {
55 PMU_PG_MSG_ENG_BUF_LOADED,
56 PMU_PG_MSG_ENG_BUF_UNLOADED,
57 PMU_PG_MSG_ENG_BUF_FAILED,
58};
59
60struct pmu_pg_msg_eng_buf_stat {
61 u8 msg_type;
62 u8 engine_id;
63 u8 buf_idx;
64 u8 status;
65};
66
67struct pmu_pg_msg {
68 union {
69 u8 msg_type;
70 struct pmu_pg_msg_elpg_msg elpg_msg;
71 struct pmu_pg_msg_stat stat;
72 struct pmu_pg_msg_eng_buf_stat eng_buf_stat;
73 /* TBD: other pg messages */
74 union pmu_ap_msg ap_msg;
75 struct nv_pmu_rppg_msg rppg_msg;
76 };
77};
78
79/* PG commands */
80enum {
81 PMU_PG_ELPG_CMD_INIT,
82 PMU_PG_ELPG_CMD_DISALLOW,
83 PMU_PG_ELPG_CMD_ALLOW,
84 PMU_PG_ELPG_CMD_FREEZE,
85 PMU_PG_ELPG_CMD_UNFREEZE,
86};
87
88enum {
89 PMU_PG_CMD_ID_ELPG_CMD = 0,
90 PMU_PG_CMD_ID_ENG_BUF_LOAD,
91 PMU_PG_CMD_ID_ENG_BUF_UNLOAD,
92 PMU_PG_CMD_ID_PG_STAT,
93 PMU_PG_CMD_ID_PG_LOG_INIT,
94 PMU_PG_CMD_ID_PG_LOG_FLUSH,
95 PMU_PG_CMD_ID_PG_PARAM,
96 PMU_PG_CMD_ID_ELPG_INIT,
97 PMU_PG_CMD_ID_ELPG_POLL_CTXSAVE,
98 PMU_PG_CMD_ID_ELPG_ABORT_POLL,
99 PMU_PG_CMD_ID_ELPG_PWR_UP,
100 PMU_PG_CMD_ID_ELPG_DISALLOW,
101 PMU_PG_CMD_ID_ELPG_ALLOW,
102 PMU_PG_CMD_ID_AP,
103 RM_PMU_PG_CMD_ID_PSI,
104 RM_PMU_PG_CMD_ID_CG,
105 PMU_PG_CMD_ID_ZBC_TABLE_UPDATE,
106 PMU_PG_CMD_ID_PWR_RAIL_GATE_DISABLE = 0x20,
107 PMU_PG_CMD_ID_PWR_RAIL_GATE_ENABLE,
108 PMU_PG_CMD_ID_PWR_RAIL_SMU_MSG_DISABLE,
109 PMU_PMU_PG_CMD_ID_RPPG = 0x24,
110};
111
112enum {
113 PMU_PG_STAT_CMD_ALLOC_DMEM = 0,
114};
115
116#define PMU_PG_PARAM_CMD_GR_INIT_PARAM 0x0
117#define PMU_PG_PARAM_CMD_MS_INIT_PARAM 0x01
118#define PMU_PG_PARAM_CMD_MCLK_CHANGE 0x04
119#define PMU_PG_PARAM_CMD_POST_INIT 0x06
120
121#define PMU_PG_FEATURE_GR_SDIV_SLOWDOWN_ENABLED (1 << 0)
122#define PMU_PG_FEATURE_GR_POWER_GATING_ENABLED (1 << 2)
123#define PMU_PG_FEATURE_GR_RPPG_ENABLED (1 << 3)
124
125#define NVGPU_PMU_GR_FEATURE_MASK_RPPG (1 << 3)
126#define NVGPU_PMU_GR_FEATURE_MASK_ALL \
127 ( \
128 NVGPU_PMU_GR_FEATURE_MASK_RPPG \
129 )
130
131#define NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING (1 << 0)
132#define NVGPU_PMU_MS_FEATURE_MASK_SW_ASR (1 << 1)
133#define NVGPU_PMU_MS_FEATURE_MASK_RPPG (1 << 8)
134#define NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING (1 << 5)
135
136#define NVGPU_PMU_MS_FEATURE_MASK_ALL \
137 ( \
138 NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING |\
139 NVGPU_PMU_MS_FEATURE_MASK_SW_ASR |\
140 NVGPU_PMU_MS_FEATURE_MASK_RPPG |\
141 NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING \
142 )
143
144
145struct pmu_pg_cmd_elpg_cmd {
146 u8 cmd_type;
147 u8 engine_id;
148 u16 cmd;
149};
150
151struct pmu_pg_cmd_eng_buf_load_v0 {
152 u8 cmd_type;
153 u8 engine_id;
154 u8 buf_idx;
155 u8 pad;
156 u16 buf_size;
157 u32 dma_base;
158 u8 dma_offset;
159 u8 dma_idx;
160};
161
162struct pmu_pg_cmd_eng_buf_load_v1 {
163 u8 cmd_type;
164 u8 engine_id;
165 u8 buf_idx;
166 u8 pad;
167 struct flcn_mem_desc {
168 struct falc_u64 dma_addr;
169 u16 dma_size;
170 u8 dma_idx;
171 } dma_desc;
172};
173
174struct pmu_pg_cmd_eng_buf_load_v2 {
175 u8 cmd_type;
176 u8 engine_id;
177 u8 buf_idx;
178 u8 pad;
179 struct flcn_mem_desc_v0 dma_desc;
180};
181
182struct pmu_pg_cmd_gr_init_param {
183 u8 cmd_type;
184 u16 sub_cmd_id;
185 u8 featuremask;
186};
187
188struct pmu_pg_cmd_ms_init_param {
189 u8 cmd_type;
190 u16 cmd_id;
191 u8 psi;
192 u8 idle_flipped_test_enabled;
193 u16 psiSettleTimeUs;
194 u8 rsvd[2];
195 u32 support_mask;
196 u32 abort_timeout_us;
197};
198
199struct pmu_pg_cmd_mclk_change {
200 u8 cmd_type;
201 u16 cmd_id;
202 u8 rsvd;
203 u32 data;
204};
205
206#define PG_VOLT_RAIL_IDX_MAX 2
207
208struct pmu_pg_volt_rail {
209 u8 volt_rail_idx;
210 u8 sleep_volt_dev_idx;
211 u8 sleep_vfe_idx;
212 u32 sleep_voltage_uv;
213 u32 therm_vid0_cache;
214 u32 therm_vid1_cache;
215};
216
217struct pmu_pg_cmd_post_init_param {
218 u8 cmd_type;
219 u16 cmd_id;
220 struct pmu_pg_volt_rail pg_volt_rail[PG_VOLT_RAIL_IDX_MAX];
221};
222
223struct pmu_pg_cmd_stat {
224 u8 cmd_type;
225 u8 engine_id;
226 u16 sub_cmd_id;
227 u32 data;
228};
229
230struct pmu_pg_cmd {
231 union {
232 u8 cmd_type;
233 struct pmu_pg_cmd_elpg_cmd elpg_cmd;
234 struct pmu_pg_cmd_eng_buf_load_v0 eng_buf_load_v0;
235 struct pmu_pg_cmd_eng_buf_load_v1 eng_buf_load_v1;
236 struct pmu_pg_cmd_eng_buf_load_v2 eng_buf_load_v2;
237 struct pmu_pg_cmd_stat stat;
238 struct pmu_pg_cmd_gr_init_param gr_init_param;
239 struct pmu_pg_cmd_ms_init_param ms_init_param;
240 struct pmu_pg_cmd_mclk_change mclk_change;
241 struct pmu_pg_cmd_post_init_param post_init;
242 /* TBD: other pg commands */
243 union pmu_ap_cmd ap_cmd;
244 struct nv_pmu_rppg_cmd rppg_cmd;
245 };
246};
247
248/* Statistics structure for PG features */
249struct pmu_pg_stats_v2 {
250 u32 entry_count;
251 u32 exit_count;
252 u32 abort_count;
253 u32 detection_count;
254 u32 prevention_activate_count;
255 u32 prevention_deactivate_count;
256 u32 powered_up_time_us;
257 u32 entry_latency_us;
258 u32 exit_latency_us;
259 u32 resident_time_us;
260 u32 entry_latency_avg_us;
261 u32 exit_latency_avg_us;
262 u32 entry_latency_max_us;
263 u32 exit_latency_max_us;
264 u32 total_sleep_time_us;
265 u32 total_non_sleep_time_us;
266};
267
268struct pmu_pg_stats_v1 {
269 /* Number of time PMU successfully engaged sleep state */
270 u32 entry_count;
271 /* Number of time PMU exit sleep state */
272 u32 exit_count;
273 /* Number of time PMU aborted in entry sequence */
274 u32 abort_count;
275 /*
276 * Time for which GPU was neither in Sleep state not
277 * executing sleep sequence.
278 */
279 u32 poweredup_timeus;
280 /* Entry and exit latency of current sleep cycle */
281 u32 entry_latency_us;
282 u32 exitlatencyus;
283 /* Resident time for current sleep cycle. */
284 u32 resident_timeus;
285 /* Rolling average entry and exit latencies */
286 u32 entrylatency_avgus;
287 u32 exitlatency_avgus;
288 /* Max entry and exit latencies */
289 u32 entrylatency_maxus;
290 u32 exitlatency_maxus;
291 /* Total time spent in sleep and non-sleep state */
292 u32 total_sleep_timeus;
293 u32 total_nonsleep_timeus;
294};
295
296struct pmu_pg_stats {
297 u64 pg_entry_start_timestamp;
298 u64 pg_ingating_start_timestamp;
299 u64 pg_exit_start_timestamp;
300 u64 pg_ungating_start_timestamp;
301 u32 pg_avg_entry_time_us;
302 u32 pg_ingating_cnt;
303 u32 pg_ingating_time_us;
304 u32 pg_avg_exit_time_us;
305 u32 pg_ungating_count;
306 u32 pg_ungating_time_us;
307 u32 pg_gating_cnt;
308 u32 pg_gating_deny_cnt;
309};
310
311#endif /* _GPMUIFPG_H_*/
diff --git a/drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h b/drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h
index 3724be2f..2ed8d61b 100644
--- a/drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h
+++ b/drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h
@@ -17,6 +17,8 @@
17#include <nvgpu/flcnif_cmn.h> 17#include <nvgpu/flcnif_cmn.h>
18#include "gpmuif_cmn.h" 18#include "gpmuif_cmn.h"
19#include "gpmuif_pmu.h" 19#include "gpmuif_pmu.h"
20#include "gpmuif_ap.h"
21#include "gpmuif_pg.h"
20#include "gpmuifboardobj.h" 22#include "gpmuifboardobj.h"
21#include "gpmuifclk.h" 23#include "gpmuifclk.h"
22#include "gpmuifperf.h" 24#include "gpmuifperf.h"
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-05 01:54:55 -0400