From 2caa3a9361bb0c9e08a7bb788387a379c73bc848 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 1 Feb 2017 15:28:05 +0530 Subject: gpu: nvgpu: PMU PG interface headers reorg Moved Power Gating (PG) interface from pmu_api.h & pmu_gk20a.h to gpmuif_ap/pg header files. gpmuif_pg.h - PMU Command/Message Interfaces for power gating (PG) gpmuif_ap.h - PMU Command/Message Interfaces for Adaptive Power Jira NVGPU-19 Change-Id: I1eeee78bdf89d894f9a4731435cdb121f73b1e0f Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/1297203 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gk20a/pmu_api.h | 469 ----------------------------- drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 81 +---- drivers/gpu/nvgpu/pmuif/gpmuif_ap.h | 247 +++++++++++++++ drivers/gpu/nvgpu/pmuif/gpmuif_pg.h | 311 +++++++++++++++++++ drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h | 2 + 5 files changed, 574 insertions(+), 536 deletions(-) create mode 100644 drivers/gpu/nvgpu/pmuif/gpmuif_ap.h create mode 100644 drivers/gpu/nvgpu/pmuif/gpmuif_pg.h (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/gk20a/pmu_api.h b/drivers/gpu/nvgpu/gk20a/pmu_api.h index d4af6bdb..6284f2f9 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_api.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_api.h @@ -17,253 +17,6 @@ #include #include "pmuif/gpmuif_pg_rppg.h" -/* PMU Command/Message Interfaces for Adaptive Power */ -/* Macro to get Histogram index */ -#define PMU_AP_HISTOGRAM(idx) (idx) -#define PMU_AP_HISTOGRAM_CONT (4) - -/* Total number of histogram bins */ -#define PMU_AP_CFG_HISTOGRAM_BIN_N (16) - -/* Mapping between Idle counters and histograms */ -#define PMU_AP_IDLE_MASK_HIST_IDX_0 (2) -#define PMU_AP_IDLE_MASK_HIST_IDX_1 (3) -#define PMU_AP_IDLE_MASK_HIST_IDX_2 (5) -#define PMU_AP_IDLE_MASK_HIST_IDX_3 (6) - - -/* Mapping between AP_CTRLs and Histograms */ -#define PMU_AP_HISTOGRAM_IDX_GRAPHICS (PMU_AP_HISTOGRAM(1)) - -/* Mapping between AP_CTRLs and Idle counters */ -#define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1) - -/* Adaptive Power Controls (AP_CTRL) */ -enum { - PMU_AP_CTRL_ID_GRAPHICS = 0x0, - PMU_AP_CTRL_ID_MAX, -}; - -/* AP_CTRL Statistics */ -struct pmu_ap_ctrl_stat { - /* - * Represents whether AP is active or not - */ - u8 b_active; - - /* Idle filter represented by histogram bin index */ - u8 idle_filter_x; - u8 rsvd[2]; - - /* Total predicted power saving cycles. */ - s32 power_saving_h_cycles; - - /* Counts how many times AP gave us -ve power benefits. */ - u32 bad_decision_count; - - /* - * Number of times ap structure needs to skip AP iterations - * KICK_CTRL from kernel updates this parameter. - */ - u32 skip_count; - u8 bin[PMU_AP_CFG_HISTOGRAM_BIN_N]; -}; - -/* Parameters initialized by INITn APCTRL command */ -struct pmu_ap_ctrl_init_params { - /* Minimum idle filter value in Us */ - u32 min_idle_filter_us; - - /* - * Minimum Targeted Saving in Us. AP will update idle thresholds only - * if power saving achieved by updating idle thresholds is greater than - * Minimum targeted saving. - */ - u32 min_target_saving_us; - - /* Minimum targeted residency of power feature in Us */ - u32 power_break_even_us; - - /* - * Maximum number of allowed power feature cycles per sample. - * - * We are allowing at max "pgPerSampleMax" cycles in one iteration of AP - * AKA pgPerSampleMax in original algorithm. - */ - u32 cycles_per_sample_max; -}; - -/* AP Commands/Message structures */ - -/* - * Structure for Generic AP Commands - */ -struct pmu_ap_cmd_common { - u8 cmd_type; - u16 cmd_id; -}; - -/* - * Structure for INIT AP command - */ -struct pmu_ap_cmd_init { - u8 cmd_type; - u16 cmd_id; - u8 rsvd; - u32 pg_sampling_period_us; -}; - -/* - * Structure for Enable/Disable ApCtrl Commands - */ -struct pmu_ap_cmd_enable_ctrl { - u8 cmd_type; - u16 cmd_id; - - u8 ctrl_id; -}; - -struct pmu_ap_cmd_disable_ctrl { - u8 cmd_type; - u16 cmd_id; - - u8 ctrl_id; -}; - -/* - * Structure for INIT command - */ -struct pmu_ap_cmd_init_ctrl { - u8 cmd_type; - u16 cmd_id; - u8 ctrl_id; - struct pmu_ap_ctrl_init_params params; -}; - -struct pmu_ap_cmd_init_and_enable_ctrl { - u8 cmd_type; - u16 cmd_id; - u8 ctrl_id; - struct pmu_ap_ctrl_init_params params; -}; - -/* - * Structure for KICK_CTRL command - */ -struct pmu_ap_cmd_kick_ctrl { - u8 cmd_type; - u16 cmd_id; - u8 ctrl_id; - - u32 skip_count; -}; - -/* - * Structure for PARAM command - */ -struct pmu_ap_cmd_param { - u8 cmd_type; - u16 cmd_id; - u8 ctrl_id; - - u32 data; -}; - -/* - * Defines for AP commands - */ -enum { - PMU_AP_CMD_ID_INIT = 0x0, - PMU_AP_CMD_ID_INIT_AND_ENABLE_CTRL, - PMU_AP_CMD_ID_ENABLE_CTRL, - PMU_AP_CMD_ID_DISABLE_CTRL, - PMU_AP_CMD_ID_KICK_CTRL, -}; - -/* - * AP Command - */ -union pmu_ap_cmd { - u8 cmd_type; - struct pmu_ap_cmd_common cmn; - struct pmu_ap_cmd_init init; - struct pmu_ap_cmd_init_and_enable_ctrl init_and_enable_ctrl; - struct pmu_ap_cmd_enable_ctrl enable_ctrl; - struct pmu_ap_cmd_disable_ctrl disable_ctrl; - struct pmu_ap_cmd_kick_ctrl kick_ctrl; -}; - -/* - * Structure for generic AP Message - */ -struct pmu_ap_msg_common { - u8 msg_type; - u16 msg_id; -}; - -/* - * Structure for INIT_ACK Message - */ -struct pmu_ap_msg_init_ack { - u8 msg_type; - u16 msg_id; - u8 ctrl_id; - u32 stats_dmem_offset; -}; - -/* - * Defines for AP messages - */ -enum { - PMU_AP_MSG_ID_INIT_ACK = 0x0, -}; - -/* - * AP Message - */ -union pmu_ap_msg { - u8 msg_type; - struct pmu_ap_msg_common cmn; - struct pmu_ap_msg_init_ack init_ack; -}; - -/* Default Sampling Period of AELPG */ -#define APCTRL_SAMPLING_PERIOD_PG_DEFAULT_US (1000000) - -/* Default values of APCTRL parameters */ -#define APCTRL_MINIMUM_IDLE_FILTER_DEFAULT_US (100) -#define APCTRL_MINIMUM_TARGET_SAVING_DEFAULT_US (10000) -#define APCTRL_POWER_BREAKEVEN_DEFAULT_US (2000) -#define APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT (200) - -/* - * Disable reason for Adaptive Power Controller - */ -enum { - APCTRL_DISABLE_REASON_RM_UNLOAD, - APCTRL_DISABLE_REASON_RMCTRL, -}; - -/* - * Adaptive Power Controller - */ -struct ap_ctrl { - u32 stats_dmem_offset; - u32 disable_reason_mask; - struct pmu_ap_ctrl_stat stat_cache; - u8 b_ready; -}; - -/* - * Adaptive Power structure - * - * ap structure provides generic infrastructure to make any power feature - * adaptive. - */ -struct pmu_ap { - u32 supported_mask; - struct ap_ctrl ap_ctrl[PMU_AP_CTRL_ID_MAX]; -}; /*---------------------------------------------------------*/ /*perfmon task defines*/ @@ -399,228 +152,6 @@ struct pmu_perfmon_msg { struct pmu_perfmon_msg_generic gen; }; }; -/*---------------------------------------------------------*/ -/*ELPG/PG defines*/ -enum { - PMU_PG_ELPG_MSG_INIT_ACK, - PMU_PG_ELPG_MSG_DISALLOW_ACK, - PMU_PG_ELPG_MSG_ALLOW_ACK, - PMU_PG_ELPG_MSG_FREEZE_ACK, - PMU_PG_ELPG_MSG_FREEZE_ABORT, - PMU_PG_ELPG_MSG_UNFREEZE_ACK, -}; - -struct pmu_pg_msg_elpg_msg { - u8 msg_type; - u8 engine_id; - u16 msg; -}; - -enum { - PMU_PG_STAT_MSG_RESP_DMEM_OFFSET = 0, -}; - -struct pmu_pg_msg_stat { - u8 msg_type; - u8 engine_id; - u16 sub_msg_id; - u32 data; -}; - -enum { - PMU_PG_MSG_ENG_BUF_LOADED, - PMU_PG_MSG_ENG_BUF_UNLOADED, - PMU_PG_MSG_ENG_BUF_FAILED, -}; - -struct pmu_pg_msg_eng_buf_stat { - u8 msg_type; - u8 engine_id; - u8 buf_idx; - u8 status; -}; - -struct pmu_pg_msg { - union { - u8 msg_type; - struct pmu_pg_msg_elpg_msg elpg_msg; - struct pmu_pg_msg_stat stat; - struct pmu_pg_msg_eng_buf_stat eng_buf_stat; - /* TBD: other pg messages */ - union pmu_ap_msg ap_msg; - struct nv_pmu_rppg_msg rppg_msg; - }; -}; - -enum { - PMU_PG_ELPG_CMD_INIT, - PMU_PG_ELPG_CMD_DISALLOW, - PMU_PG_ELPG_CMD_ALLOW, - PMU_PG_ELPG_CMD_FREEZE, - PMU_PG_ELPG_CMD_UNFREEZE, -}; - -enum { - PMU_PG_CMD_ID_ELPG_CMD = 0, - PMU_PG_CMD_ID_ENG_BUF_LOAD, - PMU_PG_CMD_ID_ENG_BUF_UNLOAD, - PMU_PG_CMD_ID_PG_STAT, - PMU_PG_CMD_ID_PG_LOG_INIT, - PMU_PG_CMD_ID_PG_LOG_FLUSH, - PMU_PG_CMD_ID_PG_PARAM, - PMU_PG_CMD_ID_ELPG_INIT, - PMU_PG_CMD_ID_ELPG_POLL_CTXSAVE, - PMU_PG_CMD_ID_ELPG_ABORT_POLL, - PMU_PG_CMD_ID_ELPG_PWR_UP, - PMU_PG_CMD_ID_ELPG_DISALLOW, - PMU_PG_CMD_ID_ELPG_ALLOW, - PMU_PG_CMD_ID_AP, - RM_PMU_PG_CMD_ID_PSI, - RM_PMU_PG_CMD_ID_CG, - PMU_PG_CMD_ID_ZBC_TABLE_UPDATE, - PMU_PG_CMD_ID_PWR_RAIL_GATE_DISABLE = 0x20, - PMU_PG_CMD_ID_PWR_RAIL_GATE_ENABLE, - PMU_PG_CMD_ID_PWR_RAIL_SMU_MSG_DISABLE, - PMU_PMU_PG_CMD_ID_RPPG = 0x24, -}; - -struct pmu_pg_cmd_elpg_cmd { - u8 cmd_type; - u8 engine_id; - u16 cmd; -}; - -struct pmu_pg_cmd_eng_buf_load_v0 { - u8 cmd_type; - u8 engine_id; - u8 buf_idx; - u8 pad; - u16 buf_size; - u32 dma_base; - u8 dma_offset; - u8 dma_idx; -}; - -struct pmu_pg_cmd_eng_buf_load_v1 { - u8 cmd_type; - u8 engine_id; - u8 buf_idx; - u8 pad; - struct flcn_mem_desc { - struct falc_u64 dma_addr; - u16 dma_size; - u8 dma_idx; - } dma_desc; -}; - -struct pmu_pg_cmd_eng_buf_load_v2 { - u8 cmd_type; - u8 engine_id; - u8 buf_idx; - u8 pad; - struct flcn_mem_desc_v0 dma_desc; -}; - -enum { - PMU_PG_STAT_CMD_ALLOC_DMEM = 0, -}; - -#define PMU_PG_PARAM_CMD_GR_INIT_PARAM 0x0 -#define PMU_PG_PARAM_CMD_MS_INIT_PARAM 0x01 -#define PMU_PG_PARAM_CMD_MCLK_CHANGE 0x04 -#define PMU_PG_PARAM_CMD_POST_INIT 0x06 - -#define PMU_PG_FEATURE_GR_SDIV_SLOWDOWN_ENABLED (1 << 0) -#define PMU_PG_FEATURE_GR_POWER_GATING_ENABLED (1 << 2) -#define PMU_PG_FEATURE_GR_RPPG_ENABLED (1 << 3) - -#define NVGPU_PMU_GR_FEATURE_MASK_RPPG (1 << 3) -#define NVGPU_PMU_GR_FEATURE_MASK_ALL \ - ( \ - NVGPU_PMU_GR_FEATURE_MASK_RPPG \ - ) - -#define NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING (1 << 0) -#define NVGPU_PMU_MS_FEATURE_MASK_SW_ASR (1 << 1) -#define NVGPU_PMU_MS_FEATURE_MASK_RPPG (1 << 8) -#define NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING (1 << 5) - -#define NVGPU_PMU_MS_FEATURE_MASK_ALL \ - ( \ - NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING |\ - NVGPU_PMU_MS_FEATURE_MASK_SW_ASR |\ - NVGPU_PMU_MS_FEATURE_MASK_RPPG |\ - NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING \ - ) - -#define PG_REQUEST_TYPE_GLOBAL 0x0 -#define PG_REQUEST_TYPE_PSTATE 0x1 - -struct pmu_pg_cmd_gr_init_param { - u8 cmd_type; - u16 sub_cmd_id; - u8 featuremask; -}; - -struct pmu_pg_cmd_ms_init_param { - u8 cmd_type; - u16 cmd_id; - u8 psi; - u8 idle_flipped_test_enabled; - u16 psiSettleTimeUs; - u8 rsvd[2]; - u32 support_mask; - u32 abort_timeout_us; -}; - -struct pmu_pg_cmd_mclk_change { - u8 cmd_type; - u16 cmd_id; - u8 rsvd; - u32 data; -}; - -#define PG_VOLT_RAIL_IDX_MAX 2 - -struct pmu_pg_volt_rail { - u8 volt_rail_idx; - u8 sleep_volt_dev_idx; - u8 sleep_vfe_idx; - u32 sleep_voltage_uv; - u32 therm_vid0_cache; - u32 therm_vid1_cache; -}; - -struct pmu_pg_cmd_post_init_param { - u8 cmd_type; - u16 cmd_id; - struct pmu_pg_volt_rail pg_volt_rail[PG_VOLT_RAIL_IDX_MAX]; -}; - -struct pmu_pg_cmd_stat { - u8 cmd_type; - u8 engine_id; - u16 sub_cmd_id; - u32 data; -}; - -struct pmu_pg_cmd { - union { - u8 cmd_type; - struct pmu_pg_cmd_elpg_cmd elpg_cmd; - struct pmu_pg_cmd_eng_buf_load_v0 eng_buf_load_v0; - struct pmu_pg_cmd_eng_buf_load_v1 eng_buf_load_v1; - struct pmu_pg_cmd_eng_buf_load_v2 eng_buf_load_v2; - struct pmu_pg_cmd_stat stat; - struct pmu_pg_cmd_gr_init_param gr_init_param; - struct pmu_pg_cmd_ms_init_param ms_init_param; - struct pmu_pg_cmd_mclk_change mclk_change; - struct pmu_pg_cmd_post_init_param post_init; - /* TBD: other pg commands */ - union pmu_ap_cmd ap_cmd; - struct nv_pmu_rppg_cmd rppg_cmd; - }; -}; /*---------------------------------------------------------*/ /* ACR Commands/Message structures */ diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index dc23005e..b4a69720 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h @@ -261,6 +261,7 @@ struct pmu_sequence { void* cb_params; }; +/*PG defines used by nvpgu-pmu*/ struct pmu_pg_stats_data { u32 gating_cnt; u32 ingating_time; @@ -269,79 +270,12 @@ struct pmu_pg_stats_data { u32 avg_exit_latency_us; }; -struct pmu_pg_stats_v2 { - u32 entry_count; - u32 exit_count; - u32 abort_count; - u32 detection_count; - u32 prevention_activate_count; - u32 prevention_deactivate_count; - u32 powered_up_time_us; - u32 entry_latency_us; - u32 exit_latency_us; - u32 resident_time_us; - u32 entry_latency_avg_us; - u32 exit_latency_avg_us; - u32 entry_latency_max_us; - u32 exit_latency_max_us; - u32 total_sleep_time_us; - u32 total_non_sleep_time_us; -}; - -struct pmu_pg_stats_v1 { - /* Number of time PMU successfully engaged sleep state */ - u32 entry_count; - /* Number of time PMU exit sleep state */ - u32 exit_count; - /* Number of time PMU aborted in entry sequence */ - u32 abort_count; - /* - * Time for which GPU was neither in Sleep state not - * executing sleep sequence. - * */ - u32 poweredup_timeus; - /* Entry and exit latency of current sleep cycle */ - u32 entry_latency_us; - u32 exitlatencyus; - /* Resident time for current sleep cycle. */ - u32 resident_timeus; - /* Rolling average entry and exit latencies */ - u32 entrylatency_avgus; - u32 exitlatency_avgus; - /* Max entry and exit latencies */ - u32 entrylatency_maxus; - u32 exitlatency_maxus; - /* Total time spent in sleep and non-sleep state */ - u32 total_sleep_timeus; - u32 total_nonsleep_timeus; -}; - -struct pmu_pg_stats { - u64 pg_entry_start_timestamp; - u64 pg_ingating_start_timestamp; - u64 pg_exit_start_timestamp; - u64 pg_ungating_start_timestamp; - u32 pg_avg_entry_time_us; - u32 pg_ingating_cnt; - u32 pg_ingating_time_us; - u32 pg_avg_exit_time_us; - u32 pg_ungating_count; - u32 pg_ungating_time_us; - u32 pg_gating_cnt; - u32 pg_gating_deny_cnt; -}; - #define PMU_PG_IDLE_THRESHOLD_SIM 1000 #define PMU_PG_POST_POWERUP_IDLE_THRESHOLD_SIM 4000000 /* TBD: QT or else ? */ #define PMU_PG_IDLE_THRESHOLD 15000 #define PMU_PG_POST_POWERUP_IDLE_THRESHOLD 1000000 -#define PMU_PG_ELPG_ENGINE_ID_GRAPHICS (0x00000000) -#define PMU_PG_ELPG_ENGINE_ID_MS (0x00000004) -#define PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE (0x00000005) -#define PMU_PG_ELPG_ENGINE_MAX PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE - #define PMU_PG_LPWR_FEATURE_RPPG 0x0 #define PMU_PG_LPWR_FEATURE_MSCG 0x1 @@ -355,9 +289,22 @@ struct pmu_pg_stats { #define PMU_ELPG_STAT_OFF_ON_PENDING 4 /* elpg is off, caller has requested on, but ALLOW cmd hasn't been sent due to ENABLE_ALLOW delay */ +#define PG_REQUEST_TYPE_GLOBAL 0x0 +#define PG_REQUEST_TYPE_PSTATE 0x1 + #define PMU_MSCG_DISABLED 0 #define PMU_MSCG_ENABLED 1 +/* Default Sampling Period of AELPG */ +#define APCTRL_SAMPLING_PERIOD_PG_DEFAULT_US (1000000) + +/* Default values of APCTRL parameters */ +#define APCTRL_MINIMUM_IDLE_FILTER_DEFAULT_US (100) +#define APCTRL_MINIMUM_TARGET_SAVING_DEFAULT_US (10000) +#define APCTRL_POWER_BREAKEVEN_DEFAULT_US (2000) +#define APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT (200) +/*PG defines used by nvpgu-pmu*/ + /* Falcon Register index */ #define PMU_FALCON_REG_R0 (0) #define PMU_FALCON_REG_R1 (1) diff --git a/drivers/gpu/nvgpu/pmuif/gpmuif_ap.h b/drivers/gpu/nvgpu/pmuif/gpmuif_ap.h new file mode 100644 index 00000000..7e2f546c --- /dev/null +++ b/drivers/gpu/nvgpu/pmuif/gpmuif_ap.h @@ -0,0 +1,247 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef _GPMUIFAP_H_ +#define _GPMUIFAP_H_ + +/* PMU Command/Message Interfaces for Adaptive Power */ +/* Macro to get Histogram index */ +#define PMU_AP_HISTOGRAM(idx) (idx) +#define PMU_AP_HISTOGRAM_CONT (4) + +/* Total number of histogram bins */ +#define PMU_AP_CFG_HISTOGRAM_BIN_N (16) + +/* Mapping between Idle counters and histograms */ +#define PMU_AP_IDLE_MASK_HIST_IDX_0 (2) +#define PMU_AP_IDLE_MASK_HIST_IDX_1 (3) +#define PMU_AP_IDLE_MASK_HIST_IDX_2 (5) +#define PMU_AP_IDLE_MASK_HIST_IDX_3 (6) + + +/* Mapping between AP_CTRLs and Histograms */ +#define PMU_AP_HISTOGRAM_IDX_GRAPHICS (PMU_AP_HISTOGRAM(1)) + +/* Mapping between AP_CTRLs and Idle counters */ +#define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1) + +/* Adaptive Power Controls (AP_CTRL) */ +enum { + PMU_AP_CTRL_ID_GRAPHICS = 0x0, + PMU_AP_CTRL_ID_MAX, +}; + +/* AP_CTRL Statistics */ +struct pmu_ap_ctrl_stat { + /* + * Represents whether AP is active or not + */ + u8 b_active; + + /* Idle filter represented by histogram bin index */ + u8 idle_filter_x; + u8 rsvd[2]; + + /* Total predicted power saving cycles. */ + s32 power_saving_h_cycles; + + /* Counts how many times AP gave us -ve power benefits. */ + u32 bad_decision_count; + + /* + * Number of times ap structure needs to skip AP iterations + * KICK_CTRL from kernel updates this parameter. + */ + u32 skip_count; + u8 bin[PMU_AP_CFG_HISTOGRAM_BIN_N]; +}; + +/* Parameters initialized by INITn APCTRL command */ +struct pmu_ap_ctrl_init_params { + /* Minimum idle filter value in Us */ + u32 min_idle_filter_us; + + /* + * Minimum Targeted Saving in Us. AP will update idle thresholds only + * if power saving achieved by updating idle thresholds is greater than + * Minimum targeted saving. + */ + u32 min_target_saving_us; + + /* Minimum targeted residency of power feature in Us */ + u32 power_break_even_us; + + /* + * Maximum number of allowed power feature cycles per sample. + * + * We are allowing at max "pgPerSampleMax" cycles in one iteration of AP + * AKA pgPerSampleMax in original algorithm. + */ + u32 cycles_per_sample_max; +}; + +/* AP Commands/Message structures */ + +/* + * Structure for Generic AP Commands + */ +struct pmu_ap_cmd_common { + u8 cmd_type; + u16 cmd_id; +}; + +/* + * Structure for INIT AP command + */ +struct pmu_ap_cmd_init { + u8 cmd_type; + u16 cmd_id; + u8 rsvd; + u32 pg_sampling_period_us; +}; + +/* + * Structure for Enable/Disable ApCtrl Commands + */ +struct pmu_ap_cmd_enable_ctrl { + u8 cmd_type; + u16 cmd_id; + + u8 ctrl_id; +}; + +struct pmu_ap_cmd_disable_ctrl { + u8 cmd_type; + u16 cmd_id; + + u8 ctrl_id; +}; + +/* + * Structure for INIT command + */ +struct pmu_ap_cmd_init_ctrl { + u8 cmd_type; + u16 cmd_id; + u8 ctrl_id; + struct pmu_ap_ctrl_init_params params; +}; + +struct pmu_ap_cmd_init_and_enable_ctrl { + u8 cmd_type; + u16 cmd_id; + u8 ctrl_id; + struct pmu_ap_ctrl_init_params params; +}; + +/* + * Structure for KICK_CTRL command + */ +struct pmu_ap_cmd_kick_ctrl { + u8 cmd_type; + u16 cmd_id; + u8 ctrl_id; + + u32 skip_count; +}; + +/* + * Structure for PARAM command + */ +struct pmu_ap_cmd_param { + u8 cmd_type; + u16 cmd_id; + u8 ctrl_id; + + u32 data; +}; + +/* + * Defines for AP commands + */ +enum { + PMU_AP_CMD_ID_INIT = 0x0, + PMU_AP_CMD_ID_INIT_AND_ENABLE_CTRL, + PMU_AP_CMD_ID_ENABLE_CTRL, + PMU_AP_CMD_ID_DISABLE_CTRL, + PMU_AP_CMD_ID_KICK_CTRL, +}; + +/* + * AP Command + */ +union pmu_ap_cmd { + u8 cmd_type; + struct pmu_ap_cmd_common cmn; + struct pmu_ap_cmd_init init; + struct pmu_ap_cmd_init_and_enable_ctrl init_and_enable_ctrl; + struct pmu_ap_cmd_enable_ctrl enable_ctrl; + struct pmu_ap_cmd_disable_ctrl disable_ctrl; + struct pmu_ap_cmd_kick_ctrl kick_ctrl; +}; + +/* + * Structure for generic AP Message + */ +struct pmu_ap_msg_common { + u8 msg_type; + u16 msg_id; +}; + +/* + * Structure for INIT_ACK Message + */ +struct pmu_ap_msg_init_ack { + u8 msg_type; + u16 msg_id; + u8 ctrl_id; + u32 stats_dmem_offset; +}; + +/* + * Defines for AP messages + */ +enum { + PMU_AP_MSG_ID_INIT_ACK = 0x0, +}; + +/* + * AP Message + */ +union pmu_ap_msg { + u8 msg_type; + struct pmu_ap_msg_common cmn; + struct pmu_ap_msg_init_ack init_ack; +}; + +/* + * Adaptive Power Controller + */ +struct ap_ctrl { + u32 stats_dmem_offset; + u32 disable_reason_mask; + struct pmu_ap_ctrl_stat stat_cache; + u8 b_ready; +}; + +/* + * Adaptive Power structure + * + * ap structure provides generic infrastructure to make any power feature + * adaptive. + */ +struct pmu_ap { + u32 supported_mask; + struct ap_ctrl ap_ctrl[PMU_AP_CTRL_ID_MAX]; +}; + +#endif /* _GPMUIFAP_H_*/ diff --git a/drivers/gpu/nvgpu/pmuif/gpmuif_pg.h b/drivers/gpu/nvgpu/pmuif/gpmuif_pg.h new file mode 100644 index 00000000..8c71e2a2 --- /dev/null +++ b/drivers/gpu/nvgpu/pmuif/gpmuif_pg.h @@ -0,0 +1,311 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef _GPMUIFPG_H_ +#define _GPMUIFPG_H_ + +#include "gpmuif_ap.h" +#include "gpmuif_pg_rppg.h" + +/*PG defines*/ + +/* Identifier for each PG */ +#define PMU_PG_ELPG_ENGINE_ID_GRAPHICS (0x00000000) +#define PMU_PG_ELPG_ENGINE_ID_MS (0x00000004) +#define PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE (0x00000005) +#define PMU_PG_ELPG_ENGINE_MAX PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE + +/* PG message */ +enum { + PMU_PG_ELPG_MSG_INIT_ACK, + PMU_PG_ELPG_MSG_DISALLOW_ACK, + PMU_PG_ELPG_MSG_ALLOW_ACK, + PMU_PG_ELPG_MSG_FREEZE_ACK, + PMU_PG_ELPG_MSG_FREEZE_ABORT, + PMU_PG_ELPG_MSG_UNFREEZE_ACK, +}; + +struct pmu_pg_msg_elpg_msg { + u8 msg_type; + u8 engine_id; + u16 msg; +}; + +enum { + PMU_PG_STAT_MSG_RESP_DMEM_OFFSET = 0, +}; + +struct pmu_pg_msg_stat { + u8 msg_type; + u8 engine_id; + u16 sub_msg_id; + u32 data; +}; + +enum { + PMU_PG_MSG_ENG_BUF_LOADED, + PMU_PG_MSG_ENG_BUF_UNLOADED, + PMU_PG_MSG_ENG_BUF_FAILED, +}; + +struct pmu_pg_msg_eng_buf_stat { + u8 msg_type; + u8 engine_id; + u8 buf_idx; + u8 status; +}; + +struct pmu_pg_msg { + union { + u8 msg_type; + struct pmu_pg_msg_elpg_msg elpg_msg; + struct pmu_pg_msg_stat stat; + struct pmu_pg_msg_eng_buf_stat eng_buf_stat; + /* TBD: other pg messages */ + union pmu_ap_msg ap_msg; + struct nv_pmu_rppg_msg rppg_msg; + }; +}; + +/* PG commands */ +enum { + PMU_PG_ELPG_CMD_INIT, + PMU_PG_ELPG_CMD_DISALLOW, + PMU_PG_ELPG_CMD_ALLOW, + PMU_PG_ELPG_CMD_FREEZE, + PMU_PG_ELPG_CMD_UNFREEZE, +}; + +enum { + PMU_PG_CMD_ID_ELPG_CMD = 0, + PMU_PG_CMD_ID_ENG_BUF_LOAD, + PMU_PG_CMD_ID_ENG_BUF_UNLOAD, + PMU_PG_CMD_ID_PG_STAT, + PMU_PG_CMD_ID_PG_LOG_INIT, + PMU_PG_CMD_ID_PG_LOG_FLUSH, + PMU_PG_CMD_ID_PG_PARAM, + PMU_PG_CMD_ID_ELPG_INIT, + PMU_PG_CMD_ID_ELPG_POLL_CTXSAVE, + PMU_PG_CMD_ID_ELPG_ABORT_POLL, + PMU_PG_CMD_ID_ELPG_PWR_UP, + PMU_PG_CMD_ID_ELPG_DISALLOW, + PMU_PG_CMD_ID_ELPG_ALLOW, + PMU_PG_CMD_ID_AP, + RM_PMU_PG_CMD_ID_PSI, + RM_PMU_PG_CMD_ID_CG, + PMU_PG_CMD_ID_ZBC_TABLE_UPDATE, + PMU_PG_CMD_ID_PWR_RAIL_GATE_DISABLE = 0x20, + PMU_PG_CMD_ID_PWR_RAIL_GATE_ENABLE, + PMU_PG_CMD_ID_PWR_RAIL_SMU_MSG_DISABLE, + PMU_PMU_PG_CMD_ID_RPPG = 0x24, +}; + +enum { + PMU_PG_STAT_CMD_ALLOC_DMEM = 0, +}; + +#define PMU_PG_PARAM_CMD_GR_INIT_PARAM 0x0 +#define PMU_PG_PARAM_CMD_MS_INIT_PARAM 0x01 +#define PMU_PG_PARAM_CMD_MCLK_CHANGE 0x04 +#define PMU_PG_PARAM_CMD_POST_INIT 0x06 + +#define PMU_PG_FEATURE_GR_SDIV_SLOWDOWN_ENABLED (1 << 0) +#define PMU_PG_FEATURE_GR_POWER_GATING_ENABLED (1 << 2) +#define PMU_PG_FEATURE_GR_RPPG_ENABLED (1 << 3) + +#define NVGPU_PMU_GR_FEATURE_MASK_RPPG (1 << 3) +#define NVGPU_PMU_GR_FEATURE_MASK_ALL \ + ( \ + NVGPU_PMU_GR_FEATURE_MASK_RPPG \ + ) + +#define NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING (1 << 0) +#define NVGPU_PMU_MS_FEATURE_MASK_SW_ASR (1 << 1) +#define NVGPU_PMU_MS_FEATURE_MASK_RPPG (1 << 8) +#define NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING (1 << 5) + +#define NVGPU_PMU_MS_FEATURE_MASK_ALL \ + ( \ + NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING |\ + NVGPU_PMU_MS_FEATURE_MASK_SW_ASR |\ + NVGPU_PMU_MS_FEATURE_MASK_RPPG |\ + NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING \ + ) + + +struct pmu_pg_cmd_elpg_cmd { + u8 cmd_type; + u8 engine_id; + u16 cmd; +}; + +struct pmu_pg_cmd_eng_buf_load_v0 { + u8 cmd_type; + u8 engine_id; + u8 buf_idx; + u8 pad; + u16 buf_size; + u32 dma_base; + u8 dma_offset; + u8 dma_idx; +}; + +struct pmu_pg_cmd_eng_buf_load_v1 { + u8 cmd_type; + u8 engine_id; + u8 buf_idx; + u8 pad; + struct flcn_mem_desc { + struct falc_u64 dma_addr; + u16 dma_size; + u8 dma_idx; + } dma_desc; +}; + +struct pmu_pg_cmd_eng_buf_load_v2 { + u8 cmd_type; + u8 engine_id; + u8 buf_idx; + u8 pad; + struct flcn_mem_desc_v0 dma_desc; +}; + +struct pmu_pg_cmd_gr_init_param { + u8 cmd_type; + u16 sub_cmd_id; + u8 featuremask; +}; + +struct pmu_pg_cmd_ms_init_param { + u8 cmd_type; + u16 cmd_id; + u8 psi; + u8 idle_flipped_test_enabled; + u16 psiSettleTimeUs; + u8 rsvd[2]; + u32 support_mask; + u32 abort_timeout_us; +}; + +struct pmu_pg_cmd_mclk_change { + u8 cmd_type; + u16 cmd_id; + u8 rsvd; + u32 data; +}; + +#define PG_VOLT_RAIL_IDX_MAX 2 + +struct pmu_pg_volt_rail { + u8 volt_rail_idx; + u8 sleep_volt_dev_idx; + u8 sleep_vfe_idx; + u32 sleep_voltage_uv; + u32 therm_vid0_cache; + u32 therm_vid1_cache; +}; + +struct pmu_pg_cmd_post_init_param { + u8 cmd_type; + u16 cmd_id; + struct pmu_pg_volt_rail pg_volt_rail[PG_VOLT_RAIL_IDX_MAX]; +}; + +struct pmu_pg_cmd_stat { + u8 cmd_type; + u8 engine_id; + u16 sub_cmd_id; + u32 data; +}; + +struct pmu_pg_cmd { + union { + u8 cmd_type; + struct pmu_pg_cmd_elpg_cmd elpg_cmd; + struct pmu_pg_cmd_eng_buf_load_v0 eng_buf_load_v0; + struct pmu_pg_cmd_eng_buf_load_v1 eng_buf_load_v1; + struct pmu_pg_cmd_eng_buf_load_v2 eng_buf_load_v2; + struct pmu_pg_cmd_stat stat; + struct pmu_pg_cmd_gr_init_param gr_init_param; + struct pmu_pg_cmd_ms_init_param ms_init_param; + struct pmu_pg_cmd_mclk_change mclk_change; + struct pmu_pg_cmd_post_init_param post_init; + /* TBD: other pg commands */ + union pmu_ap_cmd ap_cmd; + struct nv_pmu_rppg_cmd rppg_cmd; + }; +}; + +/* Statistics structure for PG features */ +struct pmu_pg_stats_v2 { + u32 entry_count; + u32 exit_count; + u32 abort_count; + u32 detection_count; + u32 prevention_activate_count; + u32 prevention_deactivate_count; + u32 powered_up_time_us; + u32 entry_latency_us; + u32 exit_latency_us; + u32 resident_time_us; + u32 entry_latency_avg_us; + u32 exit_latency_avg_us; + u32 entry_latency_max_us; + u32 exit_latency_max_us; + u32 total_sleep_time_us; + u32 total_non_sleep_time_us; +}; + +struct pmu_pg_stats_v1 { + /* Number of time PMU successfully engaged sleep state */ + u32 entry_count; + /* Number of time PMU exit sleep state */ + u32 exit_count; + /* Number of time PMU aborted in entry sequence */ + u32 abort_count; + /* + * Time for which GPU was neither in Sleep state not + * executing sleep sequence. + */ + u32 poweredup_timeus; + /* Entry and exit latency of current sleep cycle */ + u32 entry_latency_us; + u32 exitlatencyus; + /* Resident time for current sleep cycle. */ + u32 resident_timeus; + /* Rolling average entry and exit latencies */ + u32 entrylatency_avgus; + u32 exitlatency_avgus; + /* Max entry and exit latencies */ + u32 entrylatency_maxus; + u32 exitlatency_maxus; + /* Total time spent in sleep and non-sleep state */ + u32 total_sleep_timeus; + u32 total_nonsleep_timeus; +}; + +struct pmu_pg_stats { + u64 pg_entry_start_timestamp; + u64 pg_ingating_start_timestamp; + u64 pg_exit_start_timestamp; + u64 pg_ungating_start_timestamp; + u32 pg_avg_entry_time_us; + u32 pg_ingating_cnt; + u32 pg_ingating_time_us; + u32 pg_avg_exit_time_us; + u32 pg_ungating_count; + u32 pg_ungating_time_us; + u32 pg_gating_cnt; + u32 pg_gating_deny_cnt; +}; + +#endif /* _GPMUIFPG_H_*/ diff --git a/drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h b/drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h index 3724be2f..2ed8d61b 100644 --- a/drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h +++ b/drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h @@ -17,6 +17,8 @@ #include #include "gpmuif_cmn.h" #include "gpmuif_pmu.h" +#include "gpmuif_ap.h" +#include "gpmuif_pg.h" #include "gpmuifboardobj.h" #include "gpmuifclk.h" #include "gpmuifperf.h" -- cgit v1.2.2