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authorLaxman Dewangan <ldewangan@nvidia.com>2017-02-07 06:51:03 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2017-02-08 07:34:11 -0500
commit27dd1ce475183d00686ffa62d4cffee4786ab66d (patch)
tree1a07179ff5f58c210cfbe32b7067927e57737fe9 /drivers
parent8264681bb623ebaa1147fe3a34e8f4cd86580516 (diff)
gpu: nvgpu: gp10b: Use T186 POWER DOMAIN macros
The driver file gp10b/platform_gp10b_tegra.c is compiled for T186 SOCs and hence use the T186 power domain macros directly instead of legacy TEGRA_POWERGATE_* macros. This helps in kernel unification to not define the TEGRA_POWERGATE_* bug 200257351 Change-Id: I955c5dd11e6deaaf537377beb6e67a58ab7787ab Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/1300524 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c
index e428f9e6..90d0bb57 100644
--- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c
+++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c
@@ -16,7 +16,7 @@
16#include <linux/of_platform.h> 16#include <linux/of_platform.h>
17#include <linux/nvhost.h> 17#include <linux/nvhost.h>
18#include <linux/debugfs.h> 18#include <linux/debugfs.h>
19#include <linux/tegra-powergate.h> 19#include <soc/tegra/tegra_powergate.h>
20#include <linux/platform_data/tegra_edp.h> 20#include <linux/platform_data/tegra_edp.h>
21#include <linux/dma-buf.h> 21#include <linux/dma-buf.h>
22#include <linux/nvmap.h> 22#include <linux/nvmap.h>
@@ -207,7 +207,7 @@ static bool gp10b_tegra_is_railgated(struct device *dev)
207 bool ret = false; 207 bool ret = false;
208 208
209 if (tegra_bpmp_running()) 209 if (tegra_bpmp_running())
210 ret = !tegra_powergate_is_powered(TEGRA_POWERGATE_GPU); 210 ret = !tegra_powergate_is_powered(TEGRA186_POWER_DOMAIN_GPU);
211 211
212 return ret; 212 return ret;
213} 213}
@@ -224,13 +224,13 @@ static int gp10b_tegra_railgate(struct device *dev)
224 0, TEGRA_BWMGR_SET_EMC_FLOOR); 224 0, TEGRA_BWMGR_SET_EMC_FLOOR);
225 225
226 if (tegra_bpmp_running() && 226 if (tegra_bpmp_running() &&
227 tegra_powergate_is_powered(TEGRA_POWERGATE_GPU)) { 227 tegra_powergate_is_powered(TEGRA186_POWER_DOMAIN_GPU)) {
228 int i; 228 int i;
229 for (i = 0; i < platform->num_clks; i++) { 229 for (i = 0; i < platform->num_clks; i++) {
230 if (platform->clk[i]) 230 if (platform->clk[i])
231 clk_disable_unprepare(platform->clk[i]); 231 clk_disable_unprepare(platform->clk[i]);
232 } 232 }
233 tegra_powergate_partition(TEGRA_POWERGATE_GPU); 233 tegra_powergate_partition(TEGRA186_POWER_DOMAIN_GPU);
234 } 234 }
235 return 0; 235 return 0;
236} 236}
@@ -243,7 +243,7 @@ static int gp10b_tegra_unrailgate(struct device *dev)
243 243
244 if (tegra_bpmp_running()) { 244 if (tegra_bpmp_running()) {
245 int i; 245 int i;
246 ret = tegra_unpowergate_partition(TEGRA_POWERGATE_GPU); 246 ret = tegra_unpowergate_partition(TEGRA186_POWER_DOMAIN_GPU);
247 for (i = 0; i < platform->num_clks; i++) { 247 for (i = 0; i < platform->num_clks; i++) {
248 if (platform->clk[i]) 248 if (platform->clk[i])
249 clk_prepare_enable(platform->clk[i]); 249 clk_prepare_enable(platform->clk[i]);