From 27dd1ce475183d00686ffa62d4cffee4786ab66d Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Tue, 7 Feb 2017 17:21:03 +0530 Subject: gpu: nvgpu: gp10b: Use T186 POWER DOMAIN macros The driver file gp10b/platform_gp10b_tegra.c is compiled for T186 SOCs and hence use the T186 power domain macros directly instead of legacy TEGRA_POWERGATE_* macros. This helps in kernel unification to not define the TEGRA_POWERGATE_* bug 200257351 Change-Id: I955c5dd11e6deaaf537377beb6e67a58ab7787ab Signed-off-by: Laxman Dewangan Reviewed-on: http://git-master/r/1300524 Reviewed-by: Deepak Nibade Reviewed-by: svccoveritychecker Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c index e428f9e6..90d0bb57 100644 --- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include #include @@ -207,7 +207,7 @@ static bool gp10b_tegra_is_railgated(struct device *dev) bool ret = false; if (tegra_bpmp_running()) - ret = !tegra_powergate_is_powered(TEGRA_POWERGATE_GPU); + ret = !tegra_powergate_is_powered(TEGRA186_POWER_DOMAIN_GPU); return ret; } @@ -224,13 +224,13 @@ static int gp10b_tegra_railgate(struct device *dev) 0, TEGRA_BWMGR_SET_EMC_FLOOR); if (tegra_bpmp_running() && - tegra_powergate_is_powered(TEGRA_POWERGATE_GPU)) { + tegra_powergate_is_powered(TEGRA186_POWER_DOMAIN_GPU)) { int i; for (i = 0; i < platform->num_clks; i++) { if (platform->clk[i]) clk_disable_unprepare(platform->clk[i]); } - tegra_powergate_partition(TEGRA_POWERGATE_GPU); + tegra_powergate_partition(TEGRA186_POWER_DOMAIN_GPU); } return 0; } @@ -243,7 +243,7 @@ static int gp10b_tegra_unrailgate(struct device *dev) if (tegra_bpmp_running()) { int i; - ret = tegra_unpowergate_partition(TEGRA_POWERGATE_GPU); + ret = tegra_unpowergate_partition(TEGRA186_POWER_DOMAIN_GPU); for (i = 0; i < platform->num_clks; i++) { if (platform->clk[i]) clk_prepare_enable(platform->clk[i]); -- cgit v1.2.2