gpu: nvgpu: gp10b: Correct SMMU bit number

Bit 36 is the correct bit to indicate SMMU translation.

Bug 1580756

Change-Id: I761e70265d5981b07940f1d43716416829993827
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/658827
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
index a0b6a7d1..ff248f51 100644
--- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
@@ -18,7 +18,7 @@
 
 u32 gp10b_mm_get_physical_addr_bits(struct gk20a *g)
 {
-        return 37;
+        return 36;
 }
 
 void gp10b_init_mm(struct gpu_ops *gops)