gpu: nvgpu: Fix MISRA 15.6 violations

MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces by introducing the braces.

JIRA NVGPU-671

Change-Id: I8046a09fa7ffc74c3d737ba57132a0a9ae2ff195
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797699
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 3 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/therm/thrmpmu.c b/drivers/gpu/nvgpu/therm/thrmpmu.c
index 7814cf5e..e23d1d63 100644
--- a/drivers/gpu/nvgpu/therm/thrmpmu.c
+++ b/drivers/gpu/nvgpu/therm/thrmpmu.c
@@ -43,11 +43,12 @@ static void therm_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
                 return;
         }
 
-        if (!phandlerparams->prpccall->b_supported)
+        if (!phandlerparams->prpccall->b_supported) {
                 nvgpu_err(g, "RPC msg %x failed",
                         msg->msg.pmgr.msg_type);
-        else
+        } else {
                 phandlerparams->success = 1;
+        }
 }
 
 int therm_send_pmgr_tables_to_pmu(struct gk20a *g)