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authorTerje Bergstrom <tbergstrom@nvidia.com>2017-04-06 16:15:09 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-04-10 15:24:27 -0400
commit04d9de84783bcf16f97516fa9602d118820831f4 (patch)
treef24bf4ffb4fc0bc6216b236472e7c90d5ae686cd /drivers/gpu/nvgpu/tegra
parent5405070ecd27ce462babc1dff231fec5cd8bd6b7 (diff)
gpu: nvgpu: tegra: linux: Use new error macros
gk20a_err() and gk20a_warn() require a struct device pointer, which is not portable across operating systems. The new nvgpu_err() and nvgpu_warn() macros take struct gk20a pointer. Convert code to use the more portable macros. JIRA NVGPU-16 Change-Id: I248295107c5959a98ff00917e0474bcd03708156 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1457356 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/tegra')
-rw-r--r--drivers/gpu/nvgpu/tegra/linux/clk.c4
-rw-r--r--drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c23
-rw-r--r--drivers/gpu/nvgpu/tegra/linux/platform_gp10b_tegra.c7
3 files changed, 18 insertions, 16 deletions
diff --git a/drivers/gpu/nvgpu/tegra/linux/clk.c b/drivers/gpu/nvgpu/tegra/linux/clk.c
index 3982054c..e1d715b9 100644
--- a/drivers/gpu/nvgpu/tegra/linux/clk.c
+++ b/drivers/gpu/nvgpu/tegra/linux/clk.c
@@ -36,7 +36,7 @@ static unsigned long nvgpu_linux_clk_get_rate(struct gk20a *g, u32 api_domain)
36 ret = clk_get_rate(platform->clk[1]); 36 ret = clk_get_rate(platform->clk[1]);
37 break; 37 break;
38 default: 38 default:
39 gk20a_err(g->dev, "unknown clock: %u", api_domain); 39 nvgpu_err(g, "unknown clock: %u", api_domain);
40 ret = 0; 40 ret = 0;
41 break; 41 break;
42 } 42 }
@@ -61,7 +61,7 @@ static int nvgpu_linux_clk_set_rate(struct gk20a *g,
61 ret = clk_set_rate(platform->clk[1], rate); 61 ret = clk_set_rate(platform->clk[1], rate);
62 break; 62 break;
63 default: 63 default:
64 gk20a_err(g->dev, "unknown clock: %u", api_domain); 64 nvgpu_err(g, "unknown clock: %u", api_domain);
65 ret = -EINVAL; 65 ret = -EINVAL;
66 break; 66 break;
67 } 67 }
diff --git a/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c b/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c
index 5b2958ec..4f8faf5a 100644
--- a/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c
+++ b/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c
@@ -166,12 +166,12 @@ int gk20a_tegra_secure_alloc(struct device *dev,
166 166
167 sgt = nvgpu_kzalloc(platform->g, sizeof(*sgt)); 167 sgt = nvgpu_kzalloc(platform->g, sizeof(*sgt));
168 if (!sgt) { 168 if (!sgt) {
169 gk20a_err(dev, "failed to allocate memory\n"); 169 nvgpu_err(platform->g, "failed to allocate memory");
170 goto fail; 170 goto fail;
171 } 171 }
172 err = sg_alloc_table(sgt, 1, GFP_KERNEL); 172 err = sg_alloc_table(sgt, 1, GFP_KERNEL);
173 if (err) { 173 if (err) {
174 gk20a_err(dev, "failed to allocate sg_table\n"); 174 nvgpu_err(platform->g, "failed to allocate sg_table");
175 goto fail_sgt; 175 goto fail_sgt;
176 } 176 }
177 page = phys_to_page(iova); 177 page = phys_to_page(iova);
@@ -427,7 +427,7 @@ static int gk20a_tegra_railgate(struct device *dev)
427 return 0; 427 return 0;
428 428
429err_power_off: 429err_power_off:
430 gk20a_err(dev, "Could not railgate GPU"); 430 nvgpu_err(get_gk20a(dev), "Could not railgate GPU");
431 return ret; 431 return ret;
432} 432}
433 433
@@ -463,12 +463,12 @@ static int gk20a_tegra_unrailgate(struct device *dev)
463 if (!first) { 463 if (!first) {
464 ret = clk_enable(platform->clk[0]); 464 ret = clk_enable(platform->clk[0]);
465 if (ret) { 465 if (ret) {
466 gk20a_err(dev, "could not turn on gpu pll"); 466 nvgpu_err(platform->g, "could not turn on gpu pll");
467 goto err_clk_on; 467 goto err_clk_on;
468 } 468 }
469 ret = clk_enable(platform->clk[1]); 469 ret = clk_enable(platform->clk[1]);
470 if (ret) { 470 if (ret) {
471 gk20a_err(dev, "could not turn on pwr clock"); 471 nvgpu_err(platform->g, "could not turn on pwr clock");
472 goto err_clk_on; 472 goto err_clk_on;
473 } 473 }
474 } 474 }
@@ -581,7 +581,7 @@ static int gm20b_tegra_railgate(struct device *dev)
581 return 0; 581 return 0;
582 582
583err_power_off: 583err_power_off:
584 gk20a_err(dev, "Could not railgate GPU"); 584 nvgpu_err(platform->g, "Could not railgate GPU");
585 return ret; 585 return ret;
586} 586}
587 587
@@ -595,6 +595,7 @@ err_power_off:
595static int gm20b_tegra_unrailgate(struct device *dev) 595static int gm20b_tegra_unrailgate(struct device *dev)
596{ 596{
597 struct gk20a_platform *platform = dev_get_drvdata(dev); 597 struct gk20a_platform *platform = dev_get_drvdata(dev);
598 struct gk20a *g = platform->g;
598 int ret = 0; 599 int ret = 0;
599 bool first = false; 600 bool first = false;
600 601
@@ -625,7 +626,7 @@ static int gm20b_tegra_unrailgate(struct device *dev)
625 if (!platform->clk_reset) { 626 if (!platform->clk_reset) {
626 platform->clk_reset = clk_get(dev, "gpu_gate"); 627 platform->clk_reset = clk_get(dev, "gpu_gate");
627 if (IS_ERR(platform->clk_reset)) { 628 if (IS_ERR(platform->clk_reset)) {
628 gk20a_err(dev, "fail to get gpu reset clk\n"); 629 nvgpu_err(g, "fail to get gpu reset clk");
629 goto err_clk_on; 630 goto err_clk_on;
630 } 631 }
631 } 632 }
@@ -633,25 +634,25 @@ static int gm20b_tegra_unrailgate(struct device *dev)
633 if (!first) { 634 if (!first) {
634 ret = clk_prepare_enable(platform->clk_reset); 635 ret = clk_prepare_enable(platform->clk_reset);
635 if (ret) { 636 if (ret) {
636 gk20a_err(dev, "could not turn on gpu_gate"); 637 nvgpu_err(g, "could not turn on gpu_gate");
637 goto err_clk_on; 638 goto err_clk_on;
638 } 639 }
639 640
640 ret = clk_prepare_enable(platform->clk[0]); 641 ret = clk_prepare_enable(platform->clk[0]);
641 if (ret) { 642 if (ret) {
642 gk20a_err(dev, "could not turn on gpu pll"); 643 nvgpu_err(g, "could not turn on gpu pll");
643 goto err_clk_on; 644 goto err_clk_on;
644 } 645 }
645 ret = clk_prepare_enable(platform->clk[1]); 646 ret = clk_prepare_enable(platform->clk[1]);
646 if (ret) { 647 if (ret) {
647 gk20a_err(dev, "could not turn on pwr clock"); 648 nvgpu_err(g, "could not turn on pwr clock");
648 goto err_clk_on; 649 goto err_clk_on;
649 } 650 }
650 651
651 if (platform->clk[3]) { 652 if (platform->clk[3]) {
652 ret = clk_prepare_enable(platform->clk[3]); 653 ret = clk_prepare_enable(platform->clk[3]);
653 if (ret) { 654 if (ret) {
654 gk20a_err(dev, "could not turn on fuse clock"); 655 nvgpu_err(g, "could not turn on fuse clock");
655 goto err_clk_on; 656 goto err_clk_on;
656 } 657 }
657 } 658 }
diff --git a/drivers/gpu/nvgpu/tegra/linux/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/tegra/linux/platform_gp10b_tegra.c
index 6351e895..6d9299b7 100644
--- a/drivers/gpu/nvgpu/tegra/linux/platform_gp10b_tegra.c
+++ b/drivers/gpu/nvgpu/tegra/linux/platform_gp10b_tegra.c
@@ -84,7 +84,7 @@ int gp10b_tegra_get_clocks(struct device *dev)
84 84
85 c = clk_get(dev, tegra_gp10b_clocks[i].name); 85 c = clk_get(dev, tegra_gp10b_clocks[i].name);
86 if (IS_ERR(c)) { 86 if (IS_ERR(c)) {
87 gk20a_err(dev, "cannot get clock %s", 87 nvgpu_err(platform->g, "cannot get clock %s",
88 tegra_gp10b_clocks[i].name); 88 tegra_gp10b_clocks[i].name);
89 } else { 89 } else {
90 clk_set_rate(c, rate); 90 clk_set_rate(c, rate);
@@ -125,6 +125,7 @@ static void gp10b_tegra_scale_exit(struct device *dev)
125static int gp10b_tegra_probe(struct device *dev) 125static int gp10b_tegra_probe(struct device *dev)
126{ 126{
127 struct gk20a_platform *platform = dev_get_drvdata(dev); 127 struct gk20a_platform *platform = dev_get_drvdata(dev);
128 struct gk20a *g = platform->g;
128 struct device_node *np = dev->of_node; 129 struct device_node *np = dev->of_node;
129 struct device_node *host1x_node; 130 struct device_node *host1x_node;
130 struct platform_device *host1x_pdev; 131 struct platform_device *host1x_pdev;
@@ -132,14 +133,14 @@ static int gp10b_tegra_probe(struct device *dev)
132 133
133 host1x_ptr = of_get_property(np, "nvidia,host1x", NULL); 134 host1x_ptr = of_get_property(np, "nvidia,host1x", NULL);
134 if (!host1x_ptr) { 135 if (!host1x_ptr) {
135 gk20a_err(dev, "host1x device not available"); 136 nvgpu_err(g, "host1x device not available");
136 return -ENOSYS; 137 return -ENOSYS;
137 } 138 }
138 139
139 host1x_node = of_find_node_by_phandle(be32_to_cpup(host1x_ptr)); 140 host1x_node = of_find_node_by_phandle(be32_to_cpup(host1x_ptr));
140 host1x_pdev = of_find_device_by_node(host1x_node); 141 host1x_pdev = of_find_device_by_node(host1x_node);
141 if (!host1x_pdev) { 142 if (!host1x_pdev) {
142 gk20a_err(dev, "host1x device not available"); 143 nvgpu_err(g, "host1x device not available");
143 return -ENOSYS; 144 return -ENOSYS;
144 } 145 }
145 146