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authorddutta <ddutta@nvidia.com>2018-09-18 03:14:44 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-20 06:27:55 -0400
commitfeefb7046a88311d88a37ad2cc934ec7b9a9c28f (patch)
tree4fc16843d6a8080ed3544971be5f19b15e3a42d5 /drivers/gpu/nvgpu/include
parent7e591dced99f328f4960702dbb6235fe7dc7f6b5 (diff)
gpu: nvgpu: minor fixes in channel_sync.c
This patch comes as a follow up to commit 2517d59be282426eec7a97745b76d745ff36c388 containing minor fixes i.e. changing type of 'pos' to u32 instead of int and renaming syncpt_get_id to channel_sync_syncpt_get_id Jira NVGPU-1086 Change-Id: I8bd9271c20d88ff5f68ccfc48a0b533844bbcaaa Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1829832 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/channel_sync.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/channel_sync.h b/drivers/gpu/nvgpu/include/nvgpu/channel_sync.h
index b5936edc..f0b2b860 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/channel_sync.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/channel_sync.h
@@ -98,11 +98,11 @@ struct nvgpu_channel_sync {
98 98
99void channel_sync_semaphore_gen_wait_cmd(struct channel_gk20a *c, 99void channel_sync_semaphore_gen_wait_cmd(struct channel_gk20a *c,
100 struct nvgpu_semaphore *sema, struct priv_cmd_entry *wait_cmd, 100 struct nvgpu_semaphore *sema, struct priv_cmd_entry *wait_cmd,
101 u32 wait_cmd_size, int pos); 101 u32 wait_cmd_size, u32 pos);
102 102
103int channel_sync_syncpt_gen_wait_cmd(struct channel_gk20a *c, 103int channel_sync_syncpt_gen_wait_cmd(struct channel_gk20a *c,
104 u32 id, u32 thresh, struct priv_cmd_entry *wait_cmd, 104 u32 id, u32 thresh, struct priv_cmd_entry *wait_cmd,
105 u32 wait_cmd_size, int pos, bool preallocated); 105 u32 wait_cmd_size, u32 pos, bool preallocated);
106 106
107void nvgpu_channel_sync_destroy(struct nvgpu_channel_sync *sync, 107void nvgpu_channel_sync_destroy(struct nvgpu_channel_sync *sync,
108 bool set_safe_state); 108 bool set_safe_state);
@@ -110,4 +110,4 @@ struct nvgpu_channel_sync *nvgpu_channel_sync_create(struct channel_gk20a *c,
110 bool user_managed); 110 bool user_managed);
111bool nvgpu_channel_sync_needs_os_fence_framework(struct gk20a *g); 111bool nvgpu_channel_sync_needs_os_fence_framework(struct gk20a *g);
112 112
113#endif /* NVGPU_GK20A_CHANNEL_SYNC_GK20A_H */ 113#endif /* NVGPU_CHANNEL_SYNC_H */