diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-06-30 14:45:16 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-05 06:06:51 -0400 |
commit | 690d560e65af8096bc391064631c74a3dd14fa89 (patch) | |
tree | 80d2d74f70810b6977d760aea03687361a3d28d9 /drivers/gpu/nvgpu/include | |
parent | a4439aee3a47ed9b966e5864a8e18a2bb13a9bb7 (diff) |
gpu: nvgpu: gv11b: Use sm dbgr bpt and warp mask 0/1
Instead of assuming mask_0 and mask_1 as consecutive registers,
use mask_1 and mask_0 registers for reading/writing sm dbgr warp
and bpt mask registers
JIRA GPUT19X-75
Change-Id: Ib6843d13828d899d4bd3f12bdf6701325ea760fd
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1511736
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index daa4c08a..051961d2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | |||
@@ -3674,7 +3674,7 @@ static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f(void) | |||
3674 | { | 3674 | { |
3675 | return 0x40000000; | 3675 | return 0x40000000; |
3676 | } | 3676 | } |
3677 | static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_r(void) | 3677 | static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_0_r(void) |
3678 | { | 3678 | { |
3679 | return 0x00504708; | 3679 | return 0x00504708; |
3680 | } | 3680 | } |
@@ -3682,7 +3682,7 @@ static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_1_r(void) | |||
3682 | { | 3682 | { |
3683 | return 0x0050470c; | 3683 | return 0x0050470c; |
3684 | } | 3684 | } |
3685 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_r(void) | 3685 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_0_r(void) |
3686 | { | 3686 | { |
3687 | return 0x00504710; | 3687 | return 0x00504710; |
3688 | } | 3688 | } |
@@ -3690,7 +3690,7 @@ static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_1_r(void) | |||
3690 | { | 3690 | { |
3691 | return 0x00504714; | 3691 | return 0x00504714; |
3692 | } | 3692 | } |
3693 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_r(void) | 3693 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_0_r(void) |
3694 | { | 3694 | { |
3695 | return 0x00504718; | 3695 | return 0x00504718; |
3696 | } | 3696 | } |
@@ -3698,7 +3698,7 @@ static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_1_r(void) | |||
3698 | { | 3698 | { |
3699 | return 0x0050471c; | 3699 | return 0x0050471c; |
3700 | } | 3700 | } |
3701 | static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_r(void) | 3701 | static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r(void) |
3702 | { | 3702 | { |
3703 | return 0x00419e90; | 3703 | return 0x00419e90; |
3704 | } | 3704 | } |