diff options
author | Vinod G <vinodg@nvidia.com> | 2018-05-25 18:44:34 -0400 |
---|---|---|
committer | Tejal Kudav <tkudav@nvidia.com> | 2018-06-14 09:44:07 -0400 |
commit | 7aded206bc3eb0f36422e9f6f3dab3e065e7e7e4 (patch) | |
tree | be963b37e3ea18151e41c8d83e237255d25c7849 /drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | |
parent | c8c686f8554352fc209fda592ec3b490811532aa (diff) |
gpu: nvgpu: gv11b: Handle all SM errors
Add the missing register bits to identify the
SM errors.
Except for mmu_nack error, all other errors are
handled using a single function.
That function sets the error notifier with GR_EXCEPTION,
clears interrupt and triggers recovery process.
bug 200402677
JIRA NVGPU-573
Change-Id: Icfaff1f20f1f35adb4cd35ce288ce694845aed3c
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730963
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 17c7e77d..5de691a2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | |||
@@ -4392,10 +4392,74 @@ static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_f(void) | |||
4392 | { | 4392 | { |
4393 | return 0x0U; | 4393 | return 0x0U; |
4394 | } | 4394 | } |
4395 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_stack_error_f(void) | ||
4396 | { | ||
4397 | return 0x1U; | ||
4398 | } | ||
4399 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_api_stack_error_f(void) | ||
4400 | { | ||
4401 | return 0x2U; | ||
4402 | } | ||
4403 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_pc_wrap_f(void) | ||
4404 | { | ||
4405 | return 0x4U; | ||
4406 | } | ||
4407 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_pc_f(void) | ||
4408 | { | ||
4409 | return 0x5U; | ||
4410 | } | ||
4411 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_pc_overflow_f(void) | ||
4412 | { | ||
4413 | return 0x6U; | ||
4414 | } | ||
4415 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_reg_f(void) | ||
4416 | { | ||
4417 | return 0x8U; | ||
4418 | } | ||
4419 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_illegal_instr_encoding_f(void) | ||
4420 | { | ||
4421 | return 0x9U; | ||
4422 | } | ||
4423 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_illegal_instr_param_f(void) | ||
4424 | { | ||
4425 | return 0xbU; | ||
4426 | } | ||
4427 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_oor_reg_f(void) | ||
4428 | { | ||
4429 | return 0xdU; | ||
4430 | } | ||
4431 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_oor_addr_f(void) | ||
4432 | { | ||
4433 | return 0xeU; | ||
4434 | } | ||
4395 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_addr_f(void) | 4435 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_addr_f(void) |
4396 | { | 4436 | { |
4397 | return 0xfU; | 4437 | return 0xfU; |
4398 | } | 4438 | } |
4439 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_invalid_addr_space_f(void) | ||
4440 | { | ||
4441 | return 0x10U; | ||
4442 | } | ||
4443 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_invalid_const_addr_ldc_f(void) | ||
4444 | { | ||
4445 | return 0x12U; | ||
4446 | } | ||
4447 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_stack_overflow_f(void) | ||
4448 | { | ||
4449 | return 0x16U; | ||
4450 | } | ||
4451 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_fault_f(void) | ||
4452 | { | ||
4453 | return 0x17U; | ||
4454 | } | ||
4455 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_tex_format_f(void) | ||
4456 | { | ||
4457 | return 0x18U; | ||
4458 | } | ||
4459 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_tex_layout_f(void) | ||
4460 | { | ||
4461 | return 0x19U; | ||
4462 | } | ||
4399 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_nack_f(void) | 4463 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_nack_f(void) |
4400 | { | 4464 | { |
4401 | return 0x20U; | 4465 | return 0x20U; |
@@ -4428,6 +4492,10 @@ static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(void) | |||
4428 | { | 4492 | { |
4429 | return 0x00504738U; | 4493 | return 0x00504738U; |
4430 | } | 4494 | } |
4495 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_hi_r(void) | ||
4496 | { | ||
4497 | return 0x0050473cU; | ||
4498 | } | ||
4431 | static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) | 4499 | static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) |
4432 | { | 4500 | { |
4433 | return 0x005043a0U; | 4501 | return 0x005043a0U; |