From 7aded206bc3eb0f36422e9f6f3dab3e065e7e7e4 Mon Sep 17 00:00:00 2001
From: Vinod G <vinodg@nvidia.com>
Date: Fri, 25 May 2018 15:44:34 -0700
Subject: gpu: nvgpu: gv11b: Handle all SM errors

Add the missing register bits to identify the
SM errors.

Except for mmu_nack error, all other errors are
handled using a single function.
That function sets the error notifier with GR_EXCEPTION,
clears interrupt and triggers recovery process.

bug 200402677
JIRA NVGPU-573

Change-Id: Icfaff1f20f1f35adb4cd35ce288ce694845aed3c
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730963
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
---
 .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 68 ++++++++++++++++++++++
 1 file changed, 68 insertions(+)

(limited to 'drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h')

diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
index 17c7e77d..5de691a2 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
@@ -4392,10 +4392,74 @@ static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_f(void)
 {
 	return 0x0U;
 }
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_stack_error_f(void)
+{
+	return 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_api_stack_error_f(void)
+{
+	return 0x2U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_pc_wrap_f(void)
+{
+	return 0x4U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_pc_f(void)
+{
+	return 0x5U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_pc_overflow_f(void)
+{
+	return 0x6U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_reg_f(void)
+{
+	return 0x8U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_illegal_instr_encoding_f(void)
+{
+	return 0x9U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_illegal_instr_param_f(void)
+{
+	return 0xbU;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_oor_reg_f(void)
+{
+	return 0xdU;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_oor_addr_f(void)
+{
+	return 0xeU;
+}
 static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_addr_f(void)
 {
 	return 0xfU;
 }
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_invalid_addr_space_f(void)
+{
+	return 0x10U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_invalid_const_addr_ldc_f(void)
+{
+	return 0x12U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_stack_overflow_f(void)
+{
+	return 0x16U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_fault_f(void)
+{
+	return 0x17U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_tex_format_f(void)
+{
+	return 0x18U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_tex_layout_f(void)
+{
+	return 0x19U;
+}
 static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_nack_f(void)
 {
 	return 0x20U;
@@ -4428,6 +4492,10 @@ static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(void)
 {
 	return 0x00504738U;
 }
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_hi_r(void)
+{
+	return 0x0050473cU;
+}
 static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void)
 {
 	return 0x005043a0U;
-- 
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