gpu: nvgpu: gv11b: Use sm dbgr bpt and warp mask 0/1

Instead of assuming mask_0 and mask_1 as consecutive registers,
use mask_1 and mask_0 registers for reading/writing sm dbgr warp
and bpt mask registers

JIRA GPUT19X-75

Change-Id: Ib6843d13828d899d4bd3f12bdf6701325ea760fd
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1511736
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>

1 files changed, 4 insertions, 4 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
index daa4c08a..051961d2 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
@@ -3674,7 +3674,7 @@ static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f(void)
 {
         return 0x40000000;
 }
-static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_r(void)
+static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_0_r(void)
 {
         return 0x00504708;
 }
@@ -3682,7 +3682,7 @@ static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_1_r(void)
 {
         return 0x0050470c;
 }
-static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_r(void)
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_0_r(void)
 {
         return 0x00504710;
 }
@@ -3690,7 +3690,7 @@ static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_1_r(void)
 {
         return 0x00504714;
 }
-static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_r(void)
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_0_r(void)
 {
         return 0x00504718;
 }
@@ -3698,7 +3698,7 @@ static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_1_r(void)
 {
         return 0x0050471c;
 }
-static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_r(void)
+static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r(void)
 {
         return 0x00419e90;
 }