diff options
author | Vijayakumar Subbu <vsubbu@nvidia.com> | 2016-07-30 13:44:30 -0400 |
---|---|---|
committer | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 04:56:49 -0500 |
commit | 432017248e432df0619dc2df30f915a52634338f (patch) | |
tree | 40bb7a77983fb2753271bc46b346a44ebd6121cf /drivers/gpu/nvgpu/include/bios.h | |
parent | 38ad90b4840434df4650c617a236e1b01f8a43c6 (diff) |
gpu: nvgpu: Add dGPU clocks support
JIRA DNVGPU-42
Change-Id: Ic2fca9d0cf82f2823654ac5e8f0772a1eec7b3b5
Signed-off-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1205850
(cherry picked from commit b9f5c6bc4e649162d63e33d65b725872340ca114)
Reviewed-on: http://git-master/r/1227257
GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers/gpu/nvgpu/include/bios.h')
-rw-r--r-- | drivers/gpu/nvgpu/include/bios.h | 411 |
1 files changed, 411 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/include/bios.h b/drivers/gpu/nvgpu/include/bios.h new file mode 100644 index 00000000..3af5bcf4 --- /dev/null +++ b/drivers/gpu/nvgpu/include/bios.h | |||
@@ -0,0 +1,411 @@ | |||
1 | /* | ||
2 | * vbios tables support | ||
3 | * | ||
4 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | |||
16 | #ifndef NVGPU_INCLUDE_BIOS_H | ||
17 | #define NVGPU_INCLUDE_BIOS_H | ||
18 | |||
19 | #include "gk20a/gk20a.h" | ||
20 | |||
21 | #define BIOS_GET_FIELD(value, name) ((value & name##_MASK) >> name##_SHIFT) | ||
22 | |||
23 | struct fll_descriptor_header { | ||
24 | u8 version; | ||
25 | u8 size; | ||
26 | } __packed; | ||
27 | |||
28 | #define FLL_DESCRIPTOR_HEADER_10_SIZE_4 4 | ||
29 | #define FLL_DESCRIPTOR_HEADER_10_SIZE_6 6 | ||
30 | |||
31 | struct fll_descriptor_header_10 { | ||
32 | u8 version; | ||
33 | u8 header_size; | ||
34 | u8 entry_size; | ||
35 | u8 entry_count; | ||
36 | u16 max_min_freq_mhz; | ||
37 | } __packed; | ||
38 | |||
39 | #define FLL_DESCRIPTOR_ENTRY_10_SIZE 15 | ||
40 | |||
41 | struct fll_descriptor_entry_10 { | ||
42 | u8 fll_device_type; | ||
43 | u8 clk_domain; | ||
44 | u8 fll_device_id; | ||
45 | u16 lut_params; | ||
46 | u8 vin_idx_logic; | ||
47 | u8 vin_idx_sram; | ||
48 | u16 fll_params; | ||
49 | u8 min_freq_vfe_idx; | ||
50 | u8 freq_ctrl_idx; | ||
51 | u16 ref_freq_mhz; | ||
52 | u16 ffr_cutoff_freq_mhz; | ||
53 | } __packed; | ||
54 | |||
55 | #define NV_FLL_DESC_FLL_PARAMS_MDIV_MASK 0x1F | ||
56 | #define NV_FLL_DESC_FLL_PARAMS_MDIV_SHIFT 0 | ||
57 | |||
58 | #define NV_FLL_DESC_LUT_PARAMS_VSELECT_MASK 0x3 | ||
59 | #define NV_FLL_DESC_LUT_PARAMS_VSELECT_SHIFT 0 | ||
60 | |||
61 | #define NV_FLL_DESC_LUT_PARAMS_HYSTERISIS_THRESHOLD_MASK 0x3C | ||
62 | #define NV_FLL_DESC_LUT_PARAMS_HYSTERISIS_THRESHOLD_SHIFT 2 | ||
63 | |||
64 | struct vin_descriptor_header_10 { | ||
65 | u8 version; | ||
66 | u8 header_sizee; | ||
67 | u8 entry_size; | ||
68 | u8 entry_count; | ||
69 | u8 flags0; | ||
70 | u32 vin_cal; | ||
71 | } __packed; | ||
72 | |||
73 | struct vin_descriptor_entry_10 { | ||
74 | u8 vin_device_type; | ||
75 | u8 volt_domain_vbios; | ||
76 | u8 vin_device_id; | ||
77 | } __packed; | ||
78 | |||
79 | #define NV_VIN_DESC_FLAGS0_VIN_CAL_REVISION_MASK 0x7 | ||
80 | #define NV_VIN_DESC_FLAGS0_VIN_CAL_REVISION_SHIFT 0 | ||
81 | |||
82 | #define NV_VIN_DESC_FLAGS0_DISABLE_CONTROL_MASK 0x8 | ||
83 | #define NV_VIN_DESC_FLAGS0_DISABLE_CONTROL_SHIFT 3 | ||
84 | |||
85 | #define NV_VIN_DESC_VIN_CAL_SLOPE_FRACTION_MASK 0x1FF | ||
86 | #define NV_VIN_DESC_VIN_CAL_SLOPE_FRACTION_SHIFT 0 | ||
87 | |||
88 | #define NV_VIN_DESC_VIN_CAL_SLOPE_INTEGER_MASK 0x3C00 | ||
89 | #define NV_VIN_DESC_VIN_CAL_SLOPE_INTEGER_SHIFT 10 | ||
90 | |||
91 | #define NV_VIN_DESC_VIN_CAL_INTERCEPT_FRACTION_MASK 0x3C000 | ||
92 | #define NV_VIN_DESC_VIN_CAL_INTERCEPT_FRACTION_SHIFT 14 | ||
93 | |||
94 | #define NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER_MASK 0xFFC0000 | ||
95 | #define NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER_SHIFT 18 | ||
96 | |||
97 | #define VBIOS_CLOCKS_TABLE_1X_HEADER_SIZE_07 0x07 | ||
98 | struct vbios_clocks_table_1x_header { | ||
99 | u8 version; | ||
100 | u8 header_size; | ||
101 | u8 entry_size; | ||
102 | u8 entry_count; | ||
103 | u8 clocks_hal; | ||
104 | u16 cntr_sampling_periodms; | ||
105 | } __packed; | ||
106 | |||
107 | #define VBIOS_CLOCKS_TABLE_1X_ENTRY_SIZE_09 0x09 | ||
108 | struct vbios_clocks_table_1x_entry { | ||
109 | u8 flags0; | ||
110 | u16 param0; | ||
111 | u32 param1; | ||
112 | u16 param2; | ||
113 | } __packed; | ||
114 | |||
115 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_MASK 0x1F | ||
116 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_SHIFT 0 | ||
117 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_FIXED 0x00 | ||
118 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_MASTER 0x01 | ||
119 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_SLAVE 0x02 | ||
120 | |||
121 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST_MASK 0xFF | ||
122 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST_SHIFT 0 | ||
123 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST_MASK 0xFF00 | ||
124 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST_SHIFT 0x08 | ||
125 | |||
126 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_FIXED_FREQUENCY_MHZ_MASK 0xFFFF | ||
127 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_FIXED_FREQUENCY_MHZ_SHIFT 0 | ||
128 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MIN_MHZ_MASK 0xFFFF | ||
129 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MIN_MHZ_SHIFT 0 | ||
130 | |||
131 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MAX_MHZ_MASK 0xFFFF0000 | ||
132 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MAX_MHZ_SHIFT 0 | ||
133 | |||
134 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_SLAVE_MASTER_DOMAIN_MASK 0xF | ||
135 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_SLAVE_MASTER_DOMAIN_SHIFT 0 | ||
136 | |||
137 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX_MASK 0xF | ||
138 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX_SHIFT 0 | ||
139 | |||
140 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_AWARE_ORDERING_IDX_MASK 0xF0 | ||
141 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_AWARE_ORDERING_IDX_SHIFT 4 | ||
142 | |||
143 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_MASK 0x100 | ||
144 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_SHIFT 8 | ||
145 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_FALSE 0x00 | ||
146 | #define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_TRUE 0x01 | ||
147 | |||
148 | #define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_HEADER_SIZE_08 0x08 | ||
149 | struct vbios_clock_programming_table_1x_header { | ||
150 | u8 version; | ||
151 | u8 header_size; | ||
152 | u8 entry_size; | ||
153 | u8 entry_count; | ||
154 | u8 slave_entry_size; | ||
155 | u8 slave_entry_count; | ||
156 | u8 vf_entry_size; | ||
157 | u8 vf_entry_count; | ||
158 | } __packed; | ||
159 | |||
160 | #define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_SIZE_05 0x05 | ||
161 | #define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_SIZE_0D 0x0D | ||
162 | struct vbios_clock_programming_table_1x_entry { | ||
163 | u8 flags0; | ||
164 | u16 freq_max_mhz; | ||
165 | u8 param0; | ||
166 | u8 param1; | ||
167 | u32 rsvd; | ||
168 | u32 rsvd1; | ||
169 | } __packed; | ||
170 | |||
171 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASK 0xF | ||
172 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_SHIFT 0 | ||
173 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASTER_RATIO 0x00 | ||
174 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASTER_TABLE 0x01 | ||
175 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_SLAVE 0x02 | ||
176 | |||
177 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_MASK 0x70 | ||
178 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_SHIFT 4 | ||
179 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_PLL 0x00 | ||
180 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_ONE_SOURCE 0x01 | ||
181 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_FLL 0x02 | ||
182 | |||
183 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_MASK 0x80 | ||
184 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_SHIFT 7 | ||
185 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_FALSE 0x00 | ||
186 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_TRUE 0x01 | ||
187 | |||
188 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM0_PLL_PLL_INDEX_MASK 0xFF | ||
189 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM0_PLL_PLL_INDEX_SHIFT 0 | ||
190 | |||
191 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM1_PLL_FREQ_STEP_SIZE_MASK 0xFF | ||
192 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM1_PLL_FREQ_STEP_SIZE_SHIFT 0 | ||
193 | |||
194 | #define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_SIZE_03 0x03 | ||
195 | struct vbios_clock_programming_table_1x_slave_entry { | ||
196 | u8 clk_dom_idx; | ||
197 | u16 param0; | ||
198 | } __packed; | ||
199 | |||
200 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_RATIO_RATIO_MASK 0xFF | ||
201 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_RATIO_RATIO_SHIFT 0 | ||
202 | |||
203 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_TABLE_FREQ_MASK 0x3FFF | ||
204 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_TABLE_FREQ_SHIFT 0 | ||
205 | |||
206 | #define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_VF_ENTRY_SIZE_02 0x02 | ||
207 | struct vbios_clock_programming_table_1x_vf_entry { | ||
208 | u8 vfe_idx; | ||
209 | u8 param0; | ||
210 | } __packed; | ||
211 | |||
212 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_VF_ENTRY_PARAM0_FLL_GAIN_VFE_IDX_MASK 0xFF | ||
213 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_VF_ENTRY_PARAM0_FLL_GAIN_VFE_IDX_SHIFT 0 | ||
214 | |||
215 | struct vbios_vfe_3x_header_struct { | ||
216 | u8 version; | ||
217 | u8 header_size; | ||
218 | u8 vfe_var_entry_size; | ||
219 | u8 vfe_var_entry_count; | ||
220 | u8 vfe_equ_entry_size; | ||
221 | u8 vfe_equ_entry_count; | ||
222 | u8 polling_periodms; | ||
223 | } __packed; | ||
224 | |||
225 | #define VBIOS_VFE_3X_VAR_ENTRY_SIZE_11 0x11 | ||
226 | #define VBIOS_VFE_3X_VAR_ENTRY_SIZE_19 0x19 | ||
227 | struct vbios_vfe_3x_var_entry_struct { | ||
228 | u8 type; | ||
229 | u32 out_range_min; | ||
230 | u32 out_range_max; | ||
231 | u32 param0; | ||
232 | u32 param1; | ||
233 | u32 param2; | ||
234 | u32 param3; | ||
235 | } __packed; | ||
236 | |||
237 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DISABLED 0x00 | ||
238 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_FREQUENCY 0x01 | ||
239 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_VOLTAGE 0x02 | ||
240 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_SENSED_TEMP 0x03 | ||
241 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_SENSED_FUSE 0x04 | ||
242 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DERIVED_PRODUCT 0x05 | ||
243 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DERIVED_SUM 0x06 | ||
244 | |||
245 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_TH_CH_IDX_MASK 0xFF | ||
246 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_TH_CH_IDX_SHIFT 0 | ||
247 | |||
248 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_POS_MASK 0xFF00 | ||
249 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_POS_SHIFT 8 | ||
250 | |||
251 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_NEG_MASK 0xFF0000 | ||
252 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_NEG_SHIFT 16 | ||
253 | |||
254 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_MASK 0xFF | ||
255 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_SHIFT 0 | ||
256 | |||
257 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_VER_MASK 0xFF00 | ||
258 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_VER_SHIFT 8 | ||
259 | |||
260 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_EXPECTED_VER_MASK 0xFF0000 | ||
261 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_EXPECTED_VER_SHIFT 16 | ||
262 | |||
263 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_MASK 0x1000000 | ||
264 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_SHIFT 24 | ||
265 | |||
266 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_YES 0x00000001 | ||
267 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_NO 0x00000000 | ||
268 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_0_MASK 0xFF | ||
269 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_0_SHIFT 0 | ||
270 | |||
271 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_1_MASK 0xFF00 | ||
272 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_1_SHIFT 8 | ||
273 | |||
274 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_0_MASK 0xFF | ||
275 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_0_SHIFT 0 | ||
276 | |||
277 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_1_MASK 0xFF00 | ||
278 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_1_SHIFT 8 | ||
279 | |||
280 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_DEFAULT_VAL_MASK 0xFFFFFFFF | ||
281 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_DEFAULT_VAL_SHIFT 0 | ||
282 | |||
283 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_SCALE_MASK 0xFFFFFFFF | ||
284 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_SCALE_SHIFT 0 | ||
285 | |||
286 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_OFFSET_MASK 0xFFFFFFFF | ||
287 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_OFFSET_SHIFT 0 | ||
288 | |||
289 | #define VBIOS_VFE_3X_EQU_ENTRY_SIZE_17 0x17 | ||
290 | #define VBIOS_VFE_3X_EQU_ENTRY_SIZE_18 0x18 | ||
291 | |||
292 | struct vbios_vfe_3x_equ_entry_struct { | ||
293 | u8 type; | ||
294 | u8 var_idx; | ||
295 | u8 equ_idx_next; | ||
296 | u32 out_range_min; | ||
297 | u32 out_range_max; | ||
298 | u32 param0; | ||
299 | u32 param1; | ||
300 | u32 param2; | ||
301 | u8 param3; | ||
302 | } __packed; | ||
303 | |||
304 | |||
305 | #define VBIOS_VFE_3X_EQU_ENTRY_TYPE_DISABLED 0x00 | ||
306 | #define VBIOS_VFE_3X_EQU_ENTRY_TYPE_QUADRATIC 0x01 | ||
307 | #define VBIOS_VFE_3X_EQU_ENTRY_TYPE_MINMAX 0x02 | ||
308 | #define VBIOS_VFE_3X_EQU_ENTRY_TYPE_COMPARE 0x03 | ||
309 | #define VBIOS_VFE_3X_EQU_ENTRY_TYPE_QUADRATIC_FXP 0x04 | ||
310 | #define VBIOS_VFE_3X_EQU_ENTRY_TYPE_MINMAX_FXP 0x05 | ||
311 | |||
312 | #define VBIOS_VFE_3X_EQU_ENTRY_IDX_INVALID 0xFF | ||
313 | |||
314 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_QUADRATIC_C0_MASK 0xFFFFFFFF | ||
315 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_QUADRATIC_C0_SHIFT 0 | ||
316 | |||
317 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_0_MASK 0xFF | ||
318 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_0_SHIFT 0 | ||
319 | |||
320 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_1_MASK 0xFF00 | ||
321 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_1_SHIFT 8 | ||
322 | |||
323 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MASK 0x10000 | ||
324 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_SHIFT 16 | ||
325 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MIN 0x00000000 | ||
326 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MAX 0x00000001 | ||
327 | |||
328 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_COMPARE_CRIT_MASK 0xFFFFFFFF | ||
329 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_COMPARE_CRIT_SHIFT 0 | ||
330 | |||
331 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR1_QUADRATIC_C1_MASK 0xFFFFFFFF | ||
332 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR1_QUADRATIC_C1_SHIFT 0 | ||
333 | |||
334 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_TRUE_MASK 0xFF | ||
335 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_TRUE_SHIFT 0 | ||
336 | |||
337 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_FALSE_MASK 0xFF00 | ||
338 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_FALSE_SHIFT 8 | ||
339 | |||
340 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_MASK 0x70000 | ||
341 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_SHIFT 16 | ||
342 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_EQUAL 0x00000000 | ||
343 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_GREATER_EQ 0x00000001 | ||
344 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_GREATER 0x00000002 | ||
345 | |||
346 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_MASK 0xF | ||
347 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_SHIFT 0 | ||
348 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_UNITLESS 0x0 | ||
349 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_FREQ_MHZ 0x1 | ||
350 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VOLT_UV 0x2 | ||
351 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VF_GAIN 0x3 | ||
352 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VOLT_DELTA_UV 0x4 | ||
353 | |||
354 | #define NV_VFIELD_DESC_SIZE_BYTE 0x00000000 | ||
355 | #define NV_VFIELD_DESC_SIZE_WORD 0x00000001 | ||
356 | #define NV_VFIELD_DESC_SIZE_DWORD 0x00000002 | ||
357 | #define VFIELD_SIZE(pvregentry) ((pvregentry->strap_reg_desc & 0x18) >> 3) | ||
358 | |||
359 | #define NV_PMU_BIOS_VFIELD_DESC_CODE_INVALID 0x00000000 | ||
360 | #define NV_PMU_BIOS_VFIELD_DESC_CODE_REG 0x00000001 | ||
361 | #define NV_PMU_BIOS_VFIELD_DESC_CODE_INDEX_REG 0x00000002 | ||
362 | |||
363 | #define NV_VFIELD_DESC_CODE_INVALID NV_PMU_BIOS_VFIELD_DESC_CODE_INVALID | ||
364 | #define NV_VFIELD_DESC_CODE_REG NV_PMU_BIOS_VFIELD_DESC_CODE_REG | ||
365 | #define NV_VFIELD_DESC_CODE_INDEX_REG NV_PMU_BIOS_VFIELD_DESC_CODE_INDEX_REG | ||
366 | |||
367 | #define VFIELD_CODE(pvregentry) ((pvregentry->strap_reg_desc & 0xE0) >> 5) | ||
368 | |||
369 | #define VFIELD_ID_STRAP_IDDQ 0x09 | ||
370 | #define VFIELD_ID_STRAP_IDDQ_1 0x0B | ||
371 | |||
372 | #define VFIELD_REG_HEADER_SIZE 3 | ||
373 | struct vfield_reg_header { | ||
374 | u8 version; | ||
375 | u8 entry_size; | ||
376 | u8 count; | ||
377 | } __packed; | ||
378 | |||
379 | #define VBIOS_VFIELD_REG_TABLE_VERSION_1_0 0x10 | ||
380 | |||
381 | |||
382 | #define VFIELD_REG_ENTRY_SIZE 13 | ||
383 | struct vfield_reg_entry { | ||
384 | u8 strap_reg_desc; | ||
385 | u32 reg; | ||
386 | u32 reg_index; | ||
387 | u32 index; | ||
388 | } __packed; | ||
389 | |||
390 | #define VFIELD_HEADER_SIZE 3 | ||
391 | |||
392 | struct vfield_header { | ||
393 | u8 version; | ||
394 | u8 entry_size; | ||
395 | u8 count; | ||
396 | } __packed; | ||
397 | |||
398 | #define VBIOS_VFIELD_TABLE_VERSION_1_0 0x10 | ||
399 | |||
400 | #define VFIELD_BIT_START(ventry) (ventry.strap_desc & 0x1F) | ||
401 | #define VFIELD_BIT_STOP(ventry) ((ventry.strap_desc & 0x3E0) >> 5) | ||
402 | #define VFIELD_BIT_REG(ventry) ((ventry.strap_desc & 0x3C00) >> 10) | ||
403 | |||
404 | #define VFIELD_ENTRY_SIZE 3 | ||
405 | |||
406 | struct vfield_entry { | ||
407 | u8 strap_id; | ||
408 | u16 strap_desc; | ||
409 | } __packed; | ||
410 | |||
411 | #endif | ||