From 432017248e432df0619dc2df30f915a52634338f Mon Sep 17 00:00:00 2001 From: Vijayakumar Subbu Date: Sat, 30 Jul 2016 10:44:30 -0700 Subject: gpu: nvgpu: Add dGPU clocks support JIRA DNVGPU-42 Change-Id: Ic2fca9d0cf82f2823654ac5e8f0772a1eec7b3b5 Signed-off-by: Vijayakumar Subbu Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1205850 (cherry picked from commit b9f5c6bc4e649162d63e33d65b725872340ca114) Reviewed-on: http://git-master/r/1227257 GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/include/bios.h | 411 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 411 insertions(+) create mode 100644 drivers/gpu/nvgpu/include/bios.h (limited to 'drivers/gpu/nvgpu/include/bios.h') diff --git a/drivers/gpu/nvgpu/include/bios.h b/drivers/gpu/nvgpu/include/bios.h new file mode 100644 index 00000000..3af5bcf4 --- /dev/null +++ b/drivers/gpu/nvgpu/include/bios.h @@ -0,0 +1,411 @@ +/* + * vbios tables support + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef NVGPU_INCLUDE_BIOS_H +#define NVGPU_INCLUDE_BIOS_H + +#include "gk20a/gk20a.h" + +#define BIOS_GET_FIELD(value, name) ((value & name##_MASK) >> name##_SHIFT) + +struct fll_descriptor_header { + u8 version; + u8 size; +} __packed; + +#define FLL_DESCRIPTOR_HEADER_10_SIZE_4 4 +#define FLL_DESCRIPTOR_HEADER_10_SIZE_6 6 + +struct fll_descriptor_header_10 { + u8 version; + u8 header_size; + u8 entry_size; + u8 entry_count; + u16 max_min_freq_mhz; +} __packed; + +#define FLL_DESCRIPTOR_ENTRY_10_SIZE 15 + +struct fll_descriptor_entry_10 { + u8 fll_device_type; + u8 clk_domain; + u8 fll_device_id; + u16 lut_params; + u8 vin_idx_logic; + u8 vin_idx_sram; + u16 fll_params; + u8 min_freq_vfe_idx; + u8 freq_ctrl_idx; + u16 ref_freq_mhz; + u16 ffr_cutoff_freq_mhz; +} __packed; + +#define NV_FLL_DESC_FLL_PARAMS_MDIV_MASK 0x1F +#define NV_FLL_DESC_FLL_PARAMS_MDIV_SHIFT 0 + +#define NV_FLL_DESC_LUT_PARAMS_VSELECT_MASK 0x3 +#define NV_FLL_DESC_LUT_PARAMS_VSELECT_SHIFT 0 + +#define NV_FLL_DESC_LUT_PARAMS_HYSTERISIS_THRESHOLD_MASK 0x3C +#define NV_FLL_DESC_LUT_PARAMS_HYSTERISIS_THRESHOLD_SHIFT 2 + +struct vin_descriptor_header_10 { + u8 version; + u8 header_sizee; + u8 entry_size; + u8 entry_count; + u8 flags0; + u32 vin_cal; +} __packed; + +struct vin_descriptor_entry_10 { + u8 vin_device_type; + u8 volt_domain_vbios; + u8 vin_device_id; +} __packed; + +#define NV_VIN_DESC_FLAGS0_VIN_CAL_REVISION_MASK 0x7 +#define NV_VIN_DESC_FLAGS0_VIN_CAL_REVISION_SHIFT 0 + +#define NV_VIN_DESC_FLAGS0_DISABLE_CONTROL_MASK 0x8 +#define NV_VIN_DESC_FLAGS0_DISABLE_CONTROL_SHIFT 3 + +#define NV_VIN_DESC_VIN_CAL_SLOPE_FRACTION_MASK 0x1FF +#define NV_VIN_DESC_VIN_CAL_SLOPE_FRACTION_SHIFT 0 + +#define NV_VIN_DESC_VIN_CAL_SLOPE_INTEGER_MASK 0x3C00 +#define NV_VIN_DESC_VIN_CAL_SLOPE_INTEGER_SHIFT 10 + +#define NV_VIN_DESC_VIN_CAL_INTERCEPT_FRACTION_MASK 0x3C000 +#define NV_VIN_DESC_VIN_CAL_INTERCEPT_FRACTION_SHIFT 14 + +#define NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER_MASK 0xFFC0000 +#define NV_VIN_DESC_VIN_CAL_INTERCEPT_INTEGER_SHIFT 18 + +#define VBIOS_CLOCKS_TABLE_1X_HEADER_SIZE_07 0x07 +struct vbios_clocks_table_1x_header { + u8 version; + u8 header_size; + u8 entry_size; + u8 entry_count; + u8 clocks_hal; + u16 cntr_sampling_periodms; +} __packed; + +#define VBIOS_CLOCKS_TABLE_1X_ENTRY_SIZE_09 0x09 +struct vbios_clocks_table_1x_entry { + u8 flags0; + u16 param0; + u32 param1; + u16 param2; +} __packed; + +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_MASK 0x1F +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_SHIFT 0 +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_FIXED 0x00 +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_MASTER 0x01 +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_SLAVE 0x02 + +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST_MASK 0xFF +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST_SHIFT 0 +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST_MASK 0xFF00 +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST_SHIFT 0x08 + +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_FIXED_FREQUENCY_MHZ_MASK 0xFFFF +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_FIXED_FREQUENCY_MHZ_SHIFT 0 +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MIN_MHZ_MASK 0xFFFF +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MIN_MHZ_SHIFT 0 + +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MAX_MHZ_MASK 0xFFFF0000 +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MAX_MHZ_SHIFT 0 + +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_SLAVE_MASTER_DOMAIN_MASK 0xF +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_SLAVE_MASTER_DOMAIN_SHIFT 0 + +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX_MASK 0xF +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX_SHIFT 0 + +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_AWARE_ORDERING_IDX_MASK 0xF0 +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_AWARE_ORDERING_IDX_SHIFT 4 + +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_MASK 0x100 +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_SHIFT 8 +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_FALSE 0x00 +#define NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING_TRUE 0x01 + +#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_HEADER_SIZE_08 0x08 +struct vbios_clock_programming_table_1x_header { + u8 version; + u8 header_size; + u8 entry_size; + u8 entry_count; + u8 slave_entry_size; + u8 slave_entry_count; + u8 vf_entry_size; + u8 vf_entry_count; +} __packed; + +#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_SIZE_05 0x05 +#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_SIZE_0D 0x0D +struct vbios_clock_programming_table_1x_entry { + u8 flags0; + u16 freq_max_mhz; + u8 param0; + u8 param1; + u32 rsvd; + u32 rsvd1; +} __packed; + +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASK 0xF +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_SHIFT 0 +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASTER_RATIO 0x00 +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_MASTER_TABLE 0x01 +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_TYPE_SLAVE 0x02 + +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_MASK 0x70 +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_SHIFT 4 +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_PLL 0x00 +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_ONE_SOURCE 0x01 +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_SOURCE_FLL 0x02 + +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_MASK 0x80 +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_SHIFT 7 +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_FALSE 0x00 +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_FLAGS0_OVOC_ENABLED_TRUE 0x01 + +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM0_PLL_PLL_INDEX_MASK 0xFF +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM0_PLL_PLL_INDEX_SHIFT 0 + +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM1_PLL_FREQ_STEP_SIZE_MASK 0xFF +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM1_PLL_FREQ_STEP_SIZE_SHIFT 0 + +#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_SIZE_03 0x03 +struct vbios_clock_programming_table_1x_slave_entry { + u8 clk_dom_idx; + u16 param0; +} __packed; + +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_RATIO_RATIO_MASK 0xFF +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_RATIO_RATIO_SHIFT 0 + +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_TABLE_FREQ_MASK 0x3FFF +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_TABLE_FREQ_SHIFT 0 + +#define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_VF_ENTRY_SIZE_02 0x02 +struct vbios_clock_programming_table_1x_vf_entry { + u8 vfe_idx; + u8 param0; +} __packed; + +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_VF_ENTRY_PARAM0_FLL_GAIN_VFE_IDX_MASK 0xFF +#define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_VF_ENTRY_PARAM0_FLL_GAIN_VFE_IDX_SHIFT 0 + +struct vbios_vfe_3x_header_struct { + u8 version; + u8 header_size; + u8 vfe_var_entry_size; + u8 vfe_var_entry_count; + u8 vfe_equ_entry_size; + u8 vfe_equ_entry_count; + u8 polling_periodms; +} __packed; + +#define VBIOS_VFE_3X_VAR_ENTRY_SIZE_11 0x11 +#define VBIOS_VFE_3X_VAR_ENTRY_SIZE_19 0x19 +struct vbios_vfe_3x_var_entry_struct { + u8 type; + u32 out_range_min; + u32 out_range_max; + u32 param0; + u32 param1; + u32 param2; + u32 param3; +} __packed; + +#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DISABLED 0x00 +#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_FREQUENCY 0x01 +#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_VOLTAGE 0x02 +#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_SENSED_TEMP 0x03 +#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_SENSED_FUSE 0x04 +#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DERIVED_PRODUCT 0x05 +#define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DERIVED_SUM 0x06 + +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_TH_CH_IDX_MASK 0xFF +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_TH_CH_IDX_SHIFT 0 + +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_POS_MASK 0xFF00 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_POS_SHIFT 8 + +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_NEG_MASK 0xFF0000 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_HYS_NEG_SHIFT 16 + +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_MASK 0xFF +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_SHIFT 0 + +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_VER_MASK 0xFF00 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VFIELD_ID_VER_SHIFT 8 + +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_EXPECTED_VER_MASK 0xFF0000 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_EXPECTED_VER_SHIFT 16 + +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_MASK 0x1000000 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_SHIFT 24 + +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_YES 0x00000001 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_NO 0x00000000 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_0_MASK 0xFF +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_0_SHIFT 0 + +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_1_MASK 0xFF00 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_1_SHIFT 8 + +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_0_MASK 0xFF +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_0_SHIFT 0 + +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_1_MASK 0xFF00 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DSUM_VFE_VAR_IDX_1_SHIFT 8 + +#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_DEFAULT_VAL_MASK 0xFFFFFFFF +#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_DEFAULT_VAL_SHIFT 0 + +#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_SCALE_MASK 0xFFFFFFFF +#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_SCALE_SHIFT 0 + +#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_OFFSET_MASK 0xFFFFFFFF +#define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_OFFSET_SHIFT 0 + +#define VBIOS_VFE_3X_EQU_ENTRY_SIZE_17 0x17 +#define VBIOS_VFE_3X_EQU_ENTRY_SIZE_18 0x18 + +struct vbios_vfe_3x_equ_entry_struct { + u8 type; + u8 var_idx; + u8 equ_idx_next; + u32 out_range_min; + u32 out_range_max; + u32 param0; + u32 param1; + u32 param2; + u8 param3; +} __packed; + + +#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_DISABLED 0x00 +#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_QUADRATIC 0x01 +#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_MINMAX 0x02 +#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_COMPARE 0x03 +#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_QUADRATIC_FXP 0x04 +#define VBIOS_VFE_3X_EQU_ENTRY_TYPE_MINMAX_FXP 0x05 + +#define VBIOS_VFE_3X_EQU_ENTRY_IDX_INVALID 0xFF + +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_QUADRATIC_C0_MASK 0xFFFFFFFF +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_QUADRATIC_C0_SHIFT 0 + +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_0_MASK 0xFF +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_0_SHIFT 0 + +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_1_MASK 0xFF00 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_VFE_EQU_IDX_1_SHIFT 8 + +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MASK 0x10000 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_SHIFT 16 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MIN 0x00000000 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_MINMAX_CRIT_MAX 0x00000001 + +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_COMPARE_CRIT_MASK 0xFFFFFFFF +#define VBIOS_VFE_3X_EQU_ENTRY_PAR0_COMPARE_CRIT_SHIFT 0 + +#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_QUADRATIC_C1_MASK 0xFFFFFFFF +#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_QUADRATIC_C1_SHIFT 0 + +#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_TRUE_MASK 0xFF +#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_TRUE_SHIFT 0 + +#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_FALSE_MASK 0xFF00 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_VFE_EQU_IDX_FALSE_SHIFT 8 + +#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_MASK 0x70000 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_SHIFT 16 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_EQUAL 0x00000000 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_GREATER_EQ 0x00000001 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR1_COMPARE_FUNCTION_GREATER 0x00000002 + +#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_MASK 0xF +#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_SHIFT 0 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_UNITLESS 0x0 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_FREQ_MHZ 0x1 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VOLT_UV 0x2 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VF_GAIN 0x3 +#define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VOLT_DELTA_UV 0x4 + +#define NV_VFIELD_DESC_SIZE_BYTE 0x00000000 +#define NV_VFIELD_DESC_SIZE_WORD 0x00000001 +#define NV_VFIELD_DESC_SIZE_DWORD 0x00000002 +#define VFIELD_SIZE(pvregentry) ((pvregentry->strap_reg_desc & 0x18) >> 3) + +#define NV_PMU_BIOS_VFIELD_DESC_CODE_INVALID 0x00000000 +#define NV_PMU_BIOS_VFIELD_DESC_CODE_REG 0x00000001 +#define NV_PMU_BIOS_VFIELD_DESC_CODE_INDEX_REG 0x00000002 + +#define NV_VFIELD_DESC_CODE_INVALID NV_PMU_BIOS_VFIELD_DESC_CODE_INVALID +#define NV_VFIELD_DESC_CODE_REG NV_PMU_BIOS_VFIELD_DESC_CODE_REG +#define NV_VFIELD_DESC_CODE_INDEX_REG NV_PMU_BIOS_VFIELD_DESC_CODE_INDEX_REG + +#define VFIELD_CODE(pvregentry) ((pvregentry->strap_reg_desc & 0xE0) >> 5) + +#define VFIELD_ID_STRAP_IDDQ 0x09 +#define VFIELD_ID_STRAP_IDDQ_1 0x0B + +#define VFIELD_REG_HEADER_SIZE 3 +struct vfield_reg_header { + u8 version; + u8 entry_size; + u8 count; +} __packed; + +#define VBIOS_VFIELD_REG_TABLE_VERSION_1_0 0x10 + + +#define VFIELD_REG_ENTRY_SIZE 13 +struct vfield_reg_entry { + u8 strap_reg_desc; + u32 reg; + u32 reg_index; + u32 index; +} __packed; + +#define VFIELD_HEADER_SIZE 3 + +struct vfield_header { + u8 version; + u8 entry_size; + u8 count; +} __packed; + +#define VBIOS_VFIELD_TABLE_VERSION_1_0 0x10 + +#define VFIELD_BIT_START(ventry) (ventry.strap_desc & 0x1F) +#define VFIELD_BIT_STOP(ventry) ((ventry.strap_desc & 0x3E0) >> 5) +#define VFIELD_BIT_REG(ventry) ((ventry.strap_desc & 0x3C00) >> 10) + +#define VFIELD_ENTRY_SIZE 3 + +struct vfield_entry { + u8 strap_id; + u16 strap_desc; +} __packed; + +#endif -- cgit v1.2.2