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authorTerje Bergstrom <tbergstrom@nvidia.com>2018-01-17 15:39:13 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2018-01-23 01:20:15 -0500
commitf3f14cdff53f4b936e2505d44aad6e3bca143056 (patch)
tree8d6438132b8ca429758d18142c5f569f60f2bc35 /drivers/gpu/nvgpu/gv11b
parent193a2ed38ca51d898ac811820ab86237c84e18eb (diff)
gpu: nvgpu: Fold T19x code back to main code paths
Lots of code paths were split to T19x specific code paths and structs due to split repository. Now that repositories are merged, fold all of them back to main code paths and structs and remove the T19x specific Kconfig flag. Change-Id: Id0d17a5f0610fc0b49f51ab6664e716dc8b222b6 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1640606 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b')
-rw-r--r--drivers/gpu/nvgpu/gv11b/ecc_gv11b.h66
-rw-r--r--drivers/gpu/nvgpu/gv11b/fb_gv11b.c26
-rw-r--r--drivers/gpu/nvgpu/gv11b/fifo_gv11b.c14
-rw-r--r--drivers/gpu/nvgpu/gv11b/gr_gv11b.c46
-rw-r--r--drivers/gpu/nvgpu/gv11b/gr_gv11b.h6
-rw-r--r--drivers/gpu/nvgpu/gv11b/gv11b.c3
-rw-r--r--drivers/gpu/nvgpu/gv11b/ltc_gv11b.c6
-rw-r--r--drivers/gpu/nvgpu/gv11b/mm_gv11b.c4
-rw-r--r--drivers/gpu/nvgpu/gv11b/pmu_gv11b.c10
-rw-r--r--drivers/gpu/nvgpu/gv11b/subctx_gv11b.c8
10 files changed, 58 insertions, 131 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/ecc_gv11b.h b/drivers/gpu/nvgpu/gv11b/ecc_gv11b.h
deleted file mode 100644
index ebce46ce..00000000
--- a/drivers/gpu/nvgpu/gv11b/ecc_gv11b.h
+++ /dev/null
@@ -1,66 +0,0 @@
1/*
2 * GV11B GPU ECC
3 *
4 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef _NVGPU_ECC_GV11B_H_
26#define _NVGPU_ECC_GV11B_H_
27
28struct ecc_gr_t19x {
29 struct gk20a_ecc_stat sm_l1_tag_corrected_err_count;
30 struct gk20a_ecc_stat sm_l1_tag_uncorrected_err_count;
31 struct gk20a_ecc_stat sm_cbu_corrected_err_count;
32 struct gk20a_ecc_stat sm_cbu_uncorrected_err_count;
33 struct gk20a_ecc_stat sm_l1_data_corrected_err_count;
34 struct gk20a_ecc_stat sm_l1_data_uncorrected_err_count;
35 struct gk20a_ecc_stat sm_icache_corrected_err_count;
36 struct gk20a_ecc_stat sm_icache_uncorrected_err_count;
37 struct gk20a_ecc_stat gcc_l15_corrected_err_count;
38 struct gk20a_ecc_stat gcc_l15_uncorrected_err_count;
39 struct gk20a_ecc_stat fecs_corrected_err_count;
40 struct gk20a_ecc_stat fecs_uncorrected_err_count;
41 struct gk20a_ecc_stat gpccs_corrected_err_count;
42 struct gk20a_ecc_stat gpccs_uncorrected_err_count;
43 struct gk20a_ecc_stat mmu_l1tlb_corrected_err_count;
44 struct gk20a_ecc_stat mmu_l1tlb_uncorrected_err_count;
45};
46
47struct ecc_ltc_t19x {
48 struct gk20a_ecc_stat l2_cache_corrected_err_count;
49 struct gk20a_ecc_stat l2_cache_uncorrected_err_count;
50};
51
52/* TODO: PMU and FB ECC features are still under embargo */
53struct ecc_eng_t19x {
54 /* FB */
55 struct gk20a_ecc_stat mmu_l2tlb_corrected_err_count;
56 struct gk20a_ecc_stat mmu_l2tlb_uncorrected_err_count;
57 struct gk20a_ecc_stat mmu_hubtlb_corrected_err_count;
58 struct gk20a_ecc_stat mmu_hubtlb_uncorrected_err_count;
59 struct gk20a_ecc_stat mmu_fillunit_corrected_err_count;
60 struct gk20a_ecc_stat mmu_fillunit_uncorrected_err_count;
61 /* PMU */
62 struct gk20a_ecc_stat pmu_corrected_err_count;
63 struct gk20a_ecc_stat pmu_uncorrected_err_count;
64};
65
66#endif
diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c
index 8ac3cb7b..b7a0a3cf 100644
--- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GV11B FB 2 * GV11B FB
3 * 3 *
4 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -568,9 +568,9 @@ static void gv11b_handle_l2tlb_ecc_isr(struct gk20a *g, u32 ecc_status)
568 uncorrected_delta += (0x1UL << fb_mmu_l2tlb_ecc_uncorrected_err_count_total_s()); 568 uncorrected_delta += (0x1UL << fb_mmu_l2tlb_ecc_uncorrected_err_count_total_s());
569 569
570 570
571 g->ecc.eng.t19x.mmu_l2tlb_corrected_err_count.counters[0] += 571 g->ecc.fb.mmu_l2tlb_corrected_err_count.counters[0] +=
572 corrected_delta; 572 corrected_delta;
573 g->ecc.eng.t19x.mmu_l2tlb_uncorrected_err_count.counters[0] += 573 g->ecc.fb.mmu_l2tlb_uncorrected_err_count.counters[0] +=
574 uncorrected_delta; 574 uncorrected_delta;
575 575
576 if (ecc_status & fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb_sa_data_m()) 576 if (ecc_status & fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb_sa_data_m())
@@ -584,8 +584,8 @@ static void gv11b_handle_l2tlb_ecc_isr(struct gk20a *g, u32 ecc_status)
584 "ecc error address: 0x%x", ecc_addr); 584 "ecc error address: 0x%x", ecc_addr);
585 nvgpu_log(g, gpu_dbg_intr, 585 nvgpu_log(g, gpu_dbg_intr,
586 "ecc error count corrected: %d, uncorrected %d", 586 "ecc error count corrected: %d, uncorrected %d",
587 g->ecc.eng.t19x.mmu_l2tlb_corrected_err_count.counters[0], 587 g->ecc.fb.mmu_l2tlb_corrected_err_count.counters[0],
588 g->ecc.eng.t19x.mmu_l2tlb_uncorrected_err_count.counters[0]); 588 g->ecc.fb.mmu_l2tlb_uncorrected_err_count.counters[0]);
589} 589}
590 590
591static void gv11b_handle_hubtlb_ecc_isr(struct gk20a *g, u32 ecc_status) 591static void gv11b_handle_hubtlb_ecc_isr(struct gk20a *g, u32 ecc_status)
@@ -626,9 +626,9 @@ static void gv11b_handle_hubtlb_ecc_isr(struct gk20a *g, u32 ecc_status)
626 uncorrected_delta += (0x1UL << fb_mmu_hubtlb_ecc_uncorrected_err_count_total_s()); 626 uncorrected_delta += (0x1UL << fb_mmu_hubtlb_ecc_uncorrected_err_count_total_s());
627 627
628 628
629 g->ecc.eng.t19x.mmu_hubtlb_corrected_err_count.counters[0] += 629 g->ecc.fb.mmu_hubtlb_corrected_err_count.counters[0] +=
630 corrected_delta; 630 corrected_delta;
631 g->ecc.eng.t19x.mmu_hubtlb_uncorrected_err_count.counters[0] += 631 g->ecc.fb.mmu_hubtlb_uncorrected_err_count.counters[0] +=
632 uncorrected_delta; 632 uncorrected_delta;
633 633
634 if (ecc_status & fb_mmu_hubtlb_ecc_status_corrected_err_sa_data_m()) 634 if (ecc_status & fb_mmu_hubtlb_ecc_status_corrected_err_sa_data_m())
@@ -642,8 +642,8 @@ static void gv11b_handle_hubtlb_ecc_isr(struct gk20a *g, u32 ecc_status)
642 "ecc error address: 0x%x", ecc_addr); 642 "ecc error address: 0x%x", ecc_addr);
643 nvgpu_log(g, gpu_dbg_intr, 643 nvgpu_log(g, gpu_dbg_intr,
644 "ecc error count corrected: %d, uncorrected %d", 644 "ecc error count corrected: %d, uncorrected %d",
645 g->ecc.eng.t19x.mmu_hubtlb_corrected_err_count.counters[0], 645 g->ecc.fb.mmu_hubtlb_corrected_err_count.counters[0],
646 g->ecc.eng.t19x.mmu_hubtlb_uncorrected_err_count.counters[0]); 646 g->ecc.fb.mmu_hubtlb_uncorrected_err_count.counters[0]);
647} 647}
648 648
649static void gv11b_handle_fillunit_ecc_isr(struct gk20a *g, u32 ecc_status) 649static void gv11b_handle_fillunit_ecc_isr(struct gk20a *g, u32 ecc_status)
@@ -684,9 +684,9 @@ static void gv11b_handle_fillunit_ecc_isr(struct gk20a *g, u32 ecc_status)
684 uncorrected_delta += (0x1UL << fb_mmu_fillunit_ecc_uncorrected_err_count_total_s()); 684 uncorrected_delta += (0x1UL << fb_mmu_fillunit_ecc_uncorrected_err_count_total_s());
685 685
686 686
687 g->ecc.eng.t19x.mmu_fillunit_corrected_err_count.counters[0] += 687 g->ecc.fb.mmu_fillunit_corrected_err_count.counters[0] +=
688 corrected_delta; 688 corrected_delta;
689 g->ecc.eng.t19x.mmu_fillunit_uncorrected_err_count.counters[0] += 689 g->ecc.fb.mmu_fillunit_uncorrected_err_count.counters[0] +=
690 uncorrected_delta; 690 uncorrected_delta;
691 691
692 if (ecc_status & fb_mmu_fillunit_ecc_status_corrected_err_pte_data_m()) 692 if (ecc_status & fb_mmu_fillunit_ecc_status_corrected_err_pte_data_m())
@@ -705,8 +705,8 @@ static void gv11b_handle_fillunit_ecc_isr(struct gk20a *g, u32 ecc_status)
705 "ecc error address: 0x%x", ecc_addr); 705 "ecc error address: 0x%x", ecc_addr);
706 nvgpu_log(g, gpu_dbg_intr, 706 nvgpu_log(g, gpu_dbg_intr,
707 "ecc error count corrected: %d, uncorrected %d", 707 "ecc error count corrected: %d, uncorrected %d",
708 g->ecc.eng.t19x.mmu_fillunit_corrected_err_count.counters[0], 708 g->ecc.fb.mmu_fillunit_corrected_err_count.counters[0],
709 g->ecc.eng.t19x.mmu_fillunit_uncorrected_err_count.counters[0]); 709 g->ecc.fb.mmu_fillunit_uncorrected_err_count.counters[0]);
710} 710}
711 711
712static void gv11b_fb_parse_mmfault(struct mmu_fault_info *mmfault) 712static void gv11b_fb_parse_mmfault(struct mmu_fault_info *mmfault)
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
index 7d3c5c75..271dcc41 100644
--- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
@@ -30,10 +30,11 @@
30#include <nvgpu/gmmu.h> 30#include <nvgpu/gmmu.h>
31#include <nvgpu/soc.h> 31#include <nvgpu/soc.h>
32#include <nvgpu/debug.h> 32#include <nvgpu/debug.h>
33#include <nvgpu/nvhost_t19x.h> 33#include <nvgpu/nvhost.h>
34#include <nvgpu/barrier.h> 34#include <nvgpu/barrier.h>
35#include <nvgpu/mm.h> 35#include <nvgpu/mm.h>
36#include <nvgpu/ctxsw_trace.h> 36#include <nvgpu/ctxsw_trace.h>
37#include <nvgpu/io_usermode.h>
37 38
38#include "gk20a/gk20a.h" 39#include "gk20a/gk20a.h"
39#include "gk20a/fifo_gk20a.h" 40#include "gk20a/fifo_gk20a.h"
@@ -96,7 +97,7 @@ void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist)
96 /* Time being use 0 pbdma sequencer */ 97 /* Time being use 0 pbdma sequencer */
97 runlist_entry = ram_rl_entry_type_channel_v() | 98 runlist_entry = ram_rl_entry_type_channel_v() |
98 ram_rl_entry_chan_runqueue_selector_f( 99 ram_rl_entry_chan_runqueue_selector_f(
99 c->t19x.runqueue_sel) | 100 c->runqueue_sel) |
100 ram_rl_entry_chan_userd_target_f( 101 ram_rl_entry_chan_userd_target_f(
101 nvgpu_aperture_mask(g, &g->fifo.userd, 102 nvgpu_aperture_mask(g, &g->fifo.userd,
102 ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(), 103 ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(),
@@ -185,7 +186,7 @@ int channel_gv11b_setup_ramfc(struct channel_gk20a *c,
185 nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->chid)); 186 nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->chid));
186 187
187 nvgpu_mem_wr32(g, mem, ram_fc_set_channel_info_w(), 188 nvgpu_mem_wr32(g, mem, ram_fc_set_channel_info_w(),
188 pbdma_set_channel_info_veid_f(c->t19x.subctx_id)); 189 pbdma_set_channel_info_veid_f(c->subctx_id));
189 190
190 gv11b_fifo_init_ramfc_eng_method_buffer(g, c, mem); 191 gv11b_fifo_init_ramfc_eng_method_buffer(g, c, mem);
191 192
@@ -215,7 +216,7 @@ static void gv11b_ring_channel_doorbell(struct channel_gk20a *c)
215 216
216 gk20a_dbg_info("channel ring door bell %d\n", c->chid); 217 gk20a_dbg_info("channel ring door bell %d\n", c->chid);
217 218
218 gv11b_usermode_writel(c->g, usermode_notify_channel_pending_r(), 219 nvgpu_usermode_writel(c->g, usermode_notify_channel_pending_r(),
219 usermode_notify_channel_pending_id_f(hw_chid)); 220 usermode_notify_channel_pending_id_f(hw_chid));
220} 221}
221 222
@@ -1782,8 +1783,7 @@ int gv11b_init_fifo_setup_hw(struct gk20a *g)
1782{ 1783{
1783 struct fifo_gk20a *f = &g->fifo; 1784 struct fifo_gk20a *f = &g->fifo;
1784 1785
1785 f->t19x.max_subctx_count = 1786 f->max_subctx_count = gr_pri_fe_chip_def_info_max_veid_count_init_v();
1786 gr_pri_fe_chip_def_info_max_veid_count_init_v();
1787 return 0; 1787 return 0;
1788} 1788}
1789 1789
@@ -1794,7 +1794,7 @@ static u32 gv11b_mmu_fault_id_to_gr_veid(struct gk20a *g, u32 gr_eng_fault_id,
1794 u32 num_subctx; 1794 u32 num_subctx;
1795 u32 veid = FIFO_INVAL_VEID; 1795 u32 veid = FIFO_INVAL_VEID;
1796 1796
1797 num_subctx = f->t19x.max_subctx_count; 1797 num_subctx = f->max_subctx_count;
1798 1798
1799 if (mmu_fault_id >= gr_eng_fault_id && 1799 if (mmu_fault_id >= gr_eng_fault_id &&
1800 mmu_fault_id < (gr_eng_fault_id + num_subctx)) 1800 mmu_fault_id < (gr_eng_fault_id + num_subctx))
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 9c79b29b..7288284e 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -189,7 +189,7 @@ static int gr_gv11b_handle_l1_tag_exception(struct gk20a *g, u32 gpc, u32 tpc,
189 l1_tag_corrected_err_count_delta += 189 l1_tag_corrected_err_count_delta +=
190 (is_l1_tag_ecc_corrected_total_err_overflow << 190 (is_l1_tag_ecc_corrected_total_err_overflow <<
191 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_s()); 191 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_s());
192 g->ecc.gr.t19x.sm_l1_tag_corrected_err_count.counters[tpc] += 192 g->ecc.gr.sm_l1_tag_corrected_err_count.counters[tpc] +=
193 l1_tag_corrected_err_count_delta; 193 l1_tag_corrected_err_count_delta;
194 gk20a_writel(g, 194 gk20a_writel(g,
195 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_r() + offset, 195 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_r() + offset,
@@ -204,7 +204,7 @@ static int gr_gv11b_handle_l1_tag_exception(struct gk20a *g, u32 gpc, u32 tpc,
204 l1_tag_uncorrected_err_count_delta += 204 l1_tag_uncorrected_err_count_delta +=
205 (is_l1_tag_ecc_uncorrected_total_err_overflow << 205 (is_l1_tag_ecc_uncorrected_total_err_overflow <<
206 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_s()); 206 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_s());
207 g->ecc.gr.t19x.sm_l1_tag_uncorrected_err_count.counters[tpc] += 207 g->ecc.gr.sm_l1_tag_uncorrected_err_count.counters[tpc] +=
208 l1_tag_uncorrected_err_count_delta; 208 l1_tag_uncorrected_err_count_delta;
209 gk20a_writel(g, 209 gk20a_writel(g,
210 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_r() + offset, 210 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_r() + offset,
@@ -399,7 +399,7 @@ static int gr_gv11b_handle_cbu_exception(struct gk20a *g, u32 gpc, u32 tpc,
399 cbu_corrected_err_count_delta += 399 cbu_corrected_err_count_delta +=
400 (is_cbu_ecc_corrected_total_err_overflow << 400 (is_cbu_ecc_corrected_total_err_overflow <<
401 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s()); 401 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s());
402 g->ecc.gr.t19x.sm_cbu_corrected_err_count.counters[tpc] += 402 g->ecc.gr.sm_cbu_corrected_err_count.counters[tpc] +=
403 cbu_corrected_err_count_delta; 403 cbu_corrected_err_count_delta;
404 gk20a_writel(g, 404 gk20a_writel(g,
405 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r() + offset, 405 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r() + offset,
@@ -414,7 +414,7 @@ static int gr_gv11b_handle_cbu_exception(struct gk20a *g, u32 gpc, u32 tpc,
414 cbu_uncorrected_err_count_delta += 414 cbu_uncorrected_err_count_delta +=
415 (is_cbu_ecc_uncorrected_total_err_overflow << 415 (is_cbu_ecc_uncorrected_total_err_overflow <<
416 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s()); 416 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s());
417 g->ecc.gr.t19x.sm_cbu_uncorrected_err_count.counters[tpc] += 417 g->ecc.gr.sm_cbu_uncorrected_err_count.counters[tpc] +=
418 cbu_uncorrected_err_count_delta; 418 cbu_uncorrected_err_count_delta;
419 gk20a_writel(g, 419 gk20a_writel(g,
420 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r() + offset, 420 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r() + offset,
@@ -479,7 +479,7 @@ static int gr_gv11b_handle_l1_data_exception(struct gk20a *g, u32 gpc, u32 tpc,
479 l1_data_corrected_err_count_delta += 479 l1_data_corrected_err_count_delta +=
480 (is_l1_data_ecc_corrected_total_err_overflow << 480 (is_l1_data_ecc_corrected_total_err_overflow <<
481 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s()); 481 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s());
482 g->ecc.gr.t19x.sm_l1_data_corrected_err_count.counters[tpc] += 482 g->ecc.gr.sm_l1_data_corrected_err_count.counters[tpc] +=
483 l1_data_corrected_err_count_delta; 483 l1_data_corrected_err_count_delta;
484 gk20a_writel(g, 484 gk20a_writel(g,
485 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r() + offset, 485 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r() + offset,
@@ -494,7 +494,7 @@ static int gr_gv11b_handle_l1_data_exception(struct gk20a *g, u32 gpc, u32 tpc,
494 l1_data_uncorrected_err_count_delta += 494 l1_data_uncorrected_err_count_delta +=
495 (is_l1_data_ecc_uncorrected_total_err_overflow << 495 (is_l1_data_ecc_uncorrected_total_err_overflow <<
496 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s()); 496 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s());
497 g->ecc.gr.t19x.sm_l1_data_uncorrected_err_count.counters[tpc] += 497 g->ecc.gr.sm_l1_data_uncorrected_err_count.counters[tpc] +=
498 l1_data_uncorrected_err_count_delta; 498 l1_data_uncorrected_err_count_delta;
499 gk20a_writel(g, 499 gk20a_writel(g,
500 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r() + offset, 500 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r() + offset,
@@ -563,7 +563,7 @@ static int gr_gv11b_handle_icache_exception(struct gk20a *g, u32 gpc, u32 tpc,
563 icache_corrected_err_count_delta += 563 icache_corrected_err_count_delta +=
564 (is_icache_ecc_corrected_total_err_overflow << 564 (is_icache_ecc_corrected_total_err_overflow <<
565 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_s()); 565 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_s());
566 g->ecc.gr.t19x.sm_icache_corrected_err_count.counters[tpc] += 566 g->ecc.gr.sm_icache_corrected_err_count.counters[tpc] +=
567 icache_corrected_err_count_delta; 567 icache_corrected_err_count_delta;
568 gk20a_writel(g, 568 gk20a_writel(g,
569 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_r() + offset, 569 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_r() + offset,
@@ -578,7 +578,7 @@ static int gr_gv11b_handle_icache_exception(struct gk20a *g, u32 gpc, u32 tpc,
578 icache_uncorrected_err_count_delta += 578 icache_uncorrected_err_count_delta +=
579 (is_icache_ecc_uncorrected_total_err_overflow << 579 (is_icache_ecc_uncorrected_total_err_overflow <<
580 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_s()); 580 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_s());
581 g->ecc.gr.t19x.sm_icache_uncorrected_err_count.counters[tpc] += 581 g->ecc.gr.sm_icache_uncorrected_err_count.counters[tpc] +=
582 icache_uncorrected_err_count_delta; 582 icache_uncorrected_err_count_delta;
583 gk20a_writel(g, 583 gk20a_writel(g,
584 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_r() + offset, 584 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_r() + offset,
@@ -667,7 +667,7 @@ int gr_gv11b_handle_gcc_exception(struct gk20a *g, u32 gpc, u32 tpc,
667 gcc_l15_corrected_err_count_delta += 667 gcc_l15_corrected_err_count_delta +=
668 (is_gcc_l15_ecc_corrected_total_err_overflow << 668 (is_gcc_l15_ecc_corrected_total_err_overflow <<
669 gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_s()); 669 gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_s());
670 g->ecc.gr.t19x.gcc_l15_corrected_err_count.counters[gpc] += 670 g->ecc.gr.gcc_l15_corrected_err_count.counters[gpc] +=
671 gcc_l15_corrected_err_count_delta; 671 gcc_l15_corrected_err_count_delta;
672 gk20a_writel(g, 672 gk20a_writel(g,
673 gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_r() + offset, 673 gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_r() + offset,
@@ -682,7 +682,7 @@ int gr_gv11b_handle_gcc_exception(struct gk20a *g, u32 gpc, u32 tpc,
682 gcc_l15_uncorrected_err_count_delta += 682 gcc_l15_uncorrected_err_count_delta +=
683 (is_gcc_l15_ecc_uncorrected_total_err_overflow << 683 (is_gcc_l15_ecc_uncorrected_total_err_overflow <<
684 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_s()); 684 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_s());
685 g->ecc.gr.t19x.gcc_l15_uncorrected_err_count.counters[gpc] += 685 g->ecc.gr.gcc_l15_uncorrected_err_count.counters[gpc] +=
686 gcc_l15_uncorrected_err_count_delta; 686 gcc_l15_uncorrected_err_count_delta;
687 gk20a_writel(g, 687 gk20a_writel(g,
688 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_r() + offset, 688 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_r() + offset,
@@ -752,9 +752,9 @@ static int gr_gv11b_handle_gpcmmu_ecc_exception(struct gk20a *g, u32 gpc,
752 uncorrected_delta += (0x1UL << gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_s()); 752 uncorrected_delta += (0x1UL << gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_s());
753 753
754 754
755 g->ecc.gr.t19x.mmu_l1tlb_corrected_err_count.counters[gpc] += 755 g->ecc.gr.mmu_l1tlb_corrected_err_count.counters[gpc] +=
756 corrected_delta; 756 corrected_delta;
757 g->ecc.gr.t19x.mmu_l1tlb_uncorrected_err_count.counters[gpc] += 757 g->ecc.gr.mmu_l1tlb_uncorrected_err_count.counters[gpc] +=
758 uncorrected_delta; 758 uncorrected_delta;
759 nvgpu_log(g, gpu_dbg_intr, 759 nvgpu_log(g, gpu_dbg_intr,
760 "mmu l1tlb gpc:%d ecc interrupt intr: 0x%x", gpc, hww_esr); 760 "mmu l1tlb gpc:%d ecc interrupt intr: 0x%x", gpc, hww_esr);
@@ -774,8 +774,8 @@ static int gr_gv11b_handle_gpcmmu_ecc_exception(struct gk20a *g, u32 gpc,
774 "ecc error address: 0x%x", ecc_addr); 774 "ecc error address: 0x%x", ecc_addr);
775 nvgpu_log(g, gpu_dbg_intr, 775 nvgpu_log(g, gpu_dbg_intr,
776 "ecc error count corrected: %d, uncorrected %d", 776 "ecc error count corrected: %d, uncorrected %d",
777 g->ecc.gr.t19x.mmu_l1tlb_corrected_err_count.counters[gpc], 777 g->ecc.gr.mmu_l1tlb_corrected_err_count.counters[gpc],
778 g->ecc.gr.t19x.mmu_l1tlb_uncorrected_err_count.counters[gpc]); 778 g->ecc.gr.mmu_l1tlb_uncorrected_err_count.counters[gpc]);
779 779
780 return ret; 780 return ret;
781} 781}
@@ -830,9 +830,9 @@ static int gr_gv11b_handle_gpccs_ecc_exception(struct gk20a *g, u32 gpc,
830 gk20a_writel(g, gr_gpc0_gpccs_falcon_ecc_status_r() + offset, 830 gk20a_writel(g, gr_gpc0_gpccs_falcon_ecc_status_r() + offset,
831 gr_gpc0_gpccs_falcon_ecc_status_reset_task_f()); 831 gr_gpc0_gpccs_falcon_ecc_status_reset_task_f());
832 832
833 g->ecc.gr.t19x.gpccs_corrected_err_count.counters[gpc] += 833 g->ecc.gr.gpccs_corrected_err_count.counters[gpc] +=
834 corrected_delta; 834 corrected_delta;
835 g->ecc.gr.t19x.gpccs_uncorrected_err_count.counters[gpc] += 835 g->ecc.gr.gpccs_uncorrected_err_count.counters[gpc] +=
836 uncorrected_delta; 836 uncorrected_delta;
837 nvgpu_log(g, gpu_dbg_intr, 837 nvgpu_log(g, gpu_dbg_intr,
838 "gppcs gpc:%d ecc interrupt intr: 0x%x", gpc, hww_esr); 838 "gppcs gpc:%d ecc interrupt intr: 0x%x", gpc, hww_esr);
@@ -857,8 +857,8 @@ static int gr_gv11b_handle_gpccs_ecc_exception(struct gk20a *g, u32 gpc,
857 857
858 nvgpu_log(g, gpu_dbg_intr, 858 nvgpu_log(g, gpu_dbg_intr,
859 "ecc error count corrected: %d, uncorrected %d", 859 "ecc error count corrected: %d, uncorrected %d",
860 g->ecc.gr.t19x.gpccs_corrected_err_count.counters[gpc], 860 g->ecc.gr.gpccs_corrected_err_count.counters[gpc],
861 g->ecc.gr.t19x.gpccs_uncorrected_err_count.counters[gpc]); 861 g->ecc.gr.gpccs_uncorrected_err_count.counters[gpc]);
862 862
863 return ret; 863 return ret;
864} 864}
@@ -2206,9 +2206,9 @@ static void gr_gv11b_handle_fecs_ecc_error(struct gk20a *g, u32 intr)
2206 gk20a_writel(g, gr_fecs_falcon_ecc_status_r(), 2206 gk20a_writel(g, gr_fecs_falcon_ecc_status_r(),
2207 gr_fecs_falcon_ecc_status_reset_task_f()); 2207 gr_fecs_falcon_ecc_status_reset_task_f());
2208 2208
2209 g->ecc.gr.t19x.fecs_corrected_err_count.counters[0] += 2209 g->ecc.gr.fecs_corrected_err_count.counters[0] +=
2210 corrected_delta; 2210 corrected_delta;
2211 g->ecc.gr.t19x.fecs_uncorrected_err_count.counters[0] += 2211 g->ecc.gr.fecs_uncorrected_err_count.counters[0] +=
2212 uncorrected_delta; 2212 uncorrected_delta;
2213 2213
2214 nvgpu_log(g, gpu_dbg_intr, 2214 nvgpu_log(g, gpu_dbg_intr,
@@ -2237,8 +2237,8 @@ static void gr_gv11b_handle_fecs_ecc_error(struct gk20a *g, u32 intr)
2237 2237
2238 nvgpu_log(g, gpu_dbg_intr, 2238 nvgpu_log(g, gpu_dbg_intr,
2239 "ecc error count corrected: %d, uncorrected %d", 2239 "ecc error count corrected: %d, uncorrected %d",
2240 g->ecc.gr.t19x.fecs_corrected_err_count.counters[0], 2240 g->ecc.gr.fecs_corrected_err_count.counters[0],
2241 g->ecc.gr.t19x.fecs_uncorrected_err_count.counters[0]); 2241 g->ecc.gr.fecs_uncorrected_err_count.counters[0]);
2242 } 2242 }
2243} 2243}
2244 2244
@@ -2323,7 +2323,7 @@ static int gv11b_write_bundle_veid_state(struct gk20a *g, u32 index)
2323 u32 j; 2323 u32 j;
2324 u32 num_subctx, err = 0; 2324 u32 num_subctx, err = 0;
2325 2325
2326 num_subctx = g->fifo.t19x.max_subctx_count; 2326 num_subctx = g->fifo.max_subctx_count;
2327 2327
2328 for (j = 0; j < num_subctx; j++) { 2328 for (j = 0; j < num_subctx; j++) {
2329 nvgpu_log_fn(g, "write bundle_address_r for subctx: %d", j); 2329 nvgpu_log_fn(g, "write bundle_address_r for subctx: %d", j);
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
index f8f80df3..774afe56 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
@@ -34,12 +34,6 @@
34#define ZBC_STENCIL_CLEAR_FMT_INVAILD 0 34#define ZBC_STENCIL_CLEAR_FMT_INVAILD 0
35#define ZBC_STENCIL_CLEAR_FMT_U8 1 35#define ZBC_STENCIL_CLEAR_FMT_U8 1
36 36
37struct zbc_s_table {
38 u32 stencil;
39 u32 format;
40 u32 ref_cnt;
41};
42
43struct gk20a; 37struct gk20a;
44struct gr_gk20a; 38struct gr_gk20a;
45struct zbc_entry; 39struct zbc_entry;
diff --git a/drivers/gpu/nvgpu/gv11b/gv11b.c b/drivers/gpu/nvgpu/gv11b/gv11b.c
index a62e49fb..709f18df 100644
--- a/drivers/gpu/nvgpu/gv11b/gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gv11b.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GV11B Graphics 2 * GV11B Graphics
3 * 3 *
4 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -23,7 +23,6 @@
23 */ 23 */
24 24
25#include <nvgpu/enabled.h> 25#include <nvgpu/enabled.h>
26#include <nvgpu/enabled_t19x.h>
27 26
28#include "gk20a/gk20a.h" 27#include "gk20a/gk20a.h"
29#include "gp10b/gp10b.h" 28#include "gp10b/gp10b.h"
diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c
index 8661b420..a596c3b2 100644
--- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GV11B LTC 2 * GV11B LTC
3 * 3 *
4 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -177,9 +177,9 @@ void gv11b_ltc_isr(struct gk20a *g)
177 } 177 }
178 178
179 } 179 }
180 g->ecc.ltc.t19x.l2_cache_corrected_err_count.counters[ltc] += 180 g->ecc.ltc.l2_cache_corrected_err_count.counters[ltc] +=
181 ltc_corrected; 181 ltc_corrected;
182 g->ecc.ltc.t19x.l2_cache_uncorrected_err_count.counters[ltc] += 182 g->ecc.ltc.l2_cache_uncorrected_err_count.counters[ltc] +=
183 ltc_uncorrected; 183 ltc_uncorrected;
184 184
185 } 185 }
diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c
index fdc506ac..943ae22a 100644
--- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GV11B MMU 2 * GV11B MMU
3 * 3 *
4 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -273,7 +273,7 @@ void gv11b_mm_l2_flush(struct gk20a *g, bool invalidate)
273u64 gv11b_gpu_phys_addr(struct gk20a *g, 273u64 gv11b_gpu_phys_addr(struct gk20a *g,
274 struct nvgpu_gmmu_attrs *attrs, u64 phys) 274 struct nvgpu_gmmu_attrs *attrs, u64 phys)
275{ 275{
276 if (attrs && attrs->t19x_attrs.l3_alloc) 276 if (attrs && attrs->l3_alloc)
277 return phys | NVGPU_L3_ALLOC_BIT; 277 return phys | NVGPU_L3_ALLOC_BIT;
278 278
279 return phys; 279 return phys;
diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c
index a972510f..e4cfe925 100644
--- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GV11B PMU 2 * GV11B PMU
3 * 3 *
4 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -343,8 +343,8 @@ void gv11b_pmu_handle_ext_irq(struct gk20a *g, u32 intr0)
343 if (uncorrected_overflow) 343 if (uncorrected_overflow)
344 uncorrected_delta += (0x1UL << pwr_pmu_falcon_ecc_uncorrected_err_count_total_s()); 344 uncorrected_delta += (0x1UL << pwr_pmu_falcon_ecc_uncorrected_err_count_total_s());
345 345
346 g->ecc.eng.t19x.pmu_corrected_err_count.counters[0] += corrected_delta; 346 g->ecc.pmu.pmu_corrected_err_count.counters[0] += corrected_delta;
347 g->ecc.eng.t19x.pmu_uncorrected_err_count.counters[0] += uncorrected_delta; 347 g->ecc.pmu.pmu_uncorrected_err_count.counters[0] += uncorrected_delta;
348 348
349 nvgpu_log(g, gpu_dbg_intr, 349 nvgpu_log(g, gpu_dbg_intr,
350 "pmu ecc interrupt intr1: 0x%x", intr1); 350 "pmu ecc interrupt intr1: 0x%x", intr1);
@@ -371,8 +371,8 @@ void gv11b_pmu_handle_ext_irq(struct gk20a *g, u32 intr0)
371 371
372 nvgpu_log(g, gpu_dbg_intr, 372 nvgpu_log(g, gpu_dbg_intr,
373 "ecc error count corrected: %d, uncorrected %d", 373 "ecc error count corrected: %d, uncorrected %d",
374 g->ecc.eng.t19x.pmu_corrected_err_count.counters[0], 374 g->ecc.pmu.pmu_corrected_err_count.counters[0],
375 g->ecc.eng.t19x.pmu_uncorrected_err_count.counters[0]); 375 g->ecc.pmu.pmu_uncorrected_err_count.counters[0]);
376 } 376 }
377 } 377 }
378} 378}
diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c
index 607fff91..4f98d82a 100644
--- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Volta GPU series Subcontext 2 * Volta GPU series Subcontext
3 * 3 *
4 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -103,9 +103,9 @@ static void gv11b_init_subcontext_pdb(struct channel_gk20a *c,
103 gv11b_subctx_commit_pdb(c, inst_block); 103 gv11b_subctx_commit_pdb(c, inst_block);
104 gv11b_subctx_commit_valid_mask(c, inst_block); 104 gv11b_subctx_commit_valid_mask(c, inst_block);
105 105
106 nvgpu_log(g, gpu_dbg_info, " subctx %d instblk set", c->t19x.subctx_id); 106 nvgpu_log(g, gpu_dbg_info, " subctx %d instblk set", c->subctx_id);
107 nvgpu_mem_wr32(g, inst_block, ram_in_engine_wfi_veid_w(), 107 nvgpu_mem_wr32(g, inst_block, ram_in_engine_wfi_veid_w(),
108 ram_in_engine_wfi_veid_f(c->t19x.subctx_id)); 108 ram_in_engine_wfi_veid_f(c->subctx_id));
109 109
110} 110}
111 111
@@ -206,7 +206,7 @@ void gv11b_subctx_commit_pdb(struct channel_gk20a *c,
206 ram_in_sc_page_dir_base_lo_0_f(pdb_addr_lo); 206 ram_in_sc_page_dir_base_lo_0_f(pdb_addr_lo);
207 nvgpu_log(g, gpu_dbg_info, " pdb info lo %x hi %x", 207 nvgpu_log(g, gpu_dbg_info, " pdb info lo %x hi %x",
208 format_word, pdb_addr_hi); 208 format_word, pdb_addr_hi);
209 for (subctx_id = 0; subctx_id < f->t19x.max_subctx_count; subctx_id++) { 209 for (subctx_id = 0; subctx_id < f->max_subctx_count; subctx_id++) {
210 lo = ram_in_sc_page_dir_base_vol_0_w() + (4 * subctx_id); 210 lo = ram_in_sc_page_dir_base_vol_0_w() + (4 * subctx_id);
211 hi = ram_in_sc_page_dir_base_hi_0_w() + (4 * subctx_id); 211 hi = ram_in_sc_page_dir_base_hi_0_w() + (4 * subctx_id);
212 nvgpu_mem_wr32(g, inst_block, lo, format_word); 212 nvgpu_mem_wr32(g, inst_block, lo, format_word);
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-15 23:46:08 -0400