From f3f14cdff53f4b936e2505d44aad6e3bca143056 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 17 Jan 2018 12:39:13 -0800 Subject: gpu: nvgpu: Fold T19x code back to main code paths Lots of code paths were split to T19x specific code paths and structs due to split repository. Now that repositories are merged, fold all of them back to main code paths and structs and remove the T19x specific Kconfig flag. Change-Id: Id0d17a5f0610fc0b49f51ab6664e716dc8b222b6 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1640606 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/ecc_gv11b.h | 66 ---------------------------------- drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 26 +++++++------- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 14 ++++---- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 46 ++++++++++++------------ drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 6 ---- drivers/gpu/nvgpu/gv11b/gv11b.c | 3 +- drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | 6 ++-- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 4 +-- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 10 +++--- drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 8 ++--- 10 files changed, 58 insertions(+), 131 deletions(-) delete mode 100644 drivers/gpu/nvgpu/gv11b/ecc_gv11b.h (limited to 'drivers/gpu/nvgpu/gv11b') diff --git a/drivers/gpu/nvgpu/gv11b/ecc_gv11b.h b/drivers/gpu/nvgpu/gv11b/ecc_gv11b.h deleted file mode 100644 index ebce46ce..00000000 --- a/drivers/gpu/nvgpu/gv11b/ecc_gv11b.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * GV11B GPU ECC - * - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef _NVGPU_ECC_GV11B_H_ -#define _NVGPU_ECC_GV11B_H_ - -struct ecc_gr_t19x { - struct gk20a_ecc_stat sm_l1_tag_corrected_err_count; - struct gk20a_ecc_stat sm_l1_tag_uncorrected_err_count; - struct gk20a_ecc_stat sm_cbu_corrected_err_count; - struct gk20a_ecc_stat sm_cbu_uncorrected_err_count; - struct gk20a_ecc_stat sm_l1_data_corrected_err_count; - struct gk20a_ecc_stat sm_l1_data_uncorrected_err_count; - struct gk20a_ecc_stat sm_icache_corrected_err_count; - struct gk20a_ecc_stat sm_icache_uncorrected_err_count; - struct gk20a_ecc_stat gcc_l15_corrected_err_count; - struct gk20a_ecc_stat gcc_l15_uncorrected_err_count; - struct gk20a_ecc_stat fecs_corrected_err_count; - struct gk20a_ecc_stat fecs_uncorrected_err_count; - struct gk20a_ecc_stat gpccs_corrected_err_count; - struct gk20a_ecc_stat gpccs_uncorrected_err_count; - struct gk20a_ecc_stat mmu_l1tlb_corrected_err_count; - struct gk20a_ecc_stat mmu_l1tlb_uncorrected_err_count; -}; - -struct ecc_ltc_t19x { - struct gk20a_ecc_stat l2_cache_corrected_err_count; - struct gk20a_ecc_stat l2_cache_uncorrected_err_count; -}; - -/* TODO: PMU and FB ECC features are still under embargo */ -struct ecc_eng_t19x { - /* FB */ - struct gk20a_ecc_stat mmu_l2tlb_corrected_err_count; - struct gk20a_ecc_stat mmu_l2tlb_uncorrected_err_count; - struct gk20a_ecc_stat mmu_hubtlb_corrected_err_count; - struct gk20a_ecc_stat mmu_hubtlb_uncorrected_err_count; - struct gk20a_ecc_stat mmu_fillunit_corrected_err_count; - struct gk20a_ecc_stat mmu_fillunit_uncorrected_err_count; - /* PMU */ - struct gk20a_ecc_stat pmu_corrected_err_count; - struct gk20a_ecc_stat pmu_uncorrected_err_count; -}; - -#endif diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index 8ac3cb7b..b7a0a3cf 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -1,7 +1,7 @@ /* * GV11B FB * - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -568,9 +568,9 @@ static void gv11b_handle_l2tlb_ecc_isr(struct gk20a *g, u32 ecc_status) uncorrected_delta += (0x1UL << fb_mmu_l2tlb_ecc_uncorrected_err_count_total_s()); - g->ecc.eng.t19x.mmu_l2tlb_corrected_err_count.counters[0] += + g->ecc.fb.mmu_l2tlb_corrected_err_count.counters[0] += corrected_delta; - g->ecc.eng.t19x.mmu_l2tlb_uncorrected_err_count.counters[0] += + g->ecc.fb.mmu_l2tlb_uncorrected_err_count.counters[0] += uncorrected_delta; if (ecc_status & fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb_sa_data_m()) @@ -584,8 +584,8 @@ static void gv11b_handle_l2tlb_ecc_isr(struct gk20a *g, u32 ecc_status) "ecc error address: 0x%x", ecc_addr); nvgpu_log(g, gpu_dbg_intr, "ecc error count corrected: %d, uncorrected %d", - g->ecc.eng.t19x.mmu_l2tlb_corrected_err_count.counters[0], - g->ecc.eng.t19x.mmu_l2tlb_uncorrected_err_count.counters[0]); + g->ecc.fb.mmu_l2tlb_corrected_err_count.counters[0], + g->ecc.fb.mmu_l2tlb_uncorrected_err_count.counters[0]); } static void gv11b_handle_hubtlb_ecc_isr(struct gk20a *g, u32 ecc_status) @@ -626,9 +626,9 @@ static void gv11b_handle_hubtlb_ecc_isr(struct gk20a *g, u32 ecc_status) uncorrected_delta += (0x1UL << fb_mmu_hubtlb_ecc_uncorrected_err_count_total_s()); - g->ecc.eng.t19x.mmu_hubtlb_corrected_err_count.counters[0] += + g->ecc.fb.mmu_hubtlb_corrected_err_count.counters[0] += corrected_delta; - g->ecc.eng.t19x.mmu_hubtlb_uncorrected_err_count.counters[0] += + g->ecc.fb.mmu_hubtlb_uncorrected_err_count.counters[0] += uncorrected_delta; if (ecc_status & fb_mmu_hubtlb_ecc_status_corrected_err_sa_data_m()) @@ -642,8 +642,8 @@ static void gv11b_handle_hubtlb_ecc_isr(struct gk20a *g, u32 ecc_status) "ecc error address: 0x%x", ecc_addr); nvgpu_log(g, gpu_dbg_intr, "ecc error count corrected: %d, uncorrected %d", - g->ecc.eng.t19x.mmu_hubtlb_corrected_err_count.counters[0], - g->ecc.eng.t19x.mmu_hubtlb_uncorrected_err_count.counters[0]); + g->ecc.fb.mmu_hubtlb_corrected_err_count.counters[0], + g->ecc.fb.mmu_hubtlb_uncorrected_err_count.counters[0]); } static void gv11b_handle_fillunit_ecc_isr(struct gk20a *g, u32 ecc_status) @@ -684,9 +684,9 @@ static void gv11b_handle_fillunit_ecc_isr(struct gk20a *g, u32 ecc_status) uncorrected_delta += (0x1UL << fb_mmu_fillunit_ecc_uncorrected_err_count_total_s()); - g->ecc.eng.t19x.mmu_fillunit_corrected_err_count.counters[0] += + g->ecc.fb.mmu_fillunit_corrected_err_count.counters[0] += corrected_delta; - g->ecc.eng.t19x.mmu_fillunit_uncorrected_err_count.counters[0] += + g->ecc.fb.mmu_fillunit_uncorrected_err_count.counters[0] += uncorrected_delta; if (ecc_status & fb_mmu_fillunit_ecc_status_corrected_err_pte_data_m()) @@ -705,8 +705,8 @@ static void gv11b_handle_fillunit_ecc_isr(struct gk20a *g, u32 ecc_status) "ecc error address: 0x%x", ecc_addr); nvgpu_log(g, gpu_dbg_intr, "ecc error count corrected: %d, uncorrected %d", - g->ecc.eng.t19x.mmu_fillunit_corrected_err_count.counters[0], - g->ecc.eng.t19x.mmu_fillunit_uncorrected_err_count.counters[0]); + g->ecc.fb.mmu_fillunit_corrected_err_count.counters[0], + g->ecc.fb.mmu_fillunit_uncorrected_err_count.counters[0]); } static void gv11b_fb_parse_mmfault(struct mmu_fault_info *mmfault) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 7d3c5c75..271dcc41 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -30,10 +30,11 @@ #include #include #include -#include +#include #include #include #include +#include #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" @@ -96,7 +97,7 @@ void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist) /* Time being use 0 pbdma sequencer */ runlist_entry = ram_rl_entry_type_channel_v() | ram_rl_entry_chan_runqueue_selector_f( - c->t19x.runqueue_sel) | + c->runqueue_sel) | ram_rl_entry_chan_userd_target_f( nvgpu_aperture_mask(g, &g->fifo.userd, ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(), @@ -185,7 +186,7 @@ int channel_gv11b_setup_ramfc(struct channel_gk20a *c, nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->chid)); nvgpu_mem_wr32(g, mem, ram_fc_set_channel_info_w(), - pbdma_set_channel_info_veid_f(c->t19x.subctx_id)); + pbdma_set_channel_info_veid_f(c->subctx_id)); gv11b_fifo_init_ramfc_eng_method_buffer(g, c, mem); @@ -215,7 +216,7 @@ static void gv11b_ring_channel_doorbell(struct channel_gk20a *c) gk20a_dbg_info("channel ring door bell %d\n", c->chid); - gv11b_usermode_writel(c->g, usermode_notify_channel_pending_r(), + nvgpu_usermode_writel(c->g, usermode_notify_channel_pending_r(), usermode_notify_channel_pending_id_f(hw_chid)); } @@ -1782,8 +1783,7 @@ int gv11b_init_fifo_setup_hw(struct gk20a *g) { struct fifo_gk20a *f = &g->fifo; - f->t19x.max_subctx_count = - gr_pri_fe_chip_def_info_max_veid_count_init_v(); + f->max_subctx_count = gr_pri_fe_chip_def_info_max_veid_count_init_v(); return 0; } @@ -1794,7 +1794,7 @@ static u32 gv11b_mmu_fault_id_to_gr_veid(struct gk20a *g, u32 gr_eng_fault_id, u32 num_subctx; u32 veid = FIFO_INVAL_VEID; - num_subctx = f->t19x.max_subctx_count; + num_subctx = f->max_subctx_count; if (mmu_fault_id >= gr_eng_fault_id && mmu_fault_id < (gr_eng_fault_id + num_subctx)) diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 9c79b29b..7288284e 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -189,7 +189,7 @@ static int gr_gv11b_handle_l1_tag_exception(struct gk20a *g, u32 gpc, u32 tpc, l1_tag_corrected_err_count_delta += (is_l1_tag_ecc_corrected_total_err_overflow << gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_s()); - g->ecc.gr.t19x.sm_l1_tag_corrected_err_count.counters[tpc] += + g->ecc.gr.sm_l1_tag_corrected_err_count.counters[tpc] += l1_tag_corrected_err_count_delta; gk20a_writel(g, gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_r() + offset, @@ -204,7 +204,7 @@ static int gr_gv11b_handle_l1_tag_exception(struct gk20a *g, u32 gpc, u32 tpc, l1_tag_uncorrected_err_count_delta += (is_l1_tag_ecc_uncorrected_total_err_overflow << gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_s()); - g->ecc.gr.t19x.sm_l1_tag_uncorrected_err_count.counters[tpc] += + g->ecc.gr.sm_l1_tag_uncorrected_err_count.counters[tpc] += l1_tag_uncorrected_err_count_delta; gk20a_writel(g, gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_r() + offset, @@ -399,7 +399,7 @@ static int gr_gv11b_handle_cbu_exception(struct gk20a *g, u32 gpc, u32 tpc, cbu_corrected_err_count_delta += (is_cbu_ecc_corrected_total_err_overflow << gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s()); - g->ecc.gr.t19x.sm_cbu_corrected_err_count.counters[tpc] += + g->ecc.gr.sm_cbu_corrected_err_count.counters[tpc] += cbu_corrected_err_count_delta; gk20a_writel(g, gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r() + offset, @@ -414,7 +414,7 @@ static int gr_gv11b_handle_cbu_exception(struct gk20a *g, u32 gpc, u32 tpc, cbu_uncorrected_err_count_delta += (is_cbu_ecc_uncorrected_total_err_overflow << gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s()); - g->ecc.gr.t19x.sm_cbu_uncorrected_err_count.counters[tpc] += + g->ecc.gr.sm_cbu_uncorrected_err_count.counters[tpc] += cbu_uncorrected_err_count_delta; gk20a_writel(g, gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r() + offset, @@ -479,7 +479,7 @@ static int gr_gv11b_handle_l1_data_exception(struct gk20a *g, u32 gpc, u32 tpc, l1_data_corrected_err_count_delta += (is_l1_data_ecc_corrected_total_err_overflow << gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s()); - g->ecc.gr.t19x.sm_l1_data_corrected_err_count.counters[tpc] += + g->ecc.gr.sm_l1_data_corrected_err_count.counters[tpc] += l1_data_corrected_err_count_delta; gk20a_writel(g, gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r() + offset, @@ -494,7 +494,7 @@ static int gr_gv11b_handle_l1_data_exception(struct gk20a *g, u32 gpc, u32 tpc, l1_data_uncorrected_err_count_delta += (is_l1_data_ecc_uncorrected_total_err_overflow << gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s()); - g->ecc.gr.t19x.sm_l1_data_uncorrected_err_count.counters[tpc] += + g->ecc.gr.sm_l1_data_uncorrected_err_count.counters[tpc] += l1_data_uncorrected_err_count_delta; gk20a_writel(g, gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r() + offset, @@ -563,7 +563,7 @@ static int gr_gv11b_handle_icache_exception(struct gk20a *g, u32 gpc, u32 tpc, icache_corrected_err_count_delta += (is_icache_ecc_corrected_total_err_overflow << gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_s()); - g->ecc.gr.t19x.sm_icache_corrected_err_count.counters[tpc] += + g->ecc.gr.sm_icache_corrected_err_count.counters[tpc] += icache_corrected_err_count_delta; gk20a_writel(g, gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_r() + offset, @@ -578,7 +578,7 @@ static int gr_gv11b_handle_icache_exception(struct gk20a *g, u32 gpc, u32 tpc, icache_uncorrected_err_count_delta += (is_icache_ecc_uncorrected_total_err_overflow << gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_s()); - g->ecc.gr.t19x.sm_icache_uncorrected_err_count.counters[tpc] += + g->ecc.gr.sm_icache_uncorrected_err_count.counters[tpc] += icache_uncorrected_err_count_delta; gk20a_writel(g, gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_r() + offset, @@ -667,7 +667,7 @@ int gr_gv11b_handle_gcc_exception(struct gk20a *g, u32 gpc, u32 tpc, gcc_l15_corrected_err_count_delta += (is_gcc_l15_ecc_corrected_total_err_overflow << gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_s()); - g->ecc.gr.t19x.gcc_l15_corrected_err_count.counters[gpc] += + g->ecc.gr.gcc_l15_corrected_err_count.counters[gpc] += gcc_l15_corrected_err_count_delta; gk20a_writel(g, gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_r() + offset, @@ -682,7 +682,7 @@ int gr_gv11b_handle_gcc_exception(struct gk20a *g, u32 gpc, u32 tpc, gcc_l15_uncorrected_err_count_delta += (is_gcc_l15_ecc_uncorrected_total_err_overflow << gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_s()); - g->ecc.gr.t19x.gcc_l15_uncorrected_err_count.counters[gpc] += + g->ecc.gr.gcc_l15_uncorrected_err_count.counters[gpc] += gcc_l15_uncorrected_err_count_delta; gk20a_writel(g, gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_r() + offset, @@ -752,9 +752,9 @@ static int gr_gv11b_handle_gpcmmu_ecc_exception(struct gk20a *g, u32 gpc, uncorrected_delta += (0x1UL << gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_s()); - g->ecc.gr.t19x.mmu_l1tlb_corrected_err_count.counters[gpc] += + g->ecc.gr.mmu_l1tlb_corrected_err_count.counters[gpc] += corrected_delta; - g->ecc.gr.t19x.mmu_l1tlb_uncorrected_err_count.counters[gpc] += + g->ecc.gr.mmu_l1tlb_uncorrected_err_count.counters[gpc] += uncorrected_delta; nvgpu_log(g, gpu_dbg_intr, "mmu l1tlb gpc:%d ecc interrupt intr: 0x%x", gpc, hww_esr); @@ -774,8 +774,8 @@ static int gr_gv11b_handle_gpcmmu_ecc_exception(struct gk20a *g, u32 gpc, "ecc error address: 0x%x", ecc_addr); nvgpu_log(g, gpu_dbg_intr, "ecc error count corrected: %d, uncorrected %d", - g->ecc.gr.t19x.mmu_l1tlb_corrected_err_count.counters[gpc], - g->ecc.gr.t19x.mmu_l1tlb_uncorrected_err_count.counters[gpc]); + g->ecc.gr.mmu_l1tlb_corrected_err_count.counters[gpc], + g->ecc.gr.mmu_l1tlb_uncorrected_err_count.counters[gpc]); return ret; } @@ -830,9 +830,9 @@ static int gr_gv11b_handle_gpccs_ecc_exception(struct gk20a *g, u32 gpc, gk20a_writel(g, gr_gpc0_gpccs_falcon_ecc_status_r() + offset, gr_gpc0_gpccs_falcon_ecc_status_reset_task_f()); - g->ecc.gr.t19x.gpccs_corrected_err_count.counters[gpc] += + g->ecc.gr.gpccs_corrected_err_count.counters[gpc] += corrected_delta; - g->ecc.gr.t19x.gpccs_uncorrected_err_count.counters[gpc] += + g->ecc.gr.gpccs_uncorrected_err_count.counters[gpc] += uncorrected_delta; nvgpu_log(g, gpu_dbg_intr, "gppcs gpc:%d ecc interrupt intr: 0x%x", gpc, hww_esr); @@ -857,8 +857,8 @@ static int gr_gv11b_handle_gpccs_ecc_exception(struct gk20a *g, u32 gpc, nvgpu_log(g, gpu_dbg_intr, "ecc error count corrected: %d, uncorrected %d", - g->ecc.gr.t19x.gpccs_corrected_err_count.counters[gpc], - g->ecc.gr.t19x.gpccs_uncorrected_err_count.counters[gpc]); + g->ecc.gr.gpccs_corrected_err_count.counters[gpc], + g->ecc.gr.gpccs_uncorrected_err_count.counters[gpc]); return ret; } @@ -2206,9 +2206,9 @@ static void gr_gv11b_handle_fecs_ecc_error(struct gk20a *g, u32 intr) gk20a_writel(g, gr_fecs_falcon_ecc_status_r(), gr_fecs_falcon_ecc_status_reset_task_f()); - g->ecc.gr.t19x.fecs_corrected_err_count.counters[0] += + g->ecc.gr.fecs_corrected_err_count.counters[0] += corrected_delta; - g->ecc.gr.t19x.fecs_uncorrected_err_count.counters[0] += + g->ecc.gr.fecs_uncorrected_err_count.counters[0] += uncorrected_delta; nvgpu_log(g, gpu_dbg_intr, @@ -2237,8 +2237,8 @@ static void gr_gv11b_handle_fecs_ecc_error(struct gk20a *g, u32 intr) nvgpu_log(g, gpu_dbg_intr, "ecc error count corrected: %d, uncorrected %d", - g->ecc.gr.t19x.fecs_corrected_err_count.counters[0], - g->ecc.gr.t19x.fecs_uncorrected_err_count.counters[0]); + g->ecc.gr.fecs_corrected_err_count.counters[0], + g->ecc.gr.fecs_uncorrected_err_count.counters[0]); } } @@ -2323,7 +2323,7 @@ static int gv11b_write_bundle_veid_state(struct gk20a *g, u32 index) u32 j; u32 num_subctx, err = 0; - num_subctx = g->fifo.t19x.max_subctx_count; + num_subctx = g->fifo.max_subctx_count; for (j = 0; j < num_subctx; j++) { nvgpu_log_fn(g, "write bundle_address_r for subctx: %d", j); diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index f8f80df3..774afe56 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -34,12 +34,6 @@ #define ZBC_STENCIL_CLEAR_FMT_INVAILD 0 #define ZBC_STENCIL_CLEAR_FMT_U8 1 -struct zbc_s_table { - u32 stencil; - u32 format; - u32 ref_cnt; -}; - struct gk20a; struct gr_gk20a; struct zbc_entry; diff --git a/drivers/gpu/nvgpu/gv11b/gv11b.c b/drivers/gpu/nvgpu/gv11b/gv11b.c index a62e49fb..709f18df 100644 --- a/drivers/gpu/nvgpu/gv11b/gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gv11b.c @@ -1,7 +1,7 @@ /* * GV11B Graphics * - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -23,7 +23,6 @@ */ #include -#include #include "gk20a/gk20a.h" #include "gp10b/gp10b.h" diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c index 8661b420..a596c3b2 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c @@ -1,7 +1,7 @@ /* * GV11B LTC * - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -177,9 +177,9 @@ void gv11b_ltc_isr(struct gk20a *g) } } - g->ecc.ltc.t19x.l2_cache_corrected_err_count.counters[ltc] += + g->ecc.ltc.l2_cache_corrected_err_count.counters[ltc] += ltc_corrected; - g->ecc.ltc.t19x.l2_cache_uncorrected_err_count.counters[ltc] += + g->ecc.ltc.l2_cache_uncorrected_err_count.counters[ltc] += ltc_uncorrected; } diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index fdc506ac..943ae22a 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -1,7 +1,7 @@ /* * GV11B MMU * - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -273,7 +273,7 @@ void gv11b_mm_l2_flush(struct gk20a *g, bool invalidate) u64 gv11b_gpu_phys_addr(struct gk20a *g, struct nvgpu_gmmu_attrs *attrs, u64 phys) { - if (attrs && attrs->t19x_attrs.l3_alloc) + if (attrs && attrs->l3_alloc) return phys | NVGPU_L3_ALLOC_BIT; return phys; diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index a972510f..e4cfe925 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -1,7 +1,7 @@ /* * GV11B PMU * - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -343,8 +343,8 @@ void gv11b_pmu_handle_ext_irq(struct gk20a *g, u32 intr0) if (uncorrected_overflow) uncorrected_delta += (0x1UL << pwr_pmu_falcon_ecc_uncorrected_err_count_total_s()); - g->ecc.eng.t19x.pmu_corrected_err_count.counters[0] += corrected_delta; - g->ecc.eng.t19x.pmu_uncorrected_err_count.counters[0] += uncorrected_delta; + g->ecc.pmu.pmu_corrected_err_count.counters[0] += corrected_delta; + g->ecc.pmu.pmu_uncorrected_err_count.counters[0] += uncorrected_delta; nvgpu_log(g, gpu_dbg_intr, "pmu ecc interrupt intr1: 0x%x", intr1); @@ -371,8 +371,8 @@ void gv11b_pmu_handle_ext_irq(struct gk20a *g, u32 intr0) nvgpu_log(g, gpu_dbg_intr, "ecc error count corrected: %d, uncorrected %d", - g->ecc.eng.t19x.pmu_corrected_err_count.counters[0], - g->ecc.eng.t19x.pmu_uncorrected_err_count.counters[0]); + g->ecc.pmu.pmu_corrected_err_count.counters[0], + g->ecc.pmu.pmu_uncorrected_err_count.counters[0]); } } } diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 607fff91..4f98d82a 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c @@ -1,7 +1,7 @@ /* * Volta GPU series Subcontext * - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -103,9 +103,9 @@ static void gv11b_init_subcontext_pdb(struct channel_gk20a *c, gv11b_subctx_commit_pdb(c, inst_block); gv11b_subctx_commit_valid_mask(c, inst_block); - nvgpu_log(g, gpu_dbg_info, " subctx %d instblk set", c->t19x.subctx_id); + nvgpu_log(g, gpu_dbg_info, " subctx %d instblk set", c->subctx_id); nvgpu_mem_wr32(g, inst_block, ram_in_engine_wfi_veid_w(), - ram_in_engine_wfi_veid_f(c->t19x.subctx_id)); + ram_in_engine_wfi_veid_f(c->subctx_id)); } @@ -206,7 +206,7 @@ void gv11b_subctx_commit_pdb(struct channel_gk20a *c, ram_in_sc_page_dir_base_lo_0_f(pdb_addr_lo); nvgpu_log(g, gpu_dbg_info, " pdb info lo %x hi %x", format_word, pdb_addr_hi); - for (subctx_id = 0; subctx_id < f->t19x.max_subctx_count; subctx_id++) { + for (subctx_id = 0; subctx_id < f->max_subctx_count; subctx_id++) { lo = ram_in_sc_page_dir_base_vol_0_w() + (4 * subctx_id); hi = ram_in_sc_page_dir_base_hi_0_w() + (4 * subctx_id); nvgpu_mem_wr32(g, inst_block, lo, format_word); -- cgit v1.2.2