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authorAnup Mahindre <amahindre@nvidia.com>2018-09-07 11:28:44 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-10 18:25:27 -0400
commitc4ba8ee209835e6d1b95a07856805e090b72e981 (patch)
treedbbd87572af9b46b83ffe916a9f5bd2ba05f5f96 /drivers/gpu/nvgpu/gv11b
parentb8ae7eb029d46ef843ca4f048eb8a7d58ae5d8a8 (diff)
gpu: nvgpu: Fix vsm mapping used by gv11b_gr_set_sm_debug_mode
Mapping used by gv11b_gr_set_sm_debug_mode is inconsistent with mapping exposed via gk20a_ctrl_vsm_mapping as it doesn't consider non pes aware GPC/TPC to SM mapping. Bug 200448172 Change-Id: Id8a7208a779e577377464f632b819bc0cb228e92 Signed-off-by: Anup Mahindre <amahindre@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1816191 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b')
-rw-r--r--drivers/gpu/nvgpu/gv11b/gr_gv11b.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 450775b1..4f7468b3 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -3343,7 +3343,13 @@ int gv11b_gr_set_sm_debug_mode(struct gk20a *g,
3343 } 3343 }
3344 3344
3345 gpc = g->gr.sm_to_cluster[sm_id].gpc_index; 3345 gpc = g->gr.sm_to_cluster[sm_id].gpc_index;
3346 tpc = g->gr.sm_to_cluster[sm_id].tpc_index; 3346 if (g->ops.gr.get_nonpes_aware_tpc != NULL) {
3347 tpc = g->ops.gr.get_nonpes_aware_tpc(g,
3348 g->gr.sm_to_cluster[sm_id].gpc_index,
3349 g->gr.sm_to_cluster[sm_id].tpc_index);
3350 } else {
3351 tpc = g->gr.sm_to_cluster[sm_id].tpc_index;
3352 }
3347 sm = g->gr.sm_to_cluster[sm_id].sm_index; 3353 sm = g->gr.sm_to_cluster[sm_id].sm_index;
3348 3354
3349 reg_offset = gk20a_gr_gpc_offset(g, gpc) + 3355 reg_offset = gk20a_gr_gpc_offset(g, gpc) +