From c4ba8ee209835e6d1b95a07856805e090b72e981 Mon Sep 17 00:00:00 2001 From: Anup Mahindre Date: Fri, 7 Sep 2018 20:58:44 +0530 Subject: gpu: nvgpu: Fix vsm mapping used by gv11b_gr_set_sm_debug_mode Mapping used by gv11b_gr_set_sm_debug_mode is inconsistent with mapping exposed via gk20a_ctrl_vsm_mapping as it doesn't consider non pes aware GPC/TPC to SM mapping. Bug 200448172 Change-Id: Id8a7208a779e577377464f632b819bc0cb228e92 Signed-off-by: Anup Mahindre Reviewed-on: https://git-master.nvidia.com/r/1816191 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 450775b1..4f7468b3 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -3343,7 +3343,13 @@ int gv11b_gr_set_sm_debug_mode(struct gk20a *g, } gpc = g->gr.sm_to_cluster[sm_id].gpc_index; - tpc = g->gr.sm_to_cluster[sm_id].tpc_index; + if (g->ops.gr.get_nonpes_aware_tpc != NULL) { + tpc = g->ops.gr.get_nonpes_aware_tpc(g, + g->gr.sm_to_cluster[sm_id].gpc_index, + g->gr.sm_to_cluster[sm_id].tpc_index); + } else { + tpc = g->gr.sm_to_cluster[sm_id].tpc_index; + } sm = g->gr.sm_to_cluster[sm_id].sm_index; reg_offset = gk20a_gr_gpc_offset(g, gpc) + -- cgit v1.2.2