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authorAlex Waterman <alexw@nvidia.com>2018-02-21 18:59:56 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2018-02-24 00:53:38 -0500
commitb5d3cf444eeeb62a593365532b22e44f9360a484 (patch)
tree291b251e82bb469e3c8a823442d04c79ea786dbc /drivers/gpu/nvgpu/gv11b
parentbd95c2ce3f5c1bbb310d66350b33d8cc4a043073 (diff)
gpu: nvgpu: Cleanup unused variables
There are numerous places where variables are assigned to but then never used. This patch cleans up all these unused variables and in some cases simplifies surrounding logic. Also delete unused header includes and add necessary header includes. JIRA NVGPU-525 Signed-off-by: Alex Waterman <alexw@nvidia.com> Change-Id: Ice9ec2a0e97f262d0dcfebe22f83208dbea569d9 Reviewed-on: https://git-master.nvidia.com/r/1662548 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b')
-rw-r--r--drivers/gpu/nvgpu/gv11b/fifo_gv11b.c20
-rw-r--r--drivers/gpu/nvgpu/gv11b/pmu_gv11b.c4
2 files changed, 9 insertions, 15 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
index 8e9e1818..89f3f0b9 100644
--- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
@@ -33,6 +33,7 @@
33#include <nvgpu/nvhost.h> 33#include <nvgpu/nvhost.h>
34#include <nvgpu/barrier.h> 34#include <nvgpu/barrier.h>
35#include <nvgpu/mm.h> 35#include <nvgpu/mm.h>
36#include <nvgpu/log2.h>
36#include <nvgpu/ctxsw_trace.h> 37#include <nvgpu/ctxsw_trace.h>
37#include <nvgpu/io_usermode.h> 38#include <nvgpu/io_usermode.h>
38 39
@@ -932,7 +933,6 @@ void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask,
932 u32 id, unsigned int id_type, unsigned int rc_type, 933 u32 id, unsigned int id_type, unsigned int rc_type,
933 struct mmu_fault_info *mmfault) 934 struct mmu_fault_info *mmfault)
934{ 935{
935 bool verbose = false;
936 struct tsg_gk20a *tsg = NULL; 936 struct tsg_gk20a *tsg = NULL;
937 struct channel_gk20a *refch = NULL; 937 struct channel_gk20a *refch = NULL;
938 u32 runlists_mask, runlist_id; 938 u32 runlists_mask, runlist_id;
@@ -1049,22 +1049,18 @@ void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask,
1049#endif 1049#endif
1050 1050
1051 if (tsg) { 1051 if (tsg) {
1052 if (!g->fifo.deferred_reset_pending) { 1052 if (!g->fifo.deferred_reset_pending &&
1053 if (rc_type == RC_TYPE_MMU_FAULT) { 1053 rc_type == RC_TYPE_MMU_FAULT)
1054 gk20a_fifo_set_ctx_mmu_error_tsg(g, tsg); 1054 gk20a_fifo_set_ctx_mmu_error_tsg(g, tsg);
1055 verbose = gk20a_fifo_error_tsg(g, tsg); 1055
1056 }
1057 }
1058 gk20a_fifo_abort_tsg(g, tsg->tsgid, false); 1056 gk20a_fifo_abort_tsg(g, tsg->tsgid, false);
1059 if (refch) 1057 if (refch)
1060 gk20a_channel_put(refch); 1058 gk20a_channel_put(refch);
1061 } else if (refch) { 1059 } else if (refch) {
1062 if (!g->fifo.deferred_reset_pending) { 1060 if (!g->fifo.deferred_reset_pending &&
1063 if (rc_type == RC_TYPE_MMU_FAULT) { 1061 rc_type == RC_TYPE_MMU_FAULT)
1064 gk20a_fifo_set_ctx_mmu_error_ch(g, refch); 1062 gk20a_fifo_set_ctx_mmu_error_ch(g, refch);
1065 verbose = gk20a_fifo_error_ch(g, refch); 1063
1066 }
1067 }
1068 gk20a_channel_abort(refch, false); 1064 gk20a_channel_abort(refch, false);
1069 gk20a_channel_put(refch); 1065 gk20a_channel_put(refch);
1070 } else { 1066 } else {
diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c
index e4cfe925..7dd4f8f4 100644
--- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c
@@ -184,7 +184,7 @@ int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu)
184 struct mm_gk20a *mm = &g->mm; 184 struct mm_gk20a *mm = &g->mm;
185 struct pmu_ucode_desc *desc = pmu->desc; 185 struct pmu_ucode_desc *desc = pmu->desc;
186 u64 addr_code_lo, addr_data_lo, addr_load_lo; 186 u64 addr_code_lo, addr_data_lo, addr_load_lo;
187 u64 addr_code_hi, addr_data_hi, addr_load_hi; 187 u64 addr_code_hi, addr_data_hi;
188 u32 i, blocks, addr_args; 188 u32 i, blocks, addr_args;
189 189
190 gk20a_dbg_fn(""); 190 gk20a_dbg_fn("");
@@ -238,8 +238,6 @@ int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu)
238 desc->app_resident_data_offset) >> 8); 238 desc->app_resident_data_offset) >> 8);
239 addr_load_lo = u64_lo32((pmu->ucode.gpu_va + 239 addr_load_lo = u64_lo32((pmu->ucode.gpu_va +
240 desc->bootloader_start_offset) >> 8); 240 desc->bootloader_start_offset) >> 8);
241 addr_load_hi = u64_hi32((pmu->ucode.gpu_va +
242 desc->bootloader_start_offset) >> 8);
243 241
244 gk20a_writel(g, pwr_falcon_dmemd_r(0), 0x0); 242 gk20a_writel(g, pwr_falcon_dmemd_r(0), 0x0);
245 gk20a_writel(g, pwr_falcon_dmemd_r(0), 0x0); 243 gk20a_writel(g, pwr_falcon_dmemd_r(0), 0x0);