summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/gv11b
diff options
context:
space:
mode:
authorDeepak Nibade <dnibade@nvidia.com>2018-04-06 09:08:18 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-04-10 14:23:11 -0400
commit78151bb6f9cf9f355c57a28df0c7e4cd867c3322 (patch)
treeaa7413d9caae2766ce7f81384336af0556bfe63a /drivers/gpu/nvgpu/gv11b
parent19aa748be53787da6abe435ea7043a7827d0fde0 (diff)
gpu: nvgpu: use HAL for chiplet offset
We currently use hard coded values of NV_PERF_PMMGPC_CHIPLET_OFFSET and NV_PMM_FBP_STRIDE which are incorrect for Volta Add new GR HAL get_pmm_per_chiplet_offset() to get correct value per-chip Set gr_gm20b_get_pmm_per_chiplet_offset() for older chips Set gr_gv11b_get_pmm_per_chiplet_offset() for Volta Use HAL instead of hard coded values wherever required Bug 200398811 Jira NVGPU-556 Change-Id: I947e7febd4f84fae740a1bc74f99d72e1df523aa Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1690028 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gv11b')
-rw-r--r--drivers/gpu/nvgpu/gv11b/gr_gv11b.c15
-rw-r--r--drivers/gpu/nvgpu/gv11b/gr_gv11b.h1
-rw-r--r--drivers/gpu/nvgpu/gv11b/hal_gv11b.c2
3 files changed, 13 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 67603739..f8461f9d 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -4513,10 +4513,16 @@ int gr_gv11b_decode_priv_addr(struct gk20a *g, u32 addr,
4513 return 0; 4513 return 0;
4514} 4514}
4515 4515
4516static u32 gr_gv11b_pri_pmmgpc_addr(u32 gpc_num, u32 domain_idx, u32 offset) 4516u32 gr_gv11b_get_pmm_per_chiplet_offset(void)
4517{
4518 return (perf_pmmsys_extent_v() - perf_pmmsys_base_v() + 1);
4519}
4520
4521static u32 gr_gv11b_pri_pmmgpc_addr(struct gk20a *g, u32 gpc_num,
4522 u32 domain_idx, u32 offset)
4517{ 4523{
4518 return perf_pmmgpc_base_v() + 4524 return perf_pmmgpc_base_v() +
4519 (gpc_num * (perf_pmmsys_extent_v() - perf_pmmsys_base_v() + 1)) + 4525 (gpc_num * g->ops.gr.get_pmm_per_chiplet_offset()) +
4520 (domain_idx * perf_pmmgpc_perdomain_offset_v()) + 4526 (domain_idx * perf_pmmgpc_perdomain_offset_v()) +
4521 offset; 4527 offset;
4522} 4528}
@@ -4531,8 +4537,7 @@ static void gr_gv11b_split_pmm_fbp_broadcast_address(struct gk20a *g,
4531 4537
4532 for (fbp_num = 0; fbp_num < g->gr.num_fbps; fbp_num++) { 4538 for (fbp_num = 0; fbp_num < g->gr.num_fbps; fbp_num++) {
4533 base = perf_pmmfbp_base_v() + 4539 base = perf_pmmfbp_base_v() +
4534 (fbp_num * 4540 (fbp_num * g->ops.gr.get_pmm_per_chiplet_offset());
4535 (perf_pmmsys_extent_v() - perf_pmmsys_base_v() + 1));
4536 4541
4537 for (domain_idx = domain_start; 4542 for (domain_idx = domain_start;
4538 domain_idx < (domain_start + num_domains); 4543 domain_idx < (domain_start + num_domains);
@@ -4653,7 +4658,7 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g,
4653 domain_idx < (pmm_domain_start + num_domains); 4658 domain_idx < (pmm_domain_start + num_domains);
4654 domain_idx++) { 4659 domain_idx++) {
4655 priv_addr_table[t++] = 4660 priv_addr_table[t++] =
4656 gr_gv11b_pri_pmmgpc_addr(gpc_num, 4661 gr_gv11b_pri_pmmgpc_addr(g, gpc_num,
4657 domain_idx, offset); 4662 domain_idx, offset);
4658 } 4663 }
4659 } 4664 }
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
index 3c581326..1a3a851e 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h
@@ -234,6 +234,7 @@ void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g,
234int gr_gv11b_handle_ssync_hww(struct gk20a *g); 234int gr_gv11b_handle_ssync_hww(struct gk20a *g);
235u32 gv11b_gr_sm_offset(struct gk20a *g, u32 sm); 235u32 gv11b_gr_sm_offset(struct gk20a *g, u32 sm);
236 236
237u32 gr_gv11b_get_pmm_per_chiplet_offset(void);
237int gr_gv11b_decode_priv_addr(struct gk20a *g, u32 addr, 238int gr_gv11b_decode_priv_addr(struct gk20a *g, u32 addr,
238 int *addr_type, 239 int *addr_type,
239 u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num, 240 u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num,
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index e39df1db..d0a564db 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -405,6 +405,8 @@ static const struct gpu_ops gv11b_ops = {
405 .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma, 405 .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma,
406 .decode_priv_addr = gr_gv11b_decode_priv_addr, 406 .decode_priv_addr = gr_gv11b_decode_priv_addr,
407 .create_priv_addr_table = gr_gv11b_create_priv_addr_table, 407 .create_priv_addr_table = gr_gv11b_create_priv_addr_table,
408 .get_pmm_per_chiplet_offset =
409 gr_gv11b_get_pmm_per_chiplet_offset,
408 }, 410 },
409 .fb = { 411 .fb = {
410 .reset = gv11b_fb_reset, 412 .reset = gv11b_fb_reset,