From 78151bb6f9cf9f355c57a28df0c7e4cd867c3322 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Fri, 6 Apr 2018 18:38:18 +0530 Subject: gpu: nvgpu: use HAL for chiplet offset We currently use hard coded values of NV_PERF_PMMGPC_CHIPLET_OFFSET and NV_PMM_FBP_STRIDE which are incorrect for Volta Add new GR HAL get_pmm_per_chiplet_offset() to get correct value per-chip Set gr_gm20b_get_pmm_per_chiplet_offset() for older chips Set gr_gv11b_get_pmm_per_chiplet_offset() for Volta Use HAL instead of hard coded values wherever required Bug 200398811 Jira NVGPU-556 Change-Id: I947e7febd4f84fae740a1bc74f99d72e1df523aa Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1690028 Reviewed-by: svc-mobile-coverity Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 15 ++++++++++----- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 1 + drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 ++ 3 files changed, 13 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 67603739..f8461f9d 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -4513,10 +4513,16 @@ int gr_gv11b_decode_priv_addr(struct gk20a *g, u32 addr, return 0; } -static u32 gr_gv11b_pri_pmmgpc_addr(u32 gpc_num, u32 domain_idx, u32 offset) +u32 gr_gv11b_get_pmm_per_chiplet_offset(void) +{ + return (perf_pmmsys_extent_v() - perf_pmmsys_base_v() + 1); +} + +static u32 gr_gv11b_pri_pmmgpc_addr(struct gk20a *g, u32 gpc_num, + u32 domain_idx, u32 offset) { return perf_pmmgpc_base_v() + - (gpc_num * (perf_pmmsys_extent_v() - perf_pmmsys_base_v() + 1)) + + (gpc_num * g->ops.gr.get_pmm_per_chiplet_offset()) + (domain_idx * perf_pmmgpc_perdomain_offset_v()) + offset; } @@ -4531,8 +4537,7 @@ static void gr_gv11b_split_pmm_fbp_broadcast_address(struct gk20a *g, for (fbp_num = 0; fbp_num < g->gr.num_fbps; fbp_num++) { base = perf_pmmfbp_base_v() + - (fbp_num * - (perf_pmmsys_extent_v() - perf_pmmsys_base_v() + 1)); + (fbp_num * g->ops.gr.get_pmm_per_chiplet_offset()); for (domain_idx = domain_start; domain_idx < (domain_start + num_domains); @@ -4653,7 +4658,7 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g, domain_idx < (pmm_domain_start + num_domains); domain_idx++) { priv_addr_table[t++] = - gr_gv11b_pri_pmmgpc_addr(gpc_num, + gr_gv11b_pri_pmmgpc_addr(g, gpc_num, domain_idx, offset); } } diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 3c581326..1a3a851e 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -234,6 +234,7 @@ void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g, int gr_gv11b_handle_ssync_hww(struct gk20a *g); u32 gv11b_gr_sm_offset(struct gk20a *g, u32 sm); +u32 gr_gv11b_get_pmm_per_chiplet_offset(void); int gr_gv11b_decode_priv_addr(struct gk20a *g, u32 addr, int *addr_type, u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index e39df1db..d0a564db 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -405,6 +405,8 @@ static const struct gpu_ops gv11b_ops = { .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma, .decode_priv_addr = gr_gv11b_decode_priv_addr, .create_priv_addr_table = gr_gv11b_create_priv_addr_table, + .get_pmm_per_chiplet_offset = + gr_gv11b_get_pmm_per_chiplet_offset, }, .fb = { .reset = gv11b_fb_reset, -- cgit v1.2.2